Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-misc-next-2024-08-22' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.12:
Cross-subsystem Changes:
string:
- add mem_is_zero()
Core Changes:
edid:
- use mem_is_zero()
Driver Changes:
ast:
- reorganize output code by type (VGA, DP, etc)
- convert to struct drm_edid
- fix BMC handling for all outputs
bridge:
- anx7625: simplify OF array handling
- dw-hdmi: simplify clock handling
- lontium-lt8912b: fix mode validation
- nwl-dsi: fix mode vsync/hsync polarity
panel:
- ili9341: fix comments
- jd9365da: fix "exit sleep" commands
- jdi-fhd-r63452: simplify error handling with DSI multi-style
helpers
- mantix-mlaf057we51: simplify error handling with DSI multi-style
helpers
- simple: support Innolux G070ACE-LH3 plus DT bindings; support
On Tat Industrial Company KD50G21-40NT-A1 plus DT bindings
- st7701: decouple DSI and DRM code; add SPI support; support Anbernic
RG28XX plus DT bindings
vc4:
- fix PM during detect
- replace DRM_ERROR() with drm_error()
- v3d: simplify clock retrieval
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20240822150710.GA243952@localhost.localdomain
+1805
-1453
+4
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+4
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
···
158
158
- innolux,at070tn92
159
159
# Innolux G070ACE-L01 7" WVGA (800x480) TFT LCD panel
160
160
- innolux,g070ace-l01
161
+
# Innolux G070ACE-LH3 7" WVGA (800x480) TFT LCD panel with WLED backlight
162
+
- innolux,g070ace-lh3
161
163
# Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
162
164
- innolux,g070y2-l01
163
165
# Innolux G070Y2-T02 7" WVGA (800x480) TFT LCD TTL panel
···
224
222
- okaya,rs800480t-7x0gp
225
223
# Olimex 4.3" TFT LCD panel
226
224
- olimex,lcd-olinuxino-43-ts
225
+
# On Tat Industrial Company 5" DPI TFT panel.
226
+
- ontat,kd50g21-40nt-a1
227
227
# On Tat Industrial Company 7" DPI TFT panel.
228
228
- ontat,yx700wv03
229
229
# OrtusTech COM37H3M05DTC Blanview 3.7" VGA portrait TFT-LCD panel
+64
-5
Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml
+64
-5
Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml
···
20
20
Densitron DMT028VGHMCMI-1A is 480x640, 2-lane MIPI DSI LCD panel
21
21
which has built-in ST7701 chip.
22
22
23
-
allOf:
24
-
- $ref: panel-common.yaml#
25
-
26
23
properties:
27
24
compatible:
28
25
items:
29
26
- enum:
30
27
- anbernic,rg-arc-panel
28
+
- anbernic,rg28xx-panel
31
29
- densitron,dmt028vghmcmi-1a
32
30
- elida,kd50t048a
33
31
- techstar,ts8550b
34
32
- const: sitronix,st7701
35
33
36
34
reg:
37
-
description: DSI virtual channel used by that screen
35
+
description: DSI / SPI channel used by that screen
38
36
maxItems: 1
39
37
40
38
VCC-supply:
···
40
42
41
43
IOVCC-supply:
42
44
description: I/O system regulator
45
+
46
+
dc-gpios:
47
+
maxItems: 1
48
+
description:
49
+
Controller data/command selection (D/CX) in 4-line SPI mode.
50
+
If not set, the controller is in 3-line SPI mode.
51
+
Disallowed for DSI.
43
52
44
53
port: true
45
54
reset-gpios: true
···
62
57
- port
63
58
- reset-gpios
64
59
65
-
additionalProperties: false
60
+
allOf:
61
+
- $ref: panel-common.yaml#
62
+
- if:
63
+
properties:
64
+
compatible:
65
+
contains:
66
+
# SPI connected panels
67
+
enum:
68
+
- anbernic,rg28xx-panel
69
+
then:
70
+
$ref: /schemas/spi/spi-peripheral-props.yaml#
71
+
72
+
- if:
73
+
properties:
74
+
compatible:
75
+
not:
76
+
contains:
77
+
# DSI or SPI without D/CX pin
78
+
enum:
79
+
- anbernic,rg-arc-panel
80
+
- anbernic,rg28xx-panel
81
+
- densitron,dmt028vghmcmi-1a
82
+
- elida,kd50t048a
83
+
- techstar,ts8550b
84
+
then:
85
+
required:
86
+
- dc-gpios
87
+
else:
88
+
properties:
89
+
dc-gpios: false
90
+
91
+
unevaluatedProperties: false
66
92
67
93
examples:
68
94
- |
···
114
78
port {
115
79
mipi_in_panel: endpoint {
116
80
remote-endpoint = <&mipi_out_panel>;
81
+
};
82
+
};
83
+
};
84
+
};
85
+
- |
86
+
#include <dt-bindings/gpio/gpio.h>
87
+
88
+
spi {
89
+
#address-cells = <1>;
90
+
#size-cells = <0>;
91
+
92
+
panel@0 {
93
+
compatible = "anbernic,rg28xx-panel", "sitronix,st7701";
94
+
reg = <0>;
95
+
spi-max-frequency = <3125000>;
96
+
VCC-supply = <®_lcd>;
97
+
IOVCC-supply = <®_lcd>;
98
+
reset-gpios = <&pio 8 14 GPIO_ACTIVE_HIGH>; /* LCD-RST: PI14 */
99
+
backlight = <&backlight>;
100
+
101
+
port {
102
+
panel_in_rgb: endpoint {
103
+
remote-endpoint = <&tcon_lcd0_out_lcd>;
117
104
};
118
105
};
119
106
};
-1
MAINTAINERS
-1
MAINTAINERS
···
18771
18771
QUALCOMM CLOUD AI (QAIC) DRIVER
18772
18772
M: Jeffrey Hugo <quic_jhugo@quicinc.com>
18773
18773
R: Carl Vanderlip <quic_carlv@quicinc.com>
18774
-
R: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com>
18775
18774
L: linux-arm-msm@vger.kernel.org
18776
18775
L: dri-devel@lists.freedesktop.org
18777
18776
S: Supported
+3
-1
drivers/gpu/drm/ast/Makefile
+3
-1
drivers/gpu/drm/ast/Makefile
+229
-13
drivers/gpu/drm/ast/ast_dp.c
+229
-13
drivers/gpu/drm/ast/ast_dp.c
···
4
4
5
5
#include <linux/firmware.h>
6
6
#include <linux/delay.h>
7
+
8
+
#include <drm/drm_atomic_state_helper.h>
9
+
#include <drm/drm_edid.h>
10
+
#include <drm/drm_modeset_helper_vtables.h>
7
11
#include <drm/drm_print.h>
12
+
#include <drm/drm_probe_helper.h>
13
+
8
14
#include "ast_drv.h"
9
15
10
-
bool ast_astdp_is_connected(struct ast_device *ast)
16
+
static bool ast_astdp_is_connected(struct ast_device *ast)
11
17
{
12
18
if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, AST_IO_VGACRDF_HPD))
13
19
return false;
14
20
return true;
15
21
}
16
22
17
-
int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata)
23
+
static int ast_astdp_read_edid_block(void *data, u8 *buf, unsigned int block, size_t len)
18
24
{
19
-
struct ast_device *ast = to_ast_device(dev);
25
+
struct ast_device *ast = data;
26
+
size_t rdlen = round_up(len, 4);
20
27
int ret = 0;
21
-
u8 i;
28
+
unsigned int i;
29
+
30
+
if (block > 0)
31
+
return -EIO; /* extension headers not supported */
32
+
33
+
/*
34
+
* Protect access to I/O registers from concurrent modesetting
35
+
* by acquiring the I/O-register lock.
36
+
*/
37
+
mutex_lock(&ast->modeset_lock);
22
38
23
39
/* Start reading EDID data */
24
40
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe5, (u8)~AST_IO_VGACRE5_EDID_READ_DONE, 0x00);
25
41
26
-
for (i = 0; i < 32; i++) {
42
+
for (i = 0; i < rdlen; i += 4) {
43
+
unsigned int offset;
27
44
unsigned int j;
45
+
u8 ediddata[4];
46
+
u8 vgacre4;
47
+
48
+
offset = (i + block * EDID_LENGTH) / 4;
49
+
if (offset >= 64) {
50
+
ret = -EIO;
51
+
goto out;
52
+
}
53
+
vgacre4 = offset;
28
54
29
55
/*
30
56
* CRE4[7:0]: Read-Pointer for EDID (Unit: 4bytes); valid range: 0~64
31
57
*/
32
-
ast_set_index_reg(ast, AST_IO_VGACRI, 0xe4, i);
58
+
ast_set_index_reg(ast, AST_IO_VGACRI, 0xe4, vgacre4);
33
59
34
60
/*
35
61
* CRD7[b0]: valid flag for EDID
···
79
53
vgacrd7 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd7);
80
54
if (vgacrd7 & AST_IO_VGACRD7_EDID_VALID_FLAG) {
81
55
vgacrd6 = ast_get_index_reg(ast, AST_IO_VGACRI, 0xd6);
82
-
if (vgacrd6 == i)
56
+
if (vgacrd6 == offset)
83
57
break;
84
58
}
85
59
}
···
107
81
ediddata[2] = 0;
108
82
}
109
83
110
-
ediddata += 4;
84
+
memcpy(buf, ediddata, min((len - i), 4));
85
+
buf += 4;
111
86
}
112
87
113
88
out:
114
89
/* Signal end of reading */
115
90
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xe5, (u8)~AST_IO_VGACRE5_EDID_READ_DONE,
116
91
AST_IO_VGACRE5_EDID_READ_DONE);
92
+
93
+
mutex_unlock(&ast->modeset_lock);
117
94
118
95
return ret;
119
96
}
···
149
120
return 0;
150
121
}
151
122
152
-
bool ast_dp_power_is_on(struct ast_device *ast)
123
+
static bool ast_dp_power_is_on(struct ast_device *ast)
153
124
{
154
125
u8 vgacre3;
155
126
···
158
129
return !(vgacre3 & AST_DP_PHY_SLEEP);
159
130
}
160
131
161
-
void ast_dp_power_on_off(struct drm_device *dev, bool on)
132
+
static void ast_dp_power_on_off(struct drm_device *dev, bool on)
162
133
{
163
134
struct ast_device *ast = to_ast_device(dev);
164
135
// Read and Turn off DP PHY sleep
···
170
141
171
142
// DP Power on/off
172
143
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3);
144
+
145
+
msleep(50);
173
146
}
174
147
175
-
void ast_dp_link_training(struct ast_device *ast)
148
+
static void ast_dp_link_training(struct ast_device *ast)
176
149
{
177
150
struct drm_device *dev = &ast->base;
178
151
int i;
···
192
161
drm_err(dev, "Link training failed\n");
193
162
}
194
163
195
-
void ast_dp_set_on_off(struct drm_device *dev, bool on)
164
+
static void ast_dp_set_on_off(struct drm_device *dev, bool on)
196
165
{
197
166
struct ast_device *ast = to_ast_device(dev);
198
167
u8 video_on_off = on;
···
211
180
}
212
181
}
213
182
214
-
void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode)
183
+
static void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode)
215
184
{
216
185
struct ast_device *ast = to_ast_device(crtc->dev);
217
186
···
283
252
ASTDP_MISC0_24bpp);
284
253
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE1, ASTDP_AND_CLEAR_MASK, ASTDP_MISC1);
285
254
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE2, ASTDP_AND_CLEAR_MASK, ModeIdx);
255
+
}
256
+
257
+
static void ast_wait_for_vretrace(struct ast_device *ast)
258
+
{
259
+
unsigned long timeout = jiffies + HZ;
260
+
u8 vgair1;
261
+
262
+
do {
263
+
vgair1 = ast_io_read8(ast, AST_IO_VGAIR1_R);
264
+
} while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
265
+
}
266
+
267
+
/*
268
+
* Encoder
269
+
*/
270
+
271
+
static const struct drm_encoder_funcs ast_astdp_encoder_funcs = {
272
+
.destroy = drm_encoder_cleanup,
273
+
};
274
+
275
+
static void ast_astdp_encoder_helper_atomic_mode_set(struct drm_encoder *encoder,
276
+
struct drm_crtc_state *crtc_state,
277
+
struct drm_connector_state *conn_state)
278
+
{
279
+
struct drm_crtc *crtc = crtc_state->crtc;
280
+
struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
281
+
struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
282
+
283
+
ast_dp_set_mode(crtc, vbios_mode_info);
284
+
}
285
+
286
+
static void ast_astdp_encoder_helper_atomic_enable(struct drm_encoder *encoder,
287
+
struct drm_atomic_state *state)
288
+
{
289
+
struct drm_device *dev = encoder->dev;
290
+
struct ast_device *ast = to_ast_device(dev);
291
+
struct ast_connector *ast_connector = &ast->output.astdp.connector;
292
+
293
+
if (ast_connector->physical_status == connector_status_connected) {
294
+
ast_dp_power_on_off(dev, AST_DP_POWER_ON);
295
+
ast_dp_link_training(ast);
296
+
297
+
ast_wait_for_vretrace(ast);
298
+
ast_dp_set_on_off(dev, 1);
299
+
}
300
+
}
301
+
302
+
static void ast_astdp_encoder_helper_atomic_disable(struct drm_encoder *encoder,
303
+
struct drm_atomic_state *state)
304
+
{
305
+
struct drm_device *dev = encoder->dev;
306
+
307
+
ast_dp_set_on_off(dev, 0);
308
+
ast_dp_power_on_off(dev, AST_DP_POWER_OFF);
309
+
}
310
+
311
+
static const struct drm_encoder_helper_funcs ast_astdp_encoder_helper_funcs = {
312
+
.atomic_mode_set = ast_astdp_encoder_helper_atomic_mode_set,
313
+
.atomic_enable = ast_astdp_encoder_helper_atomic_enable,
314
+
.atomic_disable = ast_astdp_encoder_helper_atomic_disable,
315
+
};
316
+
317
+
/*
318
+
* Connector
319
+
*/
320
+
321
+
static int ast_astdp_connector_helper_get_modes(struct drm_connector *connector)
322
+
{
323
+
struct ast_connector *ast_connector = to_ast_connector(connector);
324
+
int count;
325
+
326
+
if (ast_connector->physical_status == connector_status_connected) {
327
+
struct ast_device *ast = to_ast_device(connector->dev);
328
+
const struct drm_edid *drm_edid;
329
+
330
+
drm_edid = drm_edid_read_custom(connector, ast_astdp_read_edid_block, ast);
331
+
drm_edid_connector_update(connector, drm_edid);
332
+
count = drm_edid_connector_add_modes(connector);
333
+
drm_edid_free(drm_edid);
334
+
} else {
335
+
drm_edid_connector_update(connector, NULL);
336
+
337
+
/*
338
+
* There's no EDID data without a connected monitor. Set BMC-
339
+
* compatible modes in this case. The XGA default resolution
340
+
* should work well for all BMCs.
341
+
*/
342
+
count = drm_add_modes_noedid(connector, 4096, 4096);
343
+
if (count)
344
+
drm_set_preferred_mode(connector, 1024, 768);
345
+
}
346
+
347
+
return count;
348
+
}
349
+
350
+
static int ast_astdp_connector_helper_detect_ctx(struct drm_connector *connector,
351
+
struct drm_modeset_acquire_ctx *ctx,
352
+
bool force)
353
+
{
354
+
struct ast_connector *ast_connector = to_ast_connector(connector);
355
+
struct drm_device *dev = connector->dev;
356
+
struct ast_device *ast = to_ast_device(connector->dev);
357
+
enum drm_connector_status status = connector_status_disconnected;
358
+
bool power_is_on;
359
+
360
+
mutex_lock(&ast->modeset_lock);
361
+
362
+
power_is_on = ast_dp_power_is_on(ast);
363
+
if (!power_is_on)
364
+
ast_dp_power_on_off(dev, true);
365
+
366
+
if (ast_astdp_is_connected(ast))
367
+
status = connector_status_connected;
368
+
369
+
if (!power_is_on && status == connector_status_disconnected)
370
+
ast_dp_power_on_off(dev, false);
371
+
372
+
mutex_unlock(&ast->modeset_lock);
373
+
374
+
if (status != ast_connector->physical_status)
375
+
++connector->epoch_counter;
376
+
ast_connector->physical_status = status;
377
+
378
+
return connector_status_connected;
379
+
}
380
+
381
+
static const struct drm_connector_helper_funcs ast_astdp_connector_helper_funcs = {
382
+
.get_modes = ast_astdp_connector_helper_get_modes,
383
+
.detect_ctx = ast_astdp_connector_helper_detect_ctx,
384
+
};
385
+
386
+
static const struct drm_connector_funcs ast_astdp_connector_funcs = {
387
+
.reset = drm_atomic_helper_connector_reset,
388
+
.fill_modes = drm_helper_probe_single_connector_modes,
389
+
.destroy = drm_connector_cleanup,
390
+
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
391
+
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
392
+
};
393
+
394
+
static int ast_astdp_connector_init(struct drm_device *dev, struct drm_connector *connector)
395
+
{
396
+
int ret;
397
+
398
+
ret = drm_connector_init(dev, connector, &ast_astdp_connector_funcs,
399
+
DRM_MODE_CONNECTOR_DisplayPort);
400
+
if (ret)
401
+
return ret;
402
+
403
+
drm_connector_helper_add(connector, &ast_astdp_connector_helper_funcs);
404
+
405
+
connector->interlace_allowed = 0;
406
+
connector->doublescan_allowed = 0;
407
+
408
+
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
409
+
410
+
return 0;
411
+
}
412
+
413
+
int ast_astdp_output_init(struct ast_device *ast)
414
+
{
415
+
struct drm_device *dev = &ast->base;
416
+
struct drm_crtc *crtc = &ast->crtc;
417
+
struct drm_encoder *encoder = &ast->output.astdp.encoder;
418
+
struct ast_connector *ast_connector = &ast->output.astdp.connector;
419
+
struct drm_connector *connector = &ast_connector->base;
420
+
int ret;
421
+
422
+
ret = drm_encoder_init(dev, encoder, &ast_astdp_encoder_funcs,
423
+
DRM_MODE_ENCODER_TMDS, NULL);
424
+
if (ret)
425
+
return ret;
426
+
drm_encoder_helper_add(encoder, &ast_astdp_encoder_helper_funcs);
427
+
428
+
encoder->possible_crtcs = drm_crtc_mask(crtc);
429
+
430
+
ret = ast_astdp_connector_init(dev, connector);
431
+
if (ret)
432
+
return ret;
433
+
ast_connector->physical_status = connector->status;
434
+
435
+
ret = drm_connector_attach_encoder(connector, encoder);
436
+
if (ret)
437
+
return ret;
438
+
439
+
return 0;
286
440
}
+164
-20
drivers/gpu/drm/ast/ast_dp501.c
+164
-20
drivers/gpu/drm/ast/ast_dp501.c
···
4
4
#include <linux/firmware.h>
5
5
#include <linux/module.h>
6
6
7
+
#include <drm/drm_atomic_state_helper.h>
8
+
#include <drm/drm_edid.h>
9
+
#include <drm/drm_modeset_helper_vtables.h>
10
+
#include <drm/drm_probe_helper.h>
11
+
7
12
#include "ast_drv.h"
8
13
9
14
MODULE_FIRMWARE("ast_dp501_fw.bin");
···
175
170
}
176
171
#endif
177
172
178
-
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
173
+
static void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
179
174
{
180
175
ast_write_cmd(dev, 0x40);
181
176
ast_write_data(dev, mode);
···
277
272
return true;
278
273
}
279
274
280
-
bool ast_dp501_is_connected(struct ast_device *ast)
275
+
static bool ast_dp501_is_connected(struct ast_device *ast)
281
276
{
282
277
u32 boot_address, offset, data;
283
278
···
318
313
return true;
319
314
}
320
315
321
-
bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
316
+
static int ast_dp512_read_edid_block(void *data, u8 *buf, unsigned int block, size_t len)
322
317
{
323
-
struct ast_device *ast = to_ast_device(dev);
324
-
u32 i, boot_address, offset, data;
325
-
u32 *pEDIDidx;
318
+
struct ast_device *ast = data;
319
+
size_t rdlen = round_up(len, 4);
320
+
u32 i, boot_address, offset, ediddata;
326
321
327
-
if (!ast_dp501_is_connected(ast))
328
-
return false;
322
+
if (block > (512 / EDID_LENGTH))
323
+
return -EIO;
324
+
325
+
offset = AST_DP501_EDID_DATA + block * EDID_LENGTH;
329
326
330
327
if (ast->config_mode == ast_use_p2a) {
331
328
boot_address = get_fw_base(ast);
332
329
333
-
/* Read EDID */
334
-
offset = AST_DP501_EDID_DATA;
335
-
for (i = 0; i < 128; i += 4) {
336
-
data = ast_mindwm(ast, boot_address + offset + i);
337
-
pEDIDidx = (u32 *)(ediddata + i);
338
-
*pEDIDidx = data;
330
+
for (i = 0; i < rdlen; i += 4) {
331
+
ediddata = ast_mindwm(ast, boot_address + offset + i);
332
+
memcpy(buf, &ediddata, min((len - i), 4));
333
+
buf += 4;
339
334
}
340
335
} else {
341
-
/* Read EDID */
342
-
offset = AST_DP501_EDID_DATA;
343
-
for (i = 0; i < 128; i += 4) {
344
-
data = readl(ast->dp501_fw_buf + offset + i);
345
-
pEDIDidx = (u32 *)(ediddata + i);
346
-
*pEDIDidx = data;
336
+
for (i = 0; i < rdlen; i += 4) {
337
+
ediddata = readl(ast->dp501_fw_buf + offset + i);
338
+
memcpy(buf, &ediddata, min((len - i), 4));
339
+
buf += 4;
347
340
}
348
341
}
349
342
···
472
469
ast_init_analog(dev);
473
470
}
474
471
}
472
+
}
473
+
474
+
/*
475
+
* Encoder
476
+
*/
477
+
478
+
static const struct drm_encoder_funcs ast_dp501_encoder_funcs = {
479
+
.destroy = drm_encoder_cleanup,
480
+
};
481
+
482
+
static void ast_dp501_encoder_helper_atomic_enable(struct drm_encoder *encoder,
483
+
struct drm_atomic_state *state)
484
+
{
485
+
struct drm_device *dev = encoder->dev;
486
+
487
+
ast_set_dp501_video_output(dev, 1);
488
+
}
489
+
490
+
static void ast_dp501_encoder_helper_atomic_disable(struct drm_encoder *encoder,
491
+
struct drm_atomic_state *state)
492
+
{
493
+
struct drm_device *dev = encoder->dev;
494
+
495
+
ast_set_dp501_video_output(dev, 0);
496
+
}
497
+
498
+
static const struct drm_encoder_helper_funcs ast_dp501_encoder_helper_funcs = {
499
+
.atomic_enable = ast_dp501_encoder_helper_atomic_enable,
500
+
.atomic_disable = ast_dp501_encoder_helper_atomic_disable,
501
+
};
502
+
503
+
/*
504
+
* Connector
505
+
*/
506
+
507
+
static int ast_dp501_connector_helper_get_modes(struct drm_connector *connector)
508
+
{
509
+
struct ast_connector *ast_connector = to_ast_connector(connector);
510
+
int count;
511
+
512
+
if (ast_connector->physical_status == connector_status_connected) {
513
+
struct ast_device *ast = to_ast_device(connector->dev);
514
+
const struct drm_edid *drm_edid;
515
+
516
+
drm_edid = drm_edid_read_custom(connector, ast_dp512_read_edid_block, ast);
517
+
drm_edid_connector_update(connector, drm_edid);
518
+
count = drm_edid_connector_add_modes(connector);
519
+
drm_edid_free(drm_edid);
520
+
} else {
521
+
drm_edid_connector_update(connector, NULL);
522
+
523
+
/*
524
+
* There's no EDID data without a connected monitor. Set BMC-
525
+
* compatible modes in this case. The XGA default resolution
526
+
* should work well for all BMCs.
527
+
*/
528
+
count = drm_add_modes_noedid(connector, 4096, 4096);
529
+
if (count)
530
+
drm_set_preferred_mode(connector, 1024, 768);
531
+
}
532
+
533
+
return count;
534
+
}
535
+
536
+
static int ast_dp501_connector_helper_detect_ctx(struct drm_connector *connector,
537
+
struct drm_modeset_acquire_ctx *ctx,
538
+
bool force)
539
+
{
540
+
struct ast_connector *ast_connector = to_ast_connector(connector);
541
+
struct ast_device *ast = to_ast_device(connector->dev);
542
+
enum drm_connector_status status = connector_status_disconnected;
543
+
544
+
if (ast_dp501_is_connected(ast))
545
+
status = connector_status_connected;
546
+
547
+
if (status != ast_connector->physical_status)
548
+
++connector->epoch_counter;
549
+
ast_connector->physical_status = status;
550
+
551
+
return connector_status_connected;
552
+
}
553
+
554
+
static const struct drm_connector_helper_funcs ast_dp501_connector_helper_funcs = {
555
+
.get_modes = ast_dp501_connector_helper_get_modes,
556
+
.detect_ctx = ast_dp501_connector_helper_detect_ctx,
557
+
};
558
+
559
+
static const struct drm_connector_funcs ast_dp501_connector_funcs = {
560
+
.reset = drm_atomic_helper_connector_reset,
561
+
.fill_modes = drm_helper_probe_single_connector_modes,
562
+
.destroy = drm_connector_cleanup,
563
+
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
564
+
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
565
+
};
566
+
567
+
static int ast_dp501_connector_init(struct drm_device *dev, struct drm_connector *connector)
568
+
{
569
+
int ret;
570
+
571
+
ret = drm_connector_init(dev, connector, &ast_dp501_connector_funcs,
572
+
DRM_MODE_CONNECTOR_DisplayPort);
573
+
if (ret)
574
+
return ret;
575
+
576
+
drm_connector_helper_add(connector, &ast_dp501_connector_helper_funcs);
577
+
578
+
connector->interlace_allowed = 0;
579
+
connector->doublescan_allowed = 0;
580
+
581
+
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
582
+
583
+
return 0;
584
+
}
585
+
586
+
int ast_dp501_output_init(struct ast_device *ast)
587
+
{
588
+
struct drm_device *dev = &ast->base;
589
+
struct drm_crtc *crtc = &ast->crtc;
590
+
struct drm_encoder *encoder = &ast->output.dp501.encoder;
591
+
struct ast_connector *ast_connector = &ast->output.dp501.connector;
592
+
struct drm_connector *connector = &ast_connector->base;
593
+
int ret;
594
+
595
+
ret = drm_encoder_init(dev, encoder, &ast_dp501_encoder_funcs,
596
+
DRM_MODE_ENCODER_TMDS, NULL);
597
+
if (ret)
598
+
return ret;
599
+
drm_encoder_helper_add(encoder, &ast_dp501_encoder_helper_funcs);
600
+
601
+
encoder->possible_crtcs = drm_crtc_mask(crtc);
602
+
603
+
ret = ast_dp501_connector_init(dev, connector);
604
+
if (ret)
605
+
return ret;
606
+
ast_connector->physical_status = connector->status;
607
+
608
+
ret = drm_connector_attach_encoder(connector, encoder);
609
+
if (ret)
610
+
return ret;
611
+
612
+
return 0;
475
613
}
+17
-25
drivers/gpu/drm/ast/ast_drv.h
+17
-25
drivers/gpu/drm/ast/ast_drv.h
···
147
147
}
148
148
149
149
/*
150
-
* BMC
150
+
* Connector
151
151
*/
152
152
153
-
struct ast_bmc_connector {
153
+
struct ast_connector {
154
154
struct drm_connector base;
155
-
struct drm_connector *physical_connector;
155
+
156
+
enum drm_connector_status physical_status;
156
157
};
157
158
158
-
static inline struct ast_bmc_connector *
159
-
to_ast_bmc_connector(struct drm_connector *connector)
159
+
static inline struct ast_connector *
160
+
to_ast_connector(struct drm_connector *connector)
160
161
{
161
-
return container_of(connector, struct ast_bmc_connector, base);
162
+
return container_of(connector, struct ast_connector, base);
162
163
}
163
164
164
165
/*
···
193
192
struct {
194
193
struct {
195
194
struct drm_encoder encoder;
196
-
struct drm_connector connector;
195
+
struct ast_connector connector;
197
196
} vga;
198
197
struct {
199
198
struct drm_encoder encoder;
200
-
struct drm_connector connector;
199
+
struct ast_connector connector;
201
200
} sil164;
202
201
struct {
203
202
struct drm_encoder encoder;
204
-
struct drm_connector connector;
203
+
struct ast_connector connector;
205
204
} dp501;
206
205
struct {
207
206
struct drm_encoder encoder;
208
-
struct drm_connector connector;
207
+
struct ast_connector connector;
209
208
} astdp;
210
-
struct {
211
-
struct drm_encoder encoder;
212
-
struct ast_bmc_connector bmc_connector;
213
-
} bmc;
214
209
} output;
215
210
216
211
bool support_wide_screen;
···
457
460
u32 ast_mindwm(struct ast_device *ast, u32 r);
458
461
void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
459
462
void ast_patch_ahb_2500(void __iomem *regs);
463
+
464
+
int ast_vga_output_init(struct ast_device *ast);
465
+
int ast_sil164_output_init(struct ast_device *ast);
466
+
460
467
/* ast dp501 */
461
-
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
462
468
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
463
-
bool ast_dp501_is_connected(struct ast_device *ast);
464
-
bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
465
-
u8 ast_get_dp501_max_clk(struct drm_device *dev);
466
469
void ast_init_3rdtx(struct drm_device *dev);
470
+
int ast_dp501_output_init(struct ast_device *ast);
467
471
468
472
/* aspeed DP */
469
-
bool ast_astdp_is_connected(struct ast_device *ast);
470
-
int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata);
471
473
int ast_dp_launch(struct ast_device *ast);
472
-
bool ast_dp_power_is_on(struct ast_device *ast);
473
-
void ast_dp_power_on_off(struct drm_device *dev, bool no);
474
-
void ast_dp_link_training(struct ast_device *ast);
475
-
void ast_dp_set_on_off(struct drm_device *dev, bool no);
476
-
void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode);
474
+
int ast_astdp_output_init(struct ast_device *ast);
477
475
478
476
#endif
-578
drivers/gpu/drm/ast/ast_mode.c
-578
drivers/gpu/drm/ast/ast_mode.c
···
34
34
35
35
#include <drm/drm_atomic.h>
36
36
#include <drm/drm_atomic_helper.h>
37
-
#include <drm/drm_atomic_state_helper.h>
38
37
#include <drm/drm_crtc.h>
39
38
#include <drm/drm_damage_helper.h>
40
-
#include <drm/drm_edid.h>
41
39
#include <drm/drm_format_helper.h>
42
40
#include <drm/drm_fourcc.h>
43
41
#include <drm/drm_gem_atomic_helper.h>
···
45
47
#include <drm/drm_panic.h>
46
48
#include <drm/drm_probe_helper.h>
47
49
48
-
#include "ast_ddc.h"
49
50
#include "ast_drv.h"
50
51
#include "ast_tables.h"
51
52
···
1308
1311
}
1309
1312
1310
1313
/*
1311
-
* VGA Encoder
1312
-
*/
1313
-
1314
-
static const struct drm_encoder_funcs ast_vga_encoder_funcs = {
1315
-
.destroy = drm_encoder_cleanup,
1316
-
};
1317
-
1318
-
/*
1319
-
* VGA Connector
1320
-
*/
1321
-
1322
-
static const struct drm_connector_helper_funcs ast_vga_connector_helper_funcs = {
1323
-
.get_modes = drm_connector_helper_get_modes,
1324
-
.detect_ctx = drm_connector_helper_detect_from_ddc,
1325
-
};
1326
-
1327
-
static const struct drm_connector_funcs ast_vga_connector_funcs = {
1328
-
.reset = drm_atomic_helper_connector_reset,
1329
-
.fill_modes = drm_helper_probe_single_connector_modes,
1330
-
.destroy = drm_connector_cleanup,
1331
-
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1332
-
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1333
-
};
1334
-
1335
-
static int ast_vga_connector_init(struct drm_device *dev, struct drm_connector *connector)
1336
-
{
1337
-
struct ast_device *ast = to_ast_device(dev);
1338
-
struct i2c_adapter *ddc;
1339
-
int ret;
1340
-
1341
-
ddc = ast_ddc_create(ast);
1342
-
if (IS_ERR(ddc)) {
1343
-
ret = PTR_ERR(ddc);
1344
-
drm_err(dev, "failed to add DDC bus for connector; ret=%d\n", ret);
1345
-
return ret;
1346
-
}
1347
-
1348
-
ret = drm_connector_init_with_ddc(dev, connector, &ast_vga_connector_funcs,
1349
-
DRM_MODE_CONNECTOR_VGA, ddc);
1350
-
if (ret)
1351
-
return ret;
1352
-
1353
-
drm_connector_helper_add(connector, &ast_vga_connector_helper_funcs);
1354
-
1355
-
connector->interlace_allowed = 0;
1356
-
connector->doublescan_allowed = 0;
1357
-
1358
-
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
1359
-
1360
-
return 0;
1361
-
}
1362
-
1363
-
static int ast_vga_output_init(struct ast_device *ast)
1364
-
{
1365
-
struct drm_device *dev = &ast->base;
1366
-
struct drm_crtc *crtc = &ast->crtc;
1367
-
struct drm_encoder *encoder = &ast->output.vga.encoder;
1368
-
struct drm_connector *connector = &ast->output.vga.connector;
1369
-
int ret;
1370
-
1371
-
ret = drm_encoder_init(dev, encoder, &ast_vga_encoder_funcs,
1372
-
DRM_MODE_ENCODER_DAC, NULL);
1373
-
if (ret)
1374
-
return ret;
1375
-
encoder->possible_crtcs = drm_crtc_mask(crtc);
1376
-
1377
-
ret = ast_vga_connector_init(dev, connector);
1378
-
if (ret)
1379
-
return ret;
1380
-
1381
-
ret = drm_connector_attach_encoder(connector, encoder);
1382
-
if (ret)
1383
-
return ret;
1384
-
1385
-
return 0;
1386
-
}
1387
-
1388
-
/*
1389
-
* SIL164 Encoder
1390
-
*/
1391
-
1392
-
static const struct drm_encoder_funcs ast_sil164_encoder_funcs = {
1393
-
.destroy = drm_encoder_cleanup,
1394
-
};
1395
-
1396
-
/*
1397
-
* SIL164 Connector
1398
-
*/
1399
-
1400
-
static const struct drm_connector_helper_funcs ast_sil164_connector_helper_funcs = {
1401
-
.get_modes = drm_connector_helper_get_modes,
1402
-
.detect_ctx = drm_connector_helper_detect_from_ddc,
1403
-
};
1404
-
1405
-
static const struct drm_connector_funcs ast_sil164_connector_funcs = {
1406
-
.reset = drm_atomic_helper_connector_reset,
1407
-
.fill_modes = drm_helper_probe_single_connector_modes,
1408
-
.destroy = drm_connector_cleanup,
1409
-
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1410
-
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1411
-
};
1412
-
1413
-
static int ast_sil164_connector_init(struct drm_device *dev, struct drm_connector *connector)
1414
-
{
1415
-
struct ast_device *ast = to_ast_device(dev);
1416
-
struct i2c_adapter *ddc;
1417
-
int ret;
1418
-
1419
-
ddc = ast_ddc_create(ast);
1420
-
if (IS_ERR(ddc)) {
1421
-
ret = PTR_ERR(ddc);
1422
-
drm_err(dev, "failed to add DDC bus for connector; ret=%d\n", ret);
1423
-
return ret;
1424
-
}
1425
-
1426
-
ret = drm_connector_init_with_ddc(dev, connector, &ast_sil164_connector_funcs,
1427
-
DRM_MODE_CONNECTOR_DVII, ddc);
1428
-
if (ret)
1429
-
return ret;
1430
-
1431
-
drm_connector_helper_add(connector, &ast_sil164_connector_helper_funcs);
1432
-
1433
-
connector->interlace_allowed = 0;
1434
-
connector->doublescan_allowed = 0;
1435
-
1436
-
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
1437
-
1438
-
return 0;
1439
-
}
1440
-
1441
-
static int ast_sil164_output_init(struct ast_device *ast)
1442
-
{
1443
-
struct drm_device *dev = &ast->base;
1444
-
struct drm_crtc *crtc = &ast->crtc;
1445
-
struct drm_encoder *encoder = &ast->output.sil164.encoder;
1446
-
struct drm_connector *connector = &ast->output.sil164.connector;
1447
-
int ret;
1448
-
1449
-
ret = drm_encoder_init(dev, encoder, &ast_sil164_encoder_funcs,
1450
-
DRM_MODE_ENCODER_TMDS, NULL);
1451
-
if (ret)
1452
-
return ret;
1453
-
encoder->possible_crtcs = drm_crtc_mask(crtc);
1454
-
1455
-
ret = ast_sil164_connector_init(dev, connector);
1456
-
if (ret)
1457
-
return ret;
1458
-
1459
-
ret = drm_connector_attach_encoder(connector, encoder);
1460
-
if (ret)
1461
-
return ret;
1462
-
1463
-
return 0;
1464
-
}
1465
-
1466
-
/*
1467
-
* DP501 Encoder
1468
-
*/
1469
-
1470
-
static const struct drm_encoder_funcs ast_dp501_encoder_funcs = {
1471
-
.destroy = drm_encoder_cleanup,
1472
-
};
1473
-
1474
-
static void ast_dp501_encoder_helper_atomic_enable(struct drm_encoder *encoder,
1475
-
struct drm_atomic_state *state)
1476
-
{
1477
-
struct drm_device *dev = encoder->dev;
1478
-
1479
-
ast_set_dp501_video_output(dev, 1);
1480
-
}
1481
-
1482
-
static void ast_dp501_encoder_helper_atomic_disable(struct drm_encoder *encoder,
1483
-
struct drm_atomic_state *state)
1484
-
{
1485
-
struct drm_device *dev = encoder->dev;
1486
-
1487
-
ast_set_dp501_video_output(dev, 0);
1488
-
}
1489
-
1490
-
static const struct drm_encoder_helper_funcs ast_dp501_encoder_helper_funcs = {
1491
-
.atomic_enable = ast_dp501_encoder_helper_atomic_enable,
1492
-
.atomic_disable = ast_dp501_encoder_helper_atomic_disable,
1493
-
};
1494
-
1495
-
/*
1496
-
* DP501 Connector
1497
-
*/
1498
-
1499
-
static int ast_dp501_connector_helper_get_modes(struct drm_connector *connector)
1500
-
{
1501
-
void *edid;
1502
-
bool succ;
1503
-
int count;
1504
-
1505
-
edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1506
-
if (!edid)
1507
-
goto err_drm_connector_update_edid_property;
1508
-
1509
-
succ = ast_dp501_read_edid(connector->dev, edid);
1510
-
if (!succ)
1511
-
goto err_kfree;
1512
-
1513
-
drm_connector_update_edid_property(connector, edid);
1514
-
count = drm_add_edid_modes(connector, edid);
1515
-
kfree(edid);
1516
-
1517
-
return count;
1518
-
1519
-
err_kfree:
1520
-
kfree(edid);
1521
-
err_drm_connector_update_edid_property:
1522
-
drm_connector_update_edid_property(connector, NULL);
1523
-
return 0;
1524
-
}
1525
-
1526
-
static int ast_dp501_connector_helper_detect_ctx(struct drm_connector *connector,
1527
-
struct drm_modeset_acquire_ctx *ctx,
1528
-
bool force)
1529
-
{
1530
-
struct ast_device *ast = to_ast_device(connector->dev);
1531
-
1532
-
if (ast_dp501_is_connected(ast))
1533
-
return connector_status_connected;
1534
-
return connector_status_disconnected;
1535
-
}
1536
-
1537
-
static const struct drm_connector_helper_funcs ast_dp501_connector_helper_funcs = {
1538
-
.get_modes = ast_dp501_connector_helper_get_modes,
1539
-
.detect_ctx = ast_dp501_connector_helper_detect_ctx,
1540
-
};
1541
-
1542
-
static const struct drm_connector_funcs ast_dp501_connector_funcs = {
1543
-
.reset = drm_atomic_helper_connector_reset,
1544
-
.fill_modes = drm_helper_probe_single_connector_modes,
1545
-
.destroy = drm_connector_cleanup,
1546
-
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1547
-
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1548
-
};
1549
-
1550
-
static int ast_dp501_connector_init(struct drm_device *dev, struct drm_connector *connector)
1551
-
{
1552
-
int ret;
1553
-
1554
-
ret = drm_connector_init(dev, connector, &ast_dp501_connector_funcs,
1555
-
DRM_MODE_CONNECTOR_DisplayPort);
1556
-
if (ret)
1557
-
return ret;
1558
-
1559
-
drm_connector_helper_add(connector, &ast_dp501_connector_helper_funcs);
1560
-
1561
-
connector->interlace_allowed = 0;
1562
-
connector->doublescan_allowed = 0;
1563
-
1564
-
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
1565
-
1566
-
return 0;
1567
-
}
1568
-
1569
-
static int ast_dp501_output_init(struct ast_device *ast)
1570
-
{
1571
-
struct drm_device *dev = &ast->base;
1572
-
struct drm_crtc *crtc = &ast->crtc;
1573
-
struct drm_encoder *encoder = &ast->output.dp501.encoder;
1574
-
struct drm_connector *connector = &ast->output.dp501.connector;
1575
-
int ret;
1576
-
1577
-
ret = drm_encoder_init(dev, encoder, &ast_dp501_encoder_funcs,
1578
-
DRM_MODE_ENCODER_TMDS, NULL);
1579
-
if (ret)
1580
-
return ret;
1581
-
drm_encoder_helper_add(encoder, &ast_dp501_encoder_helper_funcs);
1582
-
1583
-
encoder->possible_crtcs = drm_crtc_mask(crtc);
1584
-
1585
-
ret = ast_dp501_connector_init(dev, connector);
1586
-
if (ret)
1587
-
return ret;
1588
-
1589
-
ret = drm_connector_attach_encoder(connector, encoder);
1590
-
if (ret)
1591
-
return ret;
1592
-
1593
-
return 0;
1594
-
}
1595
-
1596
-
/*
1597
-
* ASPEED Display-Port Encoder
1598
-
*/
1599
-
1600
-
static const struct drm_encoder_funcs ast_astdp_encoder_funcs = {
1601
-
.destroy = drm_encoder_cleanup,
1602
-
};
1603
-
1604
-
static void ast_astdp_encoder_helper_atomic_mode_set(struct drm_encoder *encoder,
1605
-
struct drm_crtc_state *crtc_state,
1606
-
struct drm_connector_state *conn_state)
1607
-
{
1608
-
struct drm_crtc *crtc = crtc_state->crtc;
1609
-
struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1610
-
struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
1611
-
1612
-
ast_dp_set_mode(crtc, vbios_mode_info);
1613
-
}
1614
-
1615
-
static void ast_astdp_encoder_helper_atomic_enable(struct drm_encoder *encoder,
1616
-
struct drm_atomic_state *state)
1617
-
{
1618
-
struct drm_device *dev = encoder->dev;
1619
-
struct ast_device *ast = to_ast_device(dev);
1620
-
1621
-
ast_dp_power_on_off(dev, AST_DP_POWER_ON);
1622
-
ast_dp_link_training(ast);
1623
-
1624
-
ast_wait_for_vretrace(ast);
1625
-
ast_dp_set_on_off(dev, 1);
1626
-
}
1627
-
1628
-
static void ast_astdp_encoder_helper_atomic_disable(struct drm_encoder *encoder,
1629
-
struct drm_atomic_state *state)
1630
-
{
1631
-
struct drm_device *dev = encoder->dev;
1632
-
1633
-
ast_dp_set_on_off(dev, 0);
1634
-
ast_dp_power_on_off(dev, AST_DP_POWER_OFF);
1635
-
}
1636
-
1637
-
static const struct drm_encoder_helper_funcs ast_astdp_encoder_helper_funcs = {
1638
-
.atomic_mode_set = ast_astdp_encoder_helper_atomic_mode_set,
1639
-
.atomic_enable = ast_astdp_encoder_helper_atomic_enable,
1640
-
.atomic_disable = ast_astdp_encoder_helper_atomic_disable,
1641
-
};
1642
-
1643
-
/*
1644
-
* ASPEED Display-Port Connector
1645
-
*/
1646
-
1647
-
static int ast_astdp_connector_helper_get_modes(struct drm_connector *connector)
1648
-
{
1649
-
void *edid;
1650
-
struct drm_device *dev = connector->dev;
1651
-
struct ast_device *ast = to_ast_device(dev);
1652
-
1653
-
int succ;
1654
-
int count;
1655
-
1656
-
edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1657
-
if (!edid)
1658
-
goto err_drm_connector_update_edid_property;
1659
-
1660
-
/*
1661
-
* Protect access to I/O registers from concurrent modesetting
1662
-
* by acquiring the I/O-register lock.
1663
-
*/
1664
-
mutex_lock(&ast->modeset_lock);
1665
-
1666
-
succ = ast_astdp_read_edid(connector->dev, edid);
1667
-
if (succ < 0)
1668
-
goto err_mutex_unlock;
1669
-
1670
-
mutex_unlock(&ast->modeset_lock);
1671
-
1672
-
drm_connector_update_edid_property(connector, edid);
1673
-
count = drm_add_edid_modes(connector, edid);
1674
-
kfree(edid);
1675
-
1676
-
return count;
1677
-
1678
-
err_mutex_unlock:
1679
-
mutex_unlock(&ast->modeset_lock);
1680
-
kfree(edid);
1681
-
err_drm_connector_update_edid_property:
1682
-
drm_connector_update_edid_property(connector, NULL);
1683
-
return 0;
1684
-
}
1685
-
1686
-
static int ast_astdp_connector_helper_detect_ctx(struct drm_connector *connector,
1687
-
struct drm_modeset_acquire_ctx *ctx,
1688
-
bool force)
1689
-
{
1690
-
struct drm_device *dev = connector->dev;
1691
-
struct ast_device *ast = to_ast_device(connector->dev);
1692
-
enum drm_connector_status status = connector_status_disconnected;
1693
-
struct drm_connector_state *connector_state = connector->state;
1694
-
bool is_active = false;
1695
-
1696
-
mutex_lock(&ast->modeset_lock);
1697
-
1698
-
if (connector_state && connector_state->crtc) {
1699
-
struct drm_crtc_state *crtc_state = connector_state->crtc->state;
1700
-
1701
-
if (crtc_state && crtc_state->active)
1702
-
is_active = true;
1703
-
}
1704
-
1705
-
if (!is_active && !ast_dp_power_is_on(ast)) {
1706
-
ast_dp_power_on_off(dev, true);
1707
-
msleep(50);
1708
-
}
1709
-
1710
-
if (ast_astdp_is_connected(ast))
1711
-
status = connector_status_connected;
1712
-
1713
-
if (!is_active && status == connector_status_disconnected)
1714
-
ast_dp_power_on_off(dev, false);
1715
-
1716
-
mutex_unlock(&ast->modeset_lock);
1717
-
1718
-
return status;
1719
-
}
1720
-
1721
-
static const struct drm_connector_helper_funcs ast_astdp_connector_helper_funcs = {
1722
-
.get_modes = ast_astdp_connector_helper_get_modes,
1723
-
.detect_ctx = ast_astdp_connector_helper_detect_ctx,
1724
-
};
1725
-
1726
-
static const struct drm_connector_funcs ast_astdp_connector_funcs = {
1727
-
.reset = drm_atomic_helper_connector_reset,
1728
-
.fill_modes = drm_helper_probe_single_connector_modes,
1729
-
.destroy = drm_connector_cleanup,
1730
-
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1731
-
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1732
-
};
1733
-
1734
-
static int ast_astdp_connector_init(struct drm_device *dev, struct drm_connector *connector)
1735
-
{
1736
-
int ret;
1737
-
1738
-
ret = drm_connector_init(dev, connector, &ast_astdp_connector_funcs,
1739
-
DRM_MODE_CONNECTOR_DisplayPort);
1740
-
if (ret)
1741
-
return ret;
1742
-
1743
-
drm_connector_helper_add(connector, &ast_astdp_connector_helper_funcs);
1744
-
1745
-
connector->interlace_allowed = 0;
1746
-
connector->doublescan_allowed = 0;
1747
-
1748
-
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
1749
-
1750
-
return 0;
1751
-
}
1752
-
1753
-
static int ast_astdp_output_init(struct ast_device *ast)
1754
-
{
1755
-
struct drm_device *dev = &ast->base;
1756
-
struct drm_crtc *crtc = &ast->crtc;
1757
-
struct drm_encoder *encoder = &ast->output.astdp.encoder;
1758
-
struct drm_connector *connector = &ast->output.astdp.connector;
1759
-
int ret;
1760
-
1761
-
ret = drm_encoder_init(dev, encoder, &ast_astdp_encoder_funcs,
1762
-
DRM_MODE_ENCODER_TMDS, NULL);
1763
-
if (ret)
1764
-
return ret;
1765
-
drm_encoder_helper_add(encoder, &ast_astdp_encoder_helper_funcs);
1766
-
1767
-
encoder->possible_crtcs = drm_crtc_mask(crtc);
1768
-
1769
-
ret = ast_astdp_connector_init(dev, connector);
1770
-
if (ret)
1771
-
return ret;
1772
-
1773
-
ret = drm_connector_attach_encoder(connector, encoder);
1774
-
if (ret)
1775
-
return ret;
1776
-
1777
-
return 0;
1778
-
}
1779
-
1780
-
/*
1781
-
* BMC virtual Connector
1782
-
*/
1783
-
1784
-
static const struct drm_encoder_funcs ast_bmc_encoder_funcs = {
1785
-
.destroy = drm_encoder_cleanup,
1786
-
};
1787
-
1788
-
static int ast_bmc_connector_helper_detect_ctx(struct drm_connector *connector,
1789
-
struct drm_modeset_acquire_ctx *ctx,
1790
-
bool force)
1791
-
{
1792
-
struct ast_bmc_connector *bmc_connector = to_ast_bmc_connector(connector);
1793
-
struct drm_connector *physical_connector = bmc_connector->physical_connector;
1794
-
1795
-
/*
1796
-
* Most user-space compositors cannot handle more than one connected
1797
-
* connector per CRTC. Hence, we only mark the BMC as connected if the
1798
-
* physical connector is disconnected. If the physical connector's status
1799
-
* is connected or unknown, the BMC remains disconnected. This has no
1800
-
* effect on the output of the BMC.
1801
-
*
1802
-
* FIXME: Remove this logic once user-space compositors can handle more
1803
-
* than one connector per CRTC. The BMC should always be connected.
1804
-
*/
1805
-
1806
-
if (physical_connector && physical_connector->status == connector_status_disconnected)
1807
-
return connector_status_connected;
1808
-
1809
-
return connector_status_disconnected;
1810
-
}
1811
-
1812
-
static int ast_bmc_connector_helper_get_modes(struct drm_connector *connector)
1813
-
{
1814
-
return drm_add_modes_noedid(connector, 4096, 4096);
1815
-
}
1816
-
1817
-
static const struct drm_connector_helper_funcs ast_bmc_connector_helper_funcs = {
1818
-
.get_modes = ast_bmc_connector_helper_get_modes,
1819
-
.detect_ctx = ast_bmc_connector_helper_detect_ctx,
1820
-
};
1821
-
1822
-
static const struct drm_connector_funcs ast_bmc_connector_funcs = {
1823
-
.reset = drm_atomic_helper_connector_reset,
1824
-
.fill_modes = drm_helper_probe_single_connector_modes,
1825
-
.destroy = drm_connector_cleanup,
1826
-
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1827
-
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1828
-
};
1829
-
1830
-
static int ast_bmc_connector_init(struct drm_device *dev,
1831
-
struct ast_bmc_connector *bmc_connector,
1832
-
struct drm_connector *physical_connector)
1833
-
{
1834
-
struct drm_connector *connector = &bmc_connector->base;
1835
-
int ret;
1836
-
1837
-
ret = drm_connector_init(dev, connector, &ast_bmc_connector_funcs,
1838
-
DRM_MODE_CONNECTOR_VIRTUAL);
1839
-
if (ret)
1840
-
return ret;
1841
-
1842
-
drm_connector_helper_add(connector, &ast_bmc_connector_helper_funcs);
1843
-
1844
-
bmc_connector->physical_connector = physical_connector;
1845
-
1846
-
return 0;
1847
-
}
1848
-
1849
-
static int ast_bmc_output_init(struct ast_device *ast,
1850
-
struct drm_connector *physical_connector)
1851
-
{
1852
-
struct drm_device *dev = &ast->base;
1853
-
struct drm_crtc *crtc = &ast->crtc;
1854
-
struct drm_encoder *encoder = &ast->output.bmc.encoder;
1855
-
struct ast_bmc_connector *bmc_connector = &ast->output.bmc.bmc_connector;
1856
-
struct drm_connector *connector = &bmc_connector->base;
1857
-
int ret;
1858
-
1859
-
ret = drm_encoder_init(dev, encoder,
1860
-
&ast_bmc_encoder_funcs,
1861
-
DRM_MODE_ENCODER_VIRTUAL, "ast_bmc");
1862
-
if (ret)
1863
-
return ret;
1864
-
encoder->possible_crtcs = drm_crtc_mask(crtc);
1865
-
1866
-
ret = ast_bmc_connector_init(dev, bmc_connector, physical_connector);
1867
-
if (ret)
1868
-
return ret;
1869
-
1870
-
ret = drm_connector_attach_encoder(connector, encoder);
1871
-
if (ret)
1872
-
return ret;
1873
-
1874
-
return 0;
1875
-
}
1876
-
1877
-
/*
1878
1314
* Mode config
1879
1315
*/
1880
1316
···
1358
1928
int ast_mode_config_init(struct ast_device *ast)
1359
1929
{
1360
1930
struct drm_device *dev = &ast->base;
1361
-
struct drm_connector *physical_connector = NULL;
1362
1931
int ret;
1363
1932
1364
1933
ret = drmm_mutex_init(dev, &ast->modeset_lock);
···
1402
1973
ret = ast_vga_output_init(ast);
1403
1974
if (ret)
1404
1975
return ret;
1405
-
physical_connector = &ast->output.vga.connector;
1406
1976
}
1407
1977
if (ast->tx_chip_types & AST_TX_SIL164_BIT) {
1408
1978
ret = ast_sil164_output_init(ast);
1409
1979
if (ret)
1410
1980
return ret;
1411
-
physical_connector = &ast->output.sil164.connector;
1412
1981
}
1413
1982
if (ast->tx_chip_types & AST_TX_DP501_BIT) {
1414
1983
ret = ast_dp501_output_init(ast);
1415
1984
if (ret)
1416
1985
return ret;
1417
-
physical_connector = &ast->output.dp501.connector;
1418
1986
}
1419
1987
if (ast->tx_chip_types & AST_TX_ASTDP_BIT) {
1420
1988
ret = ast_astdp_output_init(ast);
1421
1989
if (ret)
1422
1990
return ret;
1423
-
physical_connector = &ast->output.astdp.connector;
1424
1991
}
1425
-
ret = ast_bmc_output_init(ast, physical_connector);
1426
-
if (ret)
1427
-
return ret;
1428
1992
1429
1993
drm_mode_config_reset(dev);
1430
1994
+127
drivers/gpu/drm/ast/ast_sil164.c
+127
drivers/gpu/drm/ast/ast_sil164.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
3
+
#include <drm/drm_atomic_state_helper.h>
4
+
#include <drm/drm_edid.h>
5
+
#include <drm/drm_modeset_helper_vtables.h>
6
+
#include <drm/drm_print.h>
7
+
#include <drm/drm_probe_helper.h>
8
+
9
+
#include "ast_ddc.h"
10
+
#include "ast_drv.h"
11
+
12
+
/*
13
+
* Encoder
14
+
*/
15
+
16
+
static const struct drm_encoder_funcs ast_sil164_encoder_funcs = {
17
+
.destroy = drm_encoder_cleanup,
18
+
};
19
+
20
+
/*
21
+
* Connector
22
+
*/
23
+
24
+
static int ast_sil164_connector_helper_get_modes(struct drm_connector *connector)
25
+
{
26
+
struct ast_connector *ast_connector = to_ast_connector(connector);
27
+
int count;
28
+
29
+
if (ast_connector->physical_status == connector_status_connected) {
30
+
count = drm_connector_helper_get_modes(connector);
31
+
} else {
32
+
/*
33
+
* There's no EDID data without a connected monitor. Set BMC-
34
+
* compatible modes in this case. The XGA default resolution
35
+
* should work well for all BMCs.
36
+
*/
37
+
count = drm_add_modes_noedid(connector, 4096, 4096);
38
+
if (count)
39
+
drm_set_preferred_mode(connector, 1024, 768);
40
+
}
41
+
42
+
return count;
43
+
}
44
+
45
+
static int ast_sil164_connector_helper_detect_ctx(struct drm_connector *connector,
46
+
struct drm_modeset_acquire_ctx *ctx,
47
+
bool force)
48
+
{
49
+
struct ast_connector *ast_connector = to_ast_connector(connector);
50
+
enum drm_connector_status status;
51
+
52
+
status = drm_connector_helper_detect_from_ddc(connector, ctx, force);
53
+
54
+
if (status != ast_connector->physical_status)
55
+
++connector->epoch_counter;
56
+
ast_connector->physical_status = status;
57
+
58
+
return connector_status_connected;
59
+
}
60
+
61
+
static const struct drm_connector_helper_funcs ast_sil164_connector_helper_funcs = {
62
+
.get_modes = ast_sil164_connector_helper_get_modes,
63
+
.detect_ctx = ast_sil164_connector_helper_detect_ctx,
64
+
};
65
+
66
+
static const struct drm_connector_funcs ast_sil164_connector_funcs = {
67
+
.reset = drm_atomic_helper_connector_reset,
68
+
.fill_modes = drm_helper_probe_single_connector_modes,
69
+
.destroy = drm_connector_cleanup,
70
+
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
71
+
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
72
+
};
73
+
74
+
static int ast_sil164_connector_init(struct drm_device *dev, struct drm_connector *connector)
75
+
{
76
+
struct ast_device *ast = to_ast_device(dev);
77
+
struct i2c_adapter *ddc;
78
+
int ret;
79
+
80
+
ddc = ast_ddc_create(ast);
81
+
if (IS_ERR(ddc)) {
82
+
ret = PTR_ERR(ddc);
83
+
drm_err(dev, "failed to add DDC bus for connector; ret=%d\n", ret);
84
+
return ret;
85
+
}
86
+
87
+
ret = drm_connector_init_with_ddc(dev, connector, &ast_sil164_connector_funcs,
88
+
DRM_MODE_CONNECTOR_DVII, ddc);
89
+
if (ret)
90
+
return ret;
91
+
92
+
drm_connector_helper_add(connector, &ast_sil164_connector_helper_funcs);
93
+
94
+
connector->interlace_allowed = 0;
95
+
connector->doublescan_allowed = 0;
96
+
97
+
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
98
+
99
+
return 0;
100
+
}
101
+
102
+
int ast_sil164_output_init(struct ast_device *ast)
103
+
{
104
+
struct drm_device *dev = &ast->base;
105
+
struct drm_crtc *crtc = &ast->crtc;
106
+
struct drm_encoder *encoder = &ast->output.sil164.encoder;
107
+
struct ast_connector *ast_connector = &ast->output.sil164.connector;
108
+
struct drm_connector *connector = &ast_connector->base;
109
+
int ret;
110
+
111
+
ret = drm_encoder_init(dev, encoder, &ast_sil164_encoder_funcs,
112
+
DRM_MODE_ENCODER_TMDS, NULL);
113
+
if (ret)
114
+
return ret;
115
+
encoder->possible_crtcs = drm_crtc_mask(crtc);
116
+
117
+
ret = ast_sil164_connector_init(dev, connector);
118
+
if (ret)
119
+
return ret;
120
+
ast_connector->physical_status = connector->status;
121
+
122
+
ret = drm_connector_attach_encoder(connector, encoder);
123
+
if (ret)
124
+
return ret;
125
+
126
+
return 0;
127
+
}
+127
drivers/gpu/drm/ast/ast_vga.c
+127
drivers/gpu/drm/ast/ast_vga.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
3
+
#include <drm/drm_atomic_state_helper.h>
4
+
#include <drm/drm_edid.h>
5
+
#include <drm/drm_modeset_helper_vtables.h>
6
+
#include <drm/drm_print.h>
7
+
#include <drm/drm_probe_helper.h>
8
+
9
+
#include "ast_ddc.h"
10
+
#include "ast_drv.h"
11
+
12
+
/*
13
+
* Encoder
14
+
*/
15
+
16
+
static const struct drm_encoder_funcs ast_vga_encoder_funcs = {
17
+
.destroy = drm_encoder_cleanup,
18
+
};
19
+
20
+
/*
21
+
* Connector
22
+
*/
23
+
24
+
static int ast_vga_connector_helper_get_modes(struct drm_connector *connector)
25
+
{
26
+
struct ast_connector *ast_connector = to_ast_connector(connector);
27
+
int count;
28
+
29
+
if (ast_connector->physical_status == connector_status_connected) {
30
+
count = drm_connector_helper_get_modes(connector);
31
+
} else {
32
+
/*
33
+
* There's no EDID data without a connected monitor. Set BMC-
34
+
* compatible modes in this case. The XGA default resolution
35
+
* should work well for all BMCs.
36
+
*/
37
+
count = drm_add_modes_noedid(connector, 4096, 4096);
38
+
if (count)
39
+
drm_set_preferred_mode(connector, 1024, 768);
40
+
}
41
+
42
+
return count;
43
+
}
44
+
45
+
static int ast_vga_connector_helper_detect_ctx(struct drm_connector *connector,
46
+
struct drm_modeset_acquire_ctx *ctx,
47
+
bool force)
48
+
{
49
+
struct ast_connector *ast_connector = to_ast_connector(connector);
50
+
enum drm_connector_status status;
51
+
52
+
status = drm_connector_helper_detect_from_ddc(connector, ctx, force);
53
+
54
+
if (status != ast_connector->physical_status)
55
+
++connector->epoch_counter;
56
+
ast_connector->physical_status = status;
57
+
58
+
return connector_status_connected;
59
+
}
60
+
61
+
static const struct drm_connector_helper_funcs ast_vga_connector_helper_funcs = {
62
+
.get_modes = ast_vga_connector_helper_get_modes,
63
+
.detect_ctx = ast_vga_connector_helper_detect_ctx,
64
+
};
65
+
66
+
static const struct drm_connector_funcs ast_vga_connector_funcs = {
67
+
.reset = drm_atomic_helper_connector_reset,
68
+
.fill_modes = drm_helper_probe_single_connector_modes,
69
+
.destroy = drm_connector_cleanup,
70
+
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
71
+
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
72
+
};
73
+
74
+
static int ast_vga_connector_init(struct drm_device *dev, struct drm_connector *connector)
75
+
{
76
+
struct ast_device *ast = to_ast_device(dev);
77
+
struct i2c_adapter *ddc;
78
+
int ret;
79
+
80
+
ddc = ast_ddc_create(ast);
81
+
if (IS_ERR(ddc)) {
82
+
ret = PTR_ERR(ddc);
83
+
drm_err(dev, "failed to add DDC bus for connector; ret=%d\n", ret);
84
+
return ret;
85
+
}
86
+
87
+
ret = drm_connector_init_with_ddc(dev, connector, &ast_vga_connector_funcs,
88
+
DRM_MODE_CONNECTOR_VGA, ddc);
89
+
if (ret)
90
+
return ret;
91
+
92
+
drm_connector_helper_add(connector, &ast_vga_connector_helper_funcs);
93
+
94
+
connector->interlace_allowed = 0;
95
+
connector->doublescan_allowed = 0;
96
+
97
+
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
98
+
99
+
return 0;
100
+
}
101
+
102
+
int ast_vga_output_init(struct ast_device *ast)
103
+
{
104
+
struct drm_device *dev = &ast->base;
105
+
struct drm_crtc *crtc = &ast->crtc;
106
+
struct drm_encoder *encoder = &ast->output.vga.encoder;
107
+
struct ast_connector *ast_connector = &ast->output.vga.connector;
108
+
struct drm_connector *connector = &ast_connector->base;
109
+
int ret;
110
+
111
+
ret = drm_encoder_init(dev, encoder, &ast_vga_encoder_funcs,
112
+
DRM_MODE_ENCODER_DAC, NULL);
113
+
if (ret)
114
+
return ret;
115
+
encoder->possible_crtcs = drm_crtc_mask(crtc);
116
+
117
+
ret = ast_vga_connector_init(dev, connector);
118
+
if (ret)
119
+
return ret;
120
+
ast_connector->physical_status = connector->status;
121
+
122
+
ret = drm_connector_attach_encoder(connector, encoder);
123
+
if (ret)
124
+
return ret;
125
+
126
+
return 0;
127
+
}
+6
-16
drivers/gpu/drm/bridge/analogix/anx7625.c
+6
-16
drivers/gpu/drm/bridge/analogix/anx7625.c
···
1647
1647
{
1648
1648
int num_regs;
1649
1649
1650
-
if (of_get_property(dev->of_node,
1651
-
"analogix,lane0-swing", &num_regs)) {
1652
-
if (num_regs > DP_TX_SWING_REG_CNT)
1653
-
num_regs = DP_TX_SWING_REG_CNT;
1654
-
1650
+
num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane0-swing",
1651
+
pdata->lane0_reg_data, 1, DP_TX_SWING_REG_CNT);
1652
+
if (num_regs > 0)
1655
1653
pdata->dp_lane0_swing_reg_cnt = num_regs;
1656
-
of_property_read_u8_array(dev->of_node, "analogix,lane0-swing",
1657
-
pdata->lane0_reg_data, num_regs);
1658
-
}
1659
1654
1660
-
if (of_get_property(dev->of_node,
1661
-
"analogix,lane1-swing", &num_regs)) {
1662
-
if (num_regs > DP_TX_SWING_REG_CNT)
1663
-
num_regs = DP_TX_SWING_REG_CNT;
1664
-
1655
+
num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane1-swing",
1656
+
pdata->lane1_reg_data, 1, DP_TX_SWING_REG_CNT);
1657
+
if (num_regs > 0)
1665
1658
pdata->dp_lane1_swing_reg_cnt = num_regs;
1666
-
of_property_read_u8_array(dev->of_node, "analogix,lane1-swing",
1667
-
pdata->lane1_reg_data, num_regs);
1668
-
}
1669
1659
1670
1660
return 0;
1671
1661
}
+18
-17
drivers/gpu/drm/bridge/lontium-lt8912b.c
+18
-17
drivers/gpu/drm/bridge/lontium-lt8912b.c
···
422
422
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
423
423
};
424
424
425
-
static enum drm_mode_status
426
-
lt8912_connector_mode_valid(struct drm_connector *connector,
427
-
struct drm_display_mode *mode)
428
-
{
429
-
if (mode->clock > 150000)
430
-
return MODE_CLOCK_HIGH;
431
-
432
-
if (mode->hdisplay > 1920)
433
-
return MODE_BAD_HVALUE;
434
-
435
-
if (mode->vdisplay > 1080)
436
-
return MODE_BAD_VVALUE;
437
-
438
-
return MODE_OK;
439
-
}
440
-
441
425
static int lt8912_connector_get_modes(struct drm_connector *connector)
442
426
{
443
427
const struct drm_edid *drm_edid;
···
447
463
448
464
static const struct drm_connector_helper_funcs lt8912_connector_helper_funcs = {
449
465
.get_modes = lt8912_connector_get_modes,
450
-
.mode_valid = lt8912_connector_mode_valid,
451
466
};
452
467
453
468
static void lt8912_bridge_mode_set(struct drm_bridge *bridge,
···
588
605
drm_bridge_hpd_disable(lt->hdmi_port);
589
606
}
590
607
608
+
static enum drm_mode_status
609
+
lt8912_bridge_mode_valid(struct drm_bridge *bridge,
610
+
const struct drm_display_info *info,
611
+
const struct drm_display_mode *mode)
612
+
{
613
+
if (mode->clock > 150000)
614
+
return MODE_CLOCK_HIGH;
615
+
616
+
if (mode->hdisplay > 1920)
617
+
return MODE_BAD_HVALUE;
618
+
619
+
if (mode->vdisplay > 1080)
620
+
return MODE_BAD_VVALUE;
621
+
622
+
return MODE_OK;
623
+
}
624
+
591
625
static enum drm_connector_status
592
626
lt8912_bridge_detect(struct drm_bridge *bridge)
593
627
{
···
635
635
static const struct drm_bridge_funcs lt8912_bridge_funcs = {
636
636
.attach = lt8912_bridge_attach,
637
637
.detach = lt8912_bridge_detach,
638
+
.mode_valid = lt8912_bridge_mode_valid,
638
639
.mode_set = lt8912_bridge_mode_set,
639
640
.enable = lt8912_bridge_enable,
640
641
.detect = lt8912_bridge_detect,
+4
-4
drivers/gpu/drm/bridge/nwl-dsi.c
+4
-4
drivers/gpu/drm/bridge/nwl-dsi.c
···
289
289
290
290
nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
291
291
nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
292
-
/*
293
-
* Adjusting input polarity based on the video mode results in
294
-
* a black screen so always pick active low:
295
-
*/
296
292
nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
293
+
dsi->mode.flags & DRM_MODE_FLAG_PVSYNC ?
294
+
NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH :
297
295
NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
298
296
nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
297
+
dsi->mode.flags & DRM_MODE_FLAG_PHSYNC ?
298
+
NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH :
299
299
NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
300
300
301
301
burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
+2
-2
drivers/gpu/drm/bridge/nwl-dsi.h
+2
-2
drivers/gpu/drm/bridge/nwl-dsi.h
···
30
30
#define NWL_DSI_PIXEL_FORMAT 0x20c
31
31
#define NWL_DSI_VSYNC_POLARITY 0x210
32
32
#define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0
33
-
#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1)
33
+
#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(0)
34
34
35
35
#define NWL_DSI_HSYNC_POLARITY 0x214
36
36
#define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0
37
-
#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1)
37
+
#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(0)
38
38
39
39
#define NWL_DSI_VIDEO_MODE 0x218
40
40
#define NWL_DSI_HFP 0x21c
+16
-50
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+16
-50
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
···
138
138
struct platform_device *audio;
139
139
struct platform_device *cec;
140
140
struct device *dev;
141
-
struct clk *isfr_clk;
142
-
struct clk *iahb_clk;
143
-
struct clk *cec_clk;
144
141
struct dw_hdmi_i2c *i2c;
145
142
146
143
struct hdmi_data_info hdmi_data;
···
3323
3326
struct device_node *ddc_node;
3324
3327
struct dw_hdmi_cec_data cec;
3325
3328
struct dw_hdmi *hdmi;
3329
+
struct clk *clk;
3326
3330
struct resource *iores = NULL;
3327
3331
int irq;
3328
3332
int ret;
···
3403
3405
hdmi->regm = plat_data->regm;
3404
3406
}
3405
3407
3406
-
hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
3407
-
if (IS_ERR(hdmi->isfr_clk)) {
3408
-
ret = PTR_ERR(hdmi->isfr_clk);
3408
+
clk = devm_clk_get_enabled(hdmi->dev, "isfr");
3409
+
if (IS_ERR(clk)) {
3410
+
ret = PTR_ERR(clk);
3409
3411
dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3410
3412
goto err_res;
3411
3413
}
3412
3414
3413
-
ret = clk_prepare_enable(hdmi->isfr_clk);
3414
-
if (ret) {
3415
-
dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
3415
+
clk = devm_clk_get_enabled(hdmi->dev, "iahb");
3416
+
if (IS_ERR(clk)) {
3417
+
ret = PTR_ERR(clk);
3418
+
dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3416
3419
goto err_res;
3417
3420
}
3418
3421
3419
-
hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
3420
-
if (IS_ERR(hdmi->iahb_clk)) {
3421
-
ret = PTR_ERR(hdmi->iahb_clk);
3422
-
dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3423
-
goto err_isfr;
3424
-
}
3425
-
3426
-
ret = clk_prepare_enable(hdmi->iahb_clk);
3427
-
if (ret) {
3428
-
dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
3429
-
goto err_isfr;
3430
-
}
3431
-
3432
-
hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
3433
-
if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
3434
-
hdmi->cec_clk = NULL;
3435
-
} else if (IS_ERR(hdmi->cec_clk)) {
3436
-
ret = PTR_ERR(hdmi->cec_clk);
3422
+
clk = devm_clk_get_optional_enabled(hdmi->dev, "cec");
3423
+
if (IS_ERR(clk)) {
3424
+
ret = PTR_ERR(clk);
3437
3425
if (ret != -EPROBE_DEFER)
3438
3426
dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3439
3427
ret);
3440
-
3441
-
hdmi->cec_clk = NULL;
3442
-
goto err_iahb;
3443
-
} else {
3444
-
ret = clk_prepare_enable(hdmi->cec_clk);
3445
-
if (ret) {
3446
-
dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
3447
-
ret);
3448
-
goto err_iahb;
3449
-
}
3428
+
goto err_res;
3450
3429
}
3451
3430
3452
3431
/* Product and revision IDs */
···
3437
3462
dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3438
3463
hdmi->version, prod_id0, prod_id1);
3439
3464
ret = -ENODEV;
3440
-
goto err_iahb;
3465
+
goto err_res;
3441
3466
}
3442
3467
3443
3468
ret = dw_hdmi_detect_phy(hdmi);
3444
3469
if (ret < 0)
3445
-
goto err_iahb;
3470
+
goto err_res;
3446
3471
3447
3472
dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3448
3473
hdmi->version >> 12, hdmi->version & 0xfff,
···
3454
3479
irq = platform_get_irq(pdev, 0);
3455
3480
if (irq < 0) {
3456
3481
ret = irq;
3457
-
goto err_iahb;
3482
+
goto err_res;
3458
3483
}
3459
3484
3460
3485
ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
3461
3486
dw_hdmi_irq, IRQF_SHARED,
3462
3487
dev_name(dev), hdmi);
3463
3488
if (ret)
3464
-
goto err_iahb;
3489
+
goto err_res;
3465
3490
3466
3491
/*
3467
3492
* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
···
3578
3603
3579
3604
return hdmi;
3580
3605
3581
-
err_iahb:
3582
-
clk_disable_unprepare(hdmi->iahb_clk);
3583
-
clk_disable_unprepare(hdmi->cec_clk);
3584
-
err_isfr:
3585
-
clk_disable_unprepare(hdmi->isfr_clk);
3586
3606
err_res:
3587
3607
i2c_put_adapter(hdmi->ddc);
3588
3608
···
3596
3626
3597
3627
/* Disable all interrupts */
3598
3628
hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3599
-
3600
-
clk_disable_unprepare(hdmi->iahb_clk);
3601
-
clk_disable_unprepare(hdmi->isfr_clk);
3602
-
clk_disable_unprepare(hdmi->cec_clk);
3603
3629
3604
3630
if (hdmi->i2c)
3605
3631
i2c_del_adapter(&hdmi->i2c->adap);
+1
-1
drivers/gpu/drm/drm_edid.c
+1
-1
drivers/gpu/drm/drm_edid.c
+31
drivers/gpu/drm/drm_mipi_dsi.c
+31
drivers/gpu/drm/drm_mipi_dsi.c
···
1339
1339
* @dsi: DSI peripheral device
1340
1340
* @scanline: scanline to use as trigger
1341
1341
*
1342
+
* This function is deprecated. Use mipi_dsi_dcs_set_tear_scanline_multi()
1343
+
* instead.
1344
+
*
1342
1345
* Return: 0 on success or a negative error code on failure
1343
1346
*/
1344
1347
int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline)
···
1835
1832
}
1836
1833
}
1837
1834
EXPORT_SYMBOL(mipi_dsi_dcs_set_page_address_multi);
1835
+
1836
+
/**
1837
+
* mipi_dsi_dcs_set_tear_scanline_multi() - set the scanline to use as trigger for
1838
+
* the Tearing Effect output signal of the display module
1839
+
* @ctx: Context for multiple DSI transactions
1840
+
* @scanline: scanline to use as trigger
1841
+
*
1842
+
* Like mipi_dsi_dcs_set_tear_scanline() but deals with errors in a way that
1843
+
* makes it convenient to make several calls in a row.
1844
+
*/
1845
+
void mipi_dsi_dcs_set_tear_scanline_multi(struct mipi_dsi_multi_context *ctx,
1846
+
u16 scanline)
1847
+
{
1848
+
struct mipi_dsi_device *dsi = ctx->dsi;
1849
+
struct device *dev = &dsi->dev;
1850
+
int ret;
1851
+
1852
+
if (ctx->accum_err)
1853
+
return;
1854
+
1855
+
ret = mipi_dsi_dcs_set_tear_scanline(dsi, scanline);
1856
+
if (ret < 0) {
1857
+
ctx->accum_err = ret;
1858
+
dev_err(dev, "Failed to set tear scanline: %d\n",
1859
+
ctx->accum_err);
1860
+
}
1861
+
}
1862
+
EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_scanline_multi);
1838
1863
1839
1864
static int mipi_dsi_drv_probe(struct device *dev)
1840
1865
{
+1
-1
drivers/gpu/drm/i915/display/intel_dp.c
+1
-1
drivers/gpu/drm/i915/display/intel_dp.c
+1
-1
drivers/gpu/drm/i915/display/intel_opregion.c
+1
-1
drivers/gpu/drm/i915/display/intel_opregion.c
···
1117
1117
1118
1118
/* Validity corresponds to number of 128-byte blocks */
1119
1119
len = (opregion->asle_ext->phed & ASLE_PHED_EDID_VALID_MASK) * 128;
1120
-
if (!len || !memchr_inv(edid, 0, len))
1120
+
if (!len || mem_is_zero(edid, len))
1121
1121
return NULL;
1122
1122
1123
1123
drm_edid = drm_edid_alloc(edid, len);
+1
-1
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+1
-1
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+1
-1
drivers/gpu/drm/imagination/pvr_device.h
+1
-1
drivers/gpu/drm/imagination/pvr_device.h
+2
-1
drivers/gpu/drm/panel/Kconfig
+2
-1
drivers/gpu/drm/panel/Kconfig
···
784
784
config DRM_PANEL_SITRONIX_ST7701
785
785
tristate "Sitronix ST7701 panel driver"
786
786
depends on OF
787
-
depends on DRM_MIPI_DSI
787
+
depends on SPI || DRM_MIPI_DSI
788
+
select DRM_MIPI_DBI if SPI
788
789
depends on BACKLIGHT_CLASS_DEVICE
789
790
help
790
791
Say Y here if you want to enable support for the Sitronix
+7
-7
drivers/gpu/drm/panel/panel-ilitek-ili9341.c
+7
-7
drivers/gpu/drm/panel/panel-ilitek-ili9341.c
···
121
121
const struct drm_display_mode mode;
122
122
/* ca: TODO: need comments for this register */
123
123
u8 ca[ILI9341_CA_LEN];
124
-
/* power_b: TODO: need comments for this register */
124
+
/* power_b: Power control B (CFh) */
125
125
u8 power_b[ILI9341_POWER_B_LEN];
126
-
/* power_seq: TODO: need comments for this register */
126
+
/* power_seq: Power on sequence control (EDh) */
127
127
u8 power_seq[ILI9341_POWER_SEQ_LEN];
128
-
/* dtca: TODO: need comments for this register */
128
+
/* dtca: Driver timing control A (E8h) */
129
129
u8 dtca[ILI9341_DTCA_LEN];
130
-
/* dtcb: TODO: need comments for this register */
130
+
/* dtcb: Driver timing control B (EAh) */
131
131
u8 dtcb[ILI9341_DTCB_LEN];
132
-
/* power_a: TODO: need comments for this register */
132
+
/* power_a: Power control A (CBh) */
133
133
u8 power_a[ILI9341_POWER_A_LEN];
134
134
/* frc: Frame Rate Control (In Normal Mode/Full Colors) (B1h) */
135
135
u8 frc[ILI9341_FRC_LEN];
136
-
/* prc: TODO: need comments for this register */
136
+
/* prc: Pump ratio control (F7h) */
137
137
u8 prc;
138
138
/* dfc_1: B6h DISCTRL (Display Function Control) */
139
139
u8 dfc_1[ILI9341_DFC_1_LEN];
···
147
147
u8 vcom_2;
148
148
/* address_mode: Memory Access Control (36h) */
149
149
u8 address_mode;
150
-
/* g3amma_en: TODO: need comments for this register */
150
+
/* g3amma_en: Enable 3G (F2h) */
151
151
u8 g3amma_en;
152
152
/* rgb_interface: RGB Interface Signal Control (B0h) */
153
153
u8 rgb_interface;
+71
-66
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+71
-66
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
···
31
31
bool reset_before_power_off_vcioo;
32
32
unsigned int vcioo_to_lp11_delay_ms;
33
33
unsigned int lp11_to_reset_delay_ms;
34
-
unsigned int exit_sleep_to_display_on_delay_ms;
35
-
unsigned int display_on_delay_ms;
36
34
unsigned int backlight_off_to_display_off_delay_ms;
37
35
unsigned int display_off_to_enter_sleep_delay_ms;
38
36
unsigned int enter_sleep_to_reset_down_delay_ms;
···
62
64
static inline struct jadard *panel_to_jadard(struct drm_panel *panel)
63
65
{
64
66
return container_of(panel, struct jadard, panel);
65
-
}
66
-
67
-
static int jadard_enable(struct drm_panel *panel)
68
-
{
69
-
struct jadard *jadard = panel_to_jadard(panel);
70
-
struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
71
-
72
-
msleep(120);
73
-
74
-
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
75
-
76
-
if (jadard->desc->exit_sleep_to_display_on_delay_ms)
77
-
mipi_dsi_msleep(&dsi_ctx, jadard->desc->exit_sleep_to_display_on_delay_ms);
78
-
79
-
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
80
-
81
-
if (jadard->desc->display_on_delay_ms)
82
-
mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_on_delay_ms);
83
-
84
-
return dsi_ctx.accum_err;
85
67
}
86
68
87
69
static int jadard_disable(struct drm_panel *panel)
···
180
202
.disable = jadard_disable,
181
203
.unprepare = jadard_unprepare,
182
204
.prepare = jadard_prepare,
183
-
.enable = jadard_enable,
184
205
.get_modes = jadard_get_modes,
185
206
.get_orientation = jadard_panel_get_orientation,
186
207
};
···
358
381
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);
359
382
360
383
jd9365da_switch_page(&dsi_ctx, 0x00);
384
+
385
+
mipi_dsi_msleep(&dsi_ctx, 120);
386
+
387
+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
388
+
389
+
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
361
390
362
391
return dsi_ctx.accum_err;
363
392
};
···
591
608
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02);
592
609
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C);
593
610
611
+
mipi_dsi_msleep(&dsi_ctx, 120);
612
+
613
+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
614
+
615
+
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
616
+
594
617
return dsi_ctx.accum_err;
595
618
};
596
619
···
820
831
821
832
jd9365da_switch_page(&dsi_ctx, 0x00);
822
833
834
+
mipi_dsi_msleep(&dsi_ctx, 120);
835
+
836
+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
837
+
838
+
mipi_dsi_msleep(&dsi_ctx, 120);
839
+
840
+
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
841
+
842
+
mipi_dsi_msleep(&dsi_ctx, 20);
843
+
823
844
return dsi_ctx.accum_err;
824
845
};
825
846
···
858
859
.reset_before_power_off_vcioo = true,
859
860
.vcioo_to_lp11_delay_ms = 5,
860
861
.lp11_to_reset_delay_ms = 10,
861
-
.exit_sleep_to_display_on_delay_ms = 120,
862
-
.display_on_delay_ms = 20,
863
862
.backlight_off_to_display_off_delay_ms = 100,
864
863
.display_off_to_enter_sleep_delay_ms = 50,
865
864
.enter_sleep_to_reset_down_delay_ms = 100,
···
873
876
jd9365da_switch_page(&dsi_ctx, 0x01);
874
877
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
875
878
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
876
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf);
877
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
879
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd7);
880
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);
878
881
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
879
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf);
880
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
882
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd7);
883
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);
881
884
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x70);
882
885
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x2d);
883
886
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x2d);
884
887
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x7e);
885
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
888
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfd);
886
889
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
887
890
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28);
888
891
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
889
892
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
890
893
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12);
891
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);
894
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e);
892
895
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
893
896
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
894
897
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);
···
899
902
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
900
903
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
901
904
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
902
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x8e);
905
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a);
903
906
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x09);
904
907
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
905
908
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e);
906
909
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);
907
910
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15);
908
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
909
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x69);
910
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x59);
911
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4e);
912
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4c);
913
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x40);
914
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x45);
915
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x30);
916
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x4a);
917
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x49);
918
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x4a);
919
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x68);
920
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x57);
921
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5b);
922
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4e);
923
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x49);
911
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x73);
912
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);
913
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);
914
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x38);
915
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x36);
916
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x28);
917
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2f);
918
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x19);
919
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x32);
920
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x31);
921
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x31);
922
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x4f);
923
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x3e);
924
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x47);
925
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x36);
926
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x31);
924
927
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x24);
925
928
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x12);
926
929
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
927
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
928
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x69);
929
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x59);
930
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4e);
931
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4c);
932
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x40);
933
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x45);
934
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x30);
935
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x4a);
936
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x49);
937
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x4a);
938
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x68);
939
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x57);
940
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5b);
941
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4e);
942
-
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x49);
930
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x73);
931
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);
932
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);
933
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x38);
934
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x36);
935
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x28);
936
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2f);
937
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x19);
938
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x32);
939
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x31);
940
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x31);
941
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x4f);
942
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x3e);
943
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x47);
944
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x36);
945
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x31);
943
946
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x24);
944
947
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x12);
945
948
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02);
···
1071
1074
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);
1072
1075
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x06);
1073
1076
1077
+
mipi_dsi_msleep(&dsi_ctx, 120);
1078
+
1079
+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
1080
+
1081
+
mipi_dsi_msleep(&dsi_ctx, 120);
1082
+
1083
+
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
1084
+
1085
+
mipi_dsi_msleep(&dsi_ctx, 20);
1086
+
1074
1087
return dsi_ctx.accum_err;
1075
1088
};
1076
1089
···
1109
1102
.reset_before_power_off_vcioo = true,
1110
1103
.vcioo_to_lp11_delay_ms = 5,
1111
1104
.lp11_to_reset_delay_ms = 10,
1112
-
.exit_sleep_to_display_on_delay_ms = 120,
1113
-
.display_on_delay_ms = 20,
1114
1105
.backlight_off_to_display_off_delay_ms = 100,
1115
1106
.display_off_to_enter_sleep_delay_ms = 50,
1116
1107
.enter_sleep_to_reset_down_delay_ms = 100,
+47
-100
drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
+47
-100
drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
···
41
41
static int jdi_fhd_r63452_on(struct jdi_fhd_r63452 *ctx)
42
42
{
43
43
struct mipi_dsi_device *dsi = ctx->dsi;
44
-
struct device *dev = &dsi->dev;
45
-
int ret;
44
+
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
46
45
47
46
dsi->mode_flags |= MIPI_DSI_MODE_LPM;
48
47
49
-
mipi_dsi_generic_write_seq(dsi, 0xb0, 0x00);
50
-
mipi_dsi_generic_write_seq(dsi, 0xd6, 0x01);
51
-
mipi_dsi_generic_write_seq(dsi, 0xec,
52
-
0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b,
53
-
0x13, 0x15, 0x68, 0x0b, 0xb5);
54
-
mipi_dsi_generic_write_seq(dsi, 0xb0, 0x03);
48
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00);
49
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x01);
50
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec,
51
+
0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b,
52
+
0x13, 0x15, 0x68, 0x0b, 0xb5);
53
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03);
55
54
56
-
ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
57
-
if (ret < 0) {
58
-
dev_err(dev, "Failed to set tear on: %d\n", ret);
59
-
return ret;
60
-
}
55
+
mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
61
56
62
-
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
57
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
63
58
64
-
ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x77);
65
-
if (ret < 0) {
66
-
dev_err(dev, "Failed to set pixel format: %d\n", ret);
67
-
return ret;
68
-
}
59
+
mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77);
60
+
mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 0x0437);
61
+
mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x077f);
62
+
mipi_dsi_dcs_set_tear_scanline_multi(&dsi_ctx, 0x0000);
63
+
mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ff);
69
64
70
-
ret = mipi_dsi_dcs_set_column_address(dsi, 0x0000, 0x0437);
71
-
if (ret < 0) {
72
-
dev_err(dev, "Failed to set column address: %d\n", ret);
73
-
return ret;
74
-
}
65
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
66
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
67
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00);
68
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x00);
75
69
76
-
ret = mipi_dsi_dcs_set_page_address(dsi, 0x0000, 0x077f);
77
-
if (ret < 0) {
78
-
dev_err(dev, "Failed to set page address: %d\n", ret);
79
-
return ret;
80
-
}
70
+
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
71
+
mipi_dsi_msleep(&dsi_ctx, 20);
72
+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
73
+
mipi_dsi_msleep(&dsi_ctx, 80);
81
74
82
-
ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x0000);
83
-
if (ret < 0) {
84
-
dev_err(dev, "Failed to set tear scanline: %d\n", ret);
85
-
return ret;
86
-
}
75
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x04);
76
+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x00);
77
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x11);
78
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03);
87
79
88
-
ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x00ff);
89
-
if (ret < 0) {
90
-
dev_err(dev, "Failed to set display brightness: %d\n", ret);
91
-
return ret;
92
-
}
93
-
94
-
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
95
-
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
96
-
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00);
97
-
mipi_dsi_dcs_write_seq(dsi, 0x84, 0x00);
98
-
99
-
ret = mipi_dsi_dcs_set_display_on(dsi);
100
-
if (ret < 0) {
101
-
dev_err(dev, "Failed to set display on: %d\n", ret);
102
-
return ret;
103
-
}
104
-
msleep(20);
105
-
106
-
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
107
-
if (ret < 0) {
108
-
dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
109
-
return ret;
110
-
}
111
-
msleep(80);
112
-
113
-
mipi_dsi_generic_write_seq(dsi, 0xb0, 0x04);
114
-
mipi_dsi_dcs_write_seq(dsi, 0x84, 0x00);
115
-
mipi_dsi_generic_write_seq(dsi, 0xc8, 0x11);
116
-
mipi_dsi_generic_write_seq(dsi, 0xb0, 0x03);
117
-
118
-
return 0;
80
+
return dsi_ctx.accum_err;
119
81
}
120
82
121
-
static int jdi_fhd_r63452_off(struct jdi_fhd_r63452 *ctx)
83
+
static void jdi_fhd_r63452_off(struct jdi_fhd_r63452 *ctx)
122
84
{
123
85
struct mipi_dsi_device *dsi = ctx->dsi;
124
-
struct device *dev = &dsi->dev;
125
-
int ret;
86
+
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
126
87
127
88
dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
128
89
129
-
mipi_dsi_generic_write_seq(dsi, 0xb0, 0x00);
130
-
mipi_dsi_generic_write_seq(dsi, 0xd6, 0x01);
131
-
mipi_dsi_generic_write_seq(dsi, 0xec,
132
-
0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b,
133
-
0x13, 0x15, 0x68, 0x0b, 0x95);
134
-
mipi_dsi_generic_write_seq(dsi, 0xb0, 0x03);
90
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00);
91
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x01);
92
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec,
93
+
0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b,
94
+
0x13, 0x15, 0x68, 0x0b, 0x95);
95
+
mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03);
135
96
136
-
ret = mipi_dsi_dcs_set_display_off(dsi);
137
-
if (ret < 0) {
138
-
dev_err(dev, "Failed to set display off: %d\n", ret);
139
-
return ret;
140
-
}
141
-
usleep_range(2000, 3000);
142
-
143
-
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
144
-
if (ret < 0) {
145
-
dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
146
-
return ret;
147
-
}
148
-
msleep(120);
149
-
150
-
return 0;
97
+
mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
98
+
mipi_dsi_usleep_range(&dsi_ctx, 2000, 3000);
99
+
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
100
+
mipi_dsi_msleep(&dsi_ctx, 120);
151
101
}
152
102
153
103
static int jdi_fhd_r63452_prepare(struct drm_panel *panel)
154
104
{
155
105
struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
156
-
struct device *dev = &ctx->dsi->dev;
157
106
int ret;
158
107
159
108
jdi_fhd_r63452_reset(ctx);
160
109
161
110
ret = jdi_fhd_r63452_on(ctx);
162
-
if (ret < 0) {
163
-
dev_err(dev, "Failed to initialize panel: %d\n", ret);
111
+
if (ret < 0)
164
112
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
165
-
return ret;
166
-
}
167
113
168
-
return 0;
114
+
return ret;
169
115
}
170
116
171
117
static int jdi_fhd_r63452_unprepare(struct drm_panel *panel)
172
118
{
173
119
struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
174
-
struct device *dev = &ctx->dsi->dev;
175
-
int ret;
176
120
177
-
ret = jdi_fhd_r63452_off(ctx);
178
-
if (ret < 0)
179
-
dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
121
+
/*
122
+
* NOTE: We don't return an error here as while the panel won't have
123
+
* been cleanly turned off at least we've asserted the reset signal
124
+
* so it should be safe to power it back on again later
125
+
*/
126
+
jdi_fhd_r63452_off(ctx);
180
127
181
128
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
182
129
+27
-52
drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c
+27
-52
drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c
···
23
23
24
24
/* Manufacturer specific Commands send via DSI */
25
25
#define MANTIX_CMD_OTP_STOP_RELOAD_MIPI 0x41
26
-
#define MANTIX_CMD_INT_CANCEL 0x4C
26
+
#define MANTIX_CMD_INT_CANCEL 0x4c
27
27
#define MANTIX_CMD_SPI_FINISH 0x90
28
28
29
29
struct mantix {
···
45
45
return container_of(panel, struct mantix, panel);
46
46
}
47
47
48
-
static int mantix_init_sequence(struct mantix *ctx)
48
+
static void mantix_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
49
49
{
50
-
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
51
-
struct device *dev = ctx->dev;
52
-
53
50
/*
54
51
* Init sequence was supplied by the panel vendor.
55
52
*/
56
-
mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5A);
53
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a);
57
54
58
-
mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_INT_CANCEL, 0x03);
59
-
mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5A, 0x03);
60
-
mipi_dsi_generic_write_seq(dsi, 0x80, 0xA9, 0x00);
55
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_INT_CANCEL, 0x03);
56
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a, 0x03);
57
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x80, 0xa9, 0x00);
61
58
62
-
mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5A, 0x09);
63
-
mipi_dsi_generic_write_seq(dsi, 0x80, 0x64, 0x00, 0x64, 0x00, 0x00);
64
-
msleep(20);
59
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a, 0x09);
60
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x80, 0x64, 0x00, 0x64, 0x00, 0x00);
61
+
mipi_dsi_msleep(dsi_ctx, 20);
65
62
66
-
mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_SPI_FINISH, 0xA5);
67
-
mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x00, 0x2F);
68
-
msleep(20);
69
-
70
-
dev_dbg(dev, "Panel init sequence done\n");
71
-
return 0;
63
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_SPI_FINISH, 0xa5);
64
+
mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x00, 0x2f);
65
+
mipi_dsi_msleep(dsi_ctx, 20);
72
66
}
73
67
74
68
static int mantix_enable(struct drm_panel *panel)
75
69
{
76
70
struct mantix *ctx = panel_to_mantix(panel);
77
-
struct device *dev = ctx->dev;
78
-
struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
79
-
int ret;
71
+
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
72
+
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
80
73
81
-
ret = mantix_init_sequence(ctx);
82
-
if (ret < 0) {
83
-
dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
84
-
return ret;
85
-
}
74
+
mantix_init_sequence(&dsi_ctx);
75
+
if (!dsi_ctx.accum_err)
76
+
dev_dbg(ctx->dev, "Panel init sequence done\n");
86
77
87
-
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
88
-
if (ret < 0) {
89
-
dev_err(dev, "Failed to exit sleep mode\n");
90
-
return ret;
91
-
}
92
-
msleep(20);
78
+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
79
+
mipi_dsi_msleep(&dsi_ctx, 20);
93
80
94
-
ret = mipi_dsi_dcs_set_display_on(dsi);
95
-
if (ret)
96
-
return ret;
97
-
usleep_range(10000, 12000);
81
+
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
82
+
mipi_dsi_usleep_range(&dsi_ctx, 10000, 12000);
98
83
99
-
ret = mipi_dsi_turn_on_peripheral(dsi);
100
-
if (ret < 0) {
101
-
dev_err(dev, "Failed to turn on peripheral\n");
102
-
return ret;
103
-
}
84
+
mipi_dsi_turn_on_peripheral_multi(&dsi_ctx);
104
85
105
-
return 0;
86
+
return dsi_ctx.accum_err;
106
87
}
107
88
108
89
static int mantix_disable(struct drm_panel *panel)
109
90
{
110
91
struct mantix *ctx = panel_to_mantix(panel);
111
92
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
112
-
int ret;
93
+
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
113
94
114
-
ret = mipi_dsi_dcs_set_display_off(dsi);
115
-
if (ret < 0)
116
-
dev_err(ctx->dev, "Failed to turn off the display: %d\n", ret);
95
+
mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
96
+
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
117
97
118
-
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
119
-
if (ret < 0)
120
-
dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret);
121
-
122
-
123
-
return 0;
98
+
return dsi_ctx.accum_err;
124
99
}
125
100
126
101
static int mantix_unprepare(struct drm_panel *panel)
+71
drivers/gpu/drm/panel/panel-simple.c
+71
drivers/gpu/drm/panel/panel-simple.c
···
2527
2527
.connector_type = DRM_MODE_CONNECTOR_LVDS,
2528
2528
};
2529
2529
2530
+
static const struct display_timing innolux_g070ace_lh3_timing = {
2531
+
.pixelclock = { 25200000, 25400000, 35700000 },
2532
+
.hactive = { 800, 800, 800 },
2533
+
.hfront_porch = { 30, 32, 87 },
2534
+
.hback_porch = { 29, 31, 86 },
2535
+
.hsync_len = { 1, 1, 1 },
2536
+
.vactive = { 480, 480, 480 },
2537
+
.vfront_porch = { 4, 5, 65 },
2538
+
.vback_porch = { 3, 4, 65 },
2539
+
.vsync_len = { 1, 1, 1 },
2540
+
.flags = DISPLAY_FLAGS_DE_HIGH,
2541
+
};
2542
+
2543
+
static const struct panel_desc innolux_g070ace_lh3 = {
2544
+
.timings = &innolux_g070ace_lh3_timing,
2545
+
.num_timings = 1,
2546
+
.bpc = 8,
2547
+
.size = {
2548
+
.width = 152,
2549
+
.height = 91,
2550
+
},
2551
+
.delay = {
2552
+
.prepare = 10,
2553
+
.enable = 450,
2554
+
.disable = 200,
2555
+
.unprepare = 510,
2556
+
},
2557
+
.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2558
+
.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2559
+
.connector_type = DRM_MODE_CONNECTOR_LVDS,
2560
+
};
2561
+
2530
2562
static const struct drm_display_mode innolux_g070y2_t02_mode = {
2531
2563
.clock = 33333,
2532
2564
.hdisplay = 800,
···
3516
3484
.height = 54,
3517
3485
},
3518
3486
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3487
+
};
3488
+
3489
+
static const struct display_timing ontat_kd50g21_40nt_a1_timing = {
3490
+
.pixelclock = { 30000000, 30000000, 50000000 },
3491
+
.hactive = { 800, 800, 800 },
3492
+
.hfront_porch = { 1, 40, 255 },
3493
+
.hback_porch = { 1, 40, 87 },
3494
+
.hsync_len = { 1, 48, 87 },
3495
+
.vactive = { 480, 480, 480 },
3496
+
.vfront_porch = { 1, 13, 255 },
3497
+
.vback_porch = { 1, 29, 29 },
3498
+
.vsync_len = { 3, 3, 31 },
3499
+
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3500
+
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3501
+
};
3502
+
3503
+
static const struct panel_desc ontat_kd50g21_40nt_a1 = {
3504
+
.timings = &ontat_kd50g21_40nt_a1_timing,
3505
+
.num_timings = 1,
3506
+
.bpc = 8,
3507
+
.size = {
3508
+
.width = 108,
3509
+
.height = 65,
3510
+
},
3511
+
.delay = {
3512
+
.prepare = 147, /* 5 VSDs */
3513
+
.enable = 147, /* 5 VSDs */
3514
+
.disable = 88, /* 3 VSDs */
3515
+
.unprepare = 117, /* 4 VSDs */
3516
+
},
3517
+
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3518
+
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3519
+
.connector_type = DRM_MODE_CONNECTOR_DPI,
3519
3520
};
3520
3521
3521
3522
/*
···
4800
4735
.compatible = "innolux,g070ace-l01",
4801
4736
.data = &innolux_g070ace_l01,
4802
4737
}, {
4738
+
.compatible = "innolux,g070ace-lh3",
4739
+
.data = &innolux_g070ace_lh3,
4740
+
}, {
4803
4741
.compatible = "innolux,g070y2-l01",
4804
4742
.data = &innolux_g070y2_l01,
4805
4743
}, {
···
4913
4845
}, {
4914
4846
.compatible = "olimex,lcd-olinuxino-43-ts",
4915
4847
.data = &olimex_lcd_olinuxino_43ts,
4848
+
}, {
4849
+
.compatible = "ontat,kd50g21-40nt-a1",
4850
+
.data = &ontat_kd50g21_40nt_a1,
4916
4851
}, {
4917
4852
.compatible = "ontat,yx700wv03",
4918
4853
.data = &ontat_yx700wv03,
+668
-406
drivers/gpu/drm/panel/panel-sitronix-st7701.c
+668
-406
drivers/gpu/drm/panel/panel-sitronix-st7701.c
···
4
4
* Author: Jagan Teki <jagan@amarulasolutions.com>
5
5
*/
6
6
7
+
#include <drm/drm_mipi_dbi.h>
7
8
#include <drm/drm_mipi_dsi.h>
8
9
#include <drm/drm_modes.h>
9
10
#include <drm/drm_panel.h>
···
15
14
#include <linux/module.h>
16
15
#include <linux/of.h>
17
16
#include <linux/regulator/consumer.h>
17
+
#include <linux/spi/spi.h>
18
18
19
19
#include <video/mipi_display.h>
20
20
21
21
/* Command2 BKx selection command */
22
-
#define DSI_CMD2BKX_SEL 0xFF
23
-
#define DSI_CMD1 0
24
-
#define DSI_CMD2 BIT(4)
25
-
#define DSI_CMD2BK_MASK GENMASK(3, 0)
22
+
#define ST7701_CMD2BKX_SEL 0xFF
23
+
#define ST7701_CMD1 0
24
+
#define ST7701_CMD2 BIT(4)
25
+
#define ST7701_CMD2BK_MASK GENMASK(3, 0)
26
26
27
27
/* Command2, BK0 commands */
28
-
#define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
29
-
#define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
30
-
#define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
31
-
#define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
32
-
#define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
28
+
#define ST7701_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
29
+
#define ST7701_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
30
+
#define ST7701_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
31
+
#define ST7701_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
32
+
#define ST7701_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
33
33
34
34
/* Command2, BK1 commands */
35
-
#define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
36
-
#define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
37
-
#define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
38
-
#define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
39
-
#define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
40
-
#define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
41
-
#define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
42
-
#define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
43
-
#define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
44
-
#define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
35
+
#define ST7701_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
36
+
#define ST7701_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
37
+
#define ST7701_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
38
+
#define ST7701_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
39
+
#define ST7701_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
40
+
#define ST7701_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
41
+
#define ST7701_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
42
+
#define ST7701_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
43
+
#define ST7701_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
44
+
#define ST7701_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
45
45
46
46
/* Command2, BK0 bytes */
47
-
#define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6)
48
-
#define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)
49
-
#define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)
50
-
#define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)
51
-
#define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)
52
-
#define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)
53
-
#define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)
54
-
#define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)
55
-
#define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0)
56
-
#define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0)
57
-
#define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0)
58
-
#define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0)
59
-
#define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0)
60
-
#define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0)
61
-
#define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0)
62
-
#define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0)
63
-
#define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0)
64
-
#define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)
65
-
#define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7)
66
-
#define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
67
-
#define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)
68
-
#define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)
69
-
#define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4)
70
-
#define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)
71
-
#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
47
+
#define ST7701_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6)
48
+
#define ST7701_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)
49
+
#define ST7701_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)
50
+
#define ST7701_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)
51
+
#define ST7701_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)
52
+
#define ST7701_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)
53
+
#define ST7701_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)
54
+
#define ST7701_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)
55
+
#define ST7701_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0)
56
+
#define ST7701_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0)
57
+
#define ST7701_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0)
58
+
#define ST7701_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0)
59
+
#define ST7701_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0)
60
+
#define ST7701_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0)
61
+
#define ST7701_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0)
62
+
#define ST7701_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0)
63
+
#define ST7701_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0)
64
+
#define ST7701_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)
65
+
#define ST7701_CMD2_BK0_LNESET_LDE_EN BIT(7)
66
+
#define ST7701_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
67
+
#define ST7701_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)
68
+
#define ST7701_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)
69
+
#define ST7701_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4)
70
+
#define ST7701_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)
71
+
#define ST7701_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
72
72
73
73
/* Command2, BK1 bytes */
74
-
#define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0)
75
-
#define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0)
76
-
#define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0)
77
-
#define DSI_CMD2_BK1_TESTCMD_VAL BIT(7)
78
-
#define DSI_CMD2_BK1_VGLS_ONES BIT(6)
79
-
#define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0)
80
-
#define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6)
81
-
#define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2)
82
-
#define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0)
83
-
#define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4)
84
-
#define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0)
85
-
#define DSI_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4)
86
-
#define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)
87
-
#define DSI_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4)
88
-
#define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)
89
-
#define DSI_CMD2_BK1_MIPISET1_ONES BIT(7)
90
-
#define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3)
74
+
#define ST7701_CMD2_BK1_VRHA_MASK GENMASK(7, 0)
75
+
#define ST7701_CMD2_BK1_VCOM_MASK GENMASK(7, 0)
76
+
#define ST7701_CMD2_BK1_VGHSS_MASK GENMASK(3, 0)
77
+
#define ST7701_CMD2_BK1_TESTCMD_VAL BIT(7)
78
+
#define ST7701_CMD2_BK1_VGLS_ONES BIT(6)
79
+
#define ST7701_CMD2_BK1_VGLS_MASK GENMASK(3, 0)
80
+
#define ST7701_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6)
81
+
#define ST7701_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2)
82
+
#define ST7701_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0)
83
+
#define ST7701_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4)
84
+
#define ST7701_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0)
85
+
#define ST7701_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4)
86
+
#define ST7701_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)
87
+
#define ST7701_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4)
88
+
#define ST7701_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)
89
+
#define ST7701_CMD2_BK1_MIPISET1_ONES BIT(7)
90
+
#define ST7701_CMD2_BK1_MIPISET1_EOT_EN BIT(3)
91
91
92
92
#define CFIELD_PREP(_mask, _val) \
93
93
(((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask))
···
132
130
struct st7701 {
133
131
struct drm_panel panel;
134
132
struct mipi_dsi_device *dsi;
133
+
struct mipi_dbi dbi;
135
134
const struct st7701_panel_desc *desc;
136
135
137
136
struct regulator_bulk_data supplies[2];
138
137
struct gpio_desc *reset;
139
138
unsigned int sleep_delay;
140
139
enum drm_panel_orientation orientation;
140
+
141
+
int (*write_command)(struct st7701 *st7701, u8 cmd, const u8 *seq,
142
+
size_t len);
141
143
};
142
144
143
145
static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
···
149
143
return container_of(panel, struct st7701, panel);
150
144
}
151
145
152
-
static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq,
153
-
size_t len)
146
+
static int st7701_dsi_write(struct st7701 *st7701, u8 cmd, const u8 *seq,
147
+
size_t len)
154
148
{
155
-
return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len);
149
+
return mipi_dsi_dcs_write(st7701->dsi, cmd, seq, len);
156
150
}
157
151
158
-
#define ST7701_DSI(st7701, seq...) \
159
-
{ \
160
-
const u8 d[] = { seq }; \
161
-
st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \
152
+
static int st7701_dbi_write(struct st7701 *st7701, u8 cmd, const u8 *seq,
153
+
size_t len)
154
+
{
155
+
return mipi_dbi_command_stackbuf(&st7701->dbi, cmd, seq, len);
156
+
}
157
+
158
+
#define ST7701_WRITE(st7701, cmd, seq...) \
159
+
{ \
160
+
const u8 d[] = { seq }; \
161
+
st7701->write_command(st7701, cmd, d, ARRAY_SIZE(d)); \
162
162
}
163
163
164
164
static u8 st7701_vgls_map(struct st7701 *st7701)
···
197
185
u8 val;
198
186
199
187
if (cmd2)
200
-
val = DSI_CMD2 | FIELD_PREP(DSI_CMD2BK_MASK, bkx);
188
+
val = ST7701_CMD2 | FIELD_PREP(ST7701_CMD2BK_MASK, bkx);
201
189
else
202
-
val = DSI_CMD1;
190
+
val = ST7701_CMD1;
203
191
204
-
ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val);
192
+
ST7701_WRITE(st7701, ST7701_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val);
205
193
}
206
194
207
195
static void st7701_init_sequence(struct st7701 *st7701)
···
211
199
const u8 linecount8 = mode->vdisplay / 8;
212
200
const u8 linecountrem2 = (mode->vdisplay % 8) / 2;
213
201
214
-
ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
202
+
ST7701_WRITE(st7701, MIPI_DCS_SOFT_RESET, 0x00);
215
203
216
204
/* We need to wait 5ms before sending new commands */
217
205
msleep(5);
218
206
219
-
ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
207
+
ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
220
208
221
209
msleep(st7701->sleep_delay);
222
210
223
211
/* Command2, BK0 */
224
212
st7701_switch_cmd_bkx(st7701, true, 0);
225
213
226
-
mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL,
227
-
desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma));
228
-
mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL,
229
-
desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma));
214
+
st7701->write_command(st7701, ST7701_CMD2_BK0_PVGAMCTRL, desc->pv_gamma,
215
+
ARRAY_SIZE(desc->pv_gamma));
216
+
st7701->write_command(st7701, ST7701_CMD2_BK0_NVGAMCTRL, desc->nv_gamma,
217
+
ARRAY_SIZE(desc->nv_gamma));
230
218
/*
231
219
* Vertical line count configuration:
232
220
* Line[6:0]: select number of vertical lines of the TFT matrix in
···
238
226
* Total number of vertical lines:
239
227
* LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0)
240
228
*/
241
-
ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
242
-
FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) |
243
-
(linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0),
244
-
FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2));
245
-
ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
246
-
FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK,
229
+
ST7701_WRITE(st7701, ST7701_CMD2_BK0_LNESET,
230
+
FIELD_PREP(ST7701_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) |
231
+
(linecountrem2 ? ST7701_CMD2_BK0_LNESET_LDE_EN : 0),
232
+
FIELD_PREP(ST7701_CMD2_BK0_LNESET_LINEDELTA, linecountrem2));
233
+
ST7701_WRITE(st7701, ST7701_CMD2_BK0_PORCTRL,
234
+
FIELD_PREP(ST7701_CMD2_BK0_PORCTRL_VBP_MASK,
247
235
mode->vtotal - mode->vsync_end),
248
-
FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK,
236
+
FIELD_PREP(ST7701_CMD2_BK0_PORCTRL_VFP_MASK,
249
237
mode->vsync_start - mode->vdisplay));
250
238
/*
251
239
* Horizontal pixel count configuration:
···
253
241
* The PCLK is number of pixel clock per line, which matches
254
242
* mode htotal. The minimum is 512 PCLK.
255
243
*/
256
-
ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
257
-
DSI_CMD2_BK0_INVSEL_ONES_MASK |
258
-
FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv),
259
-
FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK,
244
+
ST7701_WRITE(st7701, ST7701_CMD2_BK0_INVSEL,
245
+
ST7701_CMD2_BK0_INVSEL_ONES_MASK |
246
+
FIELD_PREP(ST7701_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv),
247
+
FIELD_PREP(ST7701_CMD2_BK0_INVSEL_RTNI_MASK,
260
248
(clamp((u32)mode->htotal, 512U, 1008U) - 512) / 16));
261
249
262
250
/* Command2, BK1 */
263
251
st7701_switch_cmd_bkx(st7701, true, 1);
264
252
265
253
/* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */
266
-
ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS,
267
-
FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK,
254
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_VRHS,
255
+
FIELD_PREP(ST7701_CMD2_BK1_VRHA_MASK,
268
256
DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500)));
269
257
270
258
/* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */
271
-
ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM,
272
-
FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK,
259
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_VCOM,
260
+
FIELD_PREP(ST7701_CMD2_BK1_VCOM_MASK,
273
261
DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500)));
274
262
275
263
/* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */
276
-
ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS,
277
-
FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK,
264
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_VGHSS,
265
+
FIELD_PREP(ST7701_CMD2_BK1_VGHSS_MASK,
278
266
DIV_ROUND_CLOSEST(clamp(desc->vgh_mv,
279
267
(u16)11500,
280
268
(u16)17000) - 11500,
281
269
500)));
282
270
283
-
ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);
271
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_TESTCMD, ST7701_CMD2_BK1_TESTCMD_VAL);
284
272
285
273
/* Vgl is non-linear */
286
-
ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS,
287
-
DSI_CMD2_BK1_VGLS_ONES |
288
-
FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701)));
274
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_VGLS,
275
+
ST7701_CMD2_BK1_VGLS_ONES |
276
+
FIELD_PREP(ST7701_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701)));
289
277
290
-
ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1,
291
-
FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK,
278
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_PWCTLR1,
279
+
FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL1_AP_MASK,
292
280
desc->gamma_op_bias) |
293
-
FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK,
281
+
FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL1_APIS_MASK,
294
282
desc->input_op_bias) |
295
-
FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK,
283
+
FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL1_APOS_MASK,
296
284
desc->output_op_bias));
297
285
298
286
/* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */
299
-
ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2,
300
-
FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK,
287
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_PWCTLR2,
288
+
FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL2_AVDD_MASK,
301
289
DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) |
302
-
FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK,
290
+
FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL2_AVCL_MASK,
303
291
DIV_ROUND_CLOSEST(-4400 - desc->avcl_mv, 200)));
304
292
305
293
/* T2D = 0.2us * T2D[3:0] */
306
-
ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1,
307
-
DSI_CMD2_BK1_SPD1_ONES_MASK |
308
-
FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK,
294
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_SPD1,
295
+
ST7701_CMD2_BK1_SPD1_ONES_MASK |
296
+
FIELD_PREP(ST7701_CMD2_BK1_SPD1_T2D_MASK,
309
297
DIV_ROUND_CLOSEST(desc->t2d_ns, 200)));
310
298
311
299
/* T3D = 4us + (0.8us * T3D[3:0]) */
312
-
ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2,
313
-
DSI_CMD2_BK1_SPD2_ONES_MASK |
314
-
FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK,
300
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_SPD2,
301
+
ST7701_CMD2_BK1_SPD2_ONES_MASK |
302
+
FIELD_PREP(ST7701_CMD2_BK1_SPD2_T3D_MASK,
315
303
DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800)));
316
304
317
-
ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1,
318
-
DSI_CMD2_BK1_MIPISET1_ONES |
319
-
(desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0));
305
+
ST7701_WRITE(st7701, ST7701_CMD2_BK1_MIPISET1,
306
+
ST7701_CMD2_BK1_MIPISET1_ONES |
307
+
(desc->eot_en ? ST7701_CMD2_BK1_MIPISET1_EOT_EN : 0));
320
308
}
321
309
322
310
static void ts8550b_gip_sequence(struct st7701 *st7701)
···
325
313
* ST7701_SPEC_V1.2 is unable to provide enough information above this
326
314
* specific command sequence, so grab the same from vendor BSP driver.
327
315
*/
328
-
ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
329
-
ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
316
+
ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
317
+
ST7701_WRITE(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
330
318
0x00, 0x00, 0x44, 0x44);
331
-
ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
319
+
ST7701_WRITE(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
332
320
0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
333
-
ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
334
-
ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
335
-
ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
321
+
ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
322
+
ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
323
+
ST7701_WRITE(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
336
324
0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
337
-
ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
338
-
ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
339
-
ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
325
+
ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
326
+
ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
327
+
ST7701_WRITE(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
340
328
0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
341
-
ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
342
-
ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
343
-
ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
329
+
ST7701_WRITE(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
330
+
ST7701_WRITE(st7701, 0xEC, 0x00, 0x00);
331
+
ST7701_WRITE(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
344
332
0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
345
333
}
346
334
347
335
static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701)
348
336
{
349
-
ST7701_DSI(st7701, 0xEE, 0x42);
350
-
ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
337
+
ST7701_WRITE(st7701, 0xEE, 0x42);
338
+
ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
351
339
352
-
ST7701_DSI(st7701, 0xE1,
340
+
ST7701_WRITE(st7701, 0xE1,
353
341
0x04, 0xA0, 0x06, 0xA0,
354
342
0x05, 0xA0, 0x07, 0xA0,
355
343
0x00, 0x44, 0x44);
356
-
ST7701_DSI(st7701, 0xE2,
344
+
ST7701_WRITE(st7701, 0xE2,
357
345
0x00, 0x00, 0x00, 0x00,
358
346
0x00, 0x00, 0x00, 0x00,
359
347
0x00, 0x00, 0x00, 0x00);
360
-
ST7701_DSI(st7701, 0xE3,
348
+
ST7701_WRITE(st7701, 0xE3,
361
349
0x00, 0x00, 0x22, 0x22);
362
-
ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
363
-
ST7701_DSI(st7701, 0xE5,
350
+
ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
351
+
ST7701_WRITE(st7701, 0xE5,
364
352
0x0C, 0x90, 0xA0, 0xA0,
365
353
0x0E, 0x92, 0xA0, 0xA0,
366
354
0x08, 0x8C, 0xA0, 0xA0,
367
355
0x0A, 0x8E, 0xA0, 0xA0);
368
-
ST7701_DSI(st7701, 0xE6,
356
+
ST7701_WRITE(st7701, 0xE6,
369
357
0x00, 0x00, 0x22, 0x22);
370
-
ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
371
-
ST7701_DSI(st7701, 0xE8,
358
+
ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
359
+
ST7701_WRITE(st7701, 0xE8,
372
360
0x0D, 0x91, 0xA0, 0xA0,
373
361
0x0F, 0x93, 0xA0, 0xA0,
374
362
0x09, 0x8D, 0xA0, 0xA0,
375
363
0x0B, 0x8F, 0xA0, 0xA0);
376
-
ST7701_DSI(st7701, 0xEB,
364
+
ST7701_WRITE(st7701, 0xEB,
377
365
0x00, 0x00, 0xE4, 0xE4,
378
366
0x44, 0x00, 0x00);
379
-
ST7701_DSI(st7701, 0xED,
367
+
ST7701_WRITE(st7701, 0xED,
380
368
0xFF, 0xF5, 0x47, 0x6F,
381
369
0x0B, 0xA1, 0xAB, 0xFF,
382
370
0xFF, 0xBA, 0x1A, 0xB0,
383
371
0xF6, 0x74, 0x5F, 0xFF);
384
-
ST7701_DSI(st7701, 0xEF,
372
+
ST7701_WRITE(st7701, 0xEF,
385
373
0x08, 0x08, 0x08, 0x40,
386
374
0x3F, 0x64);
387
375
388
376
st7701_switch_cmd_bkx(st7701, false, 0);
389
377
390
378
st7701_switch_cmd_bkx(st7701, true, 3);
391
-
ST7701_DSI(st7701, 0xE6, 0x7C);
392
-
ST7701_DSI(st7701, 0xE8, 0x00, 0x0E);
379
+
ST7701_WRITE(st7701, 0xE6, 0x7C);
380
+
ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E);
393
381
394
382
st7701_switch_cmd_bkx(st7701, false, 0);
395
-
ST7701_DSI(st7701, 0x11);
383
+
ST7701_WRITE(st7701, 0x11);
396
384
msleep(120);
397
385
398
386
st7701_switch_cmd_bkx(st7701, true, 3);
399
-
ST7701_DSI(st7701, 0xE8, 0x00, 0x0C);
387
+
ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C);
400
388
msleep(10);
401
-
ST7701_DSI(st7701, 0xE8, 0x00, 0x00);
389
+
ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);
402
390
403
391
st7701_switch_cmd_bkx(st7701, false, 0);
404
-
ST7701_DSI(st7701, 0x11);
392
+
ST7701_WRITE(st7701, 0x11);
405
393
msleep(120);
406
-
ST7701_DSI(st7701, 0xE8, 0x00, 0x00);
394
+
ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);
407
395
408
396
st7701_switch_cmd_bkx(st7701, false, 0);
409
397
410
-
ST7701_DSI(st7701, 0x3A, 0x70);
398
+
ST7701_WRITE(st7701, 0x3A, 0x70);
411
399
}
412
400
413
401
static void kd50t048a_gip_sequence(struct st7701 *st7701)
···
416
404
* ST7701_SPEC_V1.2 is unable to provide enough information above this
417
405
* specific command sequence, so grab the same from vendor BSP driver.
418
406
*/
419
-
ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
420
-
ST7701_DSI(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09,
407
+
ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
408
+
ST7701_WRITE(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09,
421
409
0x00, 0x00, 0x33, 0x33);
422
-
ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
410
+
ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
423
411
0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
424
-
ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
425
-
ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
426
-
ST7701_DSI(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0,
412
+
ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
413
+
ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
414
+
ST7701_WRITE(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0,
427
415
0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0);
428
-
ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
429
-
ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
430
-
ST7701_DSI(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0,
416
+
ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
417
+
ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
418
+
ST7701_WRITE(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0,
431
419
0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0);
432
-
ST7701_DSI(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40);
433
-
ST7701_DSI(st7701, 0xEC, 0x02, 0x01);
434
-
ST7701_DSI(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF,
420
+
ST7701_WRITE(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40);
421
+
ST7701_WRITE(st7701, 0xEC, 0x02, 0x01);
422
+
ST7701_WRITE(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF,
435
423
0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA);
436
424
}
437
425
438
426
static void rg_arc_gip_sequence(struct st7701 *st7701)
439
427
{
440
428
st7701_switch_cmd_bkx(st7701, true, 3);
441
-
ST7701_DSI(st7701, 0xEF, 0x08);
429
+
ST7701_WRITE(st7701, 0xEF, 0x08);
442
430
st7701_switch_cmd_bkx(st7701, true, 0);
443
-
ST7701_DSI(st7701, 0xC7, 0x04);
444
-
ST7701_DSI(st7701, 0xCC, 0x38);
431
+
ST7701_WRITE(st7701, 0xC7, 0x04);
432
+
ST7701_WRITE(st7701, 0xCC, 0x38);
445
433
st7701_switch_cmd_bkx(st7701, true, 1);
446
-
ST7701_DSI(st7701, 0xB9, 0x10);
447
-
ST7701_DSI(st7701, 0xBC, 0x03);
448
-
ST7701_DSI(st7701, 0xC0, 0x89);
449
-
ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
450
-
ST7701_DSI(st7701, 0xE1, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00,
434
+
ST7701_WRITE(st7701, 0xB9, 0x10);
435
+
ST7701_WRITE(st7701, 0xBC, 0x03);
436
+
ST7701_WRITE(st7701, 0xC0, 0x89);
437
+
ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
438
+
ST7701_WRITE(st7701, 0xE1, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00,
451
439
0x00, 0x00, 0x20, 0x20);
452
-
ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
440
+
ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
453
441
0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
454
-
ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x00);
455
-
ST7701_DSI(st7701, 0xE4, 0x22, 0x00);
456
-
ST7701_DSI(st7701, 0xE5, 0x04, 0x5C, 0xA0, 0xA0, 0x06, 0x5C, 0xA0,
442
+
ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x00);
443
+
ST7701_WRITE(st7701, 0xE4, 0x22, 0x00);
444
+
ST7701_WRITE(st7701, 0xE5, 0x04, 0x5C, 0xA0, 0xA0, 0x06, 0x5C, 0xA0,
457
445
0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
458
-
ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x00);
459
-
ST7701_DSI(st7701, 0xE7, 0x22, 0x00);
460
-
ST7701_DSI(st7701, 0xE8, 0x05, 0x5C, 0xA0, 0xA0, 0x07, 0x5C, 0xA0,
446
+
ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x00);
447
+
ST7701_WRITE(st7701, 0xE7, 0x22, 0x00);
448
+
ST7701_WRITE(st7701, 0xE8, 0x05, 0x5C, 0xA0, 0xA0, 0x07, 0x5C, 0xA0,
461
449
0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
462
-
ST7701_DSI(st7701, 0xEB, 0x02, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00);
463
-
ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
464
-
ST7701_DSI(st7701, 0xED, 0xFA, 0x45, 0x0B, 0xFF, 0xFF, 0xFF, 0xFF,
450
+
ST7701_WRITE(st7701, 0xEB, 0x02, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00);
451
+
ST7701_WRITE(st7701, 0xEC, 0x00, 0x00);
452
+
ST7701_WRITE(st7701, 0xED, 0xFA, 0x45, 0x0B, 0xFF, 0xFF, 0xFF, 0xFF,
465
453
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB0, 0x54, 0xAF);
466
-
ST7701_DSI(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);
454
+
ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);
467
455
st7701_switch_cmd_bkx(st7701, false, 0);
468
-
ST7701_DSI(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17);
469
-
ST7701_DSI(st7701, MIPI_DCS_SET_PIXEL_FORMAT, 0x77);
470
-
ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
456
+
ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17);
457
+
ST7701_WRITE(st7701, MIPI_DCS_SET_PIXEL_FORMAT, 0x77);
458
+
ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
471
459
msleep(120);
460
+
}
461
+
462
+
static void rg28xx_gip_sequence(struct st7701 *st7701)
463
+
{
464
+
st7701_switch_cmd_bkx(st7701, true, 3);
465
+
ST7701_WRITE(st7701, 0xEF, 0x08);
466
+
467
+
st7701_switch_cmd_bkx(st7701, true, 0);
468
+
ST7701_WRITE(st7701, 0xC3, 0x02, 0x10, 0x02);
469
+
ST7701_WRITE(st7701, 0xC7, 0x04);
470
+
ST7701_WRITE(st7701, 0xCC, 0x10);
471
+
472
+
st7701_switch_cmd_bkx(st7701, true, 1);
473
+
ST7701_WRITE(st7701, 0xEE, 0x42);
474
+
ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
475
+
476
+
ST7701_WRITE(st7701, 0xE1, 0x04, 0xA0, 0x06, 0xA0, 0x05, 0xA0, 0x07, 0xA0,
477
+
0x00, 0x44, 0x44);
478
+
ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
479
+
0x00, 0x00, 0x00, 0x00);
480
+
ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x22, 0x22);
481
+
ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
482
+
ST7701_WRITE(st7701, 0xE5, 0x0C, 0x90, 0xA0, 0xA0, 0x0E, 0x92, 0xA0, 0xA0,
483
+
0x08, 0x8C, 0xA0, 0xA0, 0x0A, 0x8E, 0xA0, 0xA0);
484
+
ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x22, 0x22);
485
+
ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
486
+
ST7701_WRITE(st7701, 0xE8, 0x0D, 0x91, 0xA0, 0xA0, 0x0F, 0x93, 0xA0, 0xA0,
487
+
0x09, 0x8D, 0xA0, 0xA0, 0x0B, 0x8F, 0xA0, 0xA0);
488
+
ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x44, 0x00, 0x40);
489
+
ST7701_WRITE(st7701, 0xED, 0xFF, 0xF5, 0x47, 0x6F, 0x0B, 0xA1, 0xBA, 0xFF,
490
+
0xFF, 0xAB, 0x1A, 0xB0, 0xF6, 0x74, 0x5F, 0xFF);
491
+
ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);
492
+
493
+
st7701_switch_cmd_bkx(st7701, false, 0);
494
+
495
+
st7701_switch_cmd_bkx(st7701, true, 3);
496
+
ST7701_WRITE(st7701, 0xE6, 0x16);
497
+
ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E);
498
+
499
+
st7701_switch_cmd_bkx(st7701, false, 0);
500
+
ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x10);
501
+
ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE);
502
+
msleep(120);
503
+
504
+
st7701_switch_cmd_bkx(st7701, true, 3);
505
+
ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C);
506
+
msleep(10);
507
+
ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);
508
+
st7701_switch_cmd_bkx(st7701, false, 0);
472
509
}
473
510
474
511
static int st7701_prepare(struct drm_panel *panel)
···
551
490
{
552
491
struct st7701 *st7701 = panel_to_st7701(panel);
553
492
554
-
ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
493
+
ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
555
494
556
495
return 0;
557
496
}
···
560
499
{
561
500
struct st7701 *st7701 = panel_to_st7701(panel);
562
501
563
-
ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
502
+
ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
564
503
565
504
return 0;
566
505
}
···
569
508
{
570
509
struct st7701 *st7701 = panel_to_st7701(panel);
571
510
572
-
ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
511
+
ST7701_WRITE(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
573
512
574
513
msleep(st7701->sleep_delay);
575
514
···
600
539
601
540
mode = drm_mode_duplicate(connector->dev, desc_mode);
602
541
if (!mode) {
603
-
dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n",
542
+
dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
604
543
desc_mode->hdisplay, desc_mode->vdisplay,
605
544
drm_mode_vrefresh(desc_mode));
606
545
return -ENOMEM;
···
663
602
.panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
664
603
665
604
.pv_gamma = {
666
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
667
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
668
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
669
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
670
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
671
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
672
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
605
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
606
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
607
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
608
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
609
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
610
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
611
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
673
612
674
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
675
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
676
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
677
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
678
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
613
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
614
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
615
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
616
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
617
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
679
618
680
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
681
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
682
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
683
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
684
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
619
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
620
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
621
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
622
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
623
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
685
624
686
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
687
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
688
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
689
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
690
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
691
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
692
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
625
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
626
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
627
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
628
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
629
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
630
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
631
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
693
632
},
694
633
.nv_gamma = {
695
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
696
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
697
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
698
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
699
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
700
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
701
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
634
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
635
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
636
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
637
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
638
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
639
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
640
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
702
641
703
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
704
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
705
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
706
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
707
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
642
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
643
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
644
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
645
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
646
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
708
647
709
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
710
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
711
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
712
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
713
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
648
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
649
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
650
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
651
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
652
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
714
653
715
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
716
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
717
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
718
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
719
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
720
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
721
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
654
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
655
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
656
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
657
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
658
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
659
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
660
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
722
661
},
723
662
.nlinv = 7,
724
663
.vop_uv = 4400000,
···
764
703
.panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */
765
704
766
705
.pv_gamma = {
767
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
768
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
769
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
770
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
771
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
772
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
773
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
706
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
707
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
708
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
709
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
710
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
711
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
712
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
774
713
775
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
776
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
777
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
778
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
779
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
714
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
715
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
716
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
717
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
718
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
780
719
781
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
782
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
783
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
784
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
785
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
720
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
721
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
722
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
723
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
724
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
786
725
787
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
788
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
789
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
790
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
791
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
792
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
793
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
726
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
727
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
728
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
729
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
730
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
731
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
732
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
794
733
},
795
734
.nv_gamma = {
796
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
797
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
798
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
799
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
800
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
801
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
802
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
735
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
736
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
737
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
738
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
739
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
740
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
741
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
803
742
804
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
805
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
806
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
807
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
808
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
743
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
744
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
745
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
746
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
747
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
809
748
810
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
811
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
812
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
813
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
814
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
749
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
750
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
751
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
752
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
753
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
815
754
816
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
817
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
818
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
819
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
820
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
821
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
822
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
755
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
756
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
757
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
758
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
759
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
760
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
761
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
823
762
},
824
763
.nlinv = 1,
825
764
.vop_uv = 4800000,
···
863
802
.panel_sleep_delay = 0,
864
803
865
804
.pv_gamma = {
866
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
867
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
868
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
869
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
870
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
871
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
872
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
805
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
806
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
807
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
808
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
809
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
810
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
811
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
873
812
874
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
875
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
876
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
877
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
878
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
813
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
814
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
815
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
816
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
817
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
879
818
880
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
881
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
882
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
883
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
884
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
819
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
820
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
821
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
822
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
823
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
885
824
886
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
887
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
888
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
889
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
890
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
891
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
892
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
825
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
826
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
827
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
828
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
829
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
830
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
831
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
893
832
},
894
833
.nv_gamma = {
895
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
896
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
897
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
898
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
899
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
900
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
901
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
834
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
835
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
836
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
837
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
838
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
839
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
840
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
902
841
903
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
904
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
905
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
906
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
907
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
842
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
843
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
844
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
845
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
846
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
908
847
909
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
910
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
911
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
912
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
913
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
848
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
849
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
850
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
851
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
852
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
914
853
915
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
916
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
917
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
918
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
919
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
920
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
921
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
854
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
855
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
856
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
857
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
858
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
859
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
860
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
922
861
},
923
862
.nlinv = 1,
924
863
.vop_uv = 4887500,
···
962
901
.panel_sleep_delay = 80,
963
902
964
903
.pv_gamma = {
965
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
966
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
967
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
968
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
969
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
970
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1d),
971
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
904
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
905
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
906
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
907
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
908
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
909
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1d),
910
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
972
911
973
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
974
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x12),
975
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
976
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
977
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0a),
912
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
913
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x12),
914
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
915
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
916
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0a),
978
917
979
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
980
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x25),
981
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
982
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
983
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x03),
918
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
919
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x25),
920
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
921
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
922
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x03),
984
923
985
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
986
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
987
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
988
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
989
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
990
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
991
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
924
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
925
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
926
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
927
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
928
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
929
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
930
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
992
931
},
993
932
.nv_gamma = {
994
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
995
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
996
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
997
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
998
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
999
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1e),
1000
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
933
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
934
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
935
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
936
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
937
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
938
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1e),
939
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
1001
940
1002
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1003
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1004
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
1005
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
1006
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08),
941
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
942
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
943
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
944
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
945
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08),
1007
946
1008
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
1009
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x26),
1010
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
1011
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1012
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x15),
947
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
948
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x26),
949
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
950
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
951
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x15),
1013
952
1014
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
1015
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1016
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
1017
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1018
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
1019
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1020
-
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
953
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
954
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
955
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
956
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
957
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
958
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
959
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
1021
960
},
1022
961
.nlinv = 0,
1023
962
.vop_uv = 4500000,
···
1035
974
.gip_sequence = rg_arc_gip_sequence,
1036
975
};
1037
976
1038
-
static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
977
+
static const struct drm_display_mode rg28xx_mode = {
978
+
.clock = 22325,
979
+
980
+
.hdisplay = 480,
981
+
.hsync_start = 480 + 40,
982
+
.hsync_end = 480 + 40 + 4,
983
+
.htotal = 480 + 40 + 4 + 20,
984
+
985
+
.vdisplay = 640,
986
+
.vsync_start = 640 + 2,
987
+
.vsync_end = 640 + 2 + 40,
988
+
.vtotal = 640 + 2 + 40 + 16,
989
+
990
+
.width_mm = 44,
991
+
.height_mm = 58,
992
+
993
+
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
994
+
995
+
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
996
+
};
997
+
998
+
static const struct st7701_panel_desc rg28xx_desc = {
999
+
.mode = &rg28xx_mode,
1000
+
1001
+
.panel_sleep_delay = 80,
1002
+
1003
+
.pv_gamma = {
1004
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1005
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
1006
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1007
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
1008
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1009
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
1010
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
1011
+
1012
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1013
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1014
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
1015
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
1016
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
1017
+
1018
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
1019
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
1020
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
1021
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1022
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
1023
+
1024
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
1025
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1026
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
1027
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1028
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
1029
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1030
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
1031
+
},
1032
+
.nv_gamma = {
1033
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1034
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
1035
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1036
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
1037
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1038
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
1039
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
1040
+
1041
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1042
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1043
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
1044
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
1045
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
1046
+
1047
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
1048
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
1049
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
1050
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1051
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
1052
+
1053
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
1054
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1055
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
1056
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1057
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
1058
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1059
+
CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
1060
+
},
1061
+
.nlinv = 7,
1062
+
.vop_uv = 4800000,
1063
+
.vcom_uv = 1512500,
1064
+
.vgh_mv = 15000,
1065
+
.vgl_mv = -11730,
1066
+
.avdd_mv = 6600,
1067
+
.avcl_mv = -4400,
1068
+
.gamma_op_bias = OP_BIAS_MIDDLE,
1069
+
.input_op_bias = OP_BIAS_MIN,
1070
+
.output_op_bias = OP_BIAS_MIN,
1071
+
.t2d_ns = 1600,
1072
+
.t3d_ns = 10400,
1073
+
.eot_en = true,
1074
+
.gip_sequence = rg28xx_gip_sequence,
1075
+
};
1076
+
1077
+
static void st7701_cleanup(void *data)
1078
+
{
1079
+
struct st7701 *st7701 = (struct st7701 *)data;
1080
+
1081
+
drm_panel_remove(&st7701->panel);
1082
+
drm_panel_disable(&st7701->panel);
1083
+
drm_panel_unprepare(&st7701->panel);
1084
+
}
1085
+
1086
+
static int st7701_probe(struct device *dev, int connector_type)
1039
1087
{
1040
1088
const struct st7701_panel_desc *desc;
1041
1089
struct st7701 *st7701;
1042
1090
int ret;
1043
1091
1044
-
st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL);
1092
+
st7701 = devm_kzalloc(dev, sizeof(*st7701), GFP_KERNEL);
1045
1093
if (!st7701)
1046
1094
return -ENOMEM;
1047
1095
1048
-
desc = of_device_get_match_data(&dsi->dev);
1049
-
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
1050
-
MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
1051
-
dsi->format = desc->format;
1052
-
dsi->lanes = desc->lanes;
1096
+
desc = of_device_get_match_data(dev);
1097
+
if (!desc)
1098
+
return -ENODEV;
1053
1099
1054
1100
st7701->supplies[0].supply = "VCC";
1055
1101
st7701->supplies[1].supply = "IOVCC";
1056
1102
1057
-
ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies),
1103
+
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st7701->supplies),
1058
1104
st7701->supplies);
1059
1105
if (ret < 0)
1060
1106
return ret;
1061
1107
1062
-
st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
1108
+
st7701->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1063
1109
if (IS_ERR(st7701->reset)) {
1064
-
dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
1110
+
dev_err(dev, "Couldn't get our reset GPIO\n");
1065
1111
return PTR_ERR(st7701->reset);
1066
1112
}
1067
1113
1068
-
ret = of_drm_get_panel_orientation(dsi->dev.of_node, &st7701->orientation);
1114
+
ret = of_drm_get_panel_orientation(dev->of_node, &st7701->orientation);
1069
1115
if (ret < 0)
1070
-
return dev_err_probe(&dsi->dev, ret, "Failed to get orientation\n");
1116
+
return dev_err_probe(dev, ret, "Failed to get orientation\n");
1071
1117
1072
-
drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs,
1073
-
DRM_MODE_CONNECTOR_DSI);
1118
+
drm_panel_init(&st7701->panel, dev, &st7701_funcs, connector_type);
1074
1119
1075
1120
/**
1076
1121
* Once sleep out has been issued, ST7701 IC required to wait 120ms
···
1195
1028
1196
1029
drm_panel_add(&st7701->panel);
1197
1030
1198
-
mipi_dsi_set_drvdata(dsi, st7701);
1199
-
st7701->dsi = dsi;
1031
+
dev_set_drvdata(dev, st7701);
1200
1032
st7701->desc = desc;
1201
1033
1202
-
ret = mipi_dsi_attach(dsi);
1203
-
if (ret)
1204
-
goto err_attach;
1034
+
return devm_add_action_or_reset(dev, st7701_cleanup, st7701);
1035
+
}
1036
+
1037
+
static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
1038
+
{
1039
+
struct st7701 *st7701;
1040
+
int err;
1041
+
1042
+
err = st7701_probe(&dsi->dev, DRM_MODE_CONNECTOR_DSI);
1043
+
if (err)
1044
+
return err;
1045
+
1046
+
st7701 = dev_get_drvdata(&dsi->dev);
1047
+
st7701->dsi = dsi;
1048
+
st7701->write_command = st7701_dsi_write;
1049
+
1050
+
if (!st7701->desc->lanes)
1051
+
return dev_err_probe(&dsi->dev, -EINVAL, "This panel is not for MIPI DSI\n");
1052
+
1053
+
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
1054
+
MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
1055
+
dsi->format = st7701->desc->format;
1056
+
dsi->lanes = st7701->desc->lanes;
1057
+
1058
+
err = mipi_dsi_attach(dsi);
1059
+
if (err)
1060
+
return dev_err_probe(&dsi->dev, err, "Failed to init MIPI DSI\n");
1205
1061
1206
1062
return 0;
1063
+
}
1207
1064
1208
-
err_attach:
1209
-
drm_panel_remove(&st7701->panel);
1210
-
return ret;
1065
+
static int st7701_spi_probe(struct spi_device *spi)
1066
+
{
1067
+
struct st7701 *st7701;
1068
+
struct gpio_desc *dc;
1069
+
int err;
1070
+
1071
+
err = st7701_probe(&spi->dev, DRM_MODE_CONNECTOR_DPI);
1072
+
if (err)
1073
+
return err;
1074
+
1075
+
st7701 = dev_get_drvdata(&spi->dev);
1076
+
st7701->write_command = st7701_dbi_write;
1077
+
1078
+
dc = devm_gpiod_get_optional(&spi->dev, "dc", GPIOD_OUT_LOW);
1079
+
if (IS_ERR(dc))
1080
+
return dev_err_probe(&spi->dev, PTR_ERR(dc), "Failed to get GPIO for D/CX\n");
1081
+
1082
+
err = mipi_dbi_spi_init(spi, &st7701->dbi, dc);
1083
+
if (err)
1084
+
return dev_err_probe(&spi->dev, err, "Failed to init MIPI DBI\n");
1085
+
st7701->dbi.read_commands = NULL;
1086
+
1087
+
return 0;
1211
1088
}
1212
1089
1213
1090
static void st7701_dsi_remove(struct mipi_dsi_device *dsi)
1214
1091
{
1215
-
struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
1216
-
1217
1092
mipi_dsi_detach(dsi);
1218
-
drm_panel_remove(&st7701->panel);
1219
1093
}
1220
1094
1221
-
static const struct of_device_id st7701_of_match[] = {
1095
+
static const struct of_device_id st7701_dsi_of_match[] = {
1222
1096
{ .compatible = "anbernic,rg-arc-panel", .data = &rg_arc_desc },
1223
1097
{ .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc },
1224
1098
{ .compatible = "elida,kd50t048a", .data = &kd50t048a_desc },
1225
1099
{ .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
1226
1100
{ }
1227
1101
};
1228
-
MODULE_DEVICE_TABLE(of, st7701_of_match);
1102
+
MODULE_DEVICE_TABLE(of, st7701_dsi_of_match);
1103
+
1104
+
static const struct of_device_id st7701_spi_of_match[] = {
1105
+
{ .compatible = "anbernic,rg28xx-panel", .data = &rg28xx_desc },
1106
+
{ /* sentinel */ }
1107
+
};
1108
+
MODULE_DEVICE_TABLE(of, st7701_spi_of_match);
1109
+
1110
+
static const struct spi_device_id st7701_spi_ids[] = {
1111
+
{ "rg28xx-panel" },
1112
+
{ /* sentinel */ }
1113
+
};
1114
+
MODULE_DEVICE_TABLE(spi, st7701_spi_ids);
1229
1115
1230
1116
static struct mipi_dsi_driver st7701_dsi_driver = {
1231
1117
.probe = st7701_dsi_probe,
1232
1118
.remove = st7701_dsi_remove,
1233
1119
.driver = {
1234
1120
.name = "st7701",
1235
-
.of_match_table = st7701_of_match,
1121
+
.of_match_table = st7701_dsi_of_match,
1236
1122
},
1237
1123
};
1238
-
module_mipi_dsi_driver(st7701_dsi_driver);
1124
+
1125
+
static struct spi_driver st7701_spi_driver = {
1126
+
.probe = st7701_spi_probe,
1127
+
.id_table = st7701_spi_ids,
1128
+
.driver = {
1129
+
.name = "st7701",
1130
+
.of_match_table = st7701_spi_of_match,
1131
+
},
1132
+
};
1133
+
1134
+
static int __init st7701_driver_init(void)
1135
+
{
1136
+
int err;
1137
+
1138
+
if (IS_ENABLED(CONFIG_SPI)) {
1139
+
err = spi_register_driver(&st7701_spi_driver);
1140
+
if (err)
1141
+
return err;
1142
+
}
1143
+
1144
+
if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1145
+
err = mipi_dsi_driver_register(&st7701_dsi_driver);
1146
+
if (err) {
1147
+
if (IS_ENABLED(CONFIG_SPI))
1148
+
spi_unregister_driver(&st7701_spi_driver);
1149
+
return err;
1150
+
}
1151
+
}
1152
+
1153
+
return 0;
1154
+
}
1155
+
module_init(st7701_driver_init);
1156
+
1157
+
static void __exit st7701_driver_exit(void)
1158
+
{
1159
+
if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1160
+
mipi_dsi_driver_unregister(&st7701_dsi_driver);
1161
+
1162
+
if (IS_ENABLED(CONFIG_SPI))
1163
+
spi_unregister_driver(&st7701_spi_driver);
1164
+
}
1165
+
module_exit(st7701_driver_exit);
1239
1166
1240
1167
MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
1168
+
MODULE_AUTHOR("Hironori KIKUCHI <kikuchan98@gmail.com>");
1241
1169
MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver");
1242
1170
MODULE_LICENSE("GPL");
+1
-1
drivers/gpu/drm/udl/udl_edid.c
+1
-1
drivers/gpu/drm/udl/udl_edid.c
···
69
69
* The adapter sends all-zeros if no monitor has been
70
70
* connected. We consider anything else a connection.
71
71
*/
72
-
return !!memchr_inv(hdr, 0, sizeof(hdr));
72
+
return !mem_is_zero(hdr, sizeof(hdr));
73
73
}
74
74
75
75
const struct drm_edid *udl_edid_read(struct drm_connector *connector)
+7
-7
drivers/gpu/drm/vc4/vc4_bo.c
+7
-7
drivers/gpu/drm/vc4/vc4_bo.c
···
469
469
470
470
if (IS_ERR(dma_obj)) {
471
471
struct drm_printer p = drm_info_printer(vc4->base.dev);
472
-
DRM_ERROR("Failed to allocate from GEM DMA helper:\n");
472
+
drm_err(dev, "Failed to allocate from GEM DMA helper:\n");
473
473
vc4_bo_stats_print(&p, vc4);
474
474
return ERR_PTR(-ENOMEM);
475
475
}
···
702
702
*/
703
703
ret = vc4_bo_inc_usecnt(bo);
704
704
if (ret) {
705
-
DRM_ERROR("Failed to increment BO usecnt\n");
705
+
drm_err(obj->dev, "Failed to increment BO usecnt\n");
706
706
return ERR_PTR(ret);
707
707
}
708
708
···
1050
1050
1051
1051
for (i = 0; i < vc4->num_labels; i++) {
1052
1052
if (vc4->bo_labels[i].num_allocated) {
1053
-
DRM_ERROR("Destroying BO cache with %d %s "
1054
-
"BOs still allocated\n",
1055
-
vc4->bo_labels[i].num_allocated,
1056
-
vc4->bo_labels[i].name);
1053
+
drm_err(dev, "Destroying BO cache with %d %s "
1054
+
"BOs still allocated\n",
1055
+
vc4->bo_labels[i].num_allocated,
1056
+
vc4->bo_labels[i].name);
1057
1057
}
1058
1058
1059
1059
if (is_user_label(i))
···
1083
1083
1084
1084
gem_obj = drm_gem_object_lookup(file_priv, args->handle);
1085
1085
if (!gem_obj) {
1086
-
DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
1086
+
drm_err(dev, "Failed to look up GEM BO %d\n", args->handle);
1087
1087
kfree(name);
1088
1088
return -ENOENT;
1089
1089
}
+7
-7
drivers/gpu/drm/vc4/vc4_dpi.c
+7
-7
drivers/gpu/drm/vc4/vc4_dpi.c
···
199
199
DPI_FORMAT);
200
200
break;
201
201
default:
202
-
DRM_ERROR("Unknown media bus format %d\n",
203
-
bus_format);
202
+
drm_err(dev, "Unknown media bus format %d\n",
203
+
bus_format);
204
204
break;
205
205
}
206
206
}
···
236
236
237
237
ret = clk_set_rate(dpi->pixel_clock, mode->clock * 1000);
238
238
if (ret)
239
-
DRM_ERROR("Failed to set clock rate: %d\n", ret);
239
+
drm_err(dev, "Failed to set clock rate: %d\n", ret);
240
240
241
241
ret = clk_prepare_enable(dpi->pixel_clock);
242
242
if (ret)
243
-
DRM_ERROR("Failed to set clock rate: %d\n", ret);
243
+
drm_err(dev, "Failed to set clock rate: %d\n", ret);
244
244
245
245
drm_dev_exit(idx);
246
246
}
···
339
339
if (IS_ERR(dpi->core_clock)) {
340
340
ret = PTR_ERR(dpi->core_clock);
341
341
if (ret != -EPROBE_DEFER)
342
-
DRM_ERROR("Failed to get core clock: %d\n", ret);
342
+
drm_err(drm, "Failed to get core clock: %d\n", ret);
343
343
return ret;
344
344
}
345
345
···
347
347
if (IS_ERR(dpi->pixel_clock)) {
348
348
ret = PTR_ERR(dpi->pixel_clock);
349
349
if (ret != -EPROBE_DEFER)
350
-
DRM_ERROR("Failed to get pixel clock: %d\n", ret);
350
+
drm_err(drm, "Failed to get pixel clock: %d\n", ret);
351
351
return ret;
352
352
}
353
353
354
354
ret = clk_prepare_enable(dpi->core_clock);
355
355
if (ret) {
356
-
DRM_ERROR("Failed to turn on core clock: %d\n", ret);
356
+
drm_err(drm, "Failed to turn on core clock: %d\n", ret);
357
357
return ret;
358
358
}
359
359
+18
-14
drivers/gpu/drm/vc4/vc4_dsi.c
+18
-14
drivers/gpu/drm/vc4/vc4_dsi.c
···
613
613
static inline void
614
614
dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
615
615
{
616
+
struct drm_device *drm = dsi->bridge.dev;
616
617
struct dma_chan *chan = dsi->reg_dma_chan;
617
618
struct dma_async_tx_descriptor *tx;
618
619
dma_cookie_t cookie;
···
634
633
dsi->reg_dma_paddr,
635
634
4, 0);
636
635
if (!tx) {
637
-
DRM_ERROR("Failed to set up DMA register write\n");
636
+
drm_err(drm, "Failed to set up DMA register write\n");
638
637
return;
639
638
}
640
639
641
640
cookie = tx->tx_submit(tx);
642
641
ret = dma_submit_error(cookie);
643
642
if (ret) {
644
-
DRM_ERROR("Failed to submit DMA: %d\n", ret);
643
+
drm_err(drm, "Failed to submit DMA: %d\n", ret);
645
644
return;
646
645
}
647
646
ret = dma_sync_wait(chan, cookie);
648
647
if (ret)
649
-
DRM_ERROR("Failed to wait for DMA: %d\n", ret);
648
+
drm_err(drm, "Failed to wait for DMA: %d\n", ret);
650
649
}
651
650
652
651
#define DSI_READ(offset) \
···
894
893
895
894
ret = pm_runtime_resume_and_get(dev);
896
895
if (ret) {
897
-
DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
896
+
drm_err(bridge->dev, "Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
898
897
return;
899
898
}
900
899
···
987
986
988
987
ret = clk_prepare_enable(dsi->escape_clock);
989
988
if (ret) {
990
-
DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
989
+
drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n",
990
+
ret);
991
991
return;
992
992
}
993
993
994
994
ret = clk_prepare_enable(dsi->pll_phy_clock);
995
995
if (ret) {
996
-
DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
996
+
drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret);
997
997
return;
998
998
}
999
999
···
1016
1014
1017
1015
ret = clk_prepare_enable(dsi->pixel_clock);
1018
1016
if (ret) {
1019
-
DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
1017
+
drm_err(bridge->dev, "Failed to turn on DSI pixel clock: %d\n", ret);
1020
1018
return;
1021
1019
}
1022
1020
···
1174
1172
const struct mipi_dsi_msg *msg)
1175
1173
{
1176
1174
struct vc4_dsi *dsi = host_to_dsi(host);
1175
+
struct drm_device *drm = dsi->bridge.dev;
1177
1176
struct mipi_dsi_packet packet;
1178
1177
u32 pkth = 0, pktc = 0;
1179
1178
int i, ret;
···
1306
1303
DSI_RXPKT1H_BC_PARAM);
1307
1304
1308
1305
if (rxlen != msg->rx_len) {
1309
-
DRM_ERROR("DSI returned %db, expecting %db\n",
1310
-
rxlen, (int)msg->rx_len);
1306
+
drm_err(drm, "DSI returned %db, expecting %db\n",
1307
+
rxlen, (int)msg->rx_len);
1311
1308
ret = -ENXIO;
1312
1309
goto reset_fifo_and_return;
1313
1310
}
···
1329
1326
return ret;
1330
1327
1331
1328
reset_fifo_and_return:
1332
-
DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1329
+
drm_err(drm, "DSI transfer failed, resetting: %d\n", ret);
1333
1330
1334
1331
DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1335
1332
udelay(1);
···
1471
1468
if (!(stat & bit))
1472
1469
return;
1473
1470
1474
-
DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type);
1471
+
drm_err(dsi->bridge.dev, "DSI%d: %s error\n", dsi->variant->port,
1472
+
type);
1475
1473
*ret = IRQ_HANDLED;
1476
1474
}
1477
1475
···
1691
1687
&dsi->reg_dma_paddr,
1692
1688
GFP_KERNEL);
1693
1689
if (!dsi->reg_dma_mem) {
1694
-
DRM_ERROR("Failed to get DMA memory\n");
1690
+
drm_err(drm, "Failed to get DMA memory\n");
1695
1691
return -ENOMEM;
1696
1692
}
1697
1693
···
1706
1702
if (IS_ERR(dsi->reg_dma_chan)) {
1707
1703
ret = PTR_ERR(dsi->reg_dma_chan);
1708
1704
if (ret != -EPROBE_DEFER)
1709
-
DRM_ERROR("Failed to get DMA channel: %d\n",
1710
-
ret);
1705
+
drm_err(drm, "Failed to get DMA channel: %d\n",
1706
+
ret);
1711
1707
return ret;
1712
1708
}
1713
1709
+5
-6
drivers/gpu/drm/vc4/vc4_gem.c
+5
-6
drivers/gpu/drm/vc4/vc4_gem.c
···
832
832
*/
833
833
temp = kvmalloc_array(temp_size, 1, GFP_KERNEL);
834
834
if (!temp) {
835
-
DRM_ERROR("Failed to allocate storage for copying "
836
-
"in bin/render CLs.\n");
835
+
drm_err(dev, "Failed to allocate storage for copying "
836
+
"in bin/render CLs.\n");
837
837
ret = -ENOMEM;
838
838
goto fail;
839
839
}
···
866
866
867
867
bo = vc4_bo_create(dev, exec_size, true, VC4_BO_TYPE_BCL);
868
868
if (IS_ERR(bo)) {
869
-
DRM_ERROR("Couldn't allocate BO for binning\n");
869
+
drm_err(dev, "Couldn't allocate BO for binning\n");
870
870
ret = PTR_ERR(bo);
871
871
goto fail;
872
872
}
···
1153
1153
}
1154
1154
1155
1155
exec = kcalloc(1, sizeof(*exec), GFP_KERNEL);
1156
-
if (!exec) {
1157
-
DRM_ERROR("malloc failure on exec struct\n");
1156
+
if (!exec)
1158
1157
return -ENOMEM;
1159
-
}
1158
+
1160
1159
exec->dev = vc4;
1161
1160
1162
1161
ret = vc4_v3d_pm_get(vc4);
+25
-19
drivers/gpu/drm/vc4/vc4_hdmi.c
+25
-19
drivers/gpu/drm/vc4/vc4_hdmi.c
···
429
429
{
430
430
struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
431
431
enum drm_connector_status status = connector_status_disconnected;
432
+
int ret;
432
433
433
434
/*
434
435
* NOTE: This function should really take vc4_hdmi->mutex, but
···
442
441
* the lock for now.
443
442
*/
444
443
445
-
WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
444
+
ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
445
+
if (ret) {
446
+
drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
447
+
ret);
448
+
return connector_status_unknown;
449
+
}
446
450
447
451
if (vc4_hdmi->hpd_gpio) {
448
452
if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
···
704
698
705
699
ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
706
700
if (ret) {
707
-
DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
701
+
drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
708
702
goto out;
709
703
}
710
704
···
740
734
ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
741
735
BIT(packet_id)), 100);
742
736
if (ret)
743
-
DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
737
+
drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
744
738
745
739
out:
746
740
drm_dev_exit(idx);
···
901
895
902
896
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
903
897
if (ret < 0)
904
-
DRM_ERROR("Failed to release power domain: %d\n", ret);
898
+
drm_err(drm, "Failed to release power domain: %d\n", ret);
905
899
906
900
drm_dev_exit(idx);
907
901
···
1443
1437
1444
1438
ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1445
1439
if (ret < 0) {
1446
-
DRM_ERROR("Failed to retain power domain: %d\n", ret);
1440
+
drm_err(drm, "Failed to retain power domain: %d\n", ret);
1447
1441
goto err_dev_exit;
1448
1442
}
1449
1443
···
1468
1462
div_u64(tmds_char_rate, 100) * 101);
1469
1463
ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1470
1464
if (ret) {
1471
-
DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1465
+
drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1472
1466
goto err_put_runtime_pm;
1473
1467
}
1474
1468
1475
1469
ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1476
1470
if (ret) {
1477
-
DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1471
+
drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1478
1472
goto err_put_runtime_pm;
1479
1473
}
1480
1474
1481
1475
ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1482
1476
if (ret) {
1483
-
DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1477
+
drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1484
1478
goto err_put_runtime_pm;
1485
1479
}
1486
1480
···
1496
1490
1497
1491
ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1498
1492
if (ret) {
1499
-
DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1493
+
drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1500
1494
goto err_disable_pixel_clock;
1501
1495
}
1502
1496
1503
1497
ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1504
1498
if (ret) {
1505
-
DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1499
+
drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1506
1500
goto err_disable_pixel_clock;
1507
1501
}
1508
1502
···
2951
2945
if (IS_ERR(vc4_hdmi->pixel_clock)) {
2952
2946
ret = PTR_ERR(vc4_hdmi->pixel_clock);
2953
2947
if (ret != -EPROBE_DEFER)
2954
-
DRM_ERROR("Failed to get pixel clock\n");
2948
+
drm_err(drm, "Failed to get pixel clock\n");
2955
2949
return ret;
2956
2950
}
2957
2951
2958
2952
vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2959
2953
if (IS_ERR(vc4_hdmi->hsm_clock)) {
2960
-
DRM_ERROR("Failed to get HDMI state machine clock\n");
2954
+
drm_err(drm, "Failed to get HDMI state machine clock\n");
2961
2955
return PTR_ERR(vc4_hdmi->hsm_clock);
2962
2956
}
2963
2957
vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
···
3041
3035
3042
3036
vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3043
3037
if (IS_ERR(vc4_hdmi->hsm_clock)) {
3044
-
DRM_ERROR("Failed to get HDMI state machine clock\n");
3038
+
drm_err(drm, "Failed to get HDMI state machine clock\n");
3045
3039
return PTR_ERR(vc4_hdmi->hsm_clock);
3046
3040
}
3047
3041
3048
3042
vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3049
3043
if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3050
-
DRM_ERROR("Failed to get pixel bvb clock\n");
3044
+
drm_err(drm, "Failed to get pixel bvb clock\n");
3051
3045
return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3052
3046
}
3053
3047
3054
3048
vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3055
3049
if (IS_ERR(vc4_hdmi->audio_clock)) {
3056
-
DRM_ERROR("Failed to get audio clock\n");
3050
+
drm_err(drm, "Failed to get audio clock\n");
3057
3051
return PTR_ERR(vc4_hdmi->audio_clock);
3058
3052
}
3059
3053
3060
3054
vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3061
3055
if (IS_ERR(vc4_hdmi->cec_clock)) {
3062
-
DRM_ERROR("Failed to get CEC clock\n");
3056
+
drm_err(drm, "Failed to get CEC clock\n");
3063
3057
return PTR_ERR(vc4_hdmi->cec_clock);
3064
3058
}
3065
3059
3066
3060
vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3067
3061
if (IS_ERR(vc4_hdmi->reset)) {
3068
-
DRM_ERROR("Failed to get HDMI reset line\n");
3062
+
drm_err(drm, "Failed to get HDMI reset line\n");
3069
3063
return PTR_ERR(vc4_hdmi->reset);
3070
3064
}
3071
3065
···
3221
3215
3222
3216
ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3223
3217
if (!ddc_node) {
3224
-
DRM_ERROR("Failed to find ddc node in device tree\n");
3218
+
drm_err(drm, "Failed to find ddc node in device tree\n");
3225
3219
return -ENODEV;
3226
3220
}
3227
3221
3228
3222
vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3229
3223
of_node_put(ddc_node);
3230
3224
if (!vc4_hdmi->ddc) {
3231
-
DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3225
+
drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3232
3226
return -EPROBE_DEFER;
3233
3227
}
3234
3228
+2
-2
drivers/gpu/drm/vc4/vc4_hvs.c
+2
-2
drivers/gpu/drm/vc4/vc4_hvs.c
···
191
191
192
192
ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
193
193
if (ret) {
194
-
DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
195
-
ret);
194
+
drm_err(&hvs->vc4->base, "Failed to allocate space for filter kernel: %d\n",
195
+
ret);
196
196
return ret;
197
197
}
198
198
+1
-1
drivers/gpu/drm/vc4/vc4_irq.c
+1
-1
drivers/gpu/drm/vc4/vc4_irq.c
+6
-18
drivers/gpu/drm/vc4/vc4_v3d.c
+6
-18
drivers/gpu/drm/vc4/vc4_v3d.c
···
441
441
vc4->v3d = v3d;
442
442
v3d->vc4 = vc4;
443
443
444
-
v3d->clk = devm_clk_get(dev, NULL);
445
-
if (IS_ERR(v3d->clk)) {
446
-
int ret = PTR_ERR(v3d->clk);
447
-
448
-
if (ret == -ENOENT) {
449
-
/* bcm2835 didn't have a clock reference in the DT. */
450
-
ret = 0;
451
-
v3d->clk = NULL;
452
-
} else {
453
-
if (ret != -EPROBE_DEFER)
454
-
dev_err(dev, "Failed to get V3D clock: %d\n",
455
-
ret);
456
-
return ret;
457
-
}
458
-
}
444
+
v3d->clk = devm_clk_get_optional(dev, NULL);
445
+
if (IS_ERR(v3d->clk))
446
+
return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n");
459
447
460
448
ret = platform_get_irq(pdev, 0);
461
449
if (ret < 0)
···
459
471
return ret;
460
472
461
473
if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
462
-
DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
463
-
V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
474
+
drm_err(drm, "V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
475
+
V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
464
476
ret = -EINVAL;
465
477
goto err_put_runtime_pm;
466
478
}
···
473
485
474
486
ret = vc4_irq_install(drm, vc4->irq);
475
487
if (ret) {
476
-
DRM_ERROR("Failed to install IRQ handler\n");
488
+
drm_err(drm, "Failed to install IRQ handler\n");
477
489
goto err_put_runtime_pm;
478
490
}
479
491
+4
-4
drivers/gpu/drm/vc4/vc4_validate.c
+4
-4
drivers/gpu/drm/vc4/vc4_validate.c
···
65
65
case 8:
66
66
return 2;
67
67
default:
68
-
DRM_ERROR("unknown cpp: %d\n", cpp);
68
+
pr_err("unknown cpp: %d\n", cpp);
69
69
return 1;
70
70
}
71
71
}
···
82
82
case 8:
83
83
return 4;
84
84
default:
85
-
DRM_ERROR("unknown cpp: %d\n", cpp);
85
+
pr_err("unknown cpp: %d\n", cpp);
86
86
return 1;
87
87
}
88
88
}
···
390
390
bin_slot = vc4_v3d_get_bin_slot(vc4);
391
391
if (bin_slot < 0) {
392
392
if (bin_slot != -EINTR && bin_slot != -ERESTARTSYS) {
393
-
DRM_ERROR("Failed to allocate binner memory: %d\n",
394
-
bin_slot);
393
+
drm_err(dev, "Failed to allocate binner memory: %d\n",
394
+
bin_slot);
395
395
}
396
396
return bin_slot;
397
397
}
+5
-5
drivers/gpu/drm/vc4/vc4_vec.c
+5
-5
drivers/gpu/drm/vc4/vc4_vec.c
···
557
557
558
558
ret = pm_runtime_put(&vec->pdev->dev);
559
559
if (ret < 0) {
560
-
DRM_ERROR("Failed to release power domain: %d\n", ret);
560
+
drm_err(drm, "Failed to release power domain: %d\n", ret);
561
561
goto err_dev_exit;
562
562
}
563
563
···
591
591
592
592
ret = pm_runtime_resume_and_get(&vec->pdev->dev);
593
593
if (ret < 0) {
594
-
DRM_ERROR("Failed to retain power domain: %d\n", ret);
594
+
drm_err(drm, "Failed to retain power domain: %d\n", ret);
595
595
goto err_dev_exit;
596
596
}
597
597
···
604
604
*/
605
605
ret = clk_set_rate(vec->clock, 108000000);
606
606
if (ret) {
607
-
DRM_ERROR("Failed to set clock rate: %d\n", ret);
607
+
drm_err(drm, "Failed to set clock rate: %d\n", ret);
608
608
goto err_put_runtime_pm;
609
609
}
610
610
611
611
ret = clk_prepare_enable(vec->clock);
612
612
if (ret) {
613
-
DRM_ERROR("Failed to turn on core clock: %d\n", ret);
613
+
drm_err(drm, "Failed to turn on core clock: %d\n", ret);
614
614
goto err_put_runtime_pm;
615
615
}
616
616
···
806
806
if (IS_ERR(vec->clock)) {
807
807
ret = PTR_ERR(vec->clock);
808
808
if (ret != -EPROBE_DEFER)
809
-
DRM_ERROR("Failed to get clock: %d\n", ret);
809
+
drm_err(drm, "Failed to get clock: %d\n", ret);
810
810
return ret;
811
811
}
812
812
+2
include/drm/drm_mipi_dsi.h
+2
include/drm/drm_mipi_dsi.h
···
375
375
u16 start, u16 end);
376
376
void mipi_dsi_dcs_set_page_address_multi(struct mipi_dsi_multi_context *ctx,
377
377
u16 start, u16 end);
378
+
void mipi_dsi_dcs_set_tear_scanline_multi(struct mipi_dsi_multi_context *ctx,
379
+
u16 scanline);
378
380
379
381
/**
380
382
* mipi_dsi_generic_write_seq - transmit data using a generic write packet
+12
include/linux/string.h
+12
include/linux/string.h
···
279
279
void *memchr_inv(const void *s, int c, size_t n);
280
280
char *strreplace(char *str, char old, char new);
281
281
282
+
/**
283
+
* mem_is_zero - Check if an area of memory is all 0's.
284
+
* @s: The memory area
285
+
* @n: The size of the area
286
+
*
287
+
* Return: True if the area of memory is all 0's.
288
+
*/
289
+
static inline bool mem_is_zero(const void *s, size_t n)
290
+
{
291
+
return !memchr_inv(s, 0, n);
292
+
}
293
+
282
294
extern void kfree_const(const void *x);
283
295
284
296
extern char *kstrdup(const char *s, gfp_t gfp) __malloc;