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clk: qcom: ipq9574: remove q6 bring up clocks

Q6 firmware takes care of bringup clocks, so remove them from gcc driver.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Link: https://lore.kernel.org/r/20240820055618.267554-3-quic_gokulsri@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Manikanta Mylavarapu and committed by
Bjorn Andersson fa1d5254 bef2902f

-326
-326
drivers/clk/qcom/gcc-ipq9574.c
··· 2645 2645 }, 2646 2646 }; 2647 2647 2648 - static struct clk_branch gcc_q6ss_boot_clk = { 2649 - .halt_reg = 0x25080, 2650 - .halt_check = BRANCH_HALT_SKIP, 2651 - .clkr = { 2652 - .enable_reg = 0x25080, 2653 - .enable_mask = BIT(0), 2654 - .hw.init = &(const struct clk_init_data) { 2655 - .name = "gcc_q6ss_boot_clk", 2656 - .parent_hws = (const struct clk_hw *[]) { 2657 - &system_noc_bfdcd_clk_src.clkr.hw 2658 - }, 2659 - .num_parents = 1, 2660 - .flags = CLK_SET_RATE_PARENT, 2661 - .ops = &clk_branch2_ops, 2662 - }, 2663 - }, 2664 - }; 2665 - 2666 2648 static struct clk_branch gcc_nssnoc_snoc_clk = { 2667 2649 .halt_reg = 0x17028, 2668 2650 .clkr = { ··· 2715 2733 }, 2716 2734 }; 2717 2735 2718 - static struct clk_branch gcc_q6_ahb_clk = { 2719 - .halt_reg = 0x25014, 2720 - .clkr = { 2721 - .enable_reg = 0x25014, 2722 - .enable_mask = BIT(0), 2723 - .hw.init = &(const struct clk_init_data) { 2724 - .name = "gcc_q6_ahb_clk", 2725 - .parent_hws = (const struct clk_hw *[]) { 2726 - &wcss_ahb_clk_src.clkr.hw 2727 - }, 2728 - .num_parents = 1, 2729 - .flags = CLK_SET_RATE_PARENT, 2730 - .ops = &clk_branch2_ops, 2731 - }, 2732 - }, 2733 - }; 2734 - 2735 - static struct clk_branch gcc_q6_ahb_s_clk = { 2736 - .halt_reg = 0x25018, 2737 - .clkr = { 2738 - .enable_reg = 0x25018, 2739 - .enable_mask = BIT(0), 2740 - .hw.init = &(const struct clk_init_data) { 2741 - .name = "gcc_q6_ahb_s_clk", 2742 - .parent_hws = (const struct clk_hw *[]) { 2743 - &wcss_ahb_clk_src.clkr.hw 2744 - }, 2745 - .num_parents = 1, 2746 - .flags = CLK_SET_RATE_PARENT, 2747 - .ops = &clk_branch2_ops, 2748 - }, 2749 - }, 2750 - }; 2751 - 2752 - static struct clk_branch gcc_wcss_ecahb_clk = { 2753 - .halt_reg = 0x25058, 2754 - .clkr = { 2755 - .enable_reg = 0x25058, 2756 - .enable_mask = BIT(0), 2757 - .hw.init = &(const struct clk_init_data) { 2758 - .name = "gcc_wcss_ecahb_clk", 2759 - .parent_hws = (const struct clk_hw *[]) { 2760 - &wcss_ahb_clk_src.clkr.hw 2761 - }, 2762 - .num_parents = 1, 2763 - .flags = CLK_SET_RATE_PARENT, 2764 - .ops = &clk_branch2_ops, 2765 - }, 2766 - }, 2767 - }; 2768 - 2769 - static struct clk_branch gcc_wcss_acmt_clk = { 2770 - .halt_reg = 0x2505c, 2771 - .clkr = { 2772 - .enable_reg = 0x2505c, 2773 - .enable_mask = BIT(0), 2774 - .hw.init = &(const struct clk_init_data) { 2775 - .name = "gcc_wcss_acmt_clk", 2776 - .parent_hws = (const struct clk_hw *[]) { 2777 - &wcss_ahb_clk_src.clkr.hw 2778 - }, 2779 - .num_parents = 1, 2780 - .flags = CLK_SET_RATE_PARENT, 2781 - .ops = &clk_branch2_ops, 2782 - }, 2783 - }, 2784 - }; 2785 - 2786 - static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { 2787 - .halt_reg = 0x2e030, 2788 - .clkr = { 2789 - .enable_reg = 0x2e030, 2790 - .enable_mask = BIT(0), 2791 - .hw.init = &(const struct clk_init_data) { 2792 - .name = "gcc_sys_noc_wcss_ahb_clk", 2793 - .parent_hws = (const struct clk_hw *[]) { 2794 - &wcss_ahb_clk_src.clkr.hw 2795 - }, 2796 - .num_parents = 1, 2797 - .flags = CLK_SET_RATE_PARENT, 2798 - .ops = &clk_branch2_ops, 2799 - }, 2800 - }, 2801 - }; 2802 - 2803 2736 static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = { 2804 2737 F(24000000, P_XO, 1, 0, 0), 2805 2738 F(133333333, P_GPLL0, 6, 0, 0), ··· 2735 2838 }, 2736 2839 }; 2737 2840 2738 - static struct clk_branch gcc_anoc_wcss_axi_m_clk = { 2739 - .halt_reg = 0x2e0a8, 2740 - .clkr = { 2741 - .enable_reg = 0x2e0a8, 2742 - .enable_mask = BIT(0), 2743 - .hw.init = &(const struct clk_init_data) { 2744 - .name = "gcc_anoc_wcss_axi_m_clk", 2745 - .parent_hws = (const struct clk_hw *[]) { 2746 - &wcss_axi_m_clk_src.clkr.hw 2747 - }, 2748 - .num_parents = 1, 2749 - .flags = CLK_SET_RATE_PARENT, 2750 - .ops = &clk_branch2_ops, 2751 - }, 2752 - }, 2753 - }; 2754 - 2755 2841 static const struct freq_tbl ftbl_qdss_at_clk_src[] = { 2756 2842 F(240000000, P_GPLL4, 5, 0, 0), 2757 2843 { } ··· 2750 2870 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, 2751 2871 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), 2752 2872 .ops = &clk_rcg2_ops, 2753 - }, 2754 - }; 2755 - 2756 - static struct clk_branch gcc_q6ss_atbm_clk = { 2757 - .halt_reg = 0x2501c, 2758 - .clkr = { 2759 - .enable_reg = 0x2501c, 2760 - .enable_mask = BIT(0), 2761 - .hw.init = &(const struct clk_init_data) { 2762 - .name = "gcc_q6ss_atbm_clk", 2763 - .parent_hws = (const struct clk_hw *[]) { 2764 - &qdss_at_clk_src.clkr.hw 2765 - }, 2766 - .num_parents = 1, 2767 - .flags = CLK_SET_RATE_PARENT, 2768 - .ops = &clk_branch2_ops, 2769 - }, 2770 - }, 2771 - }; 2772 - 2773 - static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { 2774 - .halt_reg = 0x2503c, 2775 - .clkr = { 2776 - .enable_reg = 0x2503c, 2777 - .enable_mask = BIT(0), 2778 - .hw.init = &(const struct clk_init_data) { 2779 - .name = "gcc_wcss_dbg_ifc_atb_clk", 2780 - .parent_hws = (const struct clk_hw *[]) { 2781 - &qdss_at_clk_src.clkr.hw 2782 - }, 2783 - .num_parents = 1, 2784 - .flags = CLK_SET_RATE_PARENT, 2785 - .ops = &clk_branch2_ops, 2786 - }, 2787 2873 }, 2788 2874 }; 2789 2875 ··· 2989 3143 }, 2990 3144 }; 2991 3145 2992 - static struct clk_branch gcc_q6_tsctr_1to2_clk = { 2993 - .halt_reg = 0x25020, 2994 - .clkr = { 2995 - .enable_reg = 0x25020, 2996 - .enable_mask = BIT(0), 2997 - .hw.init = &(const struct clk_init_data) { 2998 - .name = "gcc_q6_tsctr_1to2_clk", 2999 - .parent_hws = (const struct clk_hw *[]) { 3000 - &qdss_tsctr_div2_clk_src.hw 3001 - }, 3002 - .num_parents = 1, 3003 - .flags = CLK_SET_RATE_PARENT, 3004 - .ops = &clk_branch2_ops, 3005 - }, 3006 - }, 3007 - }; 3008 - 3009 - static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { 3010 - .halt_reg = 0x25040, 3011 - .clkr = { 3012 - .enable_reg = 0x25040, 3013 - .enable_mask = BIT(0), 3014 - .hw.init = &(const struct clk_init_data) { 3015 - .name = "gcc_wcss_dbg_ifc_nts_clk", 3016 - .parent_hws = (const struct clk_hw *[]) { 3017 - &qdss_tsctr_div2_clk_src.hw 3018 - }, 3019 - .num_parents = 1, 3020 - .flags = CLK_SET_RATE_PARENT, 3021 - .ops = &clk_branch2_ops, 3022 - }, 3023 - }, 3024 - }; 3025 - 3026 3146 static struct clk_branch gcc_qdss_tsctr_div2_clk = { 3027 3147 .halt_reg = 0x2d044, 3028 3148 .clkr = { ··· 3163 3351 }, 3164 3352 }; 3165 3353 3166 - static struct clk_branch gcc_q6ss_pclkdbg_clk = { 3167 - .halt_reg = 0x25024, 3168 - .clkr = { 3169 - .enable_reg = 0x25024, 3170 - .enable_mask = BIT(0), 3171 - .hw.init = &(const struct clk_init_data) { 3172 - .name = "gcc_q6ss_pclkdbg_clk", 3173 - .parent_hws = (const struct clk_hw *[]) { 3174 - &qdss_dap_sync_clk_src.hw 3175 - }, 3176 - .num_parents = 1, 3177 - .flags = CLK_SET_RATE_PARENT, 3178 - .ops = &clk_branch2_ops, 3179 - }, 3180 - }, 3181 - }; 3182 - 3183 - static struct clk_branch gcc_q6ss_trig_clk = { 3184 - .halt_reg = 0x25068, 3185 - .clkr = { 3186 - .enable_reg = 0x25068, 3187 - .enable_mask = BIT(0), 3188 - .hw.init = &(const struct clk_init_data) { 3189 - .name = "gcc_q6ss_trig_clk", 3190 - .parent_hws = (const struct clk_hw *[]) { 3191 - &qdss_dap_sync_clk_src.hw 3192 - }, 3193 - .num_parents = 1, 3194 - .flags = CLK_SET_RATE_PARENT, 3195 - .ops = &clk_branch2_ops, 3196 - }, 3197 - }, 3198 - }; 3199 - 3200 - static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { 3201 - .halt_reg = 0x25038, 3202 - .clkr = { 3203 - .enable_reg = 0x25038, 3204 - .enable_mask = BIT(0), 3205 - .hw.init = &(const struct clk_init_data) { 3206 - .name = "gcc_wcss_dbg_ifc_apb_clk", 3207 - .parent_hws = (const struct clk_hw *[]) { 3208 - &qdss_dap_sync_clk_src.hw 3209 - }, 3210 - .num_parents = 1, 3211 - .flags = CLK_SET_RATE_PARENT, 3212 - .ops = &clk_branch2_ops, 3213 - }, 3214 - }, 3215 - }; 3216 - 3217 - static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { 3218 - .halt_reg = 0x25044, 3219 - .clkr = { 3220 - .enable_reg = 0x25044, 3221 - .enable_mask = BIT(0), 3222 - .hw.init = &(const struct clk_init_data) { 3223 - .name = "gcc_wcss_dbg_ifc_dapbus_clk", 3224 - .parent_hws = (const struct clk_hw *[]) { 3225 - &qdss_dap_sync_clk_src.hw 3226 - }, 3227 - .num_parents = 1, 3228 - .flags = CLK_SET_RATE_PARENT, 3229 - .ops = &clk_branch2_ops, 3230 - }, 3231 - }, 3232 - }; 3233 - 3234 3354 static struct clk_branch gcc_qdss_dap_clk = { 3235 3355 .halt_reg = 0x2d058, 3236 3356 .clkr = { ··· 3281 3537 .parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep, 3282 3538 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep), 3283 3539 .ops = &clk_rcg2_ops, 3284 - }, 3285 - }; 3286 - 3287 - static struct clk_branch gcc_q6_axim_clk = { 3288 - .halt_reg = 0x2500c, 3289 - .clkr = { 3290 - .enable_reg = 0x2500c, 3291 - .enable_mask = BIT(0), 3292 - .hw.init = &(const struct clk_init_data) { 3293 - .name = "gcc_q6_axim_clk", 3294 - .parent_hws = (const struct clk_hw *[]) { 3295 - &q6_axi_clk_src.clkr.hw 3296 - }, 3297 - .num_parents = 1, 3298 - .flags = CLK_SET_RATE_PARENT, 3299 - .ops = &clk_branch2_ops, 3300 - }, 3301 - }, 3302 - }; 3303 - 3304 - static struct clk_branch gcc_wcss_q6_tbu_clk = { 3305 - .halt_reg = 0x12050, 3306 - .halt_check = BRANCH_HALT_DELAY, 3307 - .clkr = { 3308 - .enable_reg = 0xb00c, 3309 - .enable_mask = BIT(6), 3310 - .hw.init = &(const struct clk_init_data) { 3311 - .name = "gcc_wcss_q6_tbu_clk", 3312 - .parent_hws = (const struct clk_hw *[]) { 3313 - &q6_axi_clk_src.clkr.hw 3314 - }, 3315 - .num_parents = 1, 3316 - .flags = CLK_SET_RATE_PARENT, 3317 - .ops = &clk_branch2_ops, 3318 - }, 3319 - }, 3320 - }; 3321 - 3322 - static struct clk_branch gcc_mem_noc_q6_axi_clk = { 3323 - .halt_reg = 0x19010, 3324 - .clkr = { 3325 - .enable_reg = 0x19010, 3326 - .enable_mask = BIT(0), 3327 - .hw.init = &(const struct clk_init_data) { 3328 - .name = "gcc_mem_noc_q6_axi_clk", 3329 - .parent_hws = (const struct clk_hw *[]) { 3330 - &q6_axi_clk_src.clkr.hw 3331 - }, 3332 - .num_parents = 1, 3333 - .flags = CLK_SET_RATE_PARENT, 3334 - .ops = &clk_branch2_ops, 3335 - }, 3336 3540 }, 3337 3541 }; 3338 3542 ··· 3833 4141 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 3834 4142 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, 3835 4143 [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, 3836 - [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, 3837 - [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, 3838 - [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, 3839 - [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, 3840 - [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, 3841 4144 [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, 3842 - [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, 3843 4145 [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, 3844 - [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, 3845 - [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, 3846 4146 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 3847 4147 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 3848 4148 [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, ··· 3847 4163 [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, 3848 4164 [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, 3849 4165 [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, 3850 - [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, 3851 - [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, 3852 4166 [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, 3853 4167 [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, 3854 4168 [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, 3855 4169 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 3856 4170 [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, 3857 4171 [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr, 3858 - [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, 3859 - [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, 3860 - [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, 3861 - [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, 3862 4172 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 3863 4173 [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, 3864 4174 [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, 3865 4175 [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, 3866 4176 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 3867 4177 [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, 3868 - [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, 3869 - [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, 3870 - [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, 3871 4178 [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, 3872 4179 [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr, 3873 4180 [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, ··· 3882 4207 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 3883 4208 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, 3884 4209 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 3885 - [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr, 3886 4210 [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr, 3887 4211 [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr, 3888 4212 [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,