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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
fpga: dfl-pci: locate DFLs by PCIe vendor specific capability
A PCIe vendor specific extended capability is introduced by Intel to
specify the start of a number of DFLs.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Link: https://lore.kernel.org/r/20210107043714.991646-3-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Matthew Gerlach
and committed by
Greg Kroah-Hartman
fa41d105
3e265f83
+113
-1
+27
Documentation/fpga/dfl.rst
+27
Documentation/fpga/dfl.rst
···
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FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
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could be a reference.
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Location of DFLs on a PCI Device
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===========================
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The original method for finding a DFL on a PCI device assumed the start of the
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first DFL to offset 0 of bar 0. If the first node of the DFL is an FME,
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then further DFLs in the port(s) are specified in FME header registers.
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Alternatively, a PCIe vendor specific capability structure can be used to
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specify the location of all the DFLs on the device, providing flexibility
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for the type of starting node in the DFL. Intel has reserved the
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VSEC ID of 0x43 for this purpose. The vendor specific
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data begins with a 4 byte vendor specific register for the number of DFLs followed 4 byte
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Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR register
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indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are
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zero.
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+----------------------------+
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|31 Number of DFLS 0|
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+----------------------------+
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|31 Offset 3|2 BIR 0|
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+----------------------------+
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. . .
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+----------------------------+
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|31 Offset 3|2 BIR 0|
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+----------------------------+
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Being able to specify more than one DFL per BAR has been considered, but it
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was determined the use case did not provide value. Specifying a single DFL
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per BAR simplifies the implementation and allows for extra error checking.
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Open discussion
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===============
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drivers/fpga/dfl-pci.c
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-1
drivers/fpga/dfl-pci.c
···
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#define DRV_VERSION "0.8"
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#define DRV_NAME "dfl-pci"
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#define PCI_VSEC_ID_INTEL_DFLS 0x43
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#define PCI_VNDR_DFLS_CNT 0x8
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#define PCI_VNDR_DFLS_RES 0xc
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#define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0)
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#define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3)
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struct cci_drvdata {
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struct dfl_fpga_cdev *cdev; /* container device */
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};
···
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table[i] = pci_irq_vector(pcidev, i);
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return table;
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}
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static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info)
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{
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u32 bir, offset, vndr_hdr, dfl_cnt, dfl_res;
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int dfl_res_off, i, bars, voff = 0;
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resource_size_t start, len;
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while ((voff = pci_find_next_ext_capability(pcidev, voff, PCI_EXT_CAP_ID_VNDR))) {
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vndr_hdr = 0;
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pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, &vndr_hdr);
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if (PCI_VNDR_HEADER_ID(vndr_hdr) == PCI_VSEC_ID_INTEL_DFLS &&
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pcidev->vendor == PCI_VENDOR_ID_INTEL)
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break;
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}
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if (!voff) {
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dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__);
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return -ENODEV;
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}
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dfl_cnt = 0;
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pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt);
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if (dfl_cnt > PCI_STD_NUM_BARS) {
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dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n",
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__func__, dfl_cnt, PCI_STD_NUM_BARS);
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return -EINVAL;
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}
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dfl_res_off = voff + PCI_VNDR_DFLS_RES;
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if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) {
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dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n",
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__func__);
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return -EINVAL;
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}
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for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) {
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dfl_res = GENMASK(31, 0);
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pci_read_config_dword(pcidev, dfl_res_off, &dfl_res);
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bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK;
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if (bir >= PCI_STD_NUM_BARS) {
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dev_err(&pcidev->dev, "%s bad bir number %d\n",
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__func__, bir);
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return -EINVAL;
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}
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if (bars & BIT(bir)) {
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dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n",
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__func__, bir);
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return -EINVAL;
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}
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bars |= BIT(bir);
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len = pci_resource_len(pcidev, bir);
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offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
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if (offset >= len) {
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dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n",
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__func__, offset, &len);
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return -EINVAL;
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}
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dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset);
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len -= offset;
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start = pci_resource_start(pcidev, bir) + offset;
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dfl_fpga_enum_info_add_dfl(info, start, len);
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}
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return 0;
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}
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/* default method of finding dfls starting at offset 0 of bar 0 */
···
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goto irq_free_exit;
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}
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-
ret = find_dfls_by_default(pcidev, info);
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ret = find_dfls_by_vsec(pcidev, info);
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if (ret == -ENODEV)
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ret = find_dfls_by_default(pcidev, info);
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if (ret)
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goto irq_free_exit;
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