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linux
Merge branch 'net-phy-realtek-pair-order-and-polarity'
Damien Dejean says:
====================
net: phy: realtek: pair order and polarity
The RTL8224 PHY gives the manufacturer some flexbility with the pair
order and polarity to ease the wiring on the PCB. Then the correct pair
order and pair polarity must be provided to the PHY to function
properly. This series adds the support to configure the pair order and
the pair polarity to the Realtek PHY driver.
====================
Link: https://patch.msgid.link/20260318215502.106528-1-dam.dejean@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+111
+14
Documentation/devicetree/bindings/net/ethernet-phy.yaml
+14
Documentation/devicetree/bindings/net/ethernet-phy.yaml
···
126
126
e.g. wrong bootstrap configuration caused by issues in PCB
127
127
layout design.
128
128
129
+
enet-phy-pair-order:
130
+
$ref: /schemas/types.yaml#/definitions/uint32
131
+
enum: [0, 1]
132
+
description:
133
+
For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA).
134
+
135
+
enet-phy-pair-polarity:
136
+
$ref: /schemas/types.yaml#/definitions/uint32
137
+
maximum: 0xf
138
+
description:
139
+
A bitmap to describe pair polarity swap. Bit 0 to swap polarity of pair A,
140
+
bit 1 to swap polarity of pair B, bit 2 to swap polarity of pair C and bit
141
+
3 to swap polarity of pair D.
142
+
129
143
eee-broken-100tx:
130
144
$ref: /schemas/types.yaml#/definitions/flag
131
145
description:
+1
drivers/net/phy/realtek/Kconfig
+1
drivers/net/phy/realtek/Kconfig
+96
drivers/net/phy/realtek/realtek_main.c
+96
drivers/net/phy/realtek/realtek_main.c
···
171
171
172
172
#define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4)
173
173
174
+
#define RTL8224_VND1_MDI_PAIR_SWAP 0xa90
175
+
#define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94
176
+
174
177
#define RTL8366RB_POWER_SAVE 0x15
175
178
#define RTL8366RB_POWER_SAVE_ON BIT(12)
176
179
···
1823
1820
return rtl8224_cable_test_report(phydev, finished);
1824
1821
}
1825
1822
1823
+
static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad,
1824
+
u32 regnum, u16 mask, u16 set)
1825
+
{
1826
+
int val, ret;
1827
+
1828
+
phy_lock_mdio_bus(phydev);
1829
+
1830
+
val = __phy_package_read_mmd(phydev, 0, devad, regnum);
1831
+
if (val < 0) {
1832
+
ret = val;
1833
+
goto exit;
1834
+
}
1835
+
1836
+
val &= ~mask;
1837
+
val |= set;
1838
+
1839
+
ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val);
1840
+
1841
+
exit:
1842
+
phy_unlock_mdio_bus(phydev);
1843
+
return ret;
1844
+
}
1845
+
1846
+
static int rtl8224_mdi_config_order(struct phy_device *phydev)
1847
+
{
1848
+
struct device_node *np = phydev->mdio.dev.of_node;
1849
+
u8 port_offset = phydev->mdio.addr & 3;
1850
+
u32 order = 0;
1851
+
int ret;
1852
+
1853
+
ret = of_property_read_u32(np, "enet-phy-pair-order", &order);
1854
+
1855
+
/* Do nothing in case the property is not present */
1856
+
if (ret == -EINVAL || ret == -ENOSYS)
1857
+
return 0;
1858
+
1859
+
if (ret)
1860
+
return ret;
1861
+
1862
+
if (order & ~1)
1863
+
return -EINVAL;
1864
+
1865
+
return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1,
1866
+
RTL8224_VND1_MDI_PAIR_SWAP,
1867
+
BIT(port_offset),
1868
+
order ? BIT(port_offset) : 0);
1869
+
}
1870
+
1871
+
static int rtl8224_mdi_config_polarity(struct phy_device *phydev)
1872
+
{
1873
+
struct device_node *np = phydev->mdio.dev.of_node;
1874
+
u8 offset = (phydev->mdio.addr & 3) * 4;
1875
+
u32 polarity = 0;
1876
+
int ret;
1877
+
1878
+
ret = of_property_read_u32(np, "enet-phy-pair-polarity", &polarity);
1879
+
1880
+
/* Do nothing if the property is not present */
1881
+
if (ret == -EINVAL || ret == -ENOSYS)
1882
+
return 0;
1883
+
1884
+
if (ret)
1885
+
return ret;
1886
+
1887
+
if (polarity & ~0xf)
1888
+
return -EINVAL;
1889
+
1890
+
return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1,
1891
+
RTL8224_VND1_MDI_POLARITY_SWAP,
1892
+
0xf << offset,
1893
+
polarity << offset);
1894
+
}
1895
+
1896
+
static int rtl8224_config_init(struct phy_device *phydev)
1897
+
{
1898
+
int ret;
1899
+
1900
+
ret = rtl8224_mdi_config_order(phydev);
1901
+
if (ret)
1902
+
return ret;
1903
+
1904
+
return rtl8224_mdi_config_polarity(phydev);
1905
+
}
1906
+
1907
+
static int rtl8224_probe(struct phy_device *phydev)
1908
+
{
1909
+
/* Chip exposes 4 ports, join all of them in the same package */
1910
+
return devm_phy_package_join(&phydev->mdio.dev, phydev,
1911
+
phydev->mdio.addr & ~3, 0);
1912
+
}
1913
+
1826
1914
static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1827
1915
{
1828
1916
int val;
···
2489
2395
PHY_ID_MATCH_EXACT(0x001ccad0),
2490
2396
.name = "RTL8224 2.5Gbps PHY",
2491
2397
.flags = PHY_POLL_CABLE_TEST,
2398
+
.probe = rtl8224_probe,
2399
+
.config_init = rtl8224_config_init,
2492
2400
.get_features = rtl822x_c45_get_features,
2493
2401
.config_aneg = rtl822x_c45_config_aneg,
2494
2402
.read_status = rtl822x_c45_read_status,