Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"This is a rather large update post rc1 due to the final steps of
cleanups and API changes which had to wait for the preparatory patches
to hit your tree.
- Regression fixes for ARM GIC irqchips
- Regression fixes and lockdep anotations for renesas irq chips
- The leftovers of the cleanup and preparatory patches which have
been ignored by maintainers
- Final conversions of the newly merged users of obsolete APIs
- Final removal of obsolete APIs
- Final removal of ARM artifacts which had been introduced during the
conversion of ARM to the generic interrupt code.
- Final split of the irq_data into chip specific and common data to
reflect the needs of hierarchical irq domains.
- Treewide removal of the first argument of interrupt flow handlers,
i.e. the irq number, which is not used by the majority of handlers
and simple to retrieve from the other argument the irq descriptor.
- A few comment updates and build warning fixes"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits)
arm64: Remove ununsed set_irq_flags
ARM: Remove ununsed set_irq_flags
sh: Kill off set_irq_flags usage
irqchip: Kill off set_irq_flags usage
gpu/drm: Kill off set_irq_flags usage
genirq: Remove irq argument from irq flow handlers
genirq: Move field 'msi_desc' from irq_data into irq_common_data
genirq: Move field 'affinity' from irq_data into irq_common_data
genirq: Move field 'handler_data' from irq_data into irq_common_data
genirq: Move field 'node' from irq_data into irq_common_data
irqchip/gic-v3: Use IRQD_FORWARDED_TO_VCPU flag
irqchip/gic: Use IRQD_FORWARDED_TO_VCPU flag
genirq: Provide IRQD_FORWARDED_TO_VCPU status flag
genirq: Simplify irq_data_to_desc()
genirq: Remove __irq_set_handler_locked()
pinctrl/pistachio: Use irq_set_handler_locked
gpio: vf610: Use irq_set_handler_locked
powerpc/mpc8xx: Use irq_set_handler_locked()
powerpc/ipic: Use irq_set_handler_locked()
powerpc/cpm2: Use irq_set_handler_locked()
...
+482
-573
+1
-1
arch/alpha/kernel/irq.c
+1
-1
arch/alpha/kernel/irq.c
+1
-1
arch/arc/kernel/mcip.c
+1
-1
arch/arc/kernel/mcip.c
···
252
252
253
253
static int idu_first_irq;
254
254
255
-
static void idu_cascade_isr(unsigned int __core_irq, struct irq_desc *desc)
255
+
static void idu_cascade_isr(struct irq_desc *desc)
256
256
{
257
257
struct irq_domain *domain = irq_desc_get_handler_data(desc);
258
258
unsigned int core_irq = irq_desc_get_irq(desc);
+1
-1
arch/arm/common/it8152.c
+1
-1
arch/arm/common/it8152.c
+1
-1
arch/arm/common/locomo.c
+1
-1
arch/arm/common/locomo.c
+2
-4
arch/arm/common/sa1111.c
+2
-4
arch/arm/common/sa1111.c
···
196
196
* active IRQs causes the interrupt output to pulse, the upper levels
197
197
* will call us again if there are more interrupts to process.
198
198
*/
199
-
static void
200
-
sa1111_irq_handler(unsigned int __irq, struct irq_desc *desc)
199
+
static void sa1111_irq_handler(struct irq_desc *desc)
201
200
{
202
-
unsigned int irq = irq_desc_get_irq(desc);
203
201
unsigned int stat0, stat1, i;
204
202
struct sa1111 *sachip = irq_desc_get_handler_data(desc);
205
203
void __iomem *mapbase = sachip->base + SA1111_INTC;
···
212
214
sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1);
213
215
214
216
if (stat0 == 0 && stat1 == 0) {
215
-
do_bad_IRQ(irq, desc);
217
+
do_bad_IRQ(desc);
216
218
return;
217
219
}
218
220
+1
-1
arch/arm/include/asm/hardware/it8152.h
+1
-1
arch/arm/include/asm/hardware/it8152.h
···
106
106
struct pci_dev;
107
107
struct pci_sys_data;
108
108
109
-
extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
109
+
extern void it8152_irq_demux(struct irq_desc *desc);
110
110
extern void it8152_init_irq(void);
111
111
extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
112
112
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
-6
arch/arm/include/asm/hw_irq.h
-6
arch/arm/include/asm/hw_irq.h
···
11
11
pr_crit("unexpected IRQ trap at vector %02x\n", irq);
12
12
}
13
13
14
-
void set_irq_flags(unsigned int irq, unsigned int flags);
15
-
16
-
#define IRQF_VALID (1 << 0)
17
-
#define IRQF_PROBE (1 << 1)
18
-
#define IRQF_NOAUTOEN (1 << 2)
19
-
20
14
#define ARCH_IRQ_INIT_FLAGS (IRQ_NOREQUEST | IRQ_NOPROBE)
21
15
22
16
#endif
+2
-2
arch/arm/include/asm/mach/irq.h
+2
-2
arch/arm/include/asm/mach/irq.h
···
23
23
/*
24
24
* This is for easy migration, but should be changed in the source
25
25
*/
26
-
#define do_bad_IRQ(irq,desc) \
26
+
#define do_bad_IRQ(desc) \
27
27
do { \
28
28
raw_spin_lock(&desc->lock); \
29
-
handle_bad_irq(irq, desc); \
29
+
handle_bad_irq(desc); \
30
30
raw_spin_unlock(&desc->lock); \
31
31
} while(0)
32
32
-20
arch/arm/kernel/irq.c
-20
arch/arm/kernel/irq.c
···
79
79
handle_IRQ(irq, regs);
80
80
}
81
81
82
-
void set_irq_flags(unsigned int irq, unsigned int iflags)
83
-
{
84
-
unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
85
-
86
-
if (irq >= nr_irqs) {
87
-
pr_err("Trying to set irq flags for IRQ%d\n", irq);
88
-
return;
89
-
}
90
-
91
-
if (iflags & IRQF_VALID)
92
-
clr |= IRQ_NOREQUEST;
93
-
if (iflags & IRQF_PROBE)
94
-
clr |= IRQ_NOPROBE;
95
-
if (!(iflags & IRQF_NOAUTOEN))
96
-
clr |= IRQ_NOAUTOEN;
97
-
/* Order is clear bits in "clr" then set bits in "set" */
98
-
irq_modify_status(irq, clr, set & ~clr);
99
-
}
100
-
EXPORT_SYMBOL_GPL(set_irq_flags);
101
-
102
82
void __init init_IRQ(void)
103
83
{
104
84
int ret;
+3
-3
arch/arm/mach-dove/irq.c
+3
-3
arch/arm/mach-dove/irq.c
···
69
69
.irq_ack = pmu_irq_ack,
70
70
};
71
71
72
-
static void pmu_irq_handler(unsigned int __irq, struct irq_desc *desc)
72
+
static void pmu_irq_handler(struct irq_desc *desc)
73
73
{
74
-
unsigned int irq = irq_desc_get_irq(desc);
75
74
unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
75
+
unsigned int irq;
76
76
77
77
cause &= readl(PMU_INTERRUPT_MASK);
78
78
if (cause == 0) {
79
-
do_bad_IRQ(irq, desc);
79
+
do_bad_IRQ(desc);
80
80
return;
81
81
}
82
82
+2
-3
arch/arm/mach-footbridge/isa-irq.c
+2
-3
arch/arm/mach-footbridge/isa-irq.c
···
87
87
.irq_unmask = isa_unmask_pic_hi_irq,
88
88
};
89
89
90
-
static void
91
-
isa_irq_handler(unsigned int irq, struct irq_desc *desc)
90
+
static void isa_irq_handler(struct irq_desc *desc)
92
91
{
93
92
unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
94
93
95
94
if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
96
-
do_bad_IRQ(isa_irq, desc);
95
+
do_bad_IRQ(desc);
97
96
return;
98
97
}
99
98
+1
-1
arch/arm/mach-gemini/gpio.c
+1
-1
arch/arm/mach-gemini/gpio.c
···
126
126
return 0;
127
127
}
128
128
129
-
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
129
+
static void gpio_irq_handler(struct irq_desc *desc)
130
130
{
131
131
unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
132
132
unsigned int gpio_irq_no, irq_stat;
+1
-1
arch/arm/mach-imx/3ds_debugboard.c
+1
-1
arch/arm/mach-imx/3ds_debugboard.c
+1
-1
arch/arm/mach-imx/mach-mx31ads.c
+1
-1
arch/arm/mach-imx/mach-mx31ads.c
+1
-1
arch/arm/mach-iop13xx/msi.c
+1
-1
arch/arm/mach-iop13xx/msi.c
+2
-2
arch/arm/mach-lpc32xx/irq.c
+2
-2
arch/arm/mach-lpc32xx/irq.c
···
370
370
.irq_set_wake = lpc32xx_irq_wake
371
371
};
372
372
373
-
static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
373
+
static void lpc32xx_sic1_handler(struct irq_desc *desc)
374
374
{
375
375
unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
376
376
···
383
383
}
384
384
}
385
385
386
-
static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
386
+
static void lpc32xx_sic2_handler(struct irq_desc *desc)
387
387
{
388
388
unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
389
389
+1
-2
arch/arm/mach-netx/generic.c
+1
-2
arch/arm/mach-netx/generic.c
···
69
69
#define DEBUG_IRQ(fmt...) while (0) {}
70
70
#endif
71
71
72
-
static void
73
-
netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
72
+
static void netx_hif_demux_handler(struct irq_desc *desc)
74
73
{
75
74
unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
76
75
unsigned int stat;
+1
-1
arch/arm/mach-omap1/fpga.c
+1
-1
arch/arm/mach-omap1/fpga.c
+1
-1
arch/arm/mach-omap2/prm_common.c
+1
-1
arch/arm/mach-omap2/prm_common.c
···
102
102
* dispatched accordingly. Clearing of the wakeup events should be
103
103
* done by the SoC specific individual handlers.
104
104
*/
105
-
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
105
+
static void omap_prcm_irq_handler(struct irq_desc *desc)
106
106
{
107
107
unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
108
108
unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
+1
-1
arch/arm/mach-pxa/balloon3.c
+1
-1
arch/arm/mach-pxa/balloon3.c
···
496
496
.irq_unmask = balloon3_unmask_irq,
497
497
};
498
498
499
-
static void balloon3_irq_handler(unsigned int __irq, struct irq_desc *desc)
499
+
static void balloon3_irq_handler(struct irq_desc *desc)
500
500
{
501
501
unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
502
502
balloon3_irq_enabled;
+2
-3
arch/arm/mach-pxa/cm-x2xx-pci.c
+2
-3
arch/arm/mach-pxa/cm-x2xx-pci.c
···
29
29
void __iomem *it8152_base_address;
30
30
static int cmx2xx_it8152_irq_gpio;
31
31
32
-
static void cmx2xx_it8152_irq_demux(unsigned int __irq, struct irq_desc *desc)
32
+
static void cmx2xx_it8152_irq_demux(struct irq_desc *desc)
33
33
{
34
-
unsigned int irq = irq_desc_get_irq(desc);
35
34
/* clear our parent irq */
36
35
desc->irq_data.chip->irq_ack(&desc->irq_data);
37
36
38
-
it8152_irq_demux(irq, desc);
37
+
it8152_irq_demux(desc);
39
38
}
40
39
41
40
void __cmx2xx_pci_init_irq(int irq_gpio)
+1
-1
arch/arm/mach-pxa/lpd270.c
+1
-1
arch/arm/mach-pxa/lpd270.c
+1
-1
arch/arm/mach-pxa/pcm990-baseboard.c
+1
-1
arch/arm/mach-pxa/pcm990-baseboard.c
+1
-1
arch/arm/mach-pxa/viper.c
+1
-1
arch/arm/mach-pxa/viper.c
+1
-1
arch/arm/mach-pxa/zeus.c
+1
-1
arch/arm/mach-pxa/zeus.c
+1
-2
arch/arm/mach-rpc/ecard.c
+1
-2
arch/arm/mach-rpc/ecard.c
+1
-3
arch/arm/mach-s3c24xx/bast-irq.c
+1
-3
arch/arm/mach-s3c24xx/bast-irq.c
+4
-4
arch/arm/mach-s3c64xx/common.c
+4
-4
arch/arm/mach-s3c64xx/common.c
···
388
388
}
389
389
}
390
390
391
-
static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
391
+
static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
392
392
{
393
393
s3c_irq_demux_eint(0, 3);
394
394
}
395
395
396
-
static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
396
+
static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
397
397
{
398
398
s3c_irq_demux_eint(4, 11);
399
399
}
400
400
401
-
static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
401
+
static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
402
402
{
403
403
s3c_irq_demux_eint(12, 19);
404
404
}
405
405
406
-
static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
406
+
static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
407
407
{
408
408
s3c_irq_demux_eint(20, 27);
409
409
}
+1
-1
arch/arm/mach-sa1100/neponset.c
+1
-1
arch/arm/mach-sa1100/neponset.c
···
166
166
* ensure that the IRQ signal is deasserted before returning. This
167
167
* is rather unfortunate.
168
168
*/
169
-
static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
169
+
static void neponset_irq_handler(struct irq_desc *desc)
170
170
{
171
171
struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
172
172
unsigned int irr;
+1
-1
arch/arm/plat-orion/gpio.c
+1
-1
arch/arm/plat-orion/gpio.c
-5
arch/arm64/include/asm/hardirq.h
-5
arch/arm64/include/asm/hardirq.h
+1
-1
arch/avr32/mach-at32ap/extint.c
+1
-1
arch/avr32/mach-at32ap/extint.c
···
144
144
.irq_set_type = eic_set_irq_type,
145
145
};
146
146
147
-
static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
147
+
static void demux_eic_irq(struct irq_desc *desc)
148
148
{
149
149
struct eic *eic = irq_desc_get_handler_data(desc);
150
150
unsigned long status, pending;
+1
-1
arch/avr32/mach-at32ap/pio.c
+1
-1
arch/avr32/mach-at32ap/pio.c
+2
-2
arch/blackfin/include/asm/irq_handler.h
+2
-2
arch/blackfin/include/asm/irq_handler.h
···
60
60
extern void bfin_internal_unmask_irq(unsigned int irq);
61
61
62
62
struct irq_desc;
63
-
extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
64
-
extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
63
+
extern void bfin_demux_mac_status_irq(struct irq_desc *);
64
+
extern void bfin_demux_gpio_irq(struct irq_desc *);
65
65
66
66
#endif
+1
-1
arch/blackfin/kernel/irqchip.c
+1
-1
arch/blackfin/kernel/irqchip.c
+3
-7
arch/blackfin/mach-bf537/ints-priority.c
+3
-7
arch/blackfin/mach-bf537/ints-priority.c
···
89
89
.irq_unmask = bf537_generic_error_unmask_irq,
90
90
};
91
91
92
-
static void bf537_demux_error_irq(unsigned int int_err_irq,
93
-
struct irq_desc *inta_desc)
92
+
static void bf537_demux_error_irq(struct irq_desc *inta_desc)
94
93
{
95
94
int irq = 0;
96
95
···
181
182
.irq_unmask = bf537_mac_rx_unmask_irq,
182
183
};
183
184
184
-
static void bf537_demux_mac_rx_irq(unsigned int __int_irq,
185
-
struct irq_desc *desc)
185
+
static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
186
186
{
187
-
unsigned int int_irq = irq_desc_get_irq(desc);
188
-
189
187
if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
190
188
bfin_handle_irq(IRQ_MAC_RX);
191
189
else
192
-
bfin_demux_gpio_irq(int_irq, desc);
190
+
bfin_demux_gpio_irq(desc);
193
191
}
194
192
#endif
195
193
+2
-3
arch/blackfin/mach-common/ints-priority.c
+2
-3
arch/blackfin/mach-common/ints-priority.c
···
656
656
.irq_set_wake = bfin_mac_status_set_wake,
657
657
};
658
658
659
-
void bfin_demux_mac_status_irq(unsigned int int_err_irq,
660
-
struct irq_desc *inta_desc)
659
+
void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
661
660
{
662
661
int i, irq = 0;
663
662
u32 status = bfin_read_EMAC_SYSTAT();
···
824
825
}
825
826
}
826
827
827
-
void bfin_demux_gpio_irq(unsigned int __inta_irq, struct irq_desc *desc)
828
+
void bfin_demux_gpio_irq(struct irq_desc *desc)
828
829
{
829
830
unsigned int inta_irq = irq_desc_get_irq(desc);
830
831
unsigned int irq;
+1
-1
arch/c6x/platforms/megamod-pic.c
+1
-1
arch/c6x/platforms/megamod-pic.c
+4
-4
arch/m68k/amiga/amiints.c
+4
-4
arch/m68k/amiga/amiints.c
···
46
46
* The builtin Amiga hardware interrupt handlers.
47
47
*/
48
48
49
-
static void ami_int1(unsigned int irq, struct irq_desc *desc)
49
+
static void ami_int1(struct irq_desc *desc)
50
50
{
51
51
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
52
52
···
69
69
}
70
70
}
71
71
72
-
static void ami_int3(unsigned int irq, struct irq_desc *desc)
72
+
static void ami_int3(struct irq_desc *desc)
73
73
{
74
74
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
75
75
···
92
92
}
93
93
}
94
94
95
-
static void ami_int4(unsigned int irq, struct irq_desc *desc)
95
+
static void ami_int4(struct irq_desc *desc)
96
96
{
97
97
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
98
98
···
121
121
}
122
122
}
123
123
124
-
static void ami_int5(unsigned int irq, struct irq_desc *desc)
124
+
static void ami_int5(struct irq_desc *desc)
125
125
{
126
126
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
127
127
+2
-4
arch/m68k/coldfire/intc-5272.c
+2
-4
arch/m68k/coldfire/intc-5272.c
···
143
143
* We need to be careful with the masking/acking due to the side effects
144
144
* of masking an interrupt.
145
145
*/
146
-
static void intc_external_irq(unsigned int __irq, struct irq_desc *desc)
146
+
static void intc_external_irq(struct irq_desc *desc)
147
147
{
148
-
unsigned int irq = irq_desc_get_irq(desc);
149
-
150
148
irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
151
-
handle_simple_irq(irq, desc);
149
+
handle_simple_irq(desc);
152
150
}
153
151
154
152
static struct irq_chip intc_irq_chip = {
+1
-2
arch/m68k/include/asm/irq.h
+1
-2
arch/m68k/include/asm/irq.h
···
64
64
struct pt_regs *));
65
65
extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt);
66
66
extern void m68k_setup_irq_controller(struct irq_chip *,
67
-
void (*handle)(unsigned int irq,
68
-
struct irq_desc *desc),
67
+
void (*handle)(struct irq_desc *desc),
69
68
unsigned int irq, unsigned int cnt);
70
69
71
70
extern unsigned int irq_canonicalize(unsigned int irq);
+1
-1
arch/m68k/include/asm/mac_via.h
+1
-1
arch/m68k/include/asm/mac_via.h
···
261
261
extern void via_irq_disable(int);
262
262
extern void via_nubus_irq_startup(int irq);
263
263
extern void via_nubus_irq_shutdown(int irq);
264
-
extern void via1_irq(unsigned int irq, struct irq_desc *desc);
264
+
extern void via1_irq(struct irq_desc *desc);
265
265
extern void via1_set_head(int);
266
266
extern int via2_scsi_drq_pending(void);
267
267
+1
-1
arch/m68k/mac/baboon.c
+1
-1
arch/m68k/mac/baboon.c
+2
-2
arch/m68k/mac/oss.c
+2
-2
arch/m68k/mac/oss.c
···
63
63
* Handle miscellaneous OSS interrupts.
64
64
*/
65
65
66
-
static void oss_irq(unsigned int __irq, struct irq_desc *desc)
66
+
static void oss_irq(struct irq_desc *desc)
67
67
{
68
68
int events = oss->irq_pending &
69
69
(OSS_IP_IOPSCC | OSS_IP_SCSI | OSS_IP_IOPISM);
···
99
99
* Unlike the VIA/RBV this is on its own autovector interrupt level.
100
100
*/
101
101
102
-
static void oss_nubus_irq(unsigned int irq, struct irq_desc *desc)
102
+
static void oss_nubus_irq(struct irq_desc *desc)
103
103
{
104
104
int events, irq_bit, i;
105
105
+1
-1
arch/m68k/mac/psc.c
+1
-1
arch/m68k/mac/psc.c
···
113
113
* PSC interrupt handler. It's a lot like the VIA interrupt handler.
114
114
*/
115
115
116
-
static void psc_irq(unsigned int __irq, struct irq_desc *desc)
116
+
static void psc_irq(struct irq_desc *desc)
117
117
{
118
118
unsigned int offset = (unsigned int)irq_desc_get_handler_data(desc);
119
119
unsigned int irq = irq_desc_get_irq(desc);
+3
-3
arch/m68k/mac/via.c
+3
-3
arch/m68k/mac/via.c
···
446
446
* via6522.c :-), disable/pending masks added.
447
447
*/
448
448
449
-
void via1_irq(unsigned int irq, struct irq_desc *desc)
449
+
void via1_irq(struct irq_desc *desc)
450
450
{
451
451
int irq_num;
452
452
unsigned char irq_bit, events;
···
467
467
} while (events >= irq_bit);
468
468
}
469
469
470
-
static void via2_irq(unsigned int irq, struct irq_desc *desc)
470
+
static void via2_irq(struct irq_desc *desc)
471
471
{
472
472
int irq_num;
473
473
unsigned char irq_bit, events;
···
493
493
* VIA2 dispatcher as a fast interrupt handler.
494
494
*/
495
495
496
-
void via_nubus_irq(unsigned int irq, struct irq_desc *desc)
496
+
static void via_nubus_irq(struct irq_desc *desc)
497
497
{
498
498
int slot_irq;
499
499
unsigned char slot_bit, events;
+1
-3
arch/metag/kernel/irq.c
+1
-3
arch/metag/kernel/irq.c
···
94
94
"MOV D0.5,%0\n"
95
95
"MOV D1Ar1,%1\n"
96
96
"MOV D1RtP,%2\n"
97
-
"MOV D0Ar2,%3\n"
98
97
"SWAP A0StP,D0.5\n"
99
98
"SWAP PC,D1RtP\n"
100
99
"MOV A0StP,D0.5\n"
101
100
:
102
-
: "r" (isp), "r" (irq), "r" (desc->handle_irq),
103
-
"r" (desc)
101
+
: "r" (isp), "r" (desc), "r" (desc->handle_irq)
104
102
: "memory", "cc", "D1Ar1", "D0Ar2", "D1Ar3", "D0Ar4",
105
103
"D1Ar5", "D0Ar6", "D0Re0", "D1Re0", "D0.4", "D1RtP",
106
104
"D0.5"
+2
-2
arch/mips/alchemy/common/irq.c
+2
-2
arch/mips/alchemy/common/irq.c
···
851
851
852
852
/* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */
853
853
#define DISP(name, base, addr) \
854
-
static void au1000_##name##_dispatch(unsigned int irq, struct irq_desc *d) \
854
+
static void au1000_##name##_dispatch(struct irq_desc *d) \
855
855
{ \
856
856
unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr)); \
857
857
if (likely(r)) \
···
865
865
DISP(ic1r0, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ0INT)
866
866
DISP(ic1r1, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ1INT)
867
867
868
-
static void alchemy_gpic_dispatch(unsigned int irq, struct irq_desc *d)
868
+
static void alchemy_gpic_dispatch(struct irq_desc *d)
869
869
{
870
870
int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
871
871
generic_handle_irq(ALCHEMY_GPIC_INT_BASE + i);
+1
-1
arch/mips/alchemy/devboards/bcsr.c
+1
-1
arch/mips/alchemy/devboards/bcsr.c
···
86
86
/*
87
87
* DB1200/PB1200 CPLD IRQ muxer
88
88
*/
89
-
static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
89
+
static void bcsr_csc_handler(struct irq_desc *d)
90
90
{
91
91
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
92
92
struct irq_chip *chip = irq_desc_get_chip(d);
+1
-1
arch/mips/ath25/ar2315.c
+1
-1
arch/mips/ath25/ar2315.c
+1
-1
arch/mips/ath25/ar5312.c
+1
-1
arch/mips/ath25/ar5312.c
+4
-4
arch/mips/ath79/irq.c
+4
-4
arch/mips/ath79/irq.c
···
26
26
#include "common.h"
27
27
#include "machtypes.h"
28
28
29
-
static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
29
+
static void ath79_misc_irq_handler(struct irq_desc *desc)
30
30
{
31
31
void __iomem *base = ath79_reset_base;
32
32
u32 pending;
···
119
119
irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
120
120
}
121
121
122
-
static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
122
+
static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
123
123
{
124
124
u32 status;
125
125
···
148
148
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
149
149
}
150
150
151
-
static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
151
+
static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
152
152
{
153
153
u32 status;
154
154
···
171
171
}
172
172
}
173
173
174
-
static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
174
+
static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
175
175
{
176
176
u32 status;
177
177
+1
-1
arch/mips/cavium-octeon/octeon-irq.c
+1
-1
arch/mips/cavium-octeon/octeon-irq.c
+2
-2
arch/mips/include/asm/netlogic/common.h
+2
-2
arch/mips/include/asm/netlogic/common.h
···
57
57
#include <asm/mach-netlogic/multi-node.h>
58
58
59
59
struct irq_desc;
60
-
void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
61
-
void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
60
+
void nlm_smp_function_ipi_handler(struct irq_desc *desc);
61
+
void nlm_smp_resched_ipi_handler(struct irq_desc *desc);
62
62
void nlm_smp_irq_init(int hwcpuid);
63
63
void nlm_boot_secondary_cpus(void);
64
64
int nlm_wakeup_secondary_cpus(void);
+1
-1
arch/mips/jz4740/gpio.c
+1
-1
arch/mips/jz4740/gpio.c
+2
-2
arch/mips/netlogic/common/smp.c
+2
-2
arch/mips/netlogic/common/smp.c
···
82
82
}
83
83
84
84
/* IRQ_IPI_SMP_FUNCTION Handler */
85
-
void nlm_smp_function_ipi_handler(unsigned int __irq, struct irq_desc *desc)
85
+
void nlm_smp_function_ipi_handler(struct irq_desc *desc)
86
86
{
87
87
unsigned int irq = irq_desc_get_irq(desc);
88
88
clear_c0_eimr(irq);
···
92
92
}
93
93
94
94
/* IRQ_IPI_SMP_RESCHEDULE handler */
95
-
void nlm_smp_resched_ipi_handler(unsigned int __irq, struct irq_desc *desc)
95
+
void nlm_smp_resched_ipi_handler(struct irq_desc *desc)
96
96
{
97
97
unsigned int irq = irq_desc_get_irq(desc);
98
98
clear_c0_eimr(irq);
+1
-1
arch/mips/pci/pci-ar2315.c
+1
-1
arch/mips/pci/pci-ar2315.c
···
318
318
return 0;
319
319
}
320
320
321
-
static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
321
+
static void ar2315_pci_irq_handler(struct irq_desc *desc)
322
322
{
323
323
struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
324
324
u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
+1
-1
arch/mips/pci/pci-ar71xx.c
+1
-1
arch/mips/pci/pci-ar71xx.c
···
226
226
.write = ar71xx_pci_write_config,
227
227
};
228
228
229
-
static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
229
+
static void ar71xx_pci_irq_handler(struct irq_desc *desc)
230
230
{
231
231
struct ar71xx_pci_controller *apc;
232
232
void __iomem *base = ath79_reset_base;
+1
-1
arch/mips/pci/pci-ar724x.c
+1
-1
arch/mips/pci/pci-ar724x.c
+1
-1
arch/mips/pci/pci-rt3883.c
+1
-1
arch/mips/pci/pci-rt3883.c
···
129
129
rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
130
130
}
131
131
132
-
static void rt3883_pci_irq_handler(unsigned int __irq, struct irq_desc *desc)
132
+
static void rt3883_pci_irq_handler(struct irq_desc *desc)
133
133
{
134
134
struct rt3883_pci_controller *rpc;
135
135
u32 pending;
+1
-1
arch/mips/ralink/irq.c
+1
-1
arch/mips/ralink/irq.c
+9
-14
arch/powerpc/include/asm/qe_ic.h
+9
-14
arch/powerpc/include/asm/qe_ic.h
···
59
59
60
60
#ifdef CONFIG_QUICC_ENGINE
61
61
void qe_ic_init(struct device_node *node, unsigned int flags,
62
-
void (*low_handler)(unsigned int irq, struct irq_desc *desc),
63
-
void (*high_handler)(unsigned int irq, struct irq_desc *desc));
62
+
void (*low_handler)(struct irq_desc *desc),
63
+
void (*high_handler)(struct irq_desc *desc));
64
64
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
65
65
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
66
66
#else
67
67
static inline void qe_ic_init(struct device_node *node, unsigned int flags,
68
-
void (*low_handler)(unsigned int irq, struct irq_desc *desc),
69
-
void (*high_handler)(unsigned int irq, struct irq_desc *desc))
68
+
void (*low_handler)(struct irq_desc *desc),
69
+
void (*high_handler)(struct irq_desc *desc))
70
70
{}
71
71
static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
72
72
{ return 0; }
···
78
78
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
79
79
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
80
80
81
-
static inline void qe_ic_cascade_low_ipic(unsigned int irq,
82
-
struct irq_desc *desc)
81
+
static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
83
82
{
84
83
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
85
84
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
···
87
88
generic_handle_irq(cascade_irq);
88
89
}
89
90
90
-
static inline void qe_ic_cascade_high_ipic(unsigned int irq,
91
-
struct irq_desc *desc)
91
+
static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
92
92
{
93
93
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
94
94
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
···
96
98
generic_handle_irq(cascade_irq);
97
99
}
98
100
99
-
static inline void qe_ic_cascade_low_mpic(unsigned int irq,
100
-
struct irq_desc *desc)
101
+
static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
101
102
{
102
103
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
103
104
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
···
108
111
chip->irq_eoi(&desc->irq_data);
109
112
}
110
113
111
-
static inline void qe_ic_cascade_high_mpic(unsigned int irq,
112
-
struct irq_desc *desc)
114
+
static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
113
115
{
114
116
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
115
117
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
···
120
124
chip->irq_eoi(&desc->irq_data);
121
125
}
122
126
123
-
static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
124
-
struct irq_desc *desc)
127
+
static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
125
128
{
126
129
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
127
130
unsigned int cascade_irq;
+1
-1
arch/powerpc/include/asm/tsi108_pci.h
+1
-1
arch/powerpc/include/asm/tsi108_pci.h
···
39
39
40
40
extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
41
41
extern void tsi108_pci_int_init(struct device_node *node);
42
-
extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
42
+
extern void tsi108_irq_cascade(struct irq_desc *desc);
43
43
extern void tsi108_clear_pci_cfg_error(void);
44
44
45
45
#endif /* _ASM_POWERPC_TSI108_PCI_H */
+1
-1
arch/powerpc/kernel/irq.c
+1
-1
arch/powerpc/kernel/irq.c
···
441
441
442
442
chip = irq_data_get_irq_chip(data);
443
443
444
-
cpumask_and(mask, data->affinity, map);
444
+
cpumask_and(mask, irq_data_get_affinity_mask(data), map);
445
445
if (cpumask_any(mask) >= nr_cpu_ids) {
446
446
pr_warn("Breaking affinity for irq %i\n", irq);
447
447
cpumask_copy(mask, map);
+3
-2
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
+3
-2
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
···
104
104
return irq_linear_revmap(cpld_pic_host, cpld_irq);
105
105
}
106
106
107
-
static void
108
-
cpld_pic_cascade(unsigned int irq, struct irq_desc *desc)
107
+
static void cpld_pic_cascade(struct irq_desc *desc)
109
108
{
109
+
unsigned int irq;
110
+
110
111
irq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
111
112
&cpld_regs->pci_mask);
112
113
if (irq != NO_IRQ) {
+1
-1
arch/powerpc/platforms/52xx/media5200.c
+1
-1
arch/powerpc/platforms/52xx/media5200.c
+1
-1
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+1
-1
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
···
191
191
.irq_set_type = mpc52xx_gpt_irq_set_type,
192
192
};
193
193
194
-
void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
194
+
static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
195
195
{
196
196
struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
197
197
int sub_virq;
+1
-1
arch/powerpc/platforms/52xx/mpc52xx_pic.c
+1
-1
arch/powerpc/platforms/52xx/mpc52xx_pic.c
+1
-1
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+1
-1
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
···
78
78
.irq_disable = pq2ads_pci_mask_irq
79
79
};
80
80
81
-
static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
81
+
static void pq2ads_pci_irq_demux(struct irq_desc *desc)
82
82
{
83
83
struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
84
84
u32 stat, mask, pend;
+1
-1
arch/powerpc/platforms/85xx/common.c
+1
-1
arch/powerpc/platforms/85xx/common.c
···
49
49
return of_platform_bus_probe(NULL, mpc85xx_common_ids, NULL);
50
50
}
51
51
#ifdef CONFIG_CPM2
52
-
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
52
+
static void cpm2_cascade(struct irq_desc *desc)
53
53
{
54
54
struct irq_chip *chip = irq_desc_get_chip(desc);
55
55
int cascade_irq;
+2
-3
arch/powerpc/platforms/85xx/mpc85xx_cds.c
+2
-3
arch/powerpc/platforms/85xx/mpc85xx_cds.c
···
192
192
}
193
193
194
194
#ifdef CONFIG_PPC_I8259
195
-
static void mpc85xx_8259_cascade_handler(unsigned int irq,
196
-
struct irq_desc *desc)
195
+
static void mpc85xx_8259_cascade_handler(struct irq_desc *desc)
197
196
{
198
197
unsigned int cascade_irq = i8259_irq();
199
198
···
201
202
generic_handle_irq(cascade_irq);
202
203
203
204
/* check for any interrupts from the shared IRQ line */
204
-
handle_fasteoi_irq(irq, desc);
205
+
handle_fasteoi_irq(desc);
205
206
}
206
207
207
208
static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
+1
-1
arch/powerpc/platforms/85xx/mpc85xx_ds.c
+1
-1
arch/powerpc/platforms/85xx/mpc85xx_ds.c
···
46
46
#endif
47
47
48
48
#ifdef CONFIG_PPC_I8259
49
-
static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
49
+
static void mpc85xx_8259_cascade(struct irq_desc *desc)
50
50
{
51
51
struct irq_chip *chip = irq_desc_get_chip(desc);
52
52
unsigned int cascade_irq = i8259_irq();
+2
-1
arch/powerpc/platforms/85xx/socrates_fpga_pic.c
+2
-1
arch/powerpc/platforms/85xx/socrates_fpga_pic.c
···
91
91
(irq_hw_number_t)i);
92
92
}
93
93
94
-
void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc)
94
+
static void socrates_fpga_pic_cascade(struct irq_desc *desc)
95
95
{
96
96
struct irq_chip *chip = irq_desc_get_chip(desc);
97
+
unsigned int irq = irq_desc_get_irq(desc);
97
98
unsigned int cascade_irq;
98
99
99
100
/*
+1
-1
arch/powerpc/platforms/86xx/pic.c
+1
-1
arch/powerpc/platforms/86xx/pic.c
···
17
17
#include <asm/i8259.h>
18
18
19
19
#ifdef CONFIG_PPC_I8259
20
-
static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
20
+
static void mpc86xx_8259_cascade(struct irq_desc *desc)
21
21
{
22
22
struct irq_chip *chip = irq_desc_get_chip(desc);
23
23
unsigned int cascade_irq = i8259_irq();
+1
-1
arch/powerpc/platforms/8xx/m8xx_setup.c
+1
-1
arch/powerpc/platforms/8xx/m8xx_setup.c
+1
-1
arch/powerpc/platforms/cell/axon_msi.c
+1
-1
arch/powerpc/platforms/cell/axon_msi.c
···
93
93
dcr_write(msic->dcr_host, dcr_n, val);
94
94
}
95
95
96
-
static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
96
+
static void axon_msi_cascade(struct irq_desc *desc)
97
97
{
98
98
struct irq_chip *chip = irq_desc_get_chip(desc);
99
99
struct axon_msic *msic = irq_desc_get_handler_data(desc);
+2
-1
arch/powerpc/platforms/cell/interrupt.c
+2
-1
arch/powerpc/platforms/cell/interrupt.c
···
99
99
{
100
100
}
101
101
102
-
static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
102
+
static void iic_ioexc_cascade(struct irq_desc *desc)
103
103
{
104
104
struct irq_chip *chip = irq_desc_get_chip(desc);
105
105
struct cbe_iic_regs __iomem *node_iic =
106
106
(void __iomem *)irq_desc_get_handler_data(desc);
107
+
unsigned int irq = irq_desc_get_irq(desc);
107
108
unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
108
109
unsigned long bits, ack;
109
110
int cascade;
+1
-1
arch/powerpc/platforms/cell/spider-pic.c
+1
-1
arch/powerpc/platforms/cell/spider-pic.c
···
199
199
.xlate = spider_host_xlate,
200
200
};
201
201
202
-
static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc)
202
+
static void spider_irq_cascade(struct irq_desc *desc)
203
203
{
204
204
struct irq_chip *chip = irq_desc_get_chip(desc);
205
205
struct spider_pic *pic = irq_desc_get_handler_data(desc);
+1
-1
arch/powerpc/platforms/chrp/setup.c
+1
-1
arch/powerpc/platforms/chrp/setup.c
···
363
363
if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
364
364
}
365
365
366
-
static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
366
+
static void chrp_8259_cascade(struct irq_desc *desc)
367
367
{
368
368
struct irq_chip *chip = irq_desc_get_chip(desc);
369
369
unsigned int cascade_irq = i8259_irq();
+1
-2
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+1
-2
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
···
120
120
return irq_linear_revmap(h, irq);
121
121
}
122
122
123
-
static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
124
-
struct irq_desc *desc)
123
+
static void hlwd_pic_irq_cascade(struct irq_desc *desc)
125
124
{
126
125
struct irq_chip *chip = irq_desc_get_chip(desc);
127
126
struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
+1
-1
arch/powerpc/platforms/embedded6xx/mvme5100.c
+1
-1
arch/powerpc/platforms/embedded6xx/mvme5100.c
···
42
42
static phys_addr_t pci_membase;
43
43
static u_char *restart;
44
44
45
-
static void mvme5100_8259_cascade(unsigned int irq, struct irq_desc *desc)
45
+
static void mvme5100_8259_cascade(struct irq_desc *desc)
46
46
{
47
47
struct irq_chip *chip = irq_desc_get_chip(desc);
48
48
unsigned int cascade_irq = i8259_irq();
+1
-1
arch/powerpc/platforms/pseries/setup.c
+1
-1
arch/powerpc/platforms/pseries/setup.c
···
111
111
fwnmi_active = 1;
112
112
}
113
113
114
-
static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc)
114
+
static void pseries_8259_cascade(struct irq_desc *desc)
115
115
{
116
116
struct irq_chip *chip = irq_desc_get_chip(desc);
117
117
unsigned int cascade_irq = i8259_irq();
+2
-2
arch/powerpc/sysdev/cpm2_pic.c
+2
-2
arch/powerpc/sysdev/cpm2_pic.c
···
155
155
156
156
irqd_set_trigger_type(d, flow_type);
157
157
if (flow_type & IRQ_TYPE_LEVEL_LOW)
158
-
__irq_set_handler_locked(d->irq, handle_level_irq);
158
+
irq_set_handler_locked(d, handle_level_irq);
159
159
else
160
-
__irq_set_handler_locked(d->irq, handle_edge_irq);
160
+
irq_set_handler_locked(d, handle_edge_irq);
161
161
162
162
/* internal IRQ senses are LEVEL_LOW
163
163
* EXT IRQ and Port C IRQ senses are programmable
+1
-1
arch/powerpc/sysdev/ge/ge_pic.c
+1
-1
arch/powerpc/sysdev/ge/ge_pic.c
-2
arch/powerpc/sysdev/ge/ge_pic.h
-2
arch/powerpc/sysdev/ge/ge_pic.h
+2
-2
arch/powerpc/sysdev/ipic.c
+2
-2
arch/powerpc/sysdev/ipic.c
···
624
624
625
625
irqd_set_trigger_type(d, flow_type);
626
626
if (flow_type & IRQ_TYPE_LEVEL_LOW) {
627
-
__irq_set_handler_locked(d->irq, handle_level_irq);
627
+
irq_set_handler_locked(d, handle_level_irq);
628
628
d->chip = &ipic_level_irq_chip;
629
629
} else {
630
-
__irq_set_handler_locked(d->irq, handle_edge_irq);
630
+
irq_set_handler_locked(d, handle_edge_irq);
631
631
d->chip = &ipic_edge_irq_chip;
632
632
}
633
633
+1
-1
arch/powerpc/sysdev/mpc8xx_pic.c
+1
-1
arch/powerpc/sysdev/mpc8xx_pic.c
+1
-1
arch/powerpc/sysdev/mpic.c
+1
-1
arch/powerpc/sysdev/mpic.c
···
1181
1181
}
1182
1182
1183
1183
/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1184
-
static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1184
+
static void mpic_cascade(struct irq_desc *desc)
1185
1185
{
1186
1186
struct irq_chip *chip = irq_desc_get_chip(desc);
1187
1187
struct mpic *mpic = irq_desc_get_handler_data(desc);
+2
-2
arch/powerpc/sysdev/qe_lib/qe_ic.c
+2
-2
arch/powerpc/sysdev/qe_lib/qe_ic.c
···
311
311
}
312
312
313
313
void __init qe_ic_init(struct device_node *node, unsigned int flags,
314
-
void (*low_handler)(unsigned int irq, struct irq_desc *desc),
315
-
void (*high_handler)(unsigned int irq, struct irq_desc *desc))
314
+
void (*low_handler)(struct irq_desc *desc),
315
+
void (*high_handler)(struct irq_desc *desc))
316
316
{
317
317
struct qe_ic *qe_ic;
318
318
struct resource res;
+1
-1
arch/powerpc/sysdev/tsi108_pci.c
+1
-1
arch/powerpc/sysdev/tsi108_pci.c
+1
-1
arch/powerpc/sysdev/uic.c
+1
-1
arch/powerpc/sysdev/uic.c
···
194
194
.xlate = irq_domain_xlate_twocell,
195
195
};
196
196
197
-
void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
197
+
static void uic_irq_cascade(struct irq_desc *desc)
198
198
{
199
199
struct irq_chip *chip = irq_desc_get_chip(desc);
200
200
struct irq_data *idata = irq_desc_get_irq_data(desc);
+1
-1
arch/powerpc/sysdev/xics/ics-opal.c
+1
-1
arch/powerpc/sysdev/xics/ics-opal.c
···
54
54
if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
55
55
return;
56
56
57
-
server = xics_get_irq_server(d->irq, d->affinity, 0);
57
+
server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
58
58
server = ics_opal_mangle_server(server);
59
59
60
60
rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
+1
-1
arch/powerpc/sysdev/xics/ics-rtas.c
+1
-1
arch/powerpc/sysdev/xics/ics-rtas.c
···
47
47
if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
48
48
return;
49
49
50
-
server = xics_get_irq_server(d->irq, d->affinity, 0);
50
+
server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
51
51
52
52
call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hw_irq, server,
53
53
DEFAULT_PRIORITY);
+1
-1
arch/powerpc/sysdev/xilinx_intc.c
+1
-1
arch/powerpc/sysdev/xilinx_intc.c
···
222
222
/*
223
223
* Support code for cascading to 8259 interrupt controllers
224
224
*/
225
-
static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
225
+
static void xilinx_i8259_cascade(struct irq_desc *desc)
226
226
{
227
227
struct irq_chip *chip = irq_desc_get_chip(desc);
228
228
unsigned int cascade_irq = i8259_irq();
+1
-1
arch/sh/boards/mach-se/7343/irq.c
+1
-1
arch/sh/boards/mach-se/7343/irq.c
···
29
29
static void __iomem *se7343_irq_regs;
30
30
struct irq_domain *se7343_irq_domain;
31
31
32
-
static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
32
+
static void se7343_irq_demux(struct irq_desc *desc)
33
33
{
34
34
struct irq_data *data = irq_desc_get_irq_data(desc);
35
35
struct irq_chip *chip = irq_data_get_irq_chip(data);
+1
-1
arch/sh/boards/mach-se/7722/irq.c
+1
-1
arch/sh/boards/mach-se/7722/irq.c
···
28
28
static void __iomem *se7722_irq_regs;
29
29
struct irq_domain *se7722_irq_domain;
30
30
31
-
static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
31
+
static void se7722_irq_demux(struct irq_desc *desc)
32
32
{
33
33
struct irq_data *data = irq_desc_get_irq_data(desc);
34
34
struct irq_chip *chip = irq_data_get_irq_chip(data);
+1
-1
arch/sh/boards/mach-se/7724/irq.c
+1
-1
arch/sh/boards/mach-se/7724/irq.c
+1
-1
arch/sh/boards/mach-x3proto/gpio.c
+1
-1
arch/sh/boards/mach-x3proto/gpio.c
···
60
60
return virq;
61
61
}
62
62
63
-
static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
63
+
static void x3proto_gpio_irq_handler(struct irq_desc *desc)
64
64
{
65
65
struct irq_data *data = irq_desc_get_irq_data(desc);
66
66
struct irq_chip *chip = irq_data_get_irq_chip(data);
+1
-1
arch/sh/cchips/hd6446x/hd64461.c
+1
-1
arch/sh/cchips/hd6446x/hd64461.c
···
56
56
.irq_unmask = hd64461_unmask_irq,
57
57
};
58
58
59
-
static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
59
+
static void hd64461_irq_demux(struct irq_desc *desc)
60
60
{
61
61
unsigned short intv = __raw_readw(HD64461_NIRR);
62
62
unsigned int ext_irq = HD64461_IRQBASE;
+1
-1
arch/sparc/kernel/leon_kernel.c
+1
-1
arch/sparc/kernel/leon_kernel.c
+1
-1
arch/sparc/kernel/leon_pci_grpci1.c
+1
-1
arch/sparc/kernel/leon_pci_grpci1.c
···
357
357
};
358
358
359
359
/* Handle one or multiple IRQs from the PCI core */
360
-
static void grpci1_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
360
+
static void grpci1_pci_flow_irq(struct irq_desc *desc)
361
361
{
362
362
struct grpci1_priv *priv = grpci1priv;
363
363
int i, ack = 0;
+1
-1
arch/sparc/kernel/leon_pci_grpci2.c
+1
-1
arch/sparc/kernel/leon_pci_grpci2.c
···
498
498
};
499
499
500
500
/* Handle one or multiple IRQs from the PCI core */
501
-
static void grpci2_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
501
+
static void grpci2_pci_flow_irq(struct irq_desc *desc)
502
502
{
503
503
struct grpci2_priv *priv = grpci2priv;
504
504
int i, ack = 0;
+2
-3
arch/tile/kernel/pci_gx.c
+2
-3
arch/tile/kernel/pci_gx.c
···
304
304
* to Linux which just calls handle_level_irq() after clearing the
305
305
* MAC INTx Assert status bit associated with this interrupt.
306
306
*/
307
-
static void trio_handle_level_irq(unsigned int __irq, struct irq_desc *desc)
307
+
static void trio_handle_level_irq(struct irq_desc *desc)
308
308
{
309
309
struct pci_controller *controller = irq_desc_get_handler_data(desc);
310
310
gxio_trio_context_t *trio_context = controller->trio;
311
311
uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
312
-
unsigned int irq = irq_desc_get_irq(desc);
313
312
int mac = controller->mac;
314
313
unsigned int reg_offset;
315
314
uint64_t level_mask;
316
315
317
-
handle_level_irq(irq, desc);
316
+
handle_level_irq(desc);
318
317
319
318
/*
320
319
* Clear the INTx Level status, otherwise future interrupts are
+1
-1
arch/unicore32/kernel/irq.c
+1
-1
arch/unicore32/kernel/irq.c
···
112
112
* irq_controller_lock held, and IRQs disabled. Decode the IRQ
113
113
* and call the handler.
114
114
*/
115
-
static void puv3_gpio_handler(unsigned int __irq, struct irq_desc *desc)
115
+
static void puv3_gpio_handler(struct irq_desc *desc)
116
116
{
117
117
unsigned int mask, irq;
118
118
+1
-3
arch/x86/kernel/apic/vector.c
+1
-3
arch/x86/kernel/apic/vector.c
···
489
489
490
490
err = assign_irq_vector(irq, data, dest);
491
491
if (err) {
492
-
struct irq_data *top = irq_get_irq_data(irq);
493
-
494
492
if (assign_irq_vector(irq, data,
495
-
irq_data_get_affinity_mask(top)))
493
+
irq_data_get_affinity_mask(irq_data)))
496
494
pr_err("Failed to recover vector for irq %d\n", irq);
497
495
return err;
498
496
}
+7
-12
arch/x86/kernel/irq_32.c
+7
-12
arch/x86/kernel/irq_32.c
···
68
68
return (void *)(current_stack_pointer() & ~(THREAD_SIZE - 1));
69
69
}
70
70
71
-
static inline int
72
-
execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
71
+
static inline int execute_on_irq_stack(int overflow, struct irq_desc *desc)
73
72
{
74
73
struct irq_stack *curstk, *irqstk;
75
-
u32 *isp, *prev_esp, arg1, arg2;
74
+
u32 *isp, *prev_esp, arg1;
76
75
77
76
curstk = (struct irq_stack *) current_stack();
78
77
irqstk = __this_cpu_read(hardirq_stack);
···
97
98
asm volatile("xchgl %%ebx,%%esp \n"
98
99
"call *%%edi \n"
99
100
"movl %%ebx,%%esp \n"
100
-
: "=a" (arg1), "=d" (arg2), "=b" (isp)
101
-
: "0" (irq), "1" (desc), "2" (isp),
101
+
: "=a" (arg1), "=b" (isp)
102
+
: "0" (desc), "1" (isp),
102
103
"D" (desc->handle_irq)
103
104
: "memory", "cc", "ecx");
104
105
return 1;
···
149
150
150
151
bool handle_irq(struct irq_desc *desc, struct pt_regs *regs)
151
152
{
152
-
unsigned int irq;
153
-
int overflow;
154
-
155
-
overflow = check_stack_overflow();
153
+
int overflow = check_stack_overflow();
156
154
157
155
if (IS_ERR_OR_NULL(desc))
158
156
return false;
159
157
160
-
irq = irq_desc_get_irq(desc);
161
-
if (user_mode(regs) || !execute_on_irq_stack(overflow, desc, irq)) {
158
+
if (user_mode(regs) || !execute_on_irq_stack(overflow, desc)) {
162
159
if (unlikely(overflow))
163
160
print_stack_overflow();
164
-
generic_handle_irq_desc(irq, desc);
161
+
generic_handle_irq_desc(desc);
165
162
}
166
163
167
164
return true;
+1
-1
arch/x86/kernel/irq_64.c
+1
-1
arch/x86/kernel/irq_64.c
+1
-1
arch/x86/lguest/boot.c
+1
-1
arch/x86/lguest/boot.c
···
1015
1015
* This is the Guest timer interrupt handler (hardware interrupt 0). We just
1016
1016
* call the clockevent infrastructure and it does whatever needs doing.
1017
1017
*/
1018
-
static void lguest_time_irq(unsigned int irq, struct irq_desc *desc)
1018
+
static void lguest_time_irq(struct irq_desc *desc)
1019
1019
{
1020
1020
unsigned long flags;
1021
1021
+3
-15
drivers/base/platform-msi.c
+3
-15
drivers/base/platform-msi.c
···
63
63
unsigned int virq, irq_hw_number_t hwirq,
64
64
msi_alloc_info_t *arg)
65
65
{
66
-
struct irq_data *data;
67
-
68
-
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
69
-
info->chip, info->chip_data);
70
-
71
-
/*
72
-
* Save the MSI descriptor in handler_data so that the
73
-
* irq_write_msi_msg callback can retrieve it (and the
74
-
* associated device).
75
-
*/
76
-
data = irq_domain_get_irq_data(domain, virq);
77
-
data->handler_data = arg->desc;
78
-
79
-
return 0;
66
+
return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
67
+
info->chip, info->chip_data);
80
68
}
81
69
#else
82
70
#define platform_msi_set_desc NULL
···
85
97
86
98
static void platform_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
87
99
{
88
-
struct msi_desc *desc = irq_data_get_irq_handler_data(data);
100
+
struct msi_desc *desc = irq_data_get_msi_desc(data);
89
101
struct platform_msi_priv_data *priv_data;
90
102
91
103
priv_data = desc->platform.msi_priv_data;
+1
-1
drivers/dma/ipu/ipu_irq.c
+1
-1
drivers/dma/ipu/ipu_irq.c
···
266
266
}
267
267
268
268
/* Chained IRQ handler for IPU function and error interrupt */
269
-
static void ipu_irq_handler(unsigned int __irq, struct irq_desc *desc)
269
+
static void ipu_irq_handler(struct irq_desc *desc)
270
270
{
271
271
struct ipu *ipu = irq_desc_get_handler_data(desc);
272
272
u32 status;
+2
-4
drivers/gpio/gpio-altera.c
+2
-4
drivers/gpio/gpio-altera.c
···
201
201
return 0;
202
202
}
203
203
204
-
static void altera_gpio_irq_edge_handler(unsigned int irq,
205
-
struct irq_desc *desc)
204
+
static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
206
205
{
207
206
struct altera_gpio_chip *altera_gc;
208
207
struct irq_chip *chip;
···
230
231
}
231
232
232
233
233
-
static void altera_gpio_irq_leveL_high_handler(unsigned int irq,
234
-
struct irq_desc *desc)
234
+
static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
235
235
{
236
236
struct altera_gpio_chip *altera_gc;
237
237
struct irq_chip *chip;
+1
-1
drivers/gpio/gpio-bcm-kona.c
+1
-1
drivers/gpio/gpio-bcm-kona.c
+1
-1
drivers/gpio/gpio-brcmstb.c
+1
-1
drivers/gpio/gpio-brcmstb.c
···
236
236
}
237
237
238
238
/* Each UPG GIO block has one IRQ for all banks */
239
-
static void brcmstb_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
239
+
static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
240
240
{
241
241
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
242
242
struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+1
-2
drivers/gpio/gpio-davinci.c
+1
-2
drivers/gpio/gpio-davinci.c
···
326
326
.flags = IRQCHIP_SET_TYPE_MASKED,
327
327
};
328
328
329
-
static void
330
-
gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
329
+
static void gpio_irq_handler(struct irq_desc *desc)
331
330
{
332
331
unsigned int irq = irq_desc_get_irq(desc);
333
332
struct davinci_gpio_regs __iomem *g;
+1
-1
drivers/gpio/gpio-dwapb.c
+1
-1
drivers/gpio/gpio-dwapb.c
···
147
147
return ret;
148
148
}
149
149
150
-
static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
150
+
static void dwapb_irq_handler(struct irq_desc *desc)
151
151
{
152
152
struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
153
153
struct irq_chip *chip = irq_desc_get_chip(desc);
+2
-3
drivers/gpio/gpio-ep93xx.c
+2
-3
drivers/gpio/gpio-ep93xx.c
···
78
78
EP93XX_GPIO_REG(int_debounce_register_offset[port]));
79
79
}
80
80
81
-
static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
81
+
static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
82
82
{
83
83
unsigned char status;
84
84
int i;
···
100
100
}
101
101
}
102
102
103
-
static void ep93xx_gpio_f_irq_handler(unsigned int __irq,
104
-
struct irq_desc *desc)
103
+
static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
105
104
{
106
105
/*
107
106
* map discontiguous hw irq range to continuous sw irq range:
+1
-1
drivers/gpio/gpio-intel-mid.c
+1
-1
drivers/gpio/gpio-intel-mid.c
···
301
301
};
302
302
MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
303
303
304
-
static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
304
+
static void intel_mid_irq_handler(struct irq_desc *desc)
305
305
{
306
306
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
307
307
struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
+1
-1
drivers/gpio/gpio-lynxpoint.c
+1
-1
drivers/gpio/gpio-lynxpoint.c
···
234
234
return 0;
235
235
}
236
236
237
-
static void lp_gpio_irq_handler(unsigned hwirq, struct irq_desc *desc)
237
+
static void lp_gpio_irq_handler(struct irq_desc *desc)
238
238
{
239
239
struct irq_data *data = irq_desc_get_irq_data(desc);
240
240
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+1
-1
drivers/gpio/gpio-mpc8xxx.c
+1
-1
drivers/gpio/gpio-mpc8xxx.c
···
194
194
return -ENXIO;
195
195
}
196
196
197
-
static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
197
+
static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
198
198
{
199
199
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
200
200
struct irq_chip *chip = irq_desc_get_chip(desc);
+1
-1
drivers/gpio/gpio-msic.c
+1
-1
drivers/gpio/gpio-msic.c
···
232
232
.irq_bus_sync_unlock = msic_bus_sync_unlock,
233
233
};
234
234
235
-
static void msic_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
235
+
static void msic_gpio_irq_handler(struct irq_desc *desc)
236
236
{
237
237
struct irq_data *data = irq_desc_get_irq_data(desc);
238
238
struct msic_gpio *mg = irq_data_get_irq_handler_data(data);
+1
-1
drivers/gpio/gpio-msm-v2.c
+1
-1
drivers/gpio/gpio-msm-v2.c
···
305
305
* which have been set as summary IRQ lines and which are triggered,
306
306
* and to call their interrupt handlers.
307
307
*/
308
-
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
308
+
static void msm_summary_irq_handler(struct irq_desc *desc)
309
309
{
310
310
unsigned long i;
311
311
struct irq_chip *chip = irq_desc_get_chip(desc);
+1
-1
drivers/gpio/gpio-mvebu.c
+1
-1
drivers/gpio/gpio-mvebu.c
···
458
458
return 0;
459
459
}
460
460
461
-
static void mvebu_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc)
461
+
static void mvebu_gpio_irq_handler(struct irq_desc *desc)
462
462
{
463
463
struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
464
464
struct irq_chip *chip = irq_desc_get_chip(desc);
+2
-2
drivers/gpio/gpio-mxc.c
+2
-2
drivers/gpio/gpio-mxc.c
···
272
272
}
273
273
274
274
/* MX1 and MX3 has one interrupt *per* gpio port */
275
-
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
275
+
static void mx3_gpio_irq_handler(struct irq_desc *desc)
276
276
{
277
277
u32 irq_stat;
278
278
struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
···
288
288
}
289
289
290
290
/* MX2 has one interrupt *for all* gpio ports */
291
-
static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
291
+
static void mx2_gpio_irq_handler(struct irq_desc *desc)
292
292
{
293
293
u32 irq_msk, irq_stat;
294
294
struct mxc_gpio_port *port;
+1
-1
drivers/gpio/gpio-mxs.c
+1
-1
drivers/gpio/gpio-mxs.c
···
154
154
}
155
155
156
156
/* MXS has one interrupt *per* gpio port */
157
-
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
157
+
static void mxs_gpio_irq_handler(struct irq_desc *desc)
158
158
{
159
159
u32 irq_stat;
160
160
struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
+1
-1
drivers/gpio/gpio-omap.c
+1
-1
drivers/gpio/gpio-omap.c
···
709
709
* line's interrupt handler has been run, we may miss some nested
710
710
* interrupts.
711
711
*/
712
-
static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
712
+
static void omap_gpio_irq_handler(struct irq_desc *desc)
713
713
{
714
714
void __iomem *isr_reg = NULL;
715
715
u32 isr;
+1
-1
drivers/gpio/gpio-pl061.c
+1
-1
drivers/gpio/gpio-pl061.c
+1
-1
drivers/gpio/gpio-pxa.c
+1
-1
drivers/gpio/gpio-pxa.c
+1
-2
drivers/gpio/gpio-sa1100.c
+1
-2
drivers/gpio/gpio-sa1100.c
···
172
172
* irq_controller_lock held, and IRQs disabled. Decode the IRQ
173
173
* and call the handler.
174
174
*/
175
-
static void
176
-
sa1100_gpio_handler(unsigned int __irq, struct irq_desc *desc)
175
+
static void sa1100_gpio_handler(struct irq_desc *desc)
177
176
{
178
177
unsigned int irq, mask;
179
178
+1
-1
drivers/gpio/gpio-tegra.c
+1
-1
drivers/gpio/gpio-tegra.c
+1
-1
drivers/gpio/gpio-timberdale.c
+1
-1
drivers/gpio/gpio-timberdale.c
···
192
192
return ret;
193
193
}
194
194
195
-
static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
195
+
static void timbgpio_irq(struct irq_desc *desc)
196
196
{
197
197
struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
198
198
struct irq_data *data = irq_desc_get_irq_data(desc);
+2
-2
drivers/gpio/gpio-tz1090.c
+2
-2
drivers/gpio/gpio-tz1090.c
···
375
375
#define gpio_set_irq_wake NULL
376
376
#endif
377
377
378
-
static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
378
+
static void tz1090_gpio_irq_handler(struct irq_desc *desc)
379
379
{
380
380
irq_hw_number_t hw;
381
381
unsigned int irq_stat, irq_no;
···
400
400
== IRQ_TYPE_EDGE_BOTH)
401
401
tz1090_gpio_irq_next_edge(bank, hw);
402
402
403
-
generic_handle_irq_desc(irq_no, child_desc);
403
+
generic_handle_irq_desc(child_desc);
404
404
}
405
405
}
406
406
+3
-3
drivers/gpio/gpio-vf610.c
+3
-3
drivers/gpio/gpio-vf610.c
···
120
120
return pinctrl_gpio_direction_output(chip->base + gpio);
121
121
}
122
122
123
-
static void vf610_gpio_irq_handler(u32 irq, struct irq_desc *desc)
123
+
static void vf610_gpio_irq_handler(struct irq_desc *desc)
124
124
{
125
125
struct vf610_gpio_port *port = irq_desc_get_handler_data(desc);
126
126
struct irq_chip *chip = irq_desc_get_chip(desc);
···
176
176
port->irqc[d->hwirq] = irqc;
177
177
178
178
if (type & IRQ_TYPE_LEVEL_MASK)
179
-
__irq_set_handler_locked(d->irq, handle_level_irq);
179
+
irq_set_handler_locked(d, handle_level_irq);
180
180
else
181
-
__irq_set_handler_locked(d->irq, handle_edge_irq);
181
+
irq_set_handler_locked(d, handle_edge_irq);
182
182
183
183
return 0;
184
184
}
+1
-1
drivers/gpio/gpio-zx.c
+1
-1
drivers/gpio/gpio-zx.c
+1
-1
drivers/gpio/gpio-zynq.c
+1
-1
drivers/gpio/gpio-zynq.c
···
514
514
* application for that pin.
515
515
* Note: A bug is reported if no handler is set for the gpio pin.
516
516
*/
517
-
static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
517
+
static void zynq_gpio_irqhandler(struct irq_desc *desc)
518
518
{
519
519
u32 int_sts, int_enb;
520
520
unsigned int bank_num;
-1
drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
-1
drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+3
-4
drivers/gpu/ipu-v3/ipu-common.c
+3
-4
drivers/gpu/ipu-v3/ipu-common.c
···
912
912
}
913
913
}
914
914
915
-
static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
915
+
static void ipu_irq_handler(struct irq_desc *desc)
916
916
{
917
917
struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
918
918
struct irq_chip *chip = irq_desc_get_chip(desc);
···
925
925
chained_irq_exit(chip, desc);
926
926
}
927
927
928
-
static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
928
+
static void ipu_err_irq_handler(struct irq_desc *desc)
929
929
{
930
930
struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
931
931
struct irq_chip *chip = irq_desc_get_chip(desc);
···
1099
1099
}
1100
1100
1101
1101
ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1102
-
handle_level_irq, 0,
1103
-
IRQF_VALID, 0);
1102
+
handle_level_irq, 0, 0, 0);
1104
1103
if (ret < 0) {
1105
1104
dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1106
1105
irq_domain_remove(ipu->domain);
+3
-5
drivers/irqchip/exynos-combiner.c
+3
-5
drivers/irqchip/exynos-combiner.c
···
65
65
__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
66
66
}
67
67
68
-
static void combiner_handle_cascade_irq(unsigned int __irq,
69
-
struct irq_desc *desc)
68
+
static void combiner_handle_cascade_irq(struct irq_desc *desc)
70
69
{
71
70
struct combiner_chip_data *chip_data = irq_desc_get_handler_data(desc);
72
71
struct irq_chip *chip = irq_desc_get_chip(desc);
73
-
unsigned int irq = irq_desc_get_irq(desc);
74
72
unsigned int cascade_irq, combiner_irq;
75
73
unsigned long status;
76
74
···
86
88
cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);
87
89
88
90
if (unlikely(!cascade_irq))
89
-
handle_bad_irq(irq, desc);
91
+
handle_bad_irq(desc);
90
92
else
91
93
generic_handle_irq(cascade_irq);
92
94
···
163
165
164
166
irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
165
167
irq_set_chip_data(irq, &combiner_data[hw >> 3]);
166
-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
168
+
irq_set_probe(irq);
167
169
168
170
return 0;
169
171
}
+2
-4
drivers/irqchip/irq-armada-370-xp.c
+2
-4
drivers/irqchip/irq-armada-370-xp.c
···
200
200
{
201
201
irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
202
202
handle_simple_irq);
203
-
set_irq_flags(virq, IRQF_VALID);
204
203
205
204
return 0;
206
205
}
···
316
317
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
317
318
handle_level_irq);
318
319
}
319
-
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
320
+
irq_set_probe(virq);
320
321
321
322
return 0;
322
323
}
···
446
447
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
447
448
#endif
448
449
449
-
static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
450
-
struct irq_desc *desc)
450
+
static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
451
451
{
452
452
struct irq_chip *chip = irq_desc_get_chip(desc);
453
453
unsigned long irqmap, irqn, irqsrc, cpuid;
+3
-3
drivers/irqchip/irq-bcm2835.c
+3
-3
drivers/irqchip/irq-bcm2835.c
···
96
96
static struct armctrl_ic intc __read_mostly;
97
97
static void __exception_irq_entry bcm2835_handle_irq(
98
98
struct pt_regs *regs);
99
-
static void bcm2836_chained_handle_irq(unsigned int irq, struct irq_desc *desc);
99
+
static void bcm2836_chained_handle_irq(struct irq_desc *desc);
100
100
101
101
static void armctrl_mask_irq(struct irq_data *d)
102
102
{
···
166
166
BUG_ON(irq <= 0);
167
167
irq_set_chip_and_handler(irq, &armctrl_chip,
168
168
handle_level_irq);
169
-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
169
+
irq_set_probe(irq);
170
170
}
171
171
}
172
172
···
245
245
handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
246
246
}
247
247
248
-
static void bcm2836_chained_handle_irq(unsigned int irq, struct irq_desc *desc)
248
+
static void bcm2836_chained_handle_irq(struct irq_desc *desc)
249
249
{
250
250
u32 hwirq;
251
251
+1
-1
drivers/irqchip/irq-bcm7038-l1.c
+1
-1
drivers/irqchip/irq-bcm7038-l1.c
···
115
115
writel(val, reg);
116
116
}
117
117
118
-
static void bcm7038_l1_irq_handle(unsigned int irq, struct irq_desc *desc)
118
+
static void bcm7038_l1_irq_handle(struct irq_desc *desc)
119
119
{
120
120
struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
121
121
struct bcm7038_l1_cpu *cpu;
+1
-1
drivers/irqchip/irq-bcm7120-l2.c
+1
-1
drivers/irqchip/irq-bcm7120-l2.c
···
56
56
const __be32 *map_mask_prop;
57
57
};
58
58
59
-
static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
59
+
static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
60
60
{
61
61
struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
62
62
struct bcm7120_l2_intc_data *b = data->b;
+3
-4
drivers/irqchip/irq-brcmstb-l2.c
+3
-4
drivers/irqchip/irq-brcmstb-l2.c
···
49
49
u32 saved_mask; /* for suspend/resume */
50
50
};
51
51
52
-
static void brcmstb_l2_intc_irq_handle(unsigned int __irq,
53
-
struct irq_desc *desc)
52
+
static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
54
53
{
55
54
struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
56
55
struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0);
57
56
struct irq_chip *chip = irq_desc_get_chip(desc);
58
-
unsigned int irq = irq_desc_get_irq(desc);
57
+
unsigned int irq;
59
58
u32 status;
60
59
61
60
chained_irq_enter(chip, desc);
···
64
65
65
66
if (status == 0) {
66
67
raw_spin_lock(&desc->lock);
67
-
handle_bad_irq(irq, desc);
68
+
handle_bad_irq(desc);
68
69
raw_spin_unlock(&desc->lock);
69
70
goto out;
70
71
}
+3
-3
drivers/irqchip/irq-clps711x.c
+3
-3
drivers/irqchip/irq-clps711x.c
···
132
132
irq_hw_number_t hw)
133
133
{
134
134
irq_flow_handler_t handler = handle_level_irq;
135
-
unsigned int flags = IRQF_VALID | IRQF_PROBE;
135
+
unsigned int flags = 0;
136
136
137
137
if (!clps711x_irqs[hw].flags)
138
138
return 0;
139
139
140
140
if (clps711x_irqs[hw].flags & CLPS711X_FLAG_FIQ) {
141
141
handler = handle_bad_irq;
142
-
flags |= IRQF_NOAUTOEN;
142
+
flags |= IRQ_NOAUTOEN;
143
143
} else if (clps711x_irqs[hw].eoi) {
144
144
handler = handle_fasteoi_irq;
145
145
}
···
149
149
writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi);
150
150
151
151
irq_set_chip_and_handler(virq, &clps711x_intc_chip, handler);
152
-
set_irq_flags(virq, flags);
152
+
irq_modify_status(virq, IRQ_NOPROBE, flags);
153
153
154
154
return 0;
155
155
}
+1
-1
drivers/irqchip/irq-dw-apb-ictl.c
+1
-1
drivers/irqchip/irq-dw-apb-ictl.c
···
26
26
#define APB_INT_FINALSTATUS_H 0x34
27
27
#define APB_INT_BASE_OFFSET 0x04
28
28
29
-
static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
29
+
static void dw_apb_ictl_handler(struct irq_desc *desc)
30
30
{
31
31
struct irq_domain *d = irq_desc_get_handler_data(desc);
32
32
struct irq_chip *chip = irq_desc_get_chip(desc);
+2
-2
drivers/irqchip/irq-gic-v2m.c
+2
-2
drivers/irqchip/irq-gic-v2m.c
···
95
95
struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
96
96
phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
97
97
98
-
msg->address_hi = (u32) (addr >> 32);
99
-
msg->address_lo = (u32) (addr);
98
+
msg->address_hi = upper_32_bits(addr);
99
+
msg->address_lo = lower_32_bits(addr);
100
100
msg->data = data->hwirq;
101
101
}
102
102
+5
-1
drivers/irqchip/irq-gic-v3-its.c
+5
-1
drivers/irqchip/irq-gic-v3-its.c
···
898
898
* non-cacheable as well.
899
899
*/
900
900
shr = tmp & GITS_BASER_SHAREABILITY_MASK;
901
-
if (!shr)
901
+
if (!shr) {
902
902
cache = GITS_BASER_nC;
903
+
__flush_dcache_area(base, alloc_size);
904
+
}
903
905
goto retry_baser;
904
906
}
905
907
···
1141
1139
kfree(col_map);
1142
1140
return NULL;
1143
1141
}
1142
+
1143
+
__flush_dcache_area(itt, sz);
1144
1144
1145
1145
dev->its = its;
1146
1146
dev->itt = itt;
+8
-11
drivers/irqchip/irq-gic-v3.c
+8
-11
drivers/irqchip/irq-gic-v3.c
···
70
70
return gic_irq(d) < 32;
71
71
}
72
72
73
-
static inline bool forwarded_irq(struct irq_data *d)
74
-
{
75
-
return d->handler_data != NULL;
76
-
}
77
-
78
73
static inline void __iomem *gic_dist_base(struct irq_data *d)
79
74
{
80
75
if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
···
244
249
* disabled/masked will not get "stuck", because there is
245
250
* noone to deactivate it (guest is being terminated).
246
251
*/
247
-
if (forwarded_irq(d))
252
+
if (irqd_is_forwarded_to_vcpu(d))
248
253
gic_poke_irq(d, GICD_ICACTIVER);
249
254
}
250
255
···
319
324
* No need to deactivate an LPI, or an interrupt that
320
325
* is is getting forwarded to a vcpu.
321
326
*/
322
-
if (gic_irq(d) >= 8192 || forwarded_irq(d))
327
+
if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
323
328
return;
324
329
gic_write_dir(gic_irq(d));
325
330
}
···
352
357
353
358
static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
354
359
{
355
-
d->handler_data = vcpu;
360
+
if (vcpu)
361
+
irqd_set_forwarded_to_vcpu(d);
362
+
else
363
+
irqd_clr_forwarded_to_vcpu(d);
356
364
return 0;
357
365
}
358
366
···
752
754
irq_set_percpu_devid(irq);
753
755
irq_domain_set_info(d, irq, hw, chip, d->host_data,
754
756
handle_percpu_devid_irq, NULL, NULL);
755
-
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
757
+
irq_set_status_flags(irq, IRQ_NOAUTOEN);
756
758
}
757
759
/* SPIs */
758
760
if (hw >= 32 && hw < gic_data.irq_nr) {
759
761
irq_domain_set_info(d, irq, hw, chip, d->host_data,
760
762
handle_fasteoi_irq, NULL, NULL);
761
-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
763
+
irq_set_probe(irq);
762
764
}
763
765
/* LPIs */
764
766
if (hw >= 8192 && hw < GIC_ID_NR) {
···
766
768
return -EPERM;
767
769
irq_domain_set_info(d, irq, hw, chip, d->host_data,
768
770
handle_fasteoi_irq, NULL, NULL);
769
-
set_irq_flags(irq, IRQF_VALID);
770
771
}
771
772
772
773
return 0;
+52
-34
drivers/irqchip/irq-gic.c
+52
-34
drivers/irqchip/irq-gic.c
···
145
145
void *data = irq_data_get_irq_handler_data(d);
146
146
147
147
/*
148
-
* If handler_data pointing to one of the secondary GICs, then
149
-
* this is a cascading interrupt, and it cannot possibly be
150
-
* forwarded.
148
+
* If handler_data is set, this is a cascading interrupt, and
149
+
* it cannot possibly be forwarded.
151
150
*/
152
-
if (data >= (void *)(gic_data + 1) &&
153
-
data < (void *)(gic_data + MAX_GIC_NR))
154
-
return true;
155
-
156
-
return false;
157
-
}
158
-
159
-
static inline bool forwarded_irq(struct irq_data *d)
160
-
{
161
-
/*
162
-
* A forwarded interrupt:
163
-
* - is on the primary GIC
164
-
* - has its handler_data set to a value
165
-
* - that isn't a secondary GIC
166
-
*/
167
-
if (d->handler_data && !cascading_gic_irq(d))
168
-
return true;
169
-
170
-
return false;
151
+
return data != NULL;
171
152
}
172
153
173
154
/*
···
182
201
* disabled/masked will not get "stuck", because there is
183
202
* noone to deactivate it (guest is being terminated).
184
203
*/
185
-
if (forwarded_irq(d))
204
+
if (irqd_is_forwarded_to_vcpu(d))
186
205
gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
187
206
}
188
207
···
199
218
static void gic_eoimode1_eoi_irq(struct irq_data *d)
200
219
{
201
220
/* Do not deactivate an IRQ forwarded to a vcpu. */
202
-
if (forwarded_irq(d))
221
+
if (irqd_is_forwarded_to_vcpu(d))
203
222
return;
204
223
205
224
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
···
277
296
if (cascading_gic_irq(d))
278
297
return -EINVAL;
279
298
280
-
d->handler_data = vcpu;
299
+
if (vcpu)
300
+
irqd_set_forwarded_to_vcpu(d);
301
+
else
302
+
irqd_clr_forwarded_to_vcpu(d);
281
303
return 0;
282
304
}
283
305
···
341
357
} while (1);
342
358
}
343
359
344
-
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
360
+
static void gic_handle_cascade_irq(struct irq_desc *desc)
345
361
{
346
362
struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
347
363
struct irq_chip *chip = irq_desc_get_chip(desc);
···
360
376
361
377
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
362
378
if (unlikely(gic_irq < 32 || gic_irq > 1020))
363
-
handle_bad_irq(cascade_irq, desc);
379
+
handle_bad_irq(desc);
364
380
else
365
381
generic_handle_irq(cascade_irq);
366
382
···
890
906
irq_set_percpu_devid(irq);
891
907
irq_domain_set_info(d, irq, hw, chip, d->host_data,
892
908
handle_percpu_devid_irq, NULL, NULL);
893
-
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
909
+
irq_set_status_flags(irq, IRQ_NOAUTOEN);
894
910
} else {
895
911
irq_domain_set_info(d, irq, hw, chip, d->host_data,
896
912
handle_fasteoi_irq, NULL, NULL);
897
-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
913
+
irq_set_probe(irq);
898
914
}
899
915
return 0;
900
916
}
···
1103
1119
#ifdef CONFIG_OF
1104
1120
static int gic_cnt __initdata;
1105
1121
1122
+
static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1123
+
{
1124
+
struct resource cpuif_res;
1125
+
1126
+
of_address_to_resource(node, 1, &cpuif_res);
1127
+
1128
+
if (!is_hyp_mode_available())
1129
+
return false;
1130
+
if (resource_size(&cpuif_res) < SZ_8K)
1131
+
return false;
1132
+
if (resource_size(&cpuif_res) == SZ_128K) {
1133
+
u32 val_low, val_high;
1134
+
1135
+
/*
1136
+
* Verify that we have the first 4kB of a GIC400
1137
+
* aliased over the first 64kB by checking the
1138
+
* GICC_IIDR register on both ends.
1139
+
*/
1140
+
val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1141
+
val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1142
+
if ((val_low & 0xffff0fff) != 0x0202043B ||
1143
+
val_low != val_high)
1144
+
return false;
1145
+
1146
+
/*
1147
+
* Move the base up by 60kB, so that we have a 8kB
1148
+
* contiguous region, which allows us to use GICC_DIR
1149
+
* at its normal offset. Please pass me that bucket.
1150
+
*/
1151
+
*base += 0xf000;
1152
+
cpuif_res.start += 0xf000;
1153
+
pr_warn("GIC: Adjusting CPU interface base to %pa",
1154
+
&cpuif_res.start);
1155
+
}
1156
+
1157
+
return true;
1158
+
}
1159
+
1106
1160
static int __init
1107
1161
gic_of_init(struct device_node *node, struct device_node *parent)
1108
1162
{
1109
1163
void __iomem *cpu_base;
1110
1164
void __iomem *dist_base;
1111
-
struct resource cpu_res;
1112
1165
u32 percpu_offset;
1113
1166
int irq;
1114
1167
···
1158
1137
cpu_base = of_iomap(node, 1);
1159
1138
WARN(!cpu_base, "unable to map gic cpu registers\n");
1160
1139
1161
-
of_address_to_resource(node, 1, &cpu_res);
1162
-
1163
1140
/*
1164
1141
* Disable split EOI/Deactivate if either HYP is not available
1165
1142
* or the CPU interface is too small.
1166
1143
*/
1167
-
if (gic_cnt == 0 && (!is_hyp_mode_available() ||
1168
-
resource_size(&cpu_res) < SZ_8K))
1144
+
if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base))
1169
1145
static_key_slow_dec(&supports_deactivate);
1170
1146
1171
1147
if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
+2
-2
drivers/irqchip/irq-hip04.c
+2
-2
drivers/irqchip/irq-hip04.c
···
307
307
irq_set_percpu_devid(irq);
308
308
irq_set_chip_and_handler(irq, &hip04_irq_chip,
309
309
handle_percpu_devid_irq);
310
-
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
310
+
irq_set_status_flags(irq, IRQ_NOAUTOEN);
311
311
} else {
312
312
irq_set_chip_and_handler(irq, &hip04_irq_chip,
313
313
handle_fasteoi_irq);
314
-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
314
+
irq_set_probe(irq);
315
315
}
316
316
irq_set_chip_data(irq, d->host_data);
317
317
return 0;
+1
-1
drivers/irqchip/irq-i8259.c
+1
-1
drivers/irqchip/irq-i8259.c
···
352
352
__init_i8259_irqs(NULL);
353
353
}
354
354
355
-
static void i8259_irq_dispatch(unsigned int __irq, struct irq_desc *desc)
355
+
static void i8259_irq_dispatch(struct irq_desc *desc)
356
356
{
357
357
struct irq_domain *domain = irq_desc_get_handler_data(desc);
358
358
int hwirq = i8259_irq();
+2
-2
drivers/irqchip/irq-imgpdc.c
+2
-2
drivers/irqchip/irq-imgpdc.c
···
218
218
return 0;
219
219
}
220
220
221
-
static void pdc_intc_perip_isr(unsigned int __irq, struct irq_desc *desc)
221
+
static void pdc_intc_perip_isr(struct irq_desc *desc)
222
222
{
223
223
unsigned int irq = irq_desc_get_irq(desc);
224
224
struct pdc_intc_priv *priv;
···
240
240
generic_handle_irq(irq_no);
241
241
}
242
242
243
-
static void pdc_intc_syswake_isr(unsigned int irq, struct irq_desc *desc)
243
+
static void pdc_intc_syswake_isr(struct irq_desc *desc)
244
244
{
245
245
struct pdc_intc_priv *priv;
246
246
unsigned int syswake, irq_no;
+2
-2
drivers/irqchip/irq-keystone.c
+2
-2
drivers/irqchip/irq-keystone.c
···
83
83
/* nothing to do here */
84
84
}
85
85
86
-
static void keystone_irq_handler(unsigned __irq, struct irq_desc *desc)
86
+
static void keystone_irq_handler(struct irq_desc *desc)
87
87
{
88
88
unsigned int irq = irq_desc_get_irq(desc);
89
89
struct keystone_irq_device *kirq = irq_desc_get_handler_data(desc);
···
127
127
128
128
irq_set_chip_data(virq, kirq);
129
129
irq_set_chip_and_handler(virq, &kirq->chip, handle_level_irq);
130
-
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
130
+
irq_set_probe(virq);
131
131
return 0;
132
132
}
133
133
+1
-1
drivers/irqchip/irq-metag-ext.c
+1
-1
drivers/irqchip/irq-metag-ext.c
···
446
446
* Whilst using TR2 to detect external interrupts is a software convention it is
447
447
* (hopefully) unlikely to change.
448
448
*/
449
-
static void meta_intc_irq_demux(unsigned int irq, struct irq_desc *desc)
449
+
static void meta_intc_irq_demux(struct irq_desc *desc)
450
450
{
451
451
struct meta_intc_priv *priv = &meta_intc_priv;
452
452
irq_hw_number_t hw;
+1
-1
drivers/irqchip/irq-metag.c
+1
-1
drivers/irqchip/irq-metag.c
···
220
220
* occurred. It is this function's job to demux this irq and
221
221
* figure out exactly which trigger needs servicing.
222
222
*/
223
-
static void metag_internal_irq_demux(unsigned int irq, struct irq_desc *desc)
223
+
static void metag_internal_irq_demux(struct irq_desc *desc)
224
224
{
225
225
struct metag_internal_irq_priv *priv = irq_desc_get_handler_data(desc);
226
226
irq_hw_number_t hw;
+1
-1
drivers/irqchip/irq-mips-gic.c
+1
-1
drivers/irqchip/irq-mips-gic.c
+1
-4
drivers/irqchip/irq-mmp.c
+1
-4
drivers/irqchip/irq-mmp.c
···
129
129
.irq_unmask = icu_unmask_irq,
130
130
};
131
131
132
-
static void icu_mux_irq_demux(unsigned int __irq, struct irq_desc *desc)
132
+
static void icu_mux_irq_demux(struct irq_desc *desc)
133
133
{
134
134
unsigned int irq = irq_desc_get_irq(desc);
135
135
struct irq_domain *domain;
···
164
164
irq_hw_number_t hw)
165
165
{
166
166
irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
167
-
set_irq_flags(irq, IRQF_VALID);
168
167
return 0;
169
168
}
170
169
···
233
234
for (irq = 0; irq < 64; irq++) {
234
235
icu_mask_irq(irq_get_irq_data(irq));
235
236
irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
236
-
set_irq_flags(irq, IRQF_VALID);
237
237
}
238
238
irq_set_default_host(icu_data[0].domain);
239
239
set_handle_irq(mmp_handle_irq);
···
335
337
irq_set_chip_and_handler(irq, &icu_irq_chip,
336
338
handle_level_irq);
337
339
}
338
-
set_irq_flags(irq, IRQF_VALID);
339
340
}
340
341
irq_set_default_host(icu_data[0].domain);
341
342
set_handle_irq(mmp2_handle_irq);
-1
drivers/irqchip/irq-mxs.c
-1
drivers/irqchip/irq-mxs.c
+1
-1
drivers/irqchip/irq-orion.c
+1
-1
drivers/irqchip/irq-orion.c
···
106
106
#define ORION_BRIDGE_IRQ_CAUSE 0x00
107
107
#define ORION_BRIDGE_IRQ_MASK 0x04
108
108
109
-
static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
109
+
static void orion_bridge_irq_handler(struct irq_desc *desc)
110
110
{
111
111
struct irq_domain *d = irq_desc_get_handler_data(desc);
112
112
+10
-1
drivers/irqchip/irq-renesas-intc-irqpin.c
+10
-1
drivers/irqchip/irq-renesas-intc-irqpin.c
···
283
283
static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
284
284
{
285
285
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
286
+
int hw_irq = irqd_to_hwirq(d);
287
+
288
+
irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
286
289
287
290
if (!p->clk)
288
291
return 0;
···
335
332
return status;
336
333
}
337
334
335
+
/*
336
+
* This lock class tells lockdep that INTC External IRQ Pin irqs are in a
337
+
* different category than their parents, so it won't report false recursion.
338
+
*/
339
+
static struct lock_class_key intc_irqpin_irq_lock_class;
340
+
338
341
static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
339
342
irq_hw_number_t hw)
340
343
{
···
351
342
352
343
intc_irqpin_dbg(&p->irq[hw], "map");
353
344
irq_set_chip_data(virq, h->host_data);
345
+
irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class);
354
346
irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
355
-
set_irq_flags(virq, IRQF_VALID); /* kill me now */
356
347
return 0;
357
348
}
358
349
+10
drivers/irqchip/irq-renesas-irqc.c
+10
drivers/irqchip/irq-renesas-irqc.c
···
121
121
static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
122
122
{
123
123
struct irqc_priv *p = irq_data_get_irq_chip_data(d);
124
+
int hw_irq = irqd_to_hwirq(d);
125
+
126
+
irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
124
127
125
128
if (!p->clk)
126
129
return 0;
···
153
150
return IRQ_NONE;
154
151
}
155
152
153
+
/*
154
+
* This lock class tells lockdep that IRQC irqs are in a different
155
+
* category than their parents, so it won't report false recursion.
156
+
*/
157
+
static struct lock_class_key irqc_irq_lock_class;
158
+
156
159
static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
157
160
irq_hw_number_t hw)
158
161
{
···
166
157
167
158
irqc_dbg(&p->irq[hw], "map");
168
159
irq_set_chip_data(virq, h->host_data);
160
+
irq_set_lockdep_class(virq, &irqc_irq_lock_class);
169
161
irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
170
162
return 0;
171
163
}
+3
-13
drivers/irqchip/irq-s3c24xx.c
+3
-13
drivers/irqchip/irq-s3c24xx.c
···
298
298
.irq_set_type = s3c_irqext0_type,
299
299
};
300
300
301
-
static void s3c_irq_demux(unsigned int __irq, struct irq_desc *desc)
301
+
static void s3c_irq_demux(struct irq_desc *desc)
302
302
{
303
303
struct irq_chip *chip = irq_desc_get_chip(desc);
304
304
struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
···
466
466
467
467
irq_set_chip_data(virq, irq_data);
468
468
469
-
set_irq_flags(virq, IRQF_VALID);
470
-
471
469
if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
472
470
if (irq_data->parent_irq > 31) {
473
471
pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
474
472
irq_data->parent_irq);
475
-
goto err;
473
+
return -EINVAL;
476
474
}
477
475
478
476
parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
···
483
485
if (!irqno) {
484
486
pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
485
487
irq_data->parent_irq);
486
-
goto err;
488
+
return -EINVAL;
487
489
}
488
490
irq_set_chained_handler(irqno, s3c_irq_demux);
489
491
}
490
492
491
493
return 0;
492
-
493
-
err:
494
-
set_irq_flags(virq, 0);
495
-
496
-
/* the only error can result from bad mapping data*/
497
-
return -EINVAL;
498
494
}
499
495
500
496
static const struct irq_domain_ops s3c24xx_irq_ops = {
···
1165
1173
handle_edge_irq);
1166
1174
1167
1175
irq_set_chip_data(virq, irq_data);
1168
-
1169
-
set_irq_flags(virq, IRQF_VALID);
1170
1176
1171
1177
return 0;
1172
1178
}
+1
-1
drivers/irqchip/irq-sun4i.c
+1
-1
drivers/irqchip/irq-sun4i.c
+1
-1
drivers/irqchip/irq-sunxi-nmi.c
+1
-1
drivers/irqchip/irq-sunxi-nmi.c
···
58
58
return irq_reg_readl(gc, off);
59
59
}
60
60
61
-
static void sunxi_sc_nmi_handle_irq(unsigned int irq, struct irq_desc *desc)
61
+
static void sunxi_sc_nmi_handle_irq(struct irq_desc *desc)
62
62
{
63
63
struct irq_domain *domain = irq_desc_get_handler_data(desc);
64
64
struct irq_chip *chip = irq_desc_get_chip(desc);
+1
-1
drivers/irqchip/irq-tb10x.c
+1
-1
drivers/irqchip/irq-tb10x.c
···
97
97
return IRQ_SET_MASK_OK;
98
98
}
99
99
100
-
static void tb10x_irq_cascade(unsigned int __irq, struct irq_desc *desc)
100
+
static void tb10x_irq_cascade(struct irq_desc *desc)
101
101
{
102
102
struct irq_domain *domain = irq_desc_get_handler_data(desc);
103
103
unsigned int irq = irq_desc_get_irq(desc);
+5
-5
drivers/irqchip/irq-versatile-fpga.c
+5
-5
drivers/irqchip/irq-versatile-fpga.c
···
65
65
writel(mask, f->base + IRQ_ENABLE_SET);
66
66
}
67
67
68
-
static void fpga_irq_handle(unsigned int __irq, struct irq_desc *desc)
68
+
static void fpga_irq_handle(struct irq_desc *desc)
69
69
{
70
70
struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
71
-
unsigned int irq = irq_desc_get_irq(desc);
72
71
u32 status = readl(f->base + IRQ_STATUS);
73
72
74
73
if (status == 0) {
75
-
do_bad_IRQ(irq, desc);
74
+
do_bad_IRQ(desc);
76
75
return;
77
76
}
78
77
79
78
do {
80
-
irq = ffs(status) - 1;
79
+
unsigned int irq = ffs(status) - 1;
80
+
81
81
status &= ~(1 << irq);
82
82
generic_handle_irq(irq_find_mapping(f->domain, irq));
83
83
} while (status);
···
128
128
irq_set_chip_data(irq, f);
129
129
irq_set_chip_and_handler(irq, &f->chip,
130
130
handle_level_irq);
131
-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
131
+
irq_set_probe(irq);
132
132
return 0;
133
133
}
134
134
+2
-2
drivers/irqchip/irq-vic.c
+2
-2
drivers/irqchip/irq-vic.c
···
201
201
return -EPERM;
202
202
irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
203
203
irq_set_chip_data(irq, v->base);
204
-
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
204
+
irq_set_probe(irq);
205
205
return 0;
206
206
}
207
207
···
225
225
return handled;
226
226
}
227
227
228
-
static void vic_handle_irq_cascaded(unsigned int irq, struct irq_desc *desc)
228
+
static void vic_handle_irq_cascaded(struct irq_desc *desc)
229
229
{
230
230
u32 stat, hwirq;
231
231
struct irq_chip *host_chip = irq_desc_get_chip(desc);
-1
drivers/irqchip/irq-vt8500.c
-1
drivers/irqchip/irq-vt8500.c
+1
-2
drivers/irqchip/spear-shirq.c
+1
-2
drivers/irqchip/spear-shirq.c
···
182
182
&spear320_shirq_intrcomm_ras,
183
183
};
184
184
185
-
static void shirq_handler(unsigned __irq, struct irq_desc *desc)
185
+
static void shirq_handler(struct irq_desc *desc)
186
186
{
187
187
struct spear_shirq *shirq = irq_desc_get_handler_data(desc);
188
188
u32 pend;
···
211
211
for (i = 0; i < shirq->nr_irqs; i++) {
212
212
irq_set_chip_and_handler(shirq->virq_base + i,
213
213
shirq->irq_chip, handle_simple_irq);
214
-
set_irq_flags(shirq->virq_base + i, IRQF_VALID);
215
214
irq_set_chip_data(shirq->virq_base + i, shirq);
216
215
}
217
216
}
+1
-1
drivers/mfd/asic3.c
+1
-1
drivers/mfd/asic3.c
···
138
138
spin_unlock_irqrestore(&asic->lock, flags);
139
139
}
140
140
141
-
static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
141
+
static void asic3_irq_demux(struct irq_desc *desc)
142
142
{
143
143
struct asic3 *asic = irq_desc_get_handler_data(desc);
144
144
struct irq_data *data = irq_desc_get_irq_data(desc);
+1
-1
drivers/mfd/ezx-pcap.c
+1
-1
drivers/mfd/ezx-pcap.c
+1
-1
drivers/mfd/htc-egpio.c
+1
-1
drivers/mfd/htc-egpio.c
+1
-1
drivers/mfd/jz4740-adc.c
+1
-1
drivers/mfd/jz4740-adc.c
+1
-1
drivers/mfd/pm8921-core.c
+1
-1
drivers/mfd/pm8921-core.c
···
156
156
return ret;
157
157
}
158
158
159
-
static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
159
+
static void pm8xxx_irq_handler(struct irq_desc *desc)
160
160
{
161
161
struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
162
162
struct irq_chip *irq_chip = irq_desc_get_chip(desc);
+1
-1
drivers/mfd/t7l66xb.c
+1
-1
drivers/mfd/t7l66xb.c
···
185
185
/*--------------------------------------------------------------------------*/
186
186
187
187
/* Handle the T7L66XB interrupt mux */
188
-
static void t7l66xb_irq(unsigned int irq, struct irq_desc *desc)
188
+
static void t7l66xb_irq(struct irq_desc *desc)
189
189
{
190
190
struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
191
191
unsigned int isr;
+1
-2
drivers/mfd/tc6393xb.c
+1
-2
drivers/mfd/tc6393xb.c
···
522
522
523
523
/*--------------------------------------------------------------------------*/
524
524
525
-
static void
526
-
tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
525
+
static void tc6393xb_irq(struct irq_desc *desc)
527
526
{
528
527
struct tc6393xb *tc6393xb = irq_desc_get_handler_data(desc);
529
528
unsigned int isr;
+1
-1
drivers/mfd/ucb1x00-core.c
+1
-1
drivers/mfd/ucb1x00-core.c
···
282
282
* SIBCLK to talk to the chip. We leave the clock running until
283
283
* we have finished processing all interrupts from the chip.
284
284
*/
285
-
static void ucb1x00_irq(unsigned int __irq, struct irq_desc *desc)
285
+
static void ucb1x00_irq(struct irq_desc *desc)
286
286
{
287
287
struct ucb1x00 *ucb = irq_desc_get_handler_data(desc);
288
288
unsigned int isr, i;
+4
-2
drivers/net/ethernet/mellanox/mlx4/en_rx.c
+4
-2
drivers/net/ethernet/mellanox/mlx4/en_rx.c
···
1047
1047
1048
1048
/* If we used up all the quota - we're probably not done yet... */
1049
1049
if (done == budget) {
1050
-
int cpu_curr;
1051
1050
const struct cpumask *aff;
1051
+
struct irq_data *idata;
1052
+
int cpu_curr;
1052
1053
1053
1054
INC_PERF_COUNTER(priv->pstats.napi_quota);
1054
1055
1055
1056
cpu_curr = smp_processor_id();
1056
-
aff = irq_desc_get_irq_data(cq->irq_desc)->affinity;
1057
+
idata = irq_desc_get_irq_data(cq->irq_desc);
1058
+
aff = irq_data_get_affinity_mask(idata);
1057
1059
1058
1060
if (likely(cpumask_test_cpu(cpu_curr, aff)))
1059
1061
return budget;
+2
-3
drivers/pci/host/pci-keystone.c
+2
-3
drivers/pci/host/pci-keystone.c
···
110
110
return -EINVAL;
111
111
}
112
112
113
-
static void ks_pcie_msi_irq_handler(unsigned int __irq, struct irq_desc *desc)
113
+
static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
114
114
{
115
115
unsigned int irq = irq_desc_get_irq(desc);
116
116
struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
···
138
138
* Traverse through pending legacy interrupts and invoke handler for each. Also
139
139
* takes care of interrupt controller level mask/ack operation.
140
140
*/
141
-
static void ks_pcie_legacy_irq_handler(unsigned int __irq,
142
-
struct irq_desc *desc)
141
+
static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
143
142
{
144
143
unsigned int irq = irq_desc_get_irq(desc);
145
144
struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
+1
-1
drivers/pci/host/pci-xgene-msi.c
+1
-1
drivers/pci/host/pci-xgene-msi.c
+1
-1
drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
+1
-1
drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
···
143
143
return !!(readl(chip->base + offset) & BIT(shift));
144
144
}
145
145
146
-
static void cygnus_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
146
+
static void cygnus_gpio_irq_handler(struct irq_desc *desc)
147
147
{
148
148
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
149
149
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
+1
-1
drivers/pinctrl/intel/pinctrl-baytrail.c
+1
-1
drivers/pinctrl/intel/pinctrl-baytrail.c
···
425
425
}
426
426
}
427
427
428
-
static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
428
+
static void byt_gpio_irq_handler(struct irq_desc *desc)
429
429
{
430
430
struct irq_data *data = irq_desc_get_irq_data(desc);
431
431
struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
+1
-1
drivers/pinctrl/intel/pinctrl-cherryview.c
+1
-1
drivers/pinctrl/intel/pinctrl-cherryview.c
···
1414
1414
.flags = IRQCHIP_SKIP_SET_WAKE,
1415
1415
};
1416
1416
1417
-
static void chv_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1417
+
static void chv_gpio_irq_handler(struct irq_desc *desc)
1418
1418
{
1419
1419
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1420
1420
struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
+1
-1
drivers/pinctrl/intel/pinctrl-intel.c
+1
-1
drivers/pinctrl/intel/pinctrl-intel.c
···
836
836
}
837
837
}
838
838
839
-
static void intel_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
839
+
static void intel_gpio_irq_handler(struct irq_desc *desc)
840
840
{
841
841
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
842
842
struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
···
1190
1190
}
1191
1191
}
1192
1192
1193
-
static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc)
1193
+
static void mtk_eint_irq_handler(struct irq_desc *desc)
1194
1194
{
1195
1195
struct irq_chip *chip = irq_desc_get_chip(desc);
1196
1196
struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
+2
-2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
+2
-2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
···
860
860
chained_irq_exit(host_chip, desc);
861
861
}
862
862
863
-
static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
863
+
static void nmk_gpio_irq_handler(struct irq_desc *desc)
864
864
{
865
865
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
866
866
struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
···
873
873
__nmk_gpio_irq_handler(desc, status);
874
874
}
875
875
876
-
static void nmk_gpio_latent_irq_handler(unsigned int irq, struct irq_desc *desc)
876
+
static void nmk_gpio_latent_irq_handler(struct irq_desc *desc)
877
877
{
878
878
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
879
879
struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
+1
-2
drivers/pinctrl/pinctrl-adi2.c
+1
-2
drivers/pinctrl/pinctrl-adi2.c
···
530
530
static inline void preflow_handler(struct irq_desc *desc) { }
531
531
#endif
532
532
533
-
static void adi_gpio_handle_pint_irq(unsigned int inta_irq,
534
-
struct irq_desc *desc)
533
+
static void adi_gpio_handle_pint_irq(struct irq_desc *desc)
535
534
{
536
535
u32 request;
537
536
u32 level_mask, hwirq;
+3
-3
drivers/pinctrl/pinctrl-amd.c
+3
-3
drivers/pinctrl/pinctrl-amd.c
···
492
492
.irq_set_type = amd_gpio_irq_set_type,
493
493
};
494
494
495
-
static void amd_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc)
495
+
static void amd_gpio_irq_handler(struct irq_desc *desc)
496
496
{
497
-
unsigned int irq = irq_desc_get_irq(desc);
498
497
u32 i;
499
498
u32 off;
500
499
u32 reg;
501
500
u32 pin_reg;
502
501
u64 reg64;
503
502
int handled = 0;
503
+
unsigned int irq;
504
504
unsigned long flags;
505
505
struct irq_chip *chip = irq_desc_get_chip(desc);
506
506
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
···
541
541
}
542
542
543
543
if (handled == 0)
544
-
handle_bad_irq(irq, desc);
544
+
handle_bad_irq(desc);
545
545
546
546
spin_lock_irqsave(&gpio_dev->lock, flags);
547
547
reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
+1
-1
drivers/pinctrl/pinctrl-at91.c
+1
-1
drivers/pinctrl/pinctrl-at91.c
···
1585
1585
.irq_set_wake = gpio_irq_set_wake,
1586
1586
};
1587
1587
1588
-
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1588
+
static void gpio_irq_handler(struct irq_desc *desc)
1589
1589
{
1590
1590
struct irq_chip *chip = irq_desc_get_chip(desc);
1591
1591
struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
+1
-1
drivers/pinctrl/pinctrl-coh901.c
+1
-1
drivers/pinctrl/pinctrl-coh901.c
···
519
519
.irq_set_type = u300_gpio_irq_type,
520
520
};
521
521
522
-
static void u300_gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
522
+
static void u300_gpio_irq_handler(struct irq_desc *desc)
523
523
{
524
524
unsigned int irq = irq_desc_get_irq(desc);
525
525
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
+4
-6
drivers/pinctrl/pinctrl-pistachio.c
+4
-6
drivers/pinctrl/pinctrl-pistachio.c
···
1303
1303
}
1304
1304
1305
1305
if (type & IRQ_TYPE_LEVEL_MASK)
1306
-
__irq_set_handler_locked(data->irq, handle_level_irq);
1306
+
irq_set_handler_locked(data, handle_level_irq);
1307
1307
else
1308
-
__irq_set_handler_locked(data->irq, handle_edge_irq);
1308
+
irq_set_handler_locked(data, handle_edge_irq);
1309
1309
1310
1310
return 0;
1311
1311
}
1312
1312
1313
-
static void pistachio_gpio_irq_handler(unsigned int __irq,
1314
-
struct irq_desc *desc)
1313
+
static void pistachio_gpio_irq_handler(struct irq_desc *desc)
1315
1314
{
1316
-
unsigned int irq = irq_desc_get_irq(desc);
1317
1315
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1318
1316
struct pistachio_gpio_bank *bank = gc_to_bank(gc);
1319
-
struct irq_chip *chip = irq_get_chip(irq);
1317
+
struct irq_chip *chip = irq_desc_get_chip(desc);
1320
1318
unsigned long pending;
1321
1319
unsigned int pin;
1322
1320
+1
-1
drivers/pinctrl/pinctrl-rockchip.c
+1
-1
drivers/pinctrl/pinctrl-rockchip.c
···
1475
1475
* Interrupt handling
1476
1476
*/
1477
1477
1478
-
static void rockchip_irq_demux(unsigned int __irq, struct irq_desc *desc)
1478
+
static void rockchip_irq_demux(struct irq_desc *desc)
1479
1479
{
1480
1480
struct irq_chip *chip = irq_desc_get_chip(desc);
1481
1481
struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
+1
-1
drivers/pinctrl/pinctrl-single.c
+1
-1
drivers/pinctrl/pinctrl-single.c
···
1679
1679
* Use this if you have a separate interrupt for each
1680
1680
* pinctrl-single instance.
1681
1681
*/
1682
-
static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1682
+
static void pcs_irq_chain_handler(struct irq_desc *desc)
1683
1683
{
1684
1684
struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1685
1685
struct irq_chip *chip;
+2
-2
drivers/pinctrl/pinctrl-st.c
+2
-2
drivers/pinctrl/pinctrl-st.c
···
1460
1460
}
1461
1461
}
1462
1462
1463
-
static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1463
+
static void st_gpio_irq_handler(struct irq_desc *desc)
1464
1464
{
1465
1465
/* interrupt dedicated per bank */
1466
1466
struct irq_chip *chip = irq_desc_get_chip(desc);
···
1472
1472
chained_irq_exit(chip, desc);
1473
1473
}
1474
1474
1475
-
static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
1475
+
static void st_gpio_irqmux_handler(struct irq_desc *desc)
1476
1476
{
1477
1477
struct irq_chip *chip = irq_desc_get_chip(desc);
1478
1478
struct st_pinctrl *info = irq_desc_get_handler_data(desc);
+2
-3
drivers/pinctrl/qcom/pinctrl-msm.c
+2
-3
drivers/pinctrl/qcom/pinctrl-msm.c
···
765
765
.irq_set_wake = msm_gpio_irq_set_wake,
766
766
};
767
767
768
-
static void msm_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc)
768
+
static void msm_gpio_irq_handler(struct irq_desc *desc)
769
769
{
770
-
unsigned int irq = irq_desc_get_irq(desc);
771
770
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
772
771
const struct msm_pingroup *g;
773
772
struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
···
794
795
795
796
/* No interrupts were flagged */
796
797
if (handled == 0)
797
-
handle_bad_irq(irq, desc);
798
+
handle_bad_irq(desc);
798
799
799
800
chained_irq_exit(chip, desc);
800
801
}
+2
-2
drivers/pinctrl/samsung/pinctrl-exynos.c
+2
-2
drivers/pinctrl/samsung/pinctrl-exynos.c
···
419
419
};
420
420
421
421
/* interrupt handler for wakeup interrupts 0..15 */
422
-
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
422
+
static void exynos_irq_eint0_15(struct irq_desc *desc)
423
423
{
424
424
struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
425
425
struct samsung_pin_bank *bank = eintd->bank;
···
451
451
}
452
452
453
453
/* interrupt handler for wakeup interrupt 16 */
454
-
static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
454
+
static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
455
455
{
456
456
struct irq_chip *chip = irq_desc_get_chip(desc);
457
457
struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
+4
-4
drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+4
-4
drivers/pinctrl/samsung/pinctrl-s3c24xx.c
···
240
240
.irq_set_type = s3c24xx_eint_type,
241
241
};
242
242
243
-
static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
243
+
static void s3c2410_demux_eint0_3(struct irq_desc *desc)
244
244
{
245
245
struct irq_data *data = irq_desc_get_irq_data(desc);
246
246
struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
···
295
295
.irq_set_type = s3c24xx_eint_type,
296
296
};
297
297
298
-
static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
298
+
static void s3c2412_demux_eint0_3(struct irq_desc *desc)
299
299
{
300
300
struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
301
301
struct irq_data *data = irq_desc_get_irq_data(desc);
···
388
388
chained_irq_exit(chip, desc);
389
389
}
390
390
391
-
static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc)
391
+
static void s3c24xx_demux_eint4_7(struct irq_desc *desc)
392
392
{
393
393
s3c24xx_demux_eint(desc, 0, 0xf0);
394
394
}
395
395
396
-
static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc)
396
+
static void s3c24xx_demux_eint8_23(struct irq_desc *desc)
397
397
{
398
398
s3c24xx_demux_eint(desc, 8, 0xffff00);
399
399
}
+5
-5
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+5
-5
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
···
407
407
.xlate = irq_domain_xlate_twocell,
408
408
};
409
409
410
-
static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc)
410
+
static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
411
411
{
412
412
struct irq_chip *chip = irq_desc_get_chip(desc);
413
413
struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
···
631
631
chained_irq_exit(chip, desc);
632
632
}
633
633
634
-
static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
634
+
static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
635
635
{
636
636
s3c64xx_irq_demux_eint(desc, 0xf);
637
637
}
638
638
639
-
static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
639
+
static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
640
640
{
641
641
s3c64xx_irq_demux_eint(desc, 0xff0);
642
642
}
643
643
644
-
static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
644
+
static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
645
645
{
646
646
s3c64xx_irq_demux_eint(desc, 0xff000);
647
647
}
648
648
649
-
static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
649
+
static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
650
650
{
651
651
s3c64xx_irq_demux_eint(desc, 0xff00000);
652
652
}
+2
-2
drivers/pinctrl/sirf/pinctrl-atlas7.c
+2
-2
drivers/pinctrl/sirf/pinctrl-atlas7.c
···
4489
4489
.irq_set_type = atlas7_gpio_irq_type,
4490
4490
};
4491
4491
4492
-
static void atlas7_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc)
4492
+
static void atlas7_gpio_handle_irq(struct irq_desc *desc)
4493
4493
{
4494
4494
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
4495
4495
struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
···
4512
4512
if (!status) {
4513
4513
pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n",
4514
4514
__func__, gc->label, status);
4515
-
handle_bad_irq(irq, desc);
4515
+
handle_bad_irq(desc);
4516
4516
return;
4517
4517
}
4518
4518
+2
-2
drivers/pinctrl/sirf/pinctrl-sirf.c
+2
-2
drivers/pinctrl/sirf/pinctrl-sirf.c
···
545
545
.irq_set_type = sirfsoc_gpio_irq_type,
546
546
};
547
547
548
-
static void sirfsoc_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc)
548
+
static void sirfsoc_gpio_handle_irq(struct irq_desc *desc)
549
549
{
550
550
unsigned int irq = irq_desc_get_irq(desc);
551
551
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
···
570
570
printk(KERN_WARNING
571
571
"%s: gpio id %d status %#x no interrupt is flagged\n",
572
572
__func__, bank->id, status);
573
-
handle_bad_irq(irq, desc);
573
+
handle_bad_irq(desc);
574
574
return;
575
575
}
576
576
+1
-1
drivers/pinctrl/spear/pinctrl-plgpio.c
+1
-1
drivers/pinctrl/spear/pinctrl-plgpio.c
···
356
356
.irq_set_type = plgpio_irq_set_type,
357
357
};
358
358
359
-
static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
359
+
static void plgpio_irq_handler(struct irq_desc *desc)
360
360
{
361
361
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
362
362
struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
+5
-7
drivers/pinctrl/sunxi/pinctrl-sunxi.c
+5
-7
drivers/pinctrl/sunxi/pinctrl-sunxi.c
···
617
617
spin_lock_irqsave(&pctl->lock, flags);
618
618
619
619
if (type & IRQ_TYPE_LEVEL_MASK)
620
-
__irq_set_chip_handler_name_locked(d->irq,
621
-
&sunxi_pinctrl_level_irq_chip,
622
-
handle_fasteoi_irq, NULL);
620
+
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
621
+
handle_fasteoi_irq, NULL);
623
622
else
624
-
__irq_set_chip_handler_name_locked(d->irq,
625
-
&sunxi_pinctrl_edge_irq_chip,
626
-
handle_edge_irq, NULL);
623
+
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
624
+
handle_edge_irq, NULL);
627
625
628
626
regval = readl(pctl->membase + reg);
629
627
regval &= ~(IRQ_CFG_IRQ_MASK << index);
···
740
742
.xlate = sunxi_pinctrl_irq_of_xlate,
741
743
};
742
744
743
-
static void sunxi_pinctrl_irq_handler(unsigned __irq, struct irq_desc *desc)
745
+
static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
744
746
{
745
747
unsigned int irq = irq_desc_get_irq(desc);
746
748
struct irq_chip *chip = irq_desc_get_chip(desc);
+1
-1
drivers/sh/intc/core.c
+1
-1
drivers/sh/intc/core.c
+1
-9
drivers/sh/intc/internals.h
+1
-9
drivers/sh/intc/internals.h
···
99
99
*/
100
100
static inline void activate_irq(int irq)
101
101
{
102
-
#ifdef CONFIG_ARM
103
-
/* ARM requires an extra step to clear IRQ_NOREQUEST, which it
104
-
* sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
105
-
*/
106
-
set_irq_flags(irq, IRQF_VALID);
107
-
#else
108
-
/* same effect on other architectures */
109
-
irq_set_noprobe(irq);
110
-
#endif
102
+
irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
111
103
}
112
104
113
105
static inline int intc_handle_int_cmp(const void *a, const void *b)
+2
-2
drivers/sh/intc/virq.c
+2
-2
drivers/sh/intc/virq.c
···
109
109
return 0;
110
110
}
111
111
112
-
static void intc_virq_handler(unsigned int __irq, struct irq_desc *desc)
112
+
static void intc_virq_handler(struct irq_desc *desc)
113
113
{
114
114
unsigned int irq = irq_desc_get_irq(desc);
115
115
struct irq_data *data = irq_desc_get_irq_data(desc);
···
127
127
handle = (unsigned long)irq_desc_get_handler_data(vdesc);
128
128
addr = INTC_REG(d, _INTC_ADDR_E(handle), 0);
129
129
if (intc_reg_fns[_INTC_FN(handle)](addr, handle, 0))
130
-
generic_handle_irq_desc(entry->irq, vdesc);
130
+
generic_handle_irq_desc(vdesc);
131
131
}
132
132
}
133
133
+3
-3
drivers/soc/dove/pmu.c
+3
-3
drivers/soc/dove/pmu.c
···
222
222
}
223
223
224
224
/* PMU IRQ controller */
225
-
static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
225
+
static void pmu_irq_handler(struct irq_desc *desc)
226
226
{
227
-
struct pmu_data *pmu = irq_get_handler_data(irq);
227
+
struct pmu_data *pmu = irq_desc_get_handler_data(desc);
228
228
struct irq_chip_generic *gc = pmu->irq_gc;
229
229
struct irq_domain *domain = pmu->irq_domain;
230
230
void __iomem *base = gc->reg_base;
···
232
232
u32 done = ~0;
233
233
234
234
if (stat == 0) {
235
-
handle_bad_irq(irq, desc);
235
+
handle_bad_irq(desc);
236
236
return;
237
237
}
238
238
+1
-1
drivers/spmi/spmi-pmic-arb.c
+1
-1
drivers/spmi/spmi-pmic-arb.c
···
451
451
}
452
452
}
453
453
454
-
static void pmic_arb_chained_irq(unsigned int irq, struct irq_desc *desc)
454
+
static void pmic_arb_chained_irq(struct irq_desc *desc)
455
455
{
456
456
struct spmi_pmic_arb_dev *pa = irq_desc_get_handler_data(desc);
457
457
struct irq_chip *chip = irq_desc_get_chip(desc);
+52
-29
include/linux/irq.h
+52
-29
include/linux/irq.h
···
110
110
/*
111
111
* Return value for chip->irq_set_affinity()
112
112
*
113
-
* IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
114
-
* IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
113
+
* IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
114
+
* IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
115
115
* IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
116
116
* support stacked irqchips, which indicates skipping
117
117
* all descendent irqchips.
···
129
129
* struct irq_common_data - per irq data shared by all irqchips
130
130
* @state_use_accessors: status information for irq chip functions.
131
131
* Use accessor functions to deal with it
132
+
* @node: node index useful for balancing
133
+
* @handler_data: per-IRQ data for the irq_chip methods
134
+
* @affinity: IRQ affinity on SMP
135
+
* @msi_desc: MSI descriptor
132
136
*/
133
137
struct irq_common_data {
134
138
unsigned int state_use_accessors;
139
+
#ifdef CONFIG_NUMA
140
+
unsigned int node;
141
+
#endif
142
+
void *handler_data;
143
+
struct msi_desc *msi_desc;
144
+
cpumask_var_t affinity;
135
145
};
136
146
137
147
/**
···
149
139
* @mask: precomputed bitmask for accessing the chip registers
150
140
* @irq: interrupt number
151
141
* @hwirq: hardware interrupt number, local to the interrupt domain
152
-
* @node: node index useful for balancing
153
142
* @common: point to data shared by all irqchips
154
143
* @chip: low level interrupt hardware access
155
144
* @domain: Interrupt translation domain; responsible for mapping
156
145
* between hwirq number and linux irq number.
157
146
* @parent_data: pointer to parent struct irq_data to support hierarchy
158
147
* irq_domain
159
-
* @handler_data: per-IRQ data for the irq_chip methods
160
148
* @chip_data: platform-specific per-chip private data for the chip
161
149
* methods, to allow shared chip implementations
162
-
* @msi_desc: MSI descriptor
163
-
* @affinity: IRQ affinity on SMP
164
-
*
165
-
* The fields here need to overlay the ones in irq_desc until we
166
-
* cleaned up the direct references and switched everything over to
167
-
* irq_data.
168
150
*/
169
151
struct irq_data {
170
152
u32 mask;
171
153
unsigned int irq;
172
154
unsigned long hwirq;
173
-
unsigned int node;
174
155
struct irq_common_data *common;
175
156
struct irq_chip *chip;
176
157
struct irq_domain *domain;
177
158
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
178
159
struct irq_data *parent_data;
179
160
#endif
180
-
void *handler_data;
181
161
void *chip_data;
182
-
struct msi_desc *msi_desc;
183
-
cpumask_var_t affinity;
184
162
};
185
163
186
164
/*
···
188
190
* IRQD_IRQ_MASKED - Masked state of the interrupt
189
191
* IRQD_IRQ_INPROGRESS - In progress state of the interrupt
190
192
* IRQD_WAKEUP_ARMED - Wakeup mode armed
193
+
* IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
191
194
*/
192
195
enum {
193
196
IRQD_TRIGGER_MASK = 0xf,
···
203
204
IRQD_IRQ_MASKED = (1 << 17),
204
205
IRQD_IRQ_INPROGRESS = (1 << 18),
205
206
IRQD_WAKEUP_ARMED = (1 << 19),
207
+
IRQD_FORWARDED_TO_VCPU = (1 << 20),
206
208
};
207
209
208
210
#define __irqd_to_state(d) ((d)->common->state_use_accessors)
···
282
282
return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
283
283
}
284
284
285
+
static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
286
+
{
287
+
return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
288
+
}
289
+
290
+
static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
291
+
{
292
+
__irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
293
+
}
294
+
295
+
static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
296
+
{
297
+
__irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
298
+
}
285
299
286
300
/*
287
301
* Functions for chained handlers which can be enabled/disabled by the
···
475
461
* Built-in IRQ handlers for various IRQ types,
476
462
* callable via desc->handle_irq()
477
463
*/
478
-
extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
479
-
extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
480
-
extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
481
-
extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
482
-
extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
483
-
extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
484
-
extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
485
-
extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
464
+
extern void handle_level_irq(struct irq_desc *desc);
465
+
extern void handle_fasteoi_irq(struct irq_desc *desc);
466
+
extern void handle_edge_irq(struct irq_desc *desc);
467
+
extern void handle_edge_eoi_irq(struct irq_desc *desc);
468
+
extern void handle_simple_irq(struct irq_desc *desc);
469
+
extern void handle_percpu_irq(struct irq_desc *desc);
470
+
extern void handle_percpu_devid_irq(struct irq_desc *desc);
471
+
extern void handle_bad_irq(struct irq_desc *desc);
486
472
extern void handle_nested_irq(unsigned int irq);
487
473
488
474
extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
···
641
627
static inline void *irq_get_handler_data(unsigned int irq)
642
628
{
643
629
struct irq_data *d = irq_get_irq_data(irq);
644
-
return d ? d->handler_data : NULL;
630
+
return d ? d->common->handler_data : NULL;
645
631
}
646
632
647
633
static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
648
634
{
649
-
return d->handler_data;
635
+
return d->common->handler_data;
650
636
}
651
637
652
638
static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
653
639
{
654
640
struct irq_data *d = irq_get_irq_data(irq);
655
-
return d ? d->msi_desc : NULL;
641
+
return d ? d->common->msi_desc : NULL;
656
642
}
657
643
658
644
static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
659
645
{
660
-
return d->msi_desc;
646
+
return d->common->msi_desc;
661
647
}
662
648
663
649
static inline u32 irq_get_trigger_type(unsigned int irq)
···
666
652
return d ? irqd_get_trigger_type(d) : 0;
667
653
}
668
654
655
+
static inline int irq_common_data_get_node(struct irq_common_data *d)
656
+
{
657
+
#ifdef CONFIG_NUMA
658
+
return d->node;
659
+
#else
660
+
return 0;
661
+
#endif
662
+
}
663
+
669
664
static inline int irq_data_get_node(struct irq_data *d)
670
665
{
671
-
return d->node;
666
+
return irq_common_data_get_node(d->common);
672
667
}
673
668
674
669
static inline struct cpumask *irq_get_affinity_mask(int irq)
675
670
{
676
671
struct irq_data *d = irq_get_irq_data(irq);
677
672
678
-
return d ? d->affinity : NULL;
673
+
return d ? d->common->affinity : NULL;
679
674
}
680
675
681
676
static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
682
677
{
683
-
return d->affinity;
678
+
return d->common->affinity;
684
679
}
685
680
686
681
unsigned int arch_dynirq_lower_bound(unsigned int from);
+6
-35
include/linux/irqdesc.h
+6
-35
include/linux/irqdesc.h
···
98
98
99
99
static inline struct irq_desc *irq_data_to_desc(struct irq_data *data)
100
100
{
101
-
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
102
-
return irq_to_desc(data->irq);
103
-
#else
104
-
return container_of(data, struct irq_desc, irq_data);
105
-
#endif
101
+
return container_of(data->common, struct irq_desc, irq_common_data);
106
102
}
107
103
108
104
static inline unsigned int irq_desc_get_irq(struct irq_desc *desc)
···
123
127
124
128
static inline void *irq_desc_get_handler_data(struct irq_desc *desc)
125
129
{
126
-
return desc->irq_data.handler_data;
130
+
return desc->irq_common_data.handler_data;
127
131
}
128
132
129
133
static inline struct msi_desc *irq_desc_get_msi_desc(struct irq_desc *desc)
130
134
{
131
-
return desc->irq_data.msi_desc;
135
+
return desc->irq_common_data.msi_desc;
132
136
}
133
137
134
138
/*
135
139
* Architectures call this to let the generic IRQ layer
136
-
* handle an interrupt. If the descriptor is attached to an
137
-
* irqchip-style controller then we call the ->handle_irq() handler,
138
-
* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
140
+
* handle an interrupt.
139
141
*/
140
-
static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
142
+
static inline void generic_handle_irq_desc(struct irq_desc *desc)
141
143
{
142
-
desc->handle_irq(irq, desc);
144
+
desc->handle_irq(desc);
143
145
}
144
146
145
147
int generic_handle_irq(unsigned int irq);
···
168
174
static inline int irq_has_action(unsigned int irq)
169
175
{
170
176
return irq_desc_has_action(irq_to_desc(irq));
171
-
}
172
-
173
-
/* caller has locked the irq_desc and both params are valid */
174
-
static inline void __irq_set_handler_locked(unsigned int irq,
175
-
irq_flow_handler_t handler)
176
-
{
177
-
struct irq_desc *desc;
178
-
179
-
desc = irq_to_desc(irq);
180
-
desc->handle_irq = handler;
181
-
}
182
-
183
-
/* caller has locked the irq_desc and both params are valid */
184
-
static inline void
185
-
__irq_set_chip_handler_name_locked(unsigned int irq, struct irq_chip *chip,
186
-
irq_flow_handler_t handler, const char *name)
187
-
{
188
-
struct irq_desc *desc;
189
-
190
-
desc = irq_to_desc(irq);
191
-
irq_desc_get_irq_data(desc)->chip = chip;
192
-
desc->handle_irq = handler;
193
-
desc->name = name;
194
177
}
195
178
196
179
/**
+1
-1
include/linux/irqhandler.h
+1
-1
include/linux/irqhandler.h
+11
-22
kernel/irq/chip.c
+11
-22
kernel/irq/chip.c
···
83
83
84
84
if (!desc)
85
85
return -EINVAL;
86
-
desc->irq_data.handler_data = data;
86
+
desc->irq_common_data.handler_data = data;
87
87
irq_put_desc_unlock(desc, flags);
88
88
return 0;
89
89
}
···
105
105
106
106
if (!desc)
107
107
return -EINVAL;
108
-
desc->irq_data.msi_desc = entry;
108
+
desc->irq_common_data.msi_desc = entry;
109
109
if (entry && !irq_offset)
110
110
entry->irq = irq_base;
111
111
irq_put_desc_unlock(desc, flags);
···
372
372
373
373
/**
374
374
* handle_simple_irq - Simple and software-decoded IRQs.
375
-
* @irq: the interrupt number
376
375
* @desc: the interrupt description structure for this irq
377
376
*
378
377
* Simple interrupts are either sent from a demultiplexing interrupt
···
381
382
* Note: The caller is expected to handle the ack, clear, mask and
382
383
* unmask issues if necessary.
383
384
*/
384
-
void
385
-
handle_simple_irq(unsigned int irq, struct irq_desc *desc)
385
+
void handle_simple_irq(struct irq_desc *desc)
386
386
{
387
387
raw_spin_lock(&desc->lock);
388
388
···
423
425
424
426
/**
425
427
* handle_level_irq - Level type irq handler
426
-
* @irq: the interrupt number
427
428
* @desc: the interrupt description structure for this irq
428
429
*
429
430
* Level type interrupts are active as long as the hardware line has
···
430
433
* it after the associated handler has acknowledged the device, so the
431
434
* interrupt line is back to inactive.
432
435
*/
433
-
void
434
-
handle_level_irq(unsigned int irq, struct irq_desc *desc)
436
+
void handle_level_irq(struct irq_desc *desc)
435
437
{
436
438
raw_spin_lock(&desc->lock);
437
439
mask_ack_irq(desc);
···
492
496
493
497
/**
494
498
* handle_fasteoi_irq - irq handler for transparent controllers
495
-
* @irq: the interrupt number
496
499
* @desc: the interrupt description structure for this irq
497
500
*
498
501
* Only a single callback will be issued to the chip: an ->eoi()
···
499
504
* for modern forms of interrupt handlers, which handle the flow
500
505
* details in hardware, transparently.
501
506
*/
502
-
void
503
-
handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
507
+
void handle_fasteoi_irq(struct irq_desc *desc)
504
508
{
505
509
struct irq_chip *chip = desc->irq_data.chip;
506
510
···
540
546
541
547
/**
542
548
* handle_edge_irq - edge type IRQ handler
543
-
* @irq: the interrupt number
544
549
* @desc: the interrupt description structure for this irq
545
550
*
546
551
* Interrupt occures on the falling and/or rising edge of a hardware
···
553
560
* the handler was running. If all pending interrupts are handled, the
554
561
* loop is left.
555
562
*/
556
-
void
557
-
handle_edge_irq(unsigned int irq, struct irq_desc *desc)
563
+
void handle_edge_irq(struct irq_desc *desc)
558
564
{
559
565
raw_spin_lock(&desc->lock);
560
566
···
610
618
#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
611
619
/**
612
620
* handle_edge_eoi_irq - edge eoi type IRQ handler
613
-
* @irq: the interrupt number
614
621
* @desc: the interrupt description structure for this irq
615
622
*
616
623
* Similar as the above handle_edge_irq, but using eoi and w/o the
617
624
* mask/unmask logic.
618
625
*/
619
-
void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
626
+
void handle_edge_eoi_irq(struct irq_desc *desc)
620
627
{
621
628
struct irq_chip *chip = irq_desc_get_chip(desc);
622
629
···
656
665
657
666
/**
658
667
* handle_percpu_irq - Per CPU local irq handler
659
-
* @irq: the interrupt number
660
668
* @desc: the interrupt description structure for this irq
661
669
*
662
670
* Per CPU interrupts on SMP machines without locking requirements
663
671
*/
664
-
void
665
-
handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
672
+
void handle_percpu_irq(struct irq_desc *desc)
666
673
{
667
674
struct irq_chip *chip = irq_desc_get_chip(desc);
668
675
···
677
688
678
689
/**
679
690
* handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
680
-
* @irq: the interrupt number
681
691
* @desc: the interrupt description structure for this irq
682
692
*
683
693
* Per CPU interrupts on SMP machines without locking requirements. Same as
···
686
698
* contain the real device id for the cpu on which this handler is
687
699
* called
688
700
*/
689
-
void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
701
+
void handle_percpu_devid_irq(struct irq_desc *desc)
690
702
{
691
703
struct irq_chip *chip = irq_desc_get_chip(desc);
692
704
struct irqaction *action = desc->action;
693
705
void *dev_id = raw_cpu_ptr(action->percpu_dev_id);
706
+
unsigned int irq = irq_desc_get_irq(desc);
694
707
irqreturn_t res;
695
708
696
709
kstat_incr_irqs_this_cpu(desc);
···
785
796
return;
786
797
787
798
__irq_do_set_handler(desc, handle, 1, NULL);
788
-
desc->irq_data.handler_data = data;
799
+
desc->irq_common_data.handler_data = data;
789
800
790
801
irq_put_desc_busunlock(desc, flags);
791
802
}
+3
-1
kernel/irq/handle.c
+3
-1
kernel/irq/handle.c
···
27
27
*
28
28
* Handles spurious and unhandled IRQ's. It also prints a debugmessage.
29
29
*/
30
-
void handle_bad_irq(unsigned int irq, struct irq_desc *desc)
30
+
void handle_bad_irq(struct irq_desc *desc)
31
31
{
32
+
unsigned int irq = irq_desc_get_irq(desc);
33
+
32
34
print_irq_desc(irq, desc);
33
35
kstat_incr_irqs_this_cpu(desc);
34
36
ack_bad_irq(irq);
+1
-1
kernel/irq/internals.h
+1
-1
kernel/irq/internals.h
+12
-8
kernel/irq/irqdesc.c
+12
-8
kernel/irq/irqdesc.c
···
38
38
#ifdef CONFIG_SMP
39
39
static int alloc_masks(struct irq_desc *desc, gfp_t gfp, int node)
40
40
{
41
-
if (!zalloc_cpumask_var_node(&desc->irq_data.affinity, gfp, node))
41
+
if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity,
42
+
gfp, node))
42
43
return -ENOMEM;
43
44
44
45
#ifdef CONFIG_GENERIC_PENDING_IRQ
45
46
if (!zalloc_cpumask_var_node(&desc->pending_mask, gfp, node)) {
46
-
free_cpumask_var(desc->irq_data.affinity);
47
+
free_cpumask_var(desc->irq_common_data.affinity);
47
48
return -ENOMEM;
48
49
}
49
50
#endif
···
53
52
54
53
static void desc_smp_init(struct irq_desc *desc, int node)
55
54
{
56
-
desc->irq_data.node = node;
57
-
cpumask_copy(desc->irq_data.affinity, irq_default_affinity);
55
+
cpumask_copy(desc->irq_common_data.affinity, irq_default_affinity);
58
56
#ifdef CONFIG_GENERIC_PENDING_IRQ
59
57
cpumask_clear(desc->pending_mask);
58
+
#endif
59
+
#ifdef CONFIG_NUMA
60
+
desc->irq_common_data.node = node;
60
61
#endif
61
62
}
62
63
···
73
70
{
74
71
int cpu;
75
72
73
+
desc->irq_common_data.handler_data = NULL;
74
+
desc->irq_common_data.msi_desc = NULL;
75
+
76
76
desc->irq_data.common = &desc->irq_common_data;
77
77
desc->irq_data.irq = irq;
78
78
desc->irq_data.chip = &no_irq_chip;
79
79
desc->irq_data.chip_data = NULL;
80
-
desc->irq_data.handler_data = NULL;
81
-
desc->irq_data.msi_desc = NULL;
82
80
irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
83
81
irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
84
82
desc->handle_irq = handle_bad_irq;
···
125
121
#ifdef CONFIG_GENERIC_PENDING_IRQ
126
122
free_cpumask_var(desc->pending_mask);
127
123
#endif
128
-
free_cpumask_var(desc->irq_data.affinity);
124
+
free_cpumask_var(desc->irq_common_data.affinity);
129
125
}
130
126
#else
131
127
static inline void free_masks(struct irq_desc *desc) { }
···
347
343
348
344
if (!desc)
349
345
return -EINVAL;
350
-
generic_handle_irq_desc(irq, desc);
346
+
generic_handle_irq_desc(desc);
351
347
return 0;
352
348
}
353
349
EXPORT_SYMBOL_GPL(generic_handle_irq);
-1
kernel/irq/irqdomain.c
-1
kernel/irq/irqdomain.c
+6
-6
kernel/irq/manage.c
+6
-6
kernel/irq/manage.c
···
192
192
switch (ret) {
193
193
case IRQ_SET_MASK_OK:
194
194
case IRQ_SET_MASK_OK_DONE:
195
-
cpumask_copy(data->affinity, mask);
195
+
cpumask_copy(desc->irq_common_data.affinity, mask);
196
196
case IRQ_SET_MASK_OK_NOCOPY:
197
197
irq_set_thread_affinity(desc);
198
198
ret = 0;
···
304
304
if (irq_move_pending(&desc->irq_data))
305
305
irq_get_pending(cpumask, desc);
306
306
else
307
-
cpumask_copy(cpumask, desc->irq_data.affinity);
307
+
cpumask_copy(cpumask, desc->irq_common_data.affinity);
308
308
raw_spin_unlock_irqrestore(&desc->lock, flags);
309
309
310
310
notify->notify(notify, cpumask);
···
375
375
* one of the targets is online.
376
376
*/
377
377
if (irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) {
378
-
if (cpumask_intersects(desc->irq_data.affinity,
378
+
if (cpumask_intersects(desc->irq_common_data.affinity,
379
379
cpu_online_mask))
380
-
set = desc->irq_data.affinity;
380
+
set = desc->irq_common_data.affinity;
381
381
else
382
382
irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET);
383
383
}
···
829
829
* This code is triggered unconditionally. Check the affinity
830
830
* mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out.
831
831
*/
832
-
if (desc->irq_data.affinity)
833
-
cpumask_copy(mask, desc->irq_data.affinity);
832
+
if (desc->irq_common_data.affinity)
833
+
cpumask_copy(mask, desc->irq_common_data.affinity);
834
834
else
835
835
valid = false;
836
836
raw_spin_unlock_irq(&desc->lock);
+1
-1
kernel/irq/proc.c
+1
-1
kernel/irq/proc.c
···
39
39
static int show_irq_affinity(int type, struct seq_file *m, void *v)
40
40
{
41
41
struct irq_desc *desc = irq_to_desc((long)m->private);
42
-
const struct cpumask *mask = desc->irq_data.affinity;
42
+
const struct cpumask *mask = desc->irq_common_data.affinity;
43
43
44
44
#ifdef CONFIG_GENERIC_PENDING_IRQ
45
45
if (irqd_is_setaffinity_pending(&desc->irq_data))