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Merge branch 'hv-msi-parent-domain' into main
Nam Cao says:
====================
Subject: [PATCH for-netdev v2 0/2] PCI: hv: MSI parent domain conversion
This series originally belongs to a bigger series sent to PCI tree:
https://lore.kernel.org/linux-pci/024f0122314198fe0a42fef01af53e8953a687ec.1750858083.git.namcao@linutronix.de/
However, during review, we noticed that the patch conflicts with another
patch in netdev tree:
https://lore.kernel.org/netdev/1749651015-9668-1-git-send-email-shradhagupta@linux.microsoft.com/
As this series has no dependency with the rest of the series, we think it
is best to split out this one and send it to netdev, to avoid conflict
resolution headache later on.
Can netdev maintainers please pick it up?
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
+85
-28
+1
drivers/pci/Kconfig
+1
drivers/pci/Kconfig
···
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tristate "Hyper-V PCI Frontend"
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depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI && SYSFS
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select PCI_HYPERV_INTERFACE
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+
select IRQ_MSI_LIB
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help
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The PCI device frontend driver allows the kernel to import arbitrary
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PCI devices from a PCI backend to support PCI driver domains.
+83
-28
drivers/pci/controller/pci-hyperv.c
+83
-28
drivers/pci/controller/pci-hyperv.c
···
44
44
#include <linux/delay.h>
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#include <linux/semaphore.h>
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#include <linux/irq.h>
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+
#include <linux/irqchip/irq-msi-lib.h>
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#include <linux/msi.h>
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#include <linux/hyperv.h>
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#include <linux/refcount.h>
···
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struct list_head children;
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struct list_head dr_list;
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510
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-
struct msi_domain_info msi_info;
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struct irq_domain *irq_domain;
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512
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struct workqueue_struct *wq;
···
576
576
static void hv_pci_onchannelcallback(void *context);
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#ifdef CONFIG_X86
579
-
#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED
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-
#define FLOW_HANDLER handle_edge_irq
581
-
#define FLOW_NAME "edge"
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+
#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED
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+
#define HV_MSI_CHIP_FLAGS MSI_CHIP_FLAG_SET_ACK
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static int hv_pci_irqchip_init(void)
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583
{
···
722
723
#define HV_PCI_MSI_SPI_START 64
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#define HV_PCI_MSI_SPI_NR (1020 - HV_PCI_MSI_SPI_START)
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#define DELIVERY_MODE 0
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-
#define FLOW_HANDLER NULL
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-
#define FLOW_NAME NULL
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+
#define HV_MSI_CHIP_FLAGS MSI_CHIP_FLAG_SET_EOI
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#define hv_msi_prepare NULL
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struct hv_pci_chip_data {
···
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struct msi_desc *msi = irq_data_get_msi_desc(irq_data);
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pdev = msi_desc_to_pci_dev(msi);
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-
hbus = info->data;
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+
hbus = domain->host_data;
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int_desc = irq_data_get_irq_chip_data(irq_data);
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if (!int_desc)
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return;
···
1703
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static void hv_irq_mask(struct irq_data *data)
1705
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{
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-
pci_msi_mask_irq(data);
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if (data->parent_data->chip->irq_mask)
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irq_chip_mask_parent(data);
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}
···
1713
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if (data->parent_data->chip->irq_unmask)
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irq_chip_unmask_parent(data);
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-
pci_msi_unmask_irq(data);
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}
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struct compose_comp_ctxt {
···
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msg->data = 0;
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}
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+
static bool hv_pcie_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
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+
struct irq_domain *real_parent, struct msi_domain_info *info)
2106
+
{
2107
+
struct irq_chip *chip = info->chip;
2108
+
2109
+
if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
2110
+
return false;
2111
+
2112
+
info->ops->msi_prepare = hv_msi_prepare;
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+
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+
chip->irq_set_affinity = irq_chip_set_affinity_parent;
2115
+
2116
+
if (IS_ENABLED(CONFIG_X86))
2117
+
chip->flags |= IRQCHIP_MOVE_DEFERRED;
2118
+
2119
+
return true;
2120
+
}
2121
+
2122
+
#define HV_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
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+
MSI_FLAG_USE_DEF_CHIP_OPS | \
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+
MSI_FLAG_PCI_MSI_MASK_PARENT)
2125
+
#define HV_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \
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+
MSI_FLAG_PCI_MSIX | \
2127
+
MSI_FLAG_PCI_MSIX_ALLOC_DYN | \
2128
+
MSI_GENERIC_FLAGS_MASK)
2129
+
2130
+
static const struct msi_parent_ops hv_pcie_msi_parent_ops = {
2131
+
.required_flags = HV_PCIE_MSI_FLAGS_REQUIRED,
2132
+
.supported_flags = HV_PCIE_MSI_FLAGS_SUPPORTED,
2133
+
.bus_select_token = DOMAIN_BUS_PCI_MSI,
2134
+
.chip_flags = HV_MSI_CHIP_FLAGS,
2135
+
.prefix = "HV-",
2136
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.init_dev_msi_info = hv_pcie_init_dev_msi_info,
2137
+
};
2138
+
2100
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/* HW Interrupt Chip Descriptor */
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static struct irq_chip hv_msi_irq_chip = {
2102
2141
.name = "Hyper-V PCIe MSI",
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.irq_compose_msi_msg = hv_compose_msi_msg,
2104
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.irq_set_affinity = irq_chip_set_affinity_parent,
2105
-
#ifdef CONFIG_X86
2106
2144
.irq_ack = irq_chip_ack_parent,
2107
-
.flags = IRQCHIP_MOVE_DEFERRED,
2108
-
#elif defined(CONFIG_ARM64)
2109
2145
.irq_eoi = irq_chip_eoi_parent,
2110
-
#endif
2111
2146
.irq_mask = hv_irq_mask,
2112
2147
.irq_unmask = hv_irq_unmask,
2113
2148
};
2114
2149
2115
-
static struct msi_domain_ops hv_msi_ops = {
2116
-
.msi_prepare = hv_msi_prepare,
2117
-
.msi_free = hv_msi_free,
2118
-
.prepare_desc = pci_msix_prepare_desc,
2150
+
static int hv_pcie_domain_alloc(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs,
2151
+
void *arg)
2152
+
{
2153
+
/*
2154
+
* TODO: Allocating and populating struct tran_int_desc in hv_compose_msi_msg()
2155
+
* should be moved here.
2156
+
*/
2157
+
int ret;
2158
+
2159
+
ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, arg);
2160
+
if (ret < 0)
2161
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return ret;
2162
+
2163
+
for (int i = 0; i < nr_irqs; i++) {
2164
+
irq_domain_set_hwirq_and_chip(d, virq + i, 0, &hv_msi_irq_chip, NULL);
2165
+
if (IS_ENABLED(CONFIG_X86))
2166
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__irq_set_handler(virq + i, handle_edge_irq, 0, "edge");
2167
+
}
2168
+
2169
+
return 0;
2170
+
}
2171
+
2172
+
static void hv_pcie_domain_free(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs)
2173
+
{
2174
+
struct msi_domain_info *info = d->host_data;
2175
+
2176
+
for (int i = 0; i < nr_irqs; i++)
2177
+
hv_msi_free(d, info, virq + i);
2178
+
2179
+
irq_domain_free_irqs_top(d, virq, nr_irqs);
2180
+
}
2181
+
2182
+
static const struct irq_domain_ops hv_pcie_domain_ops = {
2183
+
.alloc = hv_pcie_domain_alloc,
2184
+
.free = hv_pcie_domain_free,
2119
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};
2120
2186
2121
2187
/**
···
2195
2137
*/
2196
2138
static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
2197
2139
{
2198
-
hbus->msi_info.chip = &hv_msi_irq_chip;
2199
-
hbus->msi_info.ops = &hv_msi_ops;
2200
-
hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
2201
-
MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
2202
-
MSI_FLAG_PCI_MSIX | MSI_FLAG_PCI_MSIX_ALLOC_DYN);
2203
-
hbus->msi_info.handler = FLOW_HANDLER;
2204
-
hbus->msi_info.handler_name = FLOW_NAME;
2205
-
hbus->msi_info.data = hbus;
2206
-
hbus->irq_domain = pci_msi_create_irq_domain(hbus->fwnode,
2207
-
&hbus->msi_info,
2208
-
hv_pci_get_root_domain());
2140
+
struct irq_domain_info info = {
2141
+
.fwnode = hbus->fwnode,
2142
+
.ops = &hv_pcie_domain_ops,
2143
+
.host_data = hbus,
2144
+
.parent = hv_pci_get_root_domain(),
2145
+
};
2146
+
2147
+
hbus->irq_domain = msi_create_parent_irq_domain(&info, &hv_pcie_msi_parent_ops);
2209
2148
if (!hbus->irq_domain) {
2210
2149
dev_err(&hbus->hdev->device,
2211
2150
"Failed to build an MSI IRQ domain\n");