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clk: qcom: clk-rcg2: split __clk_rcg2_configure function

__clk_rcg2_configure function does 2 things -
configures parent and mnd values. In order to
be able to add new clock options, we should split.

Move __clk_rcg2_configure logic on 2 functions:
- __clk_rcg2_configure_parent which configures clock parent
- __clk_rcg2_configure_mnd which configures mnd values

__clk_rcg2_configure delegates to mentioned functions.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-2-ac8e36a3aa65@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Dzmitry Sankouski and committed by
Bjorn Andersson faddad52 cef0523d

+31 -6
+31 -6
drivers/clk/qcom/clk-rcg2.c
··· 402 402 return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req); 403 403 } 404 404 405 - static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, 406 - u32 *_cfg) 405 + static int __clk_rcg2_configure_parent(struct clk_rcg2 *rcg, u8 src, u32 *_cfg) 407 406 { 408 - u32 cfg, mask, d_val, not2d_val, n_minus_m; 409 407 struct clk_hw *hw = &rcg->clkr.hw; 410 - int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); 408 + int index = qcom_find_src_index(hw, rcg->parent_map, src); 411 409 412 410 if (index < 0) 413 411 return index; 412 + 413 + *_cfg &= ~CFG_SRC_SEL_MASK; 414 + *_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 415 + 416 + return 0; 417 + } 418 + 419 + static int __clk_rcg2_configure_mnd(struct clk_rcg2 *rcg, const struct freq_tbl *f, 420 + u32 *_cfg) 421 + { 422 + u32 cfg, mask, d_val, not2d_val, n_minus_m; 423 + int ret; 414 424 415 425 if (rcg->mnd_width && f->n) { 416 426 mask = BIT(rcg->mnd_width) - 1; ··· 450 440 } 451 441 452 442 mask = BIT(rcg->hid_width) - 1; 453 - mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; 443 + mask |= CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; 454 444 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; 455 - cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 456 445 if (rcg->mnd_width && f->n && (f->m != f->n)) 457 446 cfg |= CFG_MODE_DUAL_EDGE; 458 447 if (rcg->hw_clk_ctrl) ··· 459 450 460 451 *_cfg &= ~mask; 461 452 *_cfg |= cfg; 453 + 454 + return 0; 455 + } 456 + 457 + static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, 458 + u32 *_cfg) 459 + { 460 + int ret; 461 + 462 + ret = __clk_rcg2_configure_parent(rcg, f->src, _cfg); 463 + if (ret) 464 + return ret; 465 + 466 + ret = __clk_rcg2_configure_mnd(rcg, f, _cfg); 467 + if (ret) 468 + return ret; 462 469 463 470 return 0; 464 471 }