drm/msm/dpu: handle pipes as array · tjh.dev/kernel@fb4c972

+16 -21

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

··· 449 449 struct dpu_plane_state *pstate = NULL; 450 450 const struct msm_format *format; 451 451 struct dpu_hw_ctl *ctl = mixer->lm_ctl; 452 - u32 lm_idx; 452 + u32 lm_idx, i; 453 453 bool bg_alpha_enable = false; 454 454 DECLARE_BITMAP(active_fetch, SSPP_MAX); 455 455 DECLARE_BITMAP(active_pipes, SSPP_MAX); ··· 472 472 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 473 473 bg_alpha_enable = true; 474 474 475 - set_bit(pstate->pipe.sspp->idx, active_fetch); 476 - set_bit(pstate->pipe.sspp->idx, active_pipes); 477 - _dpu_crtc_blend_setup_pipe(crtc, plane, 478 - mixer, cstate->num_mixers, 479 - pstate->stage, 480 - format, fb ? fb->modifier : 0, 481 - &pstate->pipe, 0, stage_cfg); 482 475 483 - if (pstate->r_pipe.sspp) { 484 - set_bit(pstate->r_pipe.sspp->idx, active_fetch); 485 - set_bit(pstate->r_pipe.sspp->idx, active_pipes); 476 + for (i = 0; i < PIPES_PER_STAGE; i++) { 477 + if (!pstate->pipe[i].sspp) 478 + continue; 479 + set_bit(pstate->pipe[i].sspp->idx, active_fetch); 480 + set_bit(pstate->pipe[i].sspp->idx, active_pipes); 486 481 _dpu_crtc_blend_setup_pipe(crtc, plane, 487 482 mixer, cstate->num_mixers, 488 483 pstate->stage, 489 484 format, fb ? fb->modifier : 0, 490 - &pstate->r_pipe, 1, stage_cfg); 485 + &pstate->pipe[i], i, stage_cfg); 491 486 } 492 487 493 488 /* blend config update */ ··· 1677 1682 seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", 1678 1683 state->crtc_x, state->crtc_y, state->crtc_w, 1679 1684 state->crtc_h); 1680 - seq_printf(s, "\tsspp[0]:%s\n", 1681 - pstate->pipe.sspp->cap->name); 1682 - seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", 1683 - pstate->pipe.multirect_mode, pstate->pipe.multirect_index); 1684 - if (pstate->r_pipe.sspp) { 1685 - seq_printf(s, "\tsspp[1]:%s\n", 1686 - pstate->r_pipe.sspp->cap->name); 1687 - seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", 1688 - pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); 1685 + 1686 + for (i = 0; i < PIPES_PER_STAGE; i++) { 1687 + if (!pstate->pipe[i].sspp) 1688 + continue; 1689 + seq_printf(s, "\tsspp[%d]:%s\n", 1690 + i, pstate->pipe[i].sspp->cap->name); 1691 + seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n", 1692 + i, pstate->pipe[i].multirect_mode, 1693 + pstate->pipe[i].multirect_index); 1689 1694 } 1690 1695 1691 1696 seq_puts(s, "\n");

+97 -81

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

··· 622 622 struct msm_drm_private *priv = plane->dev->dev_private; 623 623 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 624 624 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 625 + int i; 625 626 626 627 DPU_DEBUG_PLANE(pdpu, "\n"); 627 628 ··· 636 635 return; 637 636 638 637 /* update sspp */ 639 - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 640 - fill_color, fmt); 641 - 642 - if (pstate->r_pipe.sspp) 643 - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 638 + for (i = 0; i < PIPES_PER_STAGE; i++) { 639 + if (!pstate->pipe[i].sspp) 640 + continue; 641 + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], 642 + &pstate->pipe_cfg[i].dst_rect, 644 643 fill_color, fmt); 644 + } 645 645 } 646 646 647 647 static int dpu_plane_prepare_fb(struct drm_plane *plane, ··· 824 822 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 825 823 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 826 824 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 827 - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 828 - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 825 + struct dpu_sw_pipe_cfg *pipe_cfg; 826 + struct dpu_sw_pipe_cfg *r_pipe_cfg; 829 827 struct drm_rect fb_rect = { 0 }; 830 828 uint32_t max_linewidth; 831 829 ··· 850 848 return -EINVAL; 851 849 } 852 850 851 + /* move the assignment here, to ease handling to another pairs later */ 852 + pipe_cfg = &pstate->pipe_cfg[0]; 853 + r_pipe_cfg = &pstate->pipe_cfg[1]; 853 854 /* state->src is 16.16, src_rect is not */ 854 855 drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); 855 856 ··· 968 963 drm_atomic_get_new_plane_state(state, plane); 969 964 struct dpu_plane *pdpu = to_dpu_plane(plane); 970 965 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 971 - struct dpu_sw_pipe *pipe = &pstate->pipe; 972 - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 973 - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 974 - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 966 + struct dpu_sw_pipe *pipe = &pstate->pipe[0]; 967 + struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; 968 + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; 969 + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; 975 970 int ret = 0; 976 971 977 972 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, ··· 1026 1021 const struct msm_format *fmt, 1027 1022 uint32_t max_linewidth) 1028 1023 { 1029 - struct dpu_sw_pipe *pipe = &pstate->pipe; 1030 - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1031 - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1032 - struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe; 1033 - struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg; 1024 + struct dpu_sw_pipe *pipe = &pstate->pipe[0]; 1025 + struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; 1026 + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; 1027 + struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe[0]; 1028 + struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg[0]; 1034 1029 const struct msm_format *prev_fmt = msm_framebuffer_format(prev_adjacent_pstate->base.fb); 1035 1030 u16 max_tile_height = 1; 1036 1031 1037 - if (prev_adjacent_pstate->r_pipe.sspp != NULL || 1032 + if (prev_adjacent_pstate->pipe[1].sspp != NULL || 1038 1033 prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE) 1039 1034 return false; 1040 1035 ··· 1094 1089 struct dpu_plane *pdpu = to_dpu_plane(plane); 1095 1090 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 1096 1091 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1097 - struct dpu_sw_pipe *pipe = &pstate->pipe; 1098 - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1099 - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1100 - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1092 + struct dpu_sw_pipe *pipe = &pstate->pipe[0]; 1093 + struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; 1094 + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; 1095 + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; 1101 1096 const struct drm_crtc_state *crtc_state = NULL; 1102 1097 uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth; 1103 1098 ··· 1141 1136 drm_atomic_get_old_plane_state(state, plane); 1142 1137 struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); 1143 1138 struct drm_crtc_state *crtc_state = NULL; 1144 - int ret; 1139 + int ret, i; 1145 1140 1146 1141 if (IS_ERR(plane_state)) 1147 1142 return PTR_ERR(plane_state); ··· 1159 1154 * resources are freed by dpu_crtc_assign_plane_resources(), 1160 1155 * but clean them here. 1161 1156 */ 1162 - pstate->pipe.sspp = NULL; 1163 - pstate->r_pipe.sspp = NULL; 1157 + for (i = 0; i < PIPES_PER_STAGE; i++) 1158 + pstate->pipe[i].sspp = NULL; 1164 1159 1165 1160 return 0; 1166 1161 } ··· 1198 1193 struct dpu_sw_pipe_cfg *pipe_cfg; 1199 1194 struct dpu_sw_pipe_cfg *r_pipe_cfg; 1200 1195 const struct msm_format *fmt; 1196 + int i; 1201 1197 1202 1198 if (plane_state->crtc) 1203 1199 crtc_state = drm_atomic_get_new_crtc_state(state, ··· 1207 1201 pstate = to_dpu_plane_state(plane_state); 1208 1202 prev_adjacent_pstate = prev_adjacent_plane_state ? 1209 1203 to_dpu_plane_state(prev_adjacent_plane_state) : NULL; 1210 - pipe = &pstate->pipe; 1211 - r_pipe = &pstate->r_pipe; 1212 - pipe_cfg = &pstate->pipe_cfg; 1213 - r_pipe_cfg = &pstate->r_pipe_cfg; 1214 1204 1215 - pipe->sspp = NULL; 1216 - r_pipe->sspp = NULL; 1205 + pipe = &pstate->pipe[0]; 1206 + r_pipe = &pstate->pipe[1]; 1207 + pipe_cfg = &pstate->pipe_cfg[0]; 1208 + r_pipe_cfg = &pstate->pipe_cfg[1]; 1209 + 1210 + for (i = 0; i < PIPES_PER_STAGE; i++) 1211 + pstate->pipe[i].sspp = NULL; 1217 1212 1218 1213 if (!plane_state->fb) 1219 1214 return -EINVAL; ··· 1325 1318 { 1326 1319 struct dpu_plane *pdpu; 1327 1320 struct dpu_plane_state *pstate; 1321 + int i; 1328 1322 1329 1323 if (!plane || !plane->state) { 1330 1324 DPU_ERROR("invalid plane\n"); ··· 1346 1338 /* force 100% alpha */ 1347 1339 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1348 1340 else { 1349 - dpu_plane_flush_csc(pdpu, &pstate->pipe); 1350 - dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 1341 + for (i = 0; i < PIPES_PER_STAGE; i++) 1342 + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); 1351 1343 } 1352 1344 1353 1345 /* flag h/w flush complete */ ··· 1448 1440 struct dpu_plane *pdpu = to_dpu_plane(plane); 1449 1441 struct drm_plane_state *state = plane->state; 1450 1442 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1451 - struct dpu_sw_pipe *pipe = &pstate->pipe; 1452 - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1453 1443 struct drm_crtc *crtc = state->crtc; 1454 1444 struct drm_framebuffer *fb = state->fb; 1455 1445 bool is_rt_pipe; 1456 1446 const struct msm_format *fmt = 1457 1447 msm_framebuffer_format(fb); 1458 - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1459 - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1448 + int i; 1460 1449 1461 1450 pstate->pending = true; 1462 1451 ··· 1468 1463 crtc->base.id, DRM_RECT_ARG(&state->dst), 1469 1464 &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); 1470 1465 1471 - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1472 - drm_mode_vrefresh(&crtc->mode), 1473 - &pstate->layout); 1474 - 1475 - if (r_pipe->sspp) { 1476 - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1466 + /* move the assignment here, to ease handling to another pairs later */ 1467 + for (i = 0; i < PIPES_PER_STAGE; i++) { 1468 + if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect)) 1469 + continue; 1470 + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], 1471 + &pstate->pipe_cfg[i], fmt, 1477 1472 drm_mode_vrefresh(&crtc->mode), 1478 1473 &pstate->layout); 1479 1474 } ··· 1481 1476 if (pstate->needs_qos_remap) 1482 1477 pstate->needs_qos_remap = false; 1483 1478 1484 - pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1485 - &crtc->mode, pipe_cfg); 1479 + pstate->plane_fetch_bw = 0; 1480 + pstate->plane_clk = 0; 1481 + for (i = 0; i < PIPES_PER_STAGE; i++) { 1482 + if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect)) 1483 + continue; 1484 + pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, 1485 + &crtc->mode, &pstate->pipe_cfg[i]); 1486 1486 1487 - pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1488 - 1489 - if (r_pipe->sspp) { 1490 - pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1491 - 1492 - pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1487 + pstate->plane_clk = max(pstate->plane_clk, 1488 + _dpu_plane_calc_clk(&crtc->mode, 1489 + &pstate->pipe_cfg[i])); 1493 1490 } 1494 1491 } 1495 1492 ··· 1499 1492 { 1500 1493 struct drm_plane_state *state = plane->state; 1501 1494 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1502 - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1495 + struct dpu_sw_pipe *pipe; 1496 + int i; 1503 1497 1504 - trace_dpu_plane_disable(DRMID(plane), false, 1505 - pstate->pipe.multirect_mode); 1498 + for (i = 0; i < PIPES_PER_STAGE; i += 1) { 1499 + pipe = &pstate->pipe[i]; 1500 + if (!pipe->sspp) 1501 + continue; 1506 1502 1507 - if (r_pipe->sspp) { 1508 - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1509 - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1503 + trace_dpu_plane_disable(DRMID(plane), false, 1504 + pstate->pipe[i].multirect_mode); 1510 1505 1511 - if (r_pipe->sspp->ops.setup_multirect) 1512 - r_pipe->sspp->ops.setup_multirect(r_pipe); 1506 + if (i % PIPES_PER_STAGE == 0) 1507 + continue; 1508 + 1509 + /* 1510 + * clear multirect for the right pipe so that the SSPP 1511 + * can be further reused in the solo mode 1512 + */ 1513 + pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1514 + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1515 + if (pipe->sspp->ops.setup_multirect) 1516 + pipe->sspp->ops.setup_multirect(pipe); 1513 1517 } 1514 1518 1515 1519 pstate->pending = true; ··· 1615 1597 const struct drm_plane_state *state) 1616 1598 { 1617 1599 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1618 - const struct dpu_sw_pipe *pipe = &pstate->pipe; 1619 - const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1620 - const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1621 - const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1600 + const struct dpu_sw_pipe *pipe; 1601 + const struct dpu_sw_pipe_cfg *pipe_cfg; 1602 + int i; 1622 1603 1623 1604 drm_printf(p, "\tstage=%d\n", pstate->stage); 1624 1605 1625 - if (pipe->sspp) { 1626 - drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1627 - drm_printf(p, "\tmultirect_mode[0]=%s\n", 1606 + for (i = 0; i < PIPES_PER_STAGE; i++) { 1607 + pipe = &pstate->pipe[i]; 1608 + if (!pipe->sspp) 1609 + continue; 1610 + pipe_cfg = &pstate->pipe_cfg[i]; 1611 + drm_printf(p, "\tsspp[%d]=%s\n", i, pipe->sspp->cap->name); 1612 + drm_printf(p, "\tmultirect_mode[%d]=%s\n", i, 1628 1613 dpu_get_multirect_mode(pipe->multirect_mode)); 1629 - drm_printf(p, "\tmultirect_index[0]=%s\n", 1614 + drm_printf(p, "\tmultirect_index[%d]=%s\n", i, 1630 1615 dpu_get_multirect_index(pipe->multirect_index)); 1631 - drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1632 - drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1633 - } 1634 - 1635 - if (r_pipe->sspp) { 1636 - drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1637 - drm_printf(p, "\tmultirect_mode[1]=%s\n", 1638 - dpu_get_multirect_mode(r_pipe->multirect_mode)); 1639 - drm_printf(p, "\tmultirect_index[1]=%s\n", 1640 - dpu_get_multirect_index(r_pipe->multirect_index)); 1641 - drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1642 - drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1616 + drm_printf(p, "\tsrc[%d]=" DRM_RECT_FMT "\n", i, 1617 + DRM_RECT_ARG(&pipe_cfg->src_rect)); 1618 + drm_printf(p, "\tdst[%d]=" DRM_RECT_FMT "\n", i, 1619 + DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1643 1620 } 1644 1621 } 1645 1622 ··· 1672 1659 struct dpu_plane *pdpu = to_dpu_plane(plane); 1673 1660 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1674 1661 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1662 + int i; 1675 1663 1676 1664 if (!pdpu->is_rt_pipe) 1677 1665 return; 1678 1666 1679 1667 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1680 - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); 1681 - if (pstate->r_pipe.sspp) 1682 - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); 1668 + for (i = 0; i < PIPES_PER_STAGE; i++) { 1669 + if (!pstate->pipe[i].sspp) 1670 + continue; 1671 + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); 1672 + } 1683 1673 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1684 1674 } 1685 1675 #endif

+4 -8

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

··· 17 17 /** 18 18 * struct dpu_plane_state: Define dpu extension of drm plane state object 19 19 * @base: base drm plane state object 20 - * @pipe: software pipe description 21 - * @r_pipe: software pipe description of the second pipe 22 - * @pipe_cfg: software pipe configuration 23 - * @r_pipe_cfg: software pipe configuration for the second pipe 20 + * @pipe: software pipe description array 21 + * @pipe_cfg: software pipe configuration array 24 22 * @stage: assigned by crtc blender 25 23 * @needs_qos_remap: qos remap settings need to be updated 26 24 * @multirect_index: index of the rectangle of SSPP ··· 31 33 */ 32 34 struct dpu_plane_state { 33 35 struct drm_plane_state base; 34 - struct dpu_sw_pipe pipe; 35 - struct dpu_sw_pipe r_pipe; 36 - struct dpu_sw_pipe_cfg pipe_cfg; 37 - struct dpu_sw_pipe_cfg r_pipe_cfg; 36 + struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; 37 + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; 38 38 enum dpu_stage stage; 39 39 bool needs_qos_remap; 40 40 bool pending;

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