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drm/amdgpu: Implement TTM handling for MMIO_REMAP placement

Implement TTM-level behavior for AMDGPU_PL_MMIO_REMAP so it behaves as a
CPU-visible IO page:

* amdgpu_evict_flags(): mark as unmovable
* amdgpu_res_cpu_visible(): consider CPU-visible
* amdgpu_bo_move(): use null move when src/dst is MMIO_REMAP
* amdgpu_ttm_io_mem_reserve(): program base/is_iomem/caching using
the device's mmio_remap_* metadata
* amdgpu_ttm_io_mem_pfn(): return PFN for the remapped HDP page
* amdgpu_ttm_tt_pde_flags(): set AMDGPU_PTE_SYSTEM for this mem type

v2:
- Drop HDP-specific comment; keep generic remap (Alex).

v3:
- Fix indentation in amdgpu_res_cpu_visible (Christian).
- Use adev->rmmio_remap.bus_addr for MMIO_REMAP bus/PFN calculations
(Alex).

v4:
- Drop unnecessary (resource_size_t) casts in MMIO_REMAP io-mem paths
(Alex)

Cc: Christian König <christian.koenig@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Srinivasan Shanmugam and committed by
Alex Deucher fb5a52db 99eeb835

+16 -3
+16 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 123 123 case AMDGPU_PL_GWS: 124 124 case AMDGPU_PL_OA: 125 125 case AMDGPU_PL_DOORBELL: 126 + case AMDGPU_PL_MMIO_REMAP: 126 127 placement->num_placement = 0; 127 128 return; 128 129 ··· 448 447 return false; 449 448 450 449 if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT || 451 - res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL) 450 + res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL || 451 + res->mem_type == AMDGPU_PL_MMIO_REMAP) 452 452 return true; 453 453 454 454 if (res->mem_type != TTM_PL_VRAM) ··· 540 538 old_mem->mem_type == AMDGPU_PL_GWS || 541 539 old_mem->mem_type == AMDGPU_PL_OA || 542 540 old_mem->mem_type == AMDGPU_PL_DOORBELL || 541 + old_mem->mem_type == AMDGPU_PL_MMIO_REMAP || 543 542 new_mem->mem_type == AMDGPU_PL_GDS || 544 543 new_mem->mem_type == AMDGPU_PL_GWS || 545 544 new_mem->mem_type == AMDGPU_PL_OA || 546 - new_mem->mem_type == AMDGPU_PL_DOORBELL) { 545 + new_mem->mem_type == AMDGPU_PL_DOORBELL || 546 + new_mem->mem_type == AMDGPU_PL_MMIO_REMAP) { 547 547 /* Nothing to save here */ 548 548 amdgpu_bo_move_notify(bo, evict, new_mem); 549 549 ttm_bo_move_null(bo, new_mem); ··· 633 629 mem->bus.is_iomem = true; 634 630 mem->bus.caching = ttm_uncached; 635 631 break; 632 + case AMDGPU_PL_MMIO_REMAP: 633 + mem->bus.offset = mem->start << PAGE_SHIFT; 634 + mem->bus.offset += adev->rmmio_remap.bus_addr; 635 + mem->bus.is_iomem = true; 636 + mem->bus.caching = ttm_uncached; 637 + break; 636 638 default: 637 639 return -EINVAL; 638 640 } ··· 656 646 657 647 if (bo->resource->mem_type == AMDGPU_PL_DOORBELL) 658 648 return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT; 649 + else if (bo->resource->mem_type == AMDGPU_PL_MMIO_REMAP) 650 + return ((uint64_t)(adev->rmmio_remap.bus_addr + cursor.start)) >> PAGE_SHIFT; 659 651 660 652 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 661 653 } ··· 1367 1355 1368 1356 if (mem && (mem->mem_type == TTM_PL_TT || 1369 1357 mem->mem_type == AMDGPU_PL_DOORBELL || 1370 - mem->mem_type == AMDGPU_PL_PREEMPT)) { 1358 + mem->mem_type == AMDGPU_PL_PREEMPT || 1359 + mem->mem_type == AMDGPU_PL_MMIO_REMAP)) { 1371 1360 flags |= AMDGPU_PTE_SYSTEM; 1372 1361 1373 1362 if (ttm->caching == ttm_cached)