Merge tag 'i2c-for-7.1-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

-20

Documentation/devicetree/bindings/i2c/i2c-iop3xx.txt

··· 1 - i2c Controller on XScale platforms such as IOP3xx and IXP4xx 2 - 3 - Required properties: 4 - - compatible : Must be one of 5 - "intel,iop3xx-i2c" 6 - "intel,ixp4xx-i2c"; 7 - - reg 8 - - #address-cells = <1>; 9 - - #size-cells = <0>; 10 - 11 - Optional properties: 12 - - Child nodes conforming to i2c bus binding 13 - 14 - Example: 15 - 16 - i2c@c8011000 { 17 - compatible = "intel,ixp4xx-i2c"; 18 - reg = <0xc8011000 0x18>; 19 - interrupts = <33 IRQ_TYPE_LEVEL_LOW>; 20 - };

+41

Documentation/devicetree/bindings/i2c/intel,ixp4xx-i2c.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/intel,ixp4xx-i2c.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: I2c Controller on XScale platforms such as IOP3xx and IXP4xx 8 + 9 + maintainers: 10 + - Andi Shyti <andi.shyti@kernel.org> 11 + 12 + allOf: 13 + - $ref: /schemas/i2c/i2c-controller.yaml# 14 + 15 + properties: 16 + compatible: 17 + enum: 18 + - intel,iop3xx-i2c 19 + - intel,ixp4xx-i2c 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + interrupts: 25 + maxItems: 1 26 + 27 + required: 28 + - compatible 29 + - reg 30 + 31 + unevaluatedProperties: false 32 + 33 + examples: 34 + - | 35 + #include <dt-bindings/interrupt-controller/irq.h> 36 + 37 + i2c@c8011000 { 38 + compatible = "intel,ixp4xx-i2c"; 39 + reg = <0xc8011000 0x18>; 40 + interrupts = <33 IRQ_TYPE_LEVEL_LOW>; 41 + };

+20

Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml

··· 27 27 - items: 28 28 - enum: 29 29 - qcom,kaanapali-cci 30 + - qcom,milos-cci 30 31 - qcom,qcm2290-cci 31 32 - qcom,qcs8300-cci 32 33 - qcom,sa8775p-cci ··· 35 34 - qcom,sc8280xp-cci 36 35 - qcom,sdm670-cci 37 36 - qcom,sdm845-cci 37 + - qcom,sm6150-cci 38 38 - qcom,sm6350-cci 39 39 - qcom,sm8250-cci 40 40 - qcom,sm8450-cci ··· 253 251 contains: 254 252 enum: 255 253 - qcom,sa8775p-cci 254 + - qcom,sm6150-cci 256 255 - qcom,sm8550-cci 257 256 - qcom,sm8650-cci 258 257 - qcom,x1e80100-cci ··· 265 262 clock-names: 266 263 items: 267 264 - const: camnoc_axi 265 + - const: cpas_ahb 266 + - const: cci 267 + 268 + - if: 269 + properties: 270 + compatible: 271 + contains: 272 + enum: 273 + - qcom,milos-cci 274 + then: 275 + properties: 276 + clocks: 277 + minItems: 3 278 + maxItems: 3 279 + clock-names: 280 + items: 281 + - const: soc_ahb 268 282 - const: cpas_ahb 269 283 - const: cci 270 284

+15

Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml

··· 15 15 assigned to either I2C controller. 16 16 RTL9310 SoCs have equal capabilities but support 12 common SDA lines which 17 17 can be assigned to either I2C controller. 18 + RTL9607C SoCs have equal capabilities but each controller only supports 1 19 + SCL/SDA line. 18 20 19 21 properties: 20 22 compatible: ··· 36 34 - enum: 37 35 - realtek,rtl9301-i2c 38 36 - realtek,rtl9310-i2c 37 + - realtek,rtl9607-i2c 39 38 40 39 reg: 41 40 items: ··· 53 50 description: 54 51 The SCL line number of this I2C controller. 55 52 enum: [ 0, 1 ] 53 + 54 + clocks: 55 + maxItems: 1 56 56 57 57 patternProperties: 58 58 '^i2c@[0-9ab]$': ··· 87 81 then: 88 82 patternProperties: 89 83 '^i2c@[89ab]$': false 84 + - if: 85 + properties: 86 + compatible: 87 + contains: 88 + const: realtek,rtl9607-i2c 89 + then: 90 + required: 91 + - realtek,scl 92 + - clocks 90 93 91 94 required: 92 95 - compatible

+1

Documentation/devicetree/bindings/i2c/renesas,riic.yaml

··· 25 25 - items: 26 26 - enum: 27 27 - renesas,riic-r9a08g045 # RZ/G3S 28 + - renesas,riic-r9a08g046 # RZ/G3L 28 29 - renesas,riic-r9a09g047 # RZ/G3E 29 30 - renesas,riic-r9a09g056 # RZ/V2N 30 31 - const: renesas,riic-r9a09g057 # RZ/V2H(P)

-2

Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml

··· 32 32 - const: renesas,r9a06g032-i2c # RZ/N1D 33 33 - const: renesas,rzn1-i2c # RZ/N1 34 34 - const: snps,designware-i2c 35 - - description: Baikal-T1 SoC System I2C controller 36 - const: baikal,bt1-sys-i2c 37 35 - description: Mobileye EyeQ DesignWare I2C controller 38 36 items: 39 37 - enum:

+5 -1

Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml

··· 14 14 15 15 properties: 16 16 compatible: 17 - const: spacemit,k1-i2c 17 + oneOf: 18 + - items: 19 + - const: spacemit,k3-i2c 20 + - const: spacemit,k1-i2c 21 + - const: spacemit,k1-i2c 18 22 19 23 reg: 20 24 maxItems: 1

+1 -2

drivers/i2c/busses/Kconfig

··· 1211 1211 1212 1212 config I2C_TEGRA 1213 1213 tristate "NVIDIA Tegra internal I2C controller" 1214 - depends on ARCH_TEGRA || (COMPILE_TEST && (ARC || ARM || ARM64 || M68K || RISCV || SUPERH || SPARC)) 1215 - # COMPILE_TEST needs architectures with readsX()/writesX() primitives 1214 + depends on ARCH_TEGRA || COMPILE_TEST 1216 1215 depends on PINCTRL 1217 1216 # ARCH_TEGRA implies PINCTRL, but the COMPILE_TEST side doesn't. 1218 1217 help

+2 -3

drivers/i2c/busses/i2c-cp2615.c

··· 270 270 .max_comb_2nd_msg_len = MAX_I2C_SIZE 271 271 }; 272 272 273 - static void 274 - cp2615_i2c_remove(struct usb_interface *usbif) 273 + static void cp2615_i2c_disconnect(struct usb_interface *usbif) 275 274 { 276 275 struct i2c_adapter *adap = usb_get_intfdata(usbif); 277 276 ··· 327 328 static struct usb_driver cp2615_i2c_driver = { 328 329 .name = "i2c-cp2615", 329 330 .probe = cp2615_i2c_probe, 330 - .disconnect = cp2615_i2c_remove, 331 + .disconnect = cp2615_i2c_disconnect, 331 332 .id_table = id_table, 332 333 }; 333 334

+1

drivers/i2c/busses/i2c-designware-platdrv.c

··· 268 268 { "AMDI0510", 0 }, 269 269 { "APMC0D0F", 0 }, 270 270 { "FUJI200B", 0 }, 271 + { "GOOG5000", 0 }, 271 272 { "HISI02A1", 0 }, 272 273 { "HISI02A2", 0 }, 273 274 { "HISI02A3", 0 },

+3 -9

drivers/i2c/busses/i2c-diolan-u2c.c

··· 427 427 428 428 MODULE_DEVICE_TABLE(usb, diolan_u2c_table); 429 429 430 - static void diolan_u2c_free(struct i2c_diolan_u2c *dev) 431 - { 432 - usb_put_dev(dev->usb_dev); 433 - kfree(dev); 434 - } 435 - 436 430 static int diolan_u2c_probe(struct usb_interface *interface, 437 431 const struct usb_device_id *id) 438 432 { ··· 447 453 dev->ep_out = hostif->endpoint[0].desc.bEndpointAddress; 448 454 dev->ep_in = hostif->endpoint[1].desc.bEndpointAddress; 449 455 450 - dev->usb_dev = usb_get_dev(interface_to_usbdev(interface)); 456 + dev->usb_dev = interface_to_usbdev(interface); 451 457 dev->interface = interface; 452 458 453 459 /* save our data pointer in this interface device */ ··· 482 488 483 489 error_free: 484 490 usb_set_intfdata(interface, NULL); 485 - diolan_u2c_free(dev); 491 + kfree(dev); 486 492 error: 487 493 return ret; 488 494 } ··· 493 499 494 500 i2c_del_adapter(&dev->adapter); 495 501 usb_set_intfdata(interface, NULL); 496 - diolan_u2c_free(dev); 502 + kfree(dev); 497 503 498 504 dev_dbg(&interface->dev, "disconnected\n"); 499 505 }

+235 -79

drivers/i2c/busses/i2c-k1.c

··· 98 98 99 99 #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 100 100 101 + #define SPACEMIT_WAIT_TIMEOUT 1000 /* ms */ 102 + #define SPACEMIT_POLL_TIMEOUT 1000 /* us */ 103 + #define SPACEMIT_POLL_INTERVAL 30 /* us */ 104 + 101 105 enum spacemit_i2c_state { 102 106 SPACEMIT_STATE_IDLE, 103 107 SPACEMIT_STATE_START, ··· 130 126 131 127 enum spacemit_i2c_state state; 132 128 bool read; 129 + bool use_pio; 133 130 struct completion complete; 134 131 u32 status; 135 132 }; ··· 177 172 return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; 178 173 } 179 174 175 + static inline void spacemit_i2c_delay(struct spacemit_i2c_dev *i2c, unsigned int us) 176 + { 177 + if (i2c->use_pio) 178 + udelay(us); 179 + else 180 + fsleep(us); 181 + } 182 + 180 183 static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) 181 184 { 182 185 u32 status; ··· 196 183 return; 197 184 198 185 spacemit_i2c_reset(i2c); 199 - usleep_range(10, 20); 186 + 187 + spacemit_i2c_delay(i2c, 10); 200 188 201 189 for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { 202 190 status = readl(i2c->base + SPACEMIT_IBMR); ··· 226 212 if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) 227 213 return 0; 228 214 229 - ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, 230 - val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), 231 - 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); 215 + if (i2c->use_pio) 216 + ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, 217 + val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), 218 + 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); 219 + else 220 + ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, 221 + val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), 222 + 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); 223 + 232 224 if (ret) 233 225 spacemit_i2c_reset(i2c); 234 226 ··· 246 226 /* in case bus is not released after transfer completes */ 247 227 if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { 248 228 spacemit_i2c_conditionally_reset_bus(i2c); 249 - usleep_range(90, 150); 229 + spacemit_i2c_delay(i2c, 90); 250 230 } 251 231 } 252 232 ··· 258 238 259 239 static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) 260 240 { 261 - u32 val; 241 + u32 val = 0; 262 242 263 - /* 264 - * Unmask interrupt bits for all xfer mode: 265 - * bus error, arbitration loss detected. 266 - * For transaction complete signal, we use master stop 267 - * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. 268 - */ 269 - val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; 243 + if (!i2c->use_pio) { 244 + /* 245 + * Enable interrupt bits for all xfer mode: 246 + * bus error, arbitration loss detected. 247 + */ 248 + val |= SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; 270 249 271 - /* 272 - * Unmask interrupt bits for interrupt xfer mode: 273 - * When IDBR receives a byte, an interrupt is triggered. 274 - * 275 - * For the tx empty interrupt, it will be enabled in the 276 - * i2c_start function. 277 - * Otherwise, it will cause an erroneous empty interrupt before i2c_start. 278 - */ 279 - val |= SPACEMIT_CR_DRFIE; 250 + /* 251 + * Unmask interrupt bits for interrupt xfer mode: 252 + * When IDBR receives a byte, an interrupt is triggered. 253 + * 254 + * For the tx empty interrupt, it will be enabled in the 255 + * i2c_start(). 256 + * We don't want a TX empty interrupt until we start 257 + * a transfer in i2c_start(). 258 + */ 259 + val |= SPACEMIT_CR_DRFIE; 260 + 261 + /* 262 + * Enable master stop interrupt bit. 263 + * For transaction complete signal, we use master stop 264 + * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. 265 + */ 266 + val |= SPACEMIT_CR_MSDIE; 267 + } 280 268 281 269 if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) 282 270 val |= SPACEMIT_CR_MODE_FAST; ··· 296 268 val |= SPACEMIT_CR_SCLE; 297 269 298 270 /* enable master stop detected */ 299 - val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; 271 + val |= SPACEMIT_CR_MSDE; 300 272 301 273 writel(val, i2c->base + SPACEMIT_ICR); 302 274 ··· 329 301 /* send start pulse */ 330 302 val = readl(i2c->base + SPACEMIT_ICR); 331 303 val &= ~SPACEMIT_CR_STOP; 332 - val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE; 304 + val |= SPACEMIT_CR_START | SPACEMIT_CR_TB; 305 + 306 + /* Enable the TX empty interrupt */ 307 + if (!i2c->use_pio) 308 + val |= SPACEMIT_CR_DTEIE; 309 + 333 310 writel(val, i2c->base + SPACEMIT_ICR); 334 - } 335 - 336 - static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) 337 - { 338 - unsigned long time_left; 339 - struct i2c_msg *msg; 340 - 341 - for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { 342 - msg = &i2c->msgs[i2c->msg_idx]; 343 - i2c->msg_buf = msg->buf; 344 - i2c->unprocessed = msg->len; 345 - i2c->status = 0; 346 - 347 - reinit_completion(&i2c->complete); 348 - 349 - spacemit_i2c_start(i2c); 350 - 351 - time_left = wait_for_completion_timeout(&i2c->complete, 352 - i2c->adapt.timeout); 353 - if (!time_left) { 354 - dev_err(i2c->dev, "msg completion timeout\n"); 355 - spacemit_i2c_conditionally_reset_bus(i2c); 356 - spacemit_i2c_reset(i2c); 357 - return -ETIMEDOUT; 358 - } 359 - 360 - if (i2c->status & SPACEMIT_SR_ERR) 361 - return spacemit_i2c_handle_err(i2c); 362 - } 363 - 364 - return 0; 365 311 } 366 312 367 313 static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) ··· 349 347 return !i2c->unprocessed; 350 348 } 351 349 350 + static inline void spacemit_i2c_complete(struct spacemit_i2c_dev *i2c) 351 + { 352 + /* SPACEMIT_STATE_IDLE avoids triggering the next byte */ 353 + i2c->state = SPACEMIT_STATE_IDLE; 354 + 355 + if (i2c->use_pio) 356 + return; 357 + 358 + complete(&i2c->complete); 359 + } 360 + 352 361 static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) 353 362 { 363 + /* If there's no space in the IDBR, we're done */ 364 + if (!(i2c->status & SPACEMIT_SR_ITE)) 365 + return; 366 + 354 367 /* if transfer completes, SPACEMIT_ISR will handle it */ 355 368 if (i2c->status & SPACEMIT_SR_MSD) 356 369 return; ··· 376 359 return; 377 360 } 378 361 379 - /* SPACEMIT_STATE_IDLE avoids trigger next byte */ 380 - i2c->state = SPACEMIT_STATE_IDLE; 381 - complete(&i2c->complete); 362 + spacemit_i2c_complete(i2c); 382 363 } 383 364 384 365 static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) 385 366 { 367 + /* If there's nothing in the IDBR, we're done */ 368 + if (!(i2c->status & SPACEMIT_SR_IRF)) 369 + return; 370 + 386 371 if (i2c->unprocessed) { 387 372 *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); 388 373 i2c->unprocessed--; 374 + return; 389 375 } 390 376 391 377 /* if transfer completes, SPACEMIT_ISR will handle it */ ··· 399 379 if (i2c->unprocessed) 400 380 return; 401 381 402 - /* SPACEMIT_STATE_IDLE avoids trigger next byte */ 403 - i2c->state = SPACEMIT_STATE_IDLE; 404 - complete(&i2c->complete); 382 + spacemit_i2c_complete(i2c); 405 383 } 406 384 407 385 static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) ··· 433 415 434 416 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); 435 417 436 - i2c->state = SPACEMIT_STATE_IDLE; 437 - complete(&i2c->complete); 418 + spacemit_i2c_complete(i2c); 438 419 } 439 420 440 - static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) 421 + static void spacemit_i2c_handle_state(struct spacemit_i2c_dev *i2c) 441 422 { 442 - struct spacemit_i2c_dev *i2c = devid; 443 - u32 status, val; 444 - 445 - status = readl(i2c->base + SPACEMIT_ISR); 446 - if (!status) 447 - return IRQ_HANDLED; 448 - 449 - i2c->status = status; 450 - 451 - spacemit_i2c_clear_int_status(i2c, status); 423 + u32 val; 452 424 453 425 if (i2c->status & SPACEMIT_SR_ERR) 454 426 goto err_out; 455 - 456 - val = readl(i2c->base + SPACEMIT_ICR); 457 - val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START); 458 427 459 428 switch (i2c->state) { 460 429 case SPACEMIT_STATE_START: ··· 458 453 } 459 454 460 455 if (i2c->state != SPACEMIT_STATE_IDLE) { 461 - val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE; 456 + val = readl(i2c->base + SPACEMIT_ICR); 457 + val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | 458 + SPACEMIT_CR_STOP | SPACEMIT_CR_START); 459 + val |= SPACEMIT_CR_TB; 460 + if (!i2c->use_pio) 461 + val |= SPACEMIT_CR_ALDIE; 462 462 463 463 if (spacemit_i2c_is_last_msg(i2c)) { 464 464 /* trigger next byte with stop */ ··· 477 467 478 468 err_out: 479 469 spacemit_i2c_err_check(i2c); 470 + } 471 + 472 + /* 473 + * In PIO mode, this function is used as a replacement for 474 + * wait_for_completion_timeout(), whose return value indicates 475 + * the remaining time. 476 + * 477 + * We do not have a meaningful remaining-time value here, so 478 + * return a non-zero value on success to indicate "not timed out". 479 + * Returning 1 ensures callers treating the return value as 480 + * time_left will not incorrectly report a timeout. 481 + */ 482 + static int spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev *i2c) 483 + { 484 + u32 mask, msec = jiffies_to_msecs(i2c->adapt.timeout); 485 + ktime_t timeout = ktime_add_ms(ktime_get(), msec); 486 + int ret; 487 + 488 + mask = SPACEMIT_SR_IRF | SPACEMIT_SR_ITE; 489 + 490 + do { 491 + i2c->status = readl(i2c->base + SPACEMIT_ISR); 492 + 493 + spacemit_i2c_clear_int_status(i2c, i2c->status); 494 + 495 + if (i2c->status & mask) 496 + spacemit_i2c_handle_state(i2c); 497 + else 498 + udelay(SPACEMIT_POLL_INTERVAL); 499 + } while (i2c->unprocessed && ktime_compare(ktime_get(), timeout) < 0); 500 + 501 + if (i2c->unprocessed) 502 + return 0; 503 + 504 + if (i2c->read) 505 + return 1; 506 + 507 + /* 508 + * If this is the last byte to write of the current message, 509 + * we have to wait here. Otherwise, control will proceed directly 510 + * to start(), which would overwrite the current data. 511 + */ 512 + ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, 513 + i2c->status, i2c->status & SPACEMIT_SR_ITE, 514 + SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); 515 + if (ret) 516 + return 0; 517 + 518 + /* 519 + * For writes: in interrupt mode, an ITE (write-empty) interrupt is triggered 520 + * after the last byte, and the MSD-related handling takes place there. 521 + * In PIO mode, however, we need to explicitly call err_check() to emulate this 522 + * step, otherwise the next transfer will fail. 523 + */ 524 + if (i2c->msg_idx == i2c->msg_num - 1) { 525 + mask = SPACEMIT_SR_MSD | SPACEMIT_SR_ERR; 526 + /* 527 + * In some cases, MSD may not arrive immediately; 528 + * wait here to handle that. 529 + */ 530 + ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, 531 + i2c->status, i2c->status & mask, 532 + SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); 533 + if (ret) 534 + return 0; 535 + 536 + spacemit_i2c_err_check(i2c); 537 + } 538 + 539 + return 1; 540 + } 541 + 542 + static int spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev *i2c) 543 + { 544 + if (i2c->use_pio) 545 + return spacemit_i2c_wait_pio_xfer(i2c); 546 + 547 + return wait_for_completion_timeout(&i2c->complete, 548 + i2c->adapt.timeout); 549 + } 550 + 551 + static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) 552 + { 553 + unsigned long time_left; 554 + struct i2c_msg *msg; 555 + 556 + for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { 557 + msg = &i2c->msgs[i2c->msg_idx]; 558 + i2c->msg_buf = msg->buf; 559 + i2c->unprocessed = msg->len; 560 + i2c->status = 0; 561 + 562 + reinit_completion(&i2c->complete); 563 + 564 + spacemit_i2c_start(i2c); 565 + 566 + time_left = spacemit_i2c_wait_xfer_complete(i2c); 567 + 568 + if (!time_left) { 569 + dev_err(i2c->dev, "msg completion timeout\n"); 570 + spacemit_i2c_conditionally_reset_bus(i2c); 571 + spacemit_i2c_reset(i2c); 572 + return -ETIMEDOUT; 573 + } 574 + 575 + if (i2c->status & SPACEMIT_SR_ERR) 576 + return spacemit_i2c_handle_err(i2c); 577 + } 578 + 579 + return 0; 580 + } 581 + 582 + static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) 583 + { 584 + struct spacemit_i2c_dev *i2c = devid; 585 + u32 status; 586 + 587 + status = readl(i2c->base + SPACEMIT_ISR); 588 + if (!status) 589 + return IRQ_HANDLED; 590 + 591 + i2c->status = status; 592 + 593 + spacemit_i2c_clear_int_status(i2c, status); 594 + 595 + spacemit_i2c_handle_state(i2c); 596 + 480 597 return IRQ_HANDLED; 481 598 } 482 599 ··· 611 474 { 612 475 unsigned long timeout; 613 476 int idx = 0, cnt = 0; 477 + 478 + if (i2c->use_pio) { 479 + i2c->adapt.timeout = msecs_to_jiffies(SPACEMIT_WAIT_TIMEOUT); 480 + return; 481 + } 614 482 615 483 for (; idx < i2c->msg_num; idx++) 616 484 cnt += (i2c->msgs + idx)->len + 1; ··· 629 487 i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; 630 488 } 631 489 632 - static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) 490 + static inline int 491 + spacemit_i2c_xfer_common(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num, bool use_pio) 633 492 { 634 493 struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); 635 494 int ret; 495 + 496 + i2c->use_pio = use_pio; 636 497 637 498 i2c->msgs = msgs; 638 499 i2c->msg_num = num; ··· 664 519 return ret < 0 ? ret : num; 665 520 } 666 521 522 + static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) 523 + { 524 + return spacemit_i2c_xfer_common(adapt, msgs, num, false); 525 + } 526 + 527 + static int spacemit_i2c_pio_xfer_atomic(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) 528 + { 529 + return spacemit_i2c_xfer_common(adapt, msgs, num, true); 530 + } 531 + 667 532 static u32 spacemit_i2c_func(struct i2c_adapter *adap) 668 533 { 669 534 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); ··· 681 526 682 527 static const struct i2c_algorithm spacemit_i2c_algo = { 683 528 .xfer = spacemit_i2c_xfer, 529 + .xfer_atomic = spacemit_i2c_pio_xfer_atomic, 684 530 .functionality = spacemit_i2c_func, 685 531 }; 686 532

+1 -1

drivers/i2c/busses/i2c-npcm7xx.c

··· 1384 1384 */ 1385 1385 bus->operation = I2C_NO_OPER; 1386 1386 bus->own_slave_addr = 0xFF; 1387 - i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0); 1387 + i2c_slave_event(bus->slave, I2C_SLAVE_STOP, NULL); 1388 1388 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST); 1389 1389 if (bus->fifo_use) { 1390 1390 npcm_i2c_clear_fifo_int(bus);

+9 -15

drivers/i2c/busses/i2c-ocores.c

··· 24 24 #include <linux/io.h> 25 25 #include <linux/log2.h> 26 26 #include <linux/spinlock.h> 27 + #include <linux/iopoll.h> 27 28 #include <linux/jiffies.h> 28 29 29 30 /* ··· 259 258 * @reg: register to query 260 259 * @mask: bitmask to apply on register value 261 260 * @val: expected result 262 - * @timeout: timeout in jiffies 261 + * @timeout_us: timeout in microseconds 263 262 * 264 263 * Timeout is necessary to avoid to stay here forever when the chip 265 264 * does not answer correctly. ··· 268 267 */ 269 268 static int ocores_wait(struct ocores_i2c *i2c, 270 269 int reg, u8 mask, u8 val, 271 - const unsigned long timeout) 270 + unsigned long timeout_us) 272 271 { 273 - unsigned long j; 272 + u8 status; 274 273 275 - j = jiffies + timeout; 276 - while (1) { 277 - u8 status = oc_getreg(i2c, reg); 278 - 279 - if ((status & mask) == val) 280 - break; 281 - 282 - if (time_after(jiffies, j)) 283 - return -ETIMEDOUT; 284 - } 285 - return 0; 274 + return read_poll_timeout_atomic(oc_getreg, status, 275 + (status & mask) == val, 276 + 0, timeout_us, false, 277 + i2c, reg); 286 278 } 287 279 288 280 /** ··· 308 314 * once we are here we expect to get the expected result immediately 309 315 * so if after 1ms we timeout then something is broken. 310 316 */ 311 - err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1)); 317 + err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1000); 312 318 if (err) 313 319 dev_warn(i2c->adap.dev.parent, 314 320 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",

-3

drivers/i2c/busses/i2c-qcom-cci.c

··· 71 71 #define NUM_MASTERS 2 72 72 #define NUM_QUEUES 2 73 73 74 - /* Max number of resources + 1 for a NULL terminator */ 75 - #define CCI_RES_MAX 6 76 - 77 74 #define CCI_I2C_SET_PARAM 1 78 75 #define CCI_I2C_REPORT 8 79 76 #define CCI_I2C_WRITE 9

+19 -5

drivers/i2c/busses/i2c-qcom-geni.c

··· 625 625 { 626 626 struct gpi_i2c_config *peripheral; 627 627 unsigned int flags; 628 - void *dma_buf; 629 - dma_addr_t addr; 628 + void *dma_buf = NULL; 629 + dma_addr_t addr = 0; 630 630 enum dma_data_direction map_dirn; 631 631 enum dma_transfer_direction dma_dirn; 632 632 struct dma_async_tx_descriptor *desc; ··· 638 638 peripheral = config->peripheral_config; 639 639 gi2c_gpi_xfer = &gi2c->i2c_multi_desc_config; 640 640 msg_idx = gi2c_gpi_xfer->msg_idx_cnt; 641 + 642 + /* 643 + * Skip TX DMA mapping for a read message (I2C_M_RD) to avoid 644 + * programming an extra TX DMA TRE that would cause an unintended 645 + * write cycle on the I2C bus before the actual read operation. 646 + */ 647 + if (op == I2C_WRITE && msgs[msg_idx].flags & I2C_M_RD) { 648 + peripheral->multi_msg = true; 649 + goto skip_tx_dma_map; 650 + } 641 651 642 652 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1); 643 653 if (!dma_buf) { ··· 668 658 goto out; 669 659 } 670 660 661 + skip_tx_dma_map: 671 662 if (gi2c->is_tx_multi_desc_xfer) { 672 663 flags = DMA_CTRL_ACK; 673 664 ··· 751 740 return 0; 752 741 753 742 err_config: 754 - dma_unmap_single(gi2c->se.dev->parent, addr, 755 - msgs[msg_idx].len, map_dirn); 756 - i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 743 + /* Avoid DMA unmap as the write operation skipped DMA mapping */ 744 + if (dma_buf) { 745 + dma_unmap_single(gi2c->se.dev->parent, addr, 746 + msgs[msg_idx].len, map_dirn); 747 + i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 748 + } 757 749 758 750 out: 759 751 gi2c->err = ret;

+1 -3

drivers/i2c/busses/i2c-robotfuzz-osif.c

··· 141 141 if (!priv) 142 142 return -ENOMEM; 143 143 144 - priv->usb_dev = usb_get_dev(interface_to_usbdev(interface)); 144 + priv->usb_dev = interface_to_usbdev(interface); 145 145 priv->interface = interface; 146 146 147 147 usb_set_intfdata(interface, priv); ··· 163 163 NULL, 0); 164 164 if (ret) { 165 165 dev_err(&interface->dev, "failure sending bit rate"); 166 - usb_put_dev(priv->usb_dev); 167 166 return ret; 168 167 } 169 168 ··· 183 184 184 185 i2c_del_adapter(&(priv->adapter)); 185 186 usb_set_intfdata(interface, NULL); 186 - usb_put_dev(priv->usb_dev); 187 187 } 188 188 189 189 static struct usb_driver osif_driver = {

+164 -31

drivers/i2c/busses/i2c-rtl9300.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 3 3 #include <linux/bits.h> 4 + #include <linux/clk.h> 4 5 #include <linux/i2c.h> 5 6 #include <linux/i2c-mux.h> 6 7 #include <linux/mod_devicetable.h> ··· 12 11 #include <linux/unaligned.h> 13 12 14 13 enum rtl9300_bus_freq { 15 - RTL9300_I2C_STD_FREQ, 16 - RTL9300_I2C_FAST_FREQ, 14 + RTL9300_I2C_STD_FREQ, // 100kHz 15 + RTL9300_I2C_FAST_FREQ, // 400kHz 16 + RTL9300_I2C_SUPER_FAST_FREQ, // 2.5MHz 17 + RTL9300_I2C_SLOW_FREQ, // 50kHz 17 18 }; 19 + 20 + #define RTL9300_I2C_MAX_SUPER_FAST_FREQ 2500000 21 + #define RTL9300_I2C_MAX_SLOW_FREQ 50000 22 + 18 23 19 24 struct rtl9300_i2c; 20 25 ··· 29 22 struct rtl9300_i2c *i2c; 30 23 enum rtl9300_bus_freq bus_freq; 31 24 u8 sda_num; 25 + u32 clk_div; 32 26 }; 33 27 34 28 enum rtl9300_i2c_reg_scope { ··· 55 47 F_SCL_SEL, 56 48 F_SDA_OUT_SEL, 57 49 F_SDA_SEL, 50 + F_BUSY, 51 + F_CLK_DIV, 52 + F_EXT_SCK_5MS, 58 53 59 54 /* keep last */ 60 55 F_NUM_FIELDS ··· 66 55 struct rtl9300_i2c_drv_data { 67 56 struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS]; 68 57 int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl); 69 - u32 data_reg; 58 + int (*config_chan)(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan); 59 + void (*config_clock)(u32 clock_freq, struct rtl9300_i2c_chan *chan); 60 + int (*misc_init)(struct rtl9300_i2c *i2c); 61 + u32 rd_reg; 62 + u32 wd_reg; 70 63 u8 max_nchan; 64 + u8 max_data_len; 65 + u8 reg_addr_8bit_len; 71 66 }; 72 67 73 68 #define RTL9300_I2C_MUX_NCHAN 8 74 69 #define RTL9310_I2C_MUX_NCHAN 12 70 + #define RTL9607_I2C_MUX_NCHAN 1 71 + 72 + #define RTL9300_I2C_MAX_DATA_LEN 16 73 + #define RTL9607_I2C_MAX_DATA_LEN 4 75 74 76 75 struct rtl9300_i2c { 77 76 struct regmap *regmap; ··· 89 68 struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN]; 90 69 struct regmap_field *fields[F_NUM_FIELDS]; 91 70 u32 reg_base; 92 - u32 data_reg; 71 + u32 rd_reg; 72 + u32 wd_reg; 93 73 u8 scl_num; 94 74 u8 sda_num; 95 75 struct mutex lock; 76 + struct clk *clk; 96 77 }; 97 78 98 79 DEFINE_GUARD(rtl9300_i2c, struct rtl9300_i2c *, mutex_lock(&_T->lock), mutex_unlock(&_T->lock)) ··· 122 99 #define RTL9300_I2C_MST_DATA_WORD2 0x10 123 100 #define RTL9300_I2C_MST_DATA_WORD3 0x14 124 101 #define RTL9300_I2C_MST_GLB_CTRL 0x384 102 + #define RTL9300_REG_ADDR_8BIT_LEN 1 125 103 126 104 #define RTL9310_I2C_MST_IF_CTRL 0x1004 127 105 #define RTL9310_I2C_MST_IF_SEL 0x1008 128 106 #define RTL9310_I2C_MST_CTRL 0x0 129 107 #define RTL9310_I2C_MST_MEMADDR_CTRL 0x4 130 108 #define RTL9310_I2C_MST_DATA_CTRL 0x8 109 + 110 + #define RTL9607_I2C_CONFIG 0x22f50 111 + #define RTL9607_IO_MODE_EN 0x23014 112 + #define RTL9607_I2C_IND_WD 0x0 113 + #define RTL9607_I2C_IND_ADR 0x8 114 + #define RTL9607_I2C_IND_CMD 0x10 115 + #define RTL9607_I2C_IND_RD 0x18 116 + #define RTL9607_REG_ADDR_8BIT_LEN 0 131 117 132 118 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) 133 119 { ··· 189 157 return 0; 190 158 } 191 159 160 + static int rtl9607_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) 161 + { 162 + const struct rtl9300_i2c_drv_data *drv_data; 163 + int ret; 164 + 165 + if (i2c->sda_num == chan->sda_num) 166 + return 0; 167 + 168 + ret = regmap_field_write(i2c->fields[F_CLK_DIV], chan->clk_div); 169 + if (ret) 170 + return ret; 171 + 172 + drv_data = device_get_match_data(i2c->dev); 173 + ret = drv_data->select_scl(i2c, i2c->scl_num); 174 + if (ret) 175 + return ret; 176 + 177 + i2c->sda_num = chan->sda_num; 178 + return 0; 179 + } 180 + 181 + static void rtl9300_i2c_config_clock(u32 clock_freq, struct rtl9300_i2c_chan *chan) 182 + { 183 + struct rtl9300_i2c *i2c = chan->i2c; 184 + 185 + switch (clock_freq) { 186 + case I2C_MAX_STANDARD_MODE_FREQ: 187 + chan->bus_freq = RTL9300_I2C_STD_FREQ; 188 + break; 189 + case I2C_MAX_FAST_MODE_FREQ: 190 + chan->bus_freq = RTL9300_I2C_FAST_FREQ; 191 + break; 192 + case RTL9300_I2C_MAX_SUPER_FAST_FREQ: 193 + chan->bus_freq = RTL9300_I2C_SUPER_FAST_FREQ; 194 + break; 195 + case RTL9300_I2C_MAX_SLOW_FREQ: 196 + chan->bus_freq = RTL9300_I2C_SLOW_FREQ; 197 + break; 198 + default: 199 + dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n", 200 + chan->sda_num, clock_freq); 201 + break; 202 + } 203 + } 204 + 205 + static void rtl9607_i2c_config_clock(u32 clock_freq, struct rtl9300_i2c_chan *chan) 206 + { 207 + struct rtl9300_i2c *i2c = chan->i2c; 208 + 209 + chan->clk_div = clk_get_rate(i2c->clk) / clock_freq - 1; 210 + } 211 + 192 212 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, u8 len) 193 213 { 194 214 u32 vals[4] = {}; ··· 249 165 if (len > 16) 250 166 return -EIO; 251 167 252 - ret = regmap_bulk_read(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals)); 168 + ret = regmap_bulk_read(i2c->regmap, i2c->rd_reg, vals, ARRAY_SIZE(vals)); 253 169 if (ret) 254 170 return ret; 255 171 ··· 276 192 vals[reg] |= buf[i] << shift; 277 193 } 278 194 279 - return regmap_bulk_write(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals)); 195 + return regmap_bulk_write(i2c->regmap, i2c->wd_reg, vals, ARRAY_SIZE(vals)); 280 196 } 281 197 282 198 static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data) 283 199 { 284 - return regmap_write(i2c->regmap, i2c->data_reg, data); 200 + return regmap_write(i2c->regmap, i2c->wd_reg, data); 285 201 } 286 202 287 203 static int rtl9300_i2c_prepare_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer) 288 204 { 205 + const struct rtl9300_i2c_drv_data *drv_data; 289 206 int ret; 290 207 291 - if (xfer->data_len < 1 || xfer->data_len > 16) 208 + drv_data = device_get_match_data(i2c->dev); 209 + if (xfer->data_len < 1 || xfer->data_len > drv_data->max_data_len) 292 210 return -EINVAL; 293 211 294 212 ret = regmap_field_write(i2c->fields[F_DEV_ADDR], xfer->dev_addr); ··· 335 249 if (ret) 336 250 return ret; 337 251 338 - ret = regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 100000); 252 + ret = regmap_field_read_poll_timeout(i2c->fields[F_BUSY], val, !val, 100, 100000); 339 253 if (ret) 340 254 return ret; 341 255 ··· 348 262 if (!xfer->write) { 349 263 switch (xfer->type) { 350 264 case RTL9300_I2C_XFER_BYTE: 351 - ret = regmap_read(i2c->regmap, i2c->data_reg, &val); 265 + ret = regmap_read(i2c->regmap, i2c->rd_reg, &val); 352 266 if (ret) 353 267 return ret; 354 268 355 269 *xfer->data = val & 0xff; 356 270 break; 357 271 case RTL9300_I2C_XFER_WORD: 358 - ret = regmap_read(i2c->regmap, i2c->data_reg, &val); 272 + ret = regmap_read(i2c->regmap, i2c->rd_reg, &val); 359 273 if (ret) 360 274 return ret; 361 275 ··· 377 291 union i2c_smbus_data *data) 378 292 { 379 293 struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap); 294 + const struct rtl9300_i2c_drv_data *drv_data; 380 295 struct rtl9300_i2c *i2c = chan->i2c; 381 296 struct rtl9300_i2c_xfer xfer = {0}; 382 297 int ret; ··· 387 300 388 301 guard(rtl9300_i2c)(i2c); 389 302 390 - ret = rtl9300_i2c_config_chan(i2c, chan); 303 + drv_data = device_get_match_data(i2c->dev); 304 + ret = drv_data->config_chan(i2c, chan); 391 305 if (ret) 392 306 return ret; 393 307 394 308 xfer.dev_addr = addr & 0x7f; 395 309 xfer.write = (read_write == I2C_SMBUS_WRITE); 396 310 xfer.reg_addr = command; 397 - xfer.reg_addr_len = 1; 311 + xfer.reg_addr_len = drv_data->reg_addr_8bit_len; 398 312 399 313 switch (size) { 400 314 case I2C_SMBUS_BYTE: ··· 455 367 .max_write_len = 16, 456 368 }; 457 369 370 + static int rtl9300_i2c_init(struct rtl9300_i2c *i2c) 371 + { 372 + /* only use standard read format */ 373 + return regmap_field_write(i2c->fields[F_RD_MODE], 0); 374 + } 375 + 376 + static int rtl9607_i2c_init(struct rtl9300_i2c *i2c) 377 + { 378 + return regmap_field_write(i2c->fields[F_EXT_SCK_5MS], 1); 379 + } 380 + 458 381 static int rtl9300_i2c_probe(struct platform_device *pdev) 459 382 { 460 383 struct device *dev = &pdev->dev; ··· 501 402 if (device_get_child_node_count(dev) > drv_data->max_nchan) 502 403 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 503 404 504 - i2c->data_reg = i2c->reg_base + drv_data->data_reg; 405 + i2c->rd_reg = i2c->reg_base + drv_data->rd_reg; 406 + i2c->wd_reg = i2c->reg_base + drv_data->wd_reg; 505 407 for (i = 0; i < F_NUM_FIELDS; i++) { 506 408 fields[i] = drv_data->field_desc[i].field; 507 409 if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER) ··· 512 412 fields, F_NUM_FIELDS); 513 413 if (ret) 514 414 return ret; 415 + 416 + i2c->clk = devm_clk_get_optional_enabled(dev, NULL); 417 + if (IS_ERR(i2c->clk)) 418 + return dev_err_probe(dev, PTR_ERR(i2c->clk), "Failed to enable i2c clock\n"); 515 419 516 420 i = 0; 517 421 for_each_child_of_node_scoped(dev->of_node, child) { ··· 530 426 if (ret) 531 427 clock_freq = I2C_MAX_STANDARD_MODE_FREQ; 532 428 533 - switch (clock_freq) { 534 - case I2C_MAX_STANDARD_MODE_FREQ: 535 - chan->bus_freq = RTL9300_I2C_STD_FREQ; 536 - break; 537 - case I2C_MAX_FAST_MODE_FREQ: 538 - chan->bus_freq = RTL9300_I2C_FAST_FREQ; 539 - break; 540 - default: 541 - dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n", 542 - sda_num, clock_freq); 543 - break; 544 - } 545 - 546 429 chan->sda_num = sda_num; 547 430 chan->i2c = i2c; 431 + 432 + drv_data->config_clock(clock_freq, chan); 433 + 548 434 adap = &i2c->chans[i].adap; 549 435 adap->owner = THIS_MODULE; 550 436 adap->algo = &rtl9300_i2c_algo; ··· 552 458 } 553 459 i2c->sda_num = 0xff; 554 460 555 - /* only use standard read format */ 556 - ret = regmap_field_write(i2c->fields[F_RD_MODE], 0); 461 + ret = drv_data->misc_init(i2c); 557 462 if (ret) 558 463 return ret; 559 464 ··· 578 485 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3), 579 486 [F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1), 580 487 [F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7), 488 + [F_BUSY] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0), 581 489 }, 582 490 .select_scl = rtl9300_i2c_select_scl, 583 - .data_reg = RTL9300_I2C_MST_DATA_WORD0, 491 + .config_chan = rtl9300_i2c_config_chan, 492 + .config_clock = rtl9300_i2c_config_clock, 493 + .misc_init = rtl9300_i2c_init, 494 + .rd_reg = RTL9300_I2C_MST_DATA_WORD0, 495 + .wd_reg = RTL9300_I2C_MST_DATA_WORD0, 584 496 .max_nchan = RTL9300_I2C_MUX_NCHAN, 497 + .max_data_len = RTL9300_I2C_MAX_DATA_LEN, 498 + .reg_addr_8bit_len = RTL9300_REG_ADDR_8BIT_LEN, 585 499 }; 586 500 587 501 static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = { ··· 605 505 [F_I2C_FAIL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1), 606 506 [F_I2C_TRIG] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0), 607 507 [F_MEM_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23), 508 + [F_BUSY] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0), 608 509 }, 609 510 .select_scl = rtl9310_i2c_select_scl, 610 - .data_reg = RTL9310_I2C_MST_DATA_CTRL, 511 + .config_chan = rtl9300_i2c_config_chan, 512 + .config_clock = rtl9300_i2c_config_clock, 513 + .misc_init = rtl9300_i2c_init, 514 + .rd_reg = RTL9310_I2C_MST_DATA_CTRL, 515 + .wd_reg = RTL9310_I2C_MST_DATA_CTRL, 611 516 .max_nchan = RTL9310_I2C_MUX_NCHAN, 517 + .max_data_len = RTL9300_I2C_MAX_DATA_LEN, 518 + .reg_addr_8bit_len = RTL9300_REG_ADDR_8BIT_LEN, 519 + }; 520 + 521 + static const struct rtl9300_i2c_drv_data rtl9607_i2c_drv_data = { 522 + .field_desc = { 523 + [F_SCL_SEL] = GLB_REG_FIELD(RTL9607_IO_MODE_EN, 13, 14), 524 + [F_EXT_SCK_5MS] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 26, 26), 525 + [F_DEV_ADDR] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 14, 20), 526 + [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 12, 13), 527 + [F_DATA_WIDTH] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 10, 11), 528 + [F_CLK_DIV] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 0, 9), 529 + [F_I2C_FAIL] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 3, 3), 530 + [F_BUSY] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 2, 2), 531 + [F_RWOP] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 1, 1), 532 + [F_I2C_TRIG] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 0, 0), 533 + [F_MEM_ADDR] = MST_REG_FIELD(RTL9607_I2C_IND_ADR, 0, 31), 534 + }, 535 + .select_scl = rtl9310_i2c_select_scl, 536 + .config_chan = rtl9607_i2c_config_chan, 537 + .config_clock = rtl9607_i2c_config_clock, 538 + .misc_init = rtl9607_i2c_init, 539 + .rd_reg = RTL9607_I2C_IND_RD, 540 + .wd_reg = RTL9607_I2C_IND_WD, 541 + .max_nchan = RTL9607_I2C_MUX_NCHAN, 542 + .max_data_len = RTL9607_I2C_MAX_DATA_LEN, 543 + .reg_addr_8bit_len = RTL9607_REG_ADDR_8BIT_LEN, 612 544 }; 613 545 614 546 static const struct of_device_id i2c_rtl9300_dt_ids[] = { ··· 652 520 { .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data }, 653 521 { .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data }, 654 522 { .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data }, 523 + { .compatible = "realtek,rtl9607-i2c", .data = (void *) &rtl9607_i2c_drv_data }, 655 524 {} 656 525 }; 657 526 MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);

+6 -1

drivers/i2c/busses/i2c-s3c2410.c

··· 503 503 i2c->msg->buf[i2c->msg_ptr++] = byte; 504 504 505 505 /* Add actual length to read for smbus block read */ 506 - if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 506 + if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) { 507 + if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) { 508 + s3c24xx_i2c_stop(i2c, -EPROTO); 509 + break; 510 + } 507 511 i2c->msg->len += byte; 512 + } 508 513 prepare_read: 509 514 if (is_msglast(i2c)) { 510 515 /* last byte of buffer */

+393 -137

drivers/i2c/busses/i2c-tegra.c

··· 30 30 31 31 #define BYTES_PER_FIFO_WORD 4 32 32 33 - #define I2C_CNFG 0x000 34 33 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35 34 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 36 35 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37 36 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38 - #define I2C_STATUS 0x01c 39 - #define I2C_SL_CNFG 0x020 37 + 40 38 #define I2C_SL_CNFG_NACK BIT(1) 41 39 #define I2C_SL_CNFG_NEWSL BIT(2) 42 - #define I2C_SL_ADDR1 0x02c 43 - #define I2C_SL_ADDR2 0x030 44 - #define I2C_TLOW_SEXT 0x034 45 - #define I2C_TX_FIFO 0x050 46 - #define I2C_RX_FIFO 0x054 47 - #define I2C_PACKET_TRANSFER_STATUS 0x058 48 - #define I2C_FIFO_CONTROL 0x05c 40 + 49 41 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50 42 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51 43 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52 44 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53 - #define I2C_FIFO_STATUS 0x060 45 + 54 46 #define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55 47 #define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56 - #define I2C_INT_MASK 0x064 57 - #define I2C_INT_STATUS 0x068 48 + 58 49 #define I2C_INT_BUS_CLR_DONE BIT(11) 59 50 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60 51 #define I2C_INT_NO_ACK BIT(3) 61 52 #define I2C_INT_ARBITRATION_LOST BIT(2) 62 53 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63 54 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64 - #define I2C_CLK_DIVISOR 0x06c 55 + 65 56 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66 57 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 58 ··· 85 94 #define I2C_HEADER_CONTINUE_XFER BIT(15) 86 95 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 87 96 88 - #define I2C_BUS_CLEAR_CNFG 0x084 89 97 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 90 98 #define I2C_BC_STOP_COND BIT(2) 91 99 #define I2C_BC_TERMINATE BIT(1) 92 100 #define I2C_BC_ENABLE BIT(0) 93 - #define I2C_BUS_CLEAR_STATUS 0x088 101 + 94 102 #define I2C_BC_STATUS BIT(0) 95 103 96 - #define I2C_CONFIG_LOAD 0x08c 97 104 #define I2C_MSTR_CONFIG_LOAD BIT(0) 98 105 99 - #define I2C_CLKEN_OVERRIDE 0x090 100 106 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 101 107 102 - #define I2C_INTERFACE_TIMING_0 0x094 103 - #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 104 - #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 105 - #define I2C_INTERFACE_TIMING_1 0x098 106 - #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 107 - #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 108 - #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 109 - #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 108 + #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 109 + #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 110 + #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 111 + #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 112 + #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 113 + #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 110 114 111 - #define I2C_HS_INTERFACE_TIMING_0 0x09c 112 - #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 113 - #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 114 - #define I2C_HS_INTERFACE_TIMING_1 0x0a0 115 - #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116 - #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117 - #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 115 + #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 116 + #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 117 + #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 118 + #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 119 + #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 120 119 - #define I2C_MST_FIFO_CONTROL 0x0b4 120 121 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 121 122 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 122 123 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 123 124 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 124 125 125 - #define I2C_MST_FIFO_STATUS 0x0b8 126 126 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 127 127 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 128 128 129 - #define I2C_MASTER_RESET_CNTRL 0x0a8 130 - 131 - #define I2C_SW_MUTEX 0x0ec 132 129 #define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) 133 130 #define I2C_SW_MUTEX_GRANT GENMASK(7, 4) 134 131 #define I2C_SW_MUTEX_ID_CCPLEX 9 ··· 138 159 */ 139 160 #define I2C_PIO_MODE_PREFERRED_LEN 32 140 161 162 + struct tegra_i2c_regs { 163 + unsigned int cnfg; 164 + unsigned int status; 165 + unsigned int sl_cnfg; 166 + unsigned int sl_addr1; 167 + unsigned int sl_addr2; 168 + unsigned int tlow_sext; 169 + unsigned int tx_fifo; 170 + unsigned int rx_fifo; 171 + unsigned int packet_transfer_status; 172 + unsigned int fifo_control; 173 + unsigned int fifo_status; 174 + unsigned int int_mask; 175 + unsigned int int_status; 176 + unsigned int clk_divisor; 177 + unsigned int bus_clear_cnfg; 178 + unsigned int bus_clear_status; 179 + unsigned int config_load; 180 + unsigned int clken_override; 181 + unsigned int interface_timing_0; 182 + unsigned int interface_timing_1; 183 + unsigned int hs_interface_timing_0; 184 + unsigned int hs_interface_timing_1; 185 + unsigned int master_reset_cntrl; 186 + unsigned int mst_fifo_control; 187 + unsigned int mst_fifo_status; 188 + unsigned int sw_mutex; 189 + }; 190 + 191 + static const struct tegra_i2c_regs tegra20_i2c_regs = { 192 + .cnfg = 0x000, 193 + .status = 0x01c, 194 + .sl_cnfg = 0x020, 195 + .sl_addr1 = 0x02c, 196 + .sl_addr2 = 0x030, 197 + .tx_fifo = 0x050, 198 + .rx_fifo = 0x054, 199 + .packet_transfer_status = 0x058, 200 + .fifo_control = 0x05c, 201 + .fifo_status = 0x060, 202 + .int_mask = 0x064, 203 + .int_status = 0x068, 204 + .clk_divisor = 0x06c, 205 + .bus_clear_cnfg = 0x084, 206 + .bus_clear_status = 0x088, 207 + .config_load = 0x08c, 208 + .clken_override = 0x090, 209 + .interface_timing_0 = 0x094, 210 + .interface_timing_1 = 0x098, 211 + .hs_interface_timing_0 = 0x09c, 212 + .hs_interface_timing_1 = 0x0a0, 213 + .master_reset_cntrl = 0x0a8, 214 + .mst_fifo_control = 0x0b4, 215 + .mst_fifo_status = 0x0b8, 216 + }; 217 + 218 + #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) 219 + static const struct tegra_i2c_regs tegra20_dvc_i2c_regs = { 220 + .cnfg = 0x040, 221 + .status = 0x05c, 222 + .tx_fifo = 0x060, 223 + .rx_fifo = 0x064, 224 + .packet_transfer_status = 0x068, 225 + .fifo_control = 0x06c, 226 + .fifo_status = 0x070, 227 + .int_mask = 0x074, 228 + .int_status = 0x078, 229 + .clk_divisor = 0x07c, 230 + .bus_clear_cnfg = 0x094, 231 + .bus_clear_status = 0x098, 232 + .config_load = 0x09c, 233 + .clken_override = 0x0a0, 234 + .interface_timing_0 = 0x0a4, 235 + .interface_timing_1 = 0x0a8, 236 + .hs_interface_timing_0 = 0x0ac, 237 + .hs_interface_timing_1 = 0x0b0, 238 + .master_reset_cntrl = 0x0b8, 239 + .mst_fifo_control = 0x0c4, 240 + .mst_fifo_status = 0x0c8, 241 + }; 242 + #endif 243 + 244 + #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 245 + static const struct tegra_i2c_regs tegra210_vi_i2c_regs = { 246 + .cnfg = 0x0c00, 247 + .status = 0x0c70, 248 + .tlow_sext = 0x0cd0, 249 + .tx_fifo = 0x0d40, 250 + .rx_fifo = 0x0d50, 251 + .packet_transfer_status = 0x0d60, 252 + .fifo_control = 0x0d70, 253 + .fifo_status = 0x0d80, 254 + .int_mask = 0x0d90, 255 + .int_status = 0x0da0, 256 + .clk_divisor = 0x0db0, 257 + .bus_clear_cnfg = 0x0e10, 258 + .bus_clear_status = 0x0e20, 259 + .config_load = 0x0e30, 260 + .clken_override = 0x0e40, 261 + .interface_timing_0 = 0x0e50, 262 + .interface_timing_1 = 0x0e60, 263 + .hs_interface_timing_0 = 0x0e70, 264 + .hs_interface_timing_1 = 0x0e80, 265 + .master_reset_cntrl = 0x0ea0, 266 + .mst_fifo_control = 0x0ed0, 267 + .mst_fifo_status = 0x0ee0, 268 + }; 269 + #endif 270 + 271 + static const struct tegra_i2c_regs tegra264_i2c_regs = { 272 + .cnfg = 0x000, 273 + .status = 0x01c, 274 + .sl_cnfg = 0x020, 275 + .sl_addr1 = 0x02c, 276 + .sl_addr2 = 0x030, 277 + .tx_fifo = 0x050, 278 + .rx_fifo = 0x054, 279 + .packet_transfer_status = 0x058, 280 + .fifo_control = 0x05c, 281 + .fifo_status = 0x060, 282 + .int_mask = 0x064, 283 + .int_status = 0x068, 284 + .clk_divisor = 0x06c, 285 + .bus_clear_cnfg = 0x084, 286 + .bus_clear_status = 0x088, 287 + .config_load = 0x08c, 288 + .clken_override = 0x090, 289 + .interface_timing_0 = 0x094, 290 + .interface_timing_1 = 0x098, 291 + .hs_interface_timing_0 = 0x09c, 292 + .hs_interface_timing_1 = 0x0a0, 293 + .master_reset_cntrl = 0x0a8, 294 + .mst_fifo_control = 0x0b4, 295 + .mst_fifo_status = 0x0b8, 296 + .sw_mutex = 0x0ec, 297 + }; 298 + 299 + static const struct tegra_i2c_regs tegra410_i2c_regs = { 300 + .cnfg = 0x000, 301 + .status = 0x01c, 302 + .sl_cnfg = 0x020, 303 + .sl_addr1 = 0x02c, 304 + .sl_addr2 = 0x030, 305 + .tx_fifo = 0x054, 306 + .rx_fifo = 0x058, 307 + .packet_transfer_status = 0x05c, 308 + .fifo_control = 0x060, 309 + .fifo_status = 0x064, 310 + .int_mask = 0x068, 311 + .int_status = 0x06c, 312 + .clk_divisor = 0x070, 313 + .bus_clear_cnfg = 0x088, 314 + .bus_clear_status = 0x08c, 315 + .config_load = 0x090, 316 + .clken_override = 0x094, 317 + .interface_timing_0 = 0x098, 318 + .interface_timing_1 = 0x09c, 319 + .hs_interface_timing_0 = 0x0a0, 320 + .hs_interface_timing_1 = 0x0a4, 321 + .master_reset_cntrl = 0x0ac, 322 + .mst_fifo_control = 0x0b8, 323 + .mst_fifo_status = 0x0bc, 324 + .sw_mutex = 0x0f0, 325 + }; 326 + 141 327 /* 142 328 * msg_end_type: The bus control which needs to be sent at end of transfer. 143 329 * @MSG_END_STOP: Send stop pulse. ··· 313 169 MSG_END_STOP, 314 170 MSG_END_REPEAT_START, 315 171 MSG_END_CONTINUE, 172 + }; 173 + 174 + /* 175 + * tegra_i2c_variant: Identifies the variant of I2C controller. 176 + * @TEGRA_I2C_VARIANT_DEFAULT: Identifies the default I2C controller. 177 + * @TEGRA_I2C_VARIANT_DVC: Identifies the DVC I2C controller, has a different register layout. 178 + * @TEGRA_I2C_VARIANT_VI: Identifies the VI I2C controller, has a different register layout. 179 + */ 180 + enum tegra_i2c_variant { 181 + TEGRA_I2C_VARIANT_DEFAULT, 182 + TEGRA_I2C_VARIANT_DVC, 183 + TEGRA_I2C_VARIANT_VI, 316 184 }; 317 185 318 186 /** ··· 379 223 * timing settings. 380 224 * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers. 381 225 * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs. 226 + * @variant: This represents the I2C controller variant. 227 + * @regs: Register offsets for the specific SoC variant. 382 228 */ 383 229 struct tegra_i2c_hw_feature { 384 230 bool has_continue_xfer_support; ··· 412 254 bool has_interface_timing_reg; 413 255 bool enable_hs_mode_support; 414 256 bool has_mutex; 257 + enum tegra_i2c_variant variant; 258 + const struct tegra_i2c_regs *regs; 415 259 }; 416 260 417 261 /** ··· 428 268 * @base_phys: physical base address of the I2C controller 429 269 * @cont_id: I2C controller ID, used for packet header 430 270 * @irq: IRQ number of transfer complete interrupt 431 - * @is_dvc: identifies the DVC I2C controller, has a different register layout 432 - * @is_vi: identifies the VI I2C controller, has a different register layout 433 271 * @msg_complete: transfer completion notifier 434 272 * @msg_buf_remaining: size of unsent data in the message buffer 435 273 * @msg_len: length of message in current transfer ··· 479 321 bool atomic_mode; 480 322 bool dma_mode; 481 323 bool msg_read; 482 - bool is_dvc; 483 - bool is_vi; 484 324 }; 485 325 486 - #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc) 487 - #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi) 326 + #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \ 327 + (dev)->hw->variant == TEGRA_I2C_VARIANT_DVC) 328 + #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \ 329 + (dev)->hw->variant == TEGRA_I2C_VARIANT_VI) 488 330 489 331 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 490 332 unsigned int reg) ··· 497 339 return readl_relaxed(i2c_dev->base + reg); 498 340 } 499 341 500 - /* 501 - * If necessary, i2c_writel() and i2c_readl() will offset the register 502 - * in order to talk to the I2C block inside the DVC block. 503 - */ 504 - static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 505 - { 506 - if (IS_DVC(i2c_dev)) 507 - reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 508 - else if (IS_VI(i2c_dev)) 509 - reg = 0xc00 + (reg << 2); 510 - 511 - return reg; 512 - } 513 - 514 342 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 515 343 { 516 - writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 344 + writel_relaxed(val, i2c_dev->base + reg); 517 345 518 346 /* read back register to make sure that register writes completed */ 519 - if (reg != I2C_TX_FIFO) 520 - readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 347 + if (reg != i2c_dev->hw->regs->tx_fifo) 348 + readl_relaxed(i2c_dev->base + reg); 521 349 else if (IS_VI(i2c_dev)) 522 - readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 350 + readl_relaxed(i2c_dev->base + i2c_dev->hw->regs->int_status); 523 351 } 524 352 525 353 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 526 354 { 527 - return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 355 + return readl_relaxed(i2c_dev->base + reg); 528 356 } 529 357 530 358 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 531 359 unsigned int reg, unsigned int len) 532 360 { 533 - writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 361 + writesl(i2c_dev->base + reg, data, len); 534 362 } 535 363 536 364 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, ··· 537 393 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 538 394 unsigned int reg, unsigned int len) 539 395 { 540 - readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 396 + readsl(i2c_dev->base + reg, data, len); 541 397 } 542 398 543 399 static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) 544 400 { 545 - unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); 401 + unsigned int reg = i2c_dev->hw->regs->sw_mutex; 546 402 u32 val, id; 547 403 548 404 val = readl(i2c_dev->base + reg); ··· 553 409 554 410 static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) 555 411 { 556 - unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); 412 + unsigned int reg = i2c_dev->hw->regs->sw_mutex; 557 413 u32 val, id; 558 414 559 415 val = readl(i2c_dev->base + reg); ··· 591 447 592 448 static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) 593 449 { 594 - unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); 450 + unsigned int reg = i2c_dev->hw->regs->sw_mutex; 595 451 u32 val, id; 596 452 597 453 if (!i2c_dev->hw->has_mutex) ··· 614 470 { 615 471 u32 int_mask; 616 472 617 - int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 618 - i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 473 + int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) & ~mask; 474 + i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask); 619 475 } 620 476 621 477 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 622 478 { 623 479 u32 int_mask; 624 480 625 - int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 626 - i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 481 + int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) | mask; 482 + i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask); 627 483 } 628 484 629 485 static void tegra_i2c_dma_complete(void *args) ··· 767 623 768 624 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 769 625 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 770 - i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 626 + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_0); 771 627 772 628 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 773 629 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 774 630 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 775 631 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 776 - i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 632 + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_1); 777 633 778 634 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 779 635 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 780 - i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 636 + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_0); 781 637 782 638 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 783 639 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 784 640 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 785 - i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 641 + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_1); 786 642 787 643 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 788 - i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 644 + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->bus_clear_cnfg); 789 645 790 - i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 646 + i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->tlow_sext); 791 647 } 792 648 793 649 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 794 650 u32 reg, u32 mask, u32 delay_us, 795 651 u32 timeout_us) 796 652 { 797 - void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 653 + void __iomem *addr = i2c_dev->base + reg; 798 654 u32 val; 799 655 800 656 if (!i2c_dev->atomic_mode) ··· 813 669 if (i2c_dev->hw->has_mst_fifo) { 814 670 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 815 671 I2C_MST_FIFO_CONTROL_RX_FLUSH; 816 - offset = I2C_MST_FIFO_CONTROL; 672 + offset = i2c_dev->hw->regs->mst_fifo_control; 817 673 } else { 818 674 mask = I2C_FIFO_CONTROL_TX_FLUSH | 819 675 I2C_FIFO_CONTROL_RX_FLUSH; 820 - offset = I2C_FIFO_CONTROL; 676 + offset = i2c_dev->hw->regs->fifo_control; 821 677 } 822 678 823 679 val = i2c_readl(i2c_dev, offset); ··· 840 696 if (!i2c_dev->hw->has_config_load_reg) 841 697 return 0; 842 698 843 - i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 699 + i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, i2c_dev->hw->regs->config_load); 844 700 845 - err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 701 + err = tegra_i2c_poll_register(i2c_dev, i2c_dev->hw->regs->config_load, 0xffffffff, 846 702 1000, I2C_CONFIG_LOAD_TIMEOUT); 847 703 if (err) { 848 704 dev_err(i2c_dev->dev, "failed to load config\n"); ··· 863 719 * SW needs to wait for 2us after assertion and de-assertion of this soft 864 720 * reset. 865 721 */ 866 - i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL); 722 + i2c_writel(i2c_dev, 0x1, i2c_dev->hw->regs->master_reset_cntrl); 867 723 fsleep(2); 868 724 869 - i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL); 725 + i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->master_reset_cntrl); 870 726 fsleep(2); 871 727 872 728 return 0; ··· 908 764 if (i2c_dev->hw->has_multi_master_mode) 909 765 val |= I2C_CNFG_MULTI_MASTER_MODE; 910 766 911 - i2c_writel(i2c_dev, val, I2C_CNFG); 912 - i2c_writel(i2c_dev, 0, I2C_INT_MASK); 767 + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->cnfg); 768 + i2c_writel(i2c_dev, 0, i2c_dev->hw->regs->int_mask); 913 769 914 770 if (IS_VI(i2c_dev)) 915 771 tegra_i2c_vi_init(i2c_dev); ··· 954 810 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 955 811 i2c_dev->hw->clk_divisor_hs_mode) | 956 812 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 957 - i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 813 + i2c_writel(i2c_dev, clk_divisor, i2c_dev->hw->regs->clk_divisor); 958 814 959 815 if (i2c_dev->hw->has_interface_timing_reg) { 960 816 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 961 817 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 962 - i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 818 + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->interface_timing_0); 963 819 } 964 820 965 821 /* ··· 967 823 * Otherwise, preserve the chip default values. 968 824 */ 969 825 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 970 - i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 826 + i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->interface_timing_1); 971 827 972 828 /* Write HS mode registers. These will get used only for HS mode*/ 973 829 if (i2c_dev->hw->enable_hs_mode_support) { ··· 977 833 978 834 val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | 979 835 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); 980 - i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); 981 - i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); 836 + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->hs_interface_timing_0); 837 + i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->hs_interface_timing_1); 982 838 } 983 839 984 840 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); ··· 991 847 } 992 848 993 849 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) { 994 - u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 850 + u32 sl_cfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->sl_cnfg); 995 851 996 852 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 997 - i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 998 - i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 999 - i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 853 + i2c_writel(i2c_dev, sl_cfg, i2c_dev->hw->regs->sl_cnfg); 854 + i2c_writel(i2c_dev, 0xfc, i2c_dev->hw->regs->sl_addr1); 855 + i2c_writel(i2c_dev, 0x00, i2c_dev->hw->regs->sl_addr2); 1000 856 } 1001 857 1002 858 err = tegra_i2c_flush_fifos(i2c_dev); ··· 1004 860 return err; 1005 861 1006 862 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 1007 - i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 863 + i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, i2c_dev->hw->regs->clken_override); 1008 864 1009 865 err = tegra_i2c_wait_for_config_load(i2c_dev); 1010 866 if (err) ··· 1025 881 */ 1026 882 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 1027 883 1028 - cnfg = i2c_readl(i2c_dev, I2C_CNFG); 884 + cnfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg); 1029 885 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 1030 - i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 886 + i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, i2c_dev->hw->regs->cnfg); 1031 887 1032 888 return tegra_i2c_wait_for_config_load(i2c_dev); 1033 889 } ··· 1047 903 return -EINVAL; 1048 904 1049 905 if (i2c_dev->hw->has_mst_fifo) { 1050 - val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 906 + val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status); 1051 907 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 1052 908 } else { 1053 - val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 909 + val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status); 1054 910 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 1055 911 } 1056 912 ··· 1059 915 if (words_to_transfer > rx_fifo_avail) 1060 916 words_to_transfer = rx_fifo_avail; 1061 917 1062 - i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 918 + i2c_readsl(i2c_dev, buf, i2c_dev->hw->regs->rx_fifo, words_to_transfer); 1063 919 1064 920 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 1065 921 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; ··· 1075 931 * when (words_to_transfer was > rx_fifo_avail) earlier 1076 932 * in this function. 1077 933 */ 1078 - val = i2c_readl(i2c_dev, I2C_RX_FIFO); 934 + val = i2c_readl(i2c_dev, i2c_dev->hw->regs->rx_fifo); 1079 935 val = cpu_to_le32(val); 1080 936 memcpy(buf, &val, buf_remaining); 1081 937 buf_remaining = 0; ··· 1100 956 u32 val; 1101 957 1102 958 if (i2c_dev->hw->has_mst_fifo) { 1103 - val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 959 + val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status); 1104 960 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 1105 961 } else { 1106 - val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 962 + val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status); 1107 963 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 1108 964 } 1109 965 ··· 1134 990 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 1135 991 1136 992 if (IS_VI(i2c_dev)) 1137 - i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 993 + i2c_writesl_vi(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer); 1138 994 else 1139 - i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 995 + i2c_writesl(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer); 1140 996 1141 997 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 1142 998 } ··· 1158 1014 i2c_dev->msg_buf_remaining = 0; 1159 1015 i2c_dev->msg_buf = NULL; 1160 1016 1161 - i2c_writel(i2c_dev, val, I2C_TX_FIFO); 1017 + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->tx_fifo); 1162 1018 } 1163 1019 1164 1020 return 0; ··· 1170 1026 struct tegra_i2c_dev *i2c_dev = dev_id; 1171 1027 u32 status; 1172 1028 1173 - status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1029 + status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status); 1174 1030 1175 1031 if (status == 0) { 1176 1032 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 1177 - i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 1178 - i2c_readl(i2c_dev, I2C_STATUS), 1179 - i2c_readl(i2c_dev, I2C_CNFG)); 1033 + i2c_readl(i2c_dev, i2c_dev->hw->regs->packet_transfer_status), 1034 + i2c_readl(i2c_dev, i2c_dev->hw->regs->status), 1035 + i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg)); 1180 1036 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 1181 1037 goto err; 1182 1038 } ··· 1219 1075 } 1220 1076 } 1221 1077 1222 - i2c_writel(i2c_dev, status, I2C_INT_STATUS); 1078 + i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status); 1223 1079 if (IS_DVC(i2c_dev)) 1224 1080 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 1225 1081 ··· 1257 1113 if (i2c_dev->hw->supports_bus_clear) 1258 1114 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1259 1115 1260 - i2c_writel(i2c_dev, status, I2C_INT_STATUS); 1116 + i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status); 1261 1117 1262 1118 if (IS_DVC(i2c_dev)) 1263 1119 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); ··· 1280 1136 int err; 1281 1137 1282 1138 if (i2c_dev->hw->has_mst_fifo) 1283 - reg = I2C_MST_FIFO_CONTROL; 1139 + reg = i2c_dev->hw->regs->mst_fifo_control; 1284 1140 else 1285 - reg = I2C_FIFO_CONTROL; 1141 + reg = i2c_dev->hw->regs->fifo_control; 1286 1142 1287 1143 if (i2c_dev->dma_mode) { 1288 1144 if (len & 0xF) ··· 1293 1149 dma_burst = 8; 1294 1150 1295 1151 if (i2c_dev->msg_read) { 1296 - reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 1152 + reg_offset = i2c_dev->hw->regs->rx_fifo; 1297 1153 1298 1154 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 1299 1155 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ··· 1304 1160 else 1305 1161 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1306 1162 } else { 1307 - reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1163 + reg_offset = i2c_dev->hw->regs->tx_fifo; 1308 1164 1309 1165 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1310 1166 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ··· 1347 1203 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1348 1204 1349 1205 do { 1350 - u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1206 + u32 status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status); 1351 1207 1352 1208 if (status) 1353 1209 tegra_i2c_isr(i2c_dev->irq, i2c_dev); ··· 1406 1262 1407 1263 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1408 1264 I2C_BC_TERMINATE; 1409 - i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1265 + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg); 1410 1266 1411 1267 err = tegra_i2c_wait_for_config_load(i2c_dev); 1412 1268 if (err) 1413 1269 return err; 1414 1270 1415 1271 val |= I2C_BC_ENABLE; 1416 - i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1272 + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg); 1417 1273 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1418 1274 1419 1275 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); ··· 1424 1280 return -ETIMEDOUT; 1425 1281 } 1426 1282 1427 - val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1283 + val = i2c_readl(i2c_dev, i2c_dev->hw->regs->bus_clear_status); 1428 1284 if (!(val & I2C_BC_STATUS)) { 1429 1285 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1430 1286 return -EIO; ··· 1449 1305 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1450 1306 *dma_buf++ = packet_header; 1451 1307 else 1452 - i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1308 + i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo); 1453 1309 1454 1310 packet_header = i2c_dev->msg_len - 1; 1455 1311 1456 1312 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1457 1313 *dma_buf++ = packet_header; 1458 1314 else 1459 - i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1315 + i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo); 1460 1316 1461 1317 packet_header = I2C_HEADER_IE_ENABLE; 1462 1318 ··· 1484 1340 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1485 1341 *dma_buf++ = packet_header; 1486 1342 else 1487 - i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1343 + i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo); 1488 1344 } 1489 1345 1490 1346 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, ··· 1605 1461 1606 1462 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1607 1463 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1608 - i2c_readl(i2c_dev, I2C_INT_MASK)); 1464 + i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask)); 1609 1465 1610 1466 if (i2c_dev->dma_mode) { 1611 1467 time_left = tegra_i2c_wait_completion(i2c_dev, ··· 1779 1635 .has_interface_timing_reg = false, 1780 1636 .enable_hs_mode_support = false, 1781 1637 .has_mutex = false, 1638 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1639 + .regs = &tegra20_i2c_regs, 1782 1640 }; 1641 + 1642 + #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) 1643 + static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw = { 1644 + .has_continue_xfer_support = false, 1645 + .has_per_pkt_xfer_complete_irq = false, 1646 + .clk_divisor_hs_mode = 3, 1647 + .clk_divisor_std_mode = 0, 1648 + .clk_divisor_fast_mode = 0, 1649 + .clk_divisor_fast_plus_mode = 0, 1650 + .has_config_load_reg = false, 1651 + .has_multi_master_mode = false, 1652 + .has_slcg_override_reg = false, 1653 + .has_mst_fifo = false, 1654 + .has_mst_reset = false, 1655 + .quirks = &tegra_i2c_quirks, 1656 + .supports_bus_clear = false, 1657 + .has_apb_dma = true, 1658 + .tlow_std_mode = 0x4, 1659 + .thigh_std_mode = 0x2, 1660 + .tlow_fast_mode = 0x4, 1661 + .thigh_fast_mode = 0x2, 1662 + .tlow_fastplus_mode = 0x4, 1663 + .thigh_fastplus_mode = 0x2, 1664 + .setup_hold_time_std_mode = 0x0, 1665 + .setup_hold_time_fast_mode = 0x0, 1666 + .setup_hold_time_fastplus_mode = 0x0, 1667 + .setup_hold_time_hs_mode = 0x0, 1668 + .has_interface_timing_reg = false, 1669 + .enable_hs_mode_support = false, 1670 + .has_mutex = false, 1671 + .variant = TEGRA_I2C_VARIANT_DVC, 1672 + .regs = &tegra20_dvc_i2c_regs, 1673 + }; 1674 + #endif 1783 1675 1784 1676 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1785 1677 .has_continue_xfer_support = true, ··· 1845 1665 .has_interface_timing_reg = false, 1846 1666 .enable_hs_mode_support = false, 1847 1667 .has_mutex = false, 1668 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1669 + .regs = &tegra20_i2c_regs, 1848 1670 }; 1849 1671 1850 1672 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { ··· 1877 1695 .has_interface_timing_reg = false, 1878 1696 .enable_hs_mode_support = false, 1879 1697 .has_mutex = false, 1698 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1699 + .regs = &tegra20_i2c_regs, 1880 1700 }; 1881 1701 1882 1702 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { ··· 1909 1725 .has_interface_timing_reg = true, 1910 1726 .enable_hs_mode_support = false, 1911 1727 .has_mutex = false, 1728 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1729 + .regs = &tegra20_i2c_regs, 1912 1730 }; 1913 1731 1914 1732 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { ··· 1941 1755 .has_interface_timing_reg = true, 1942 1756 .enable_hs_mode_support = false, 1943 1757 .has_mutex = false, 1758 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1759 + .regs = &tegra20_i2c_regs, 1944 1760 }; 1761 + 1762 + #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 1763 + static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw = { 1764 + .has_continue_xfer_support = true, 1765 + .has_per_pkt_xfer_complete_irq = true, 1766 + .clk_divisor_hs_mode = 1, 1767 + .clk_divisor_std_mode = 0x19, 1768 + .clk_divisor_fast_mode = 0x19, 1769 + .clk_divisor_fast_plus_mode = 0x10, 1770 + .has_config_load_reg = true, 1771 + .has_multi_master_mode = false, 1772 + .has_slcg_override_reg = true, 1773 + .has_mst_fifo = false, 1774 + .has_mst_reset = false, 1775 + .quirks = &tegra_i2c_quirks, 1776 + .supports_bus_clear = true, 1777 + .has_apb_dma = true, 1778 + .tlow_std_mode = 0x4, 1779 + .thigh_std_mode = 0x2, 1780 + .tlow_fast_mode = 0x4, 1781 + .thigh_fast_mode = 0x2, 1782 + .tlow_fastplus_mode = 0x4, 1783 + .thigh_fastplus_mode = 0x2, 1784 + .setup_hold_time_std_mode = 0, 1785 + .setup_hold_time_fast_mode = 0, 1786 + .setup_hold_time_fastplus_mode = 0, 1787 + .setup_hold_time_hs_mode = 0, 1788 + .has_interface_timing_reg = true, 1789 + .enable_hs_mode_support = false, 1790 + .has_mutex = false, 1791 + .variant = TEGRA_I2C_VARIANT_VI, 1792 + .regs = &tegra210_vi_i2c_regs, 1793 + }; 1794 + #endif 1945 1795 1946 1796 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1947 1797 .has_continue_xfer_support = true, ··· 2007 1785 .has_interface_timing_reg = true, 2008 1786 .enable_hs_mode_support = false, 2009 1787 .has_mutex = false, 1788 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1789 + .regs = &tegra20_i2c_regs, 2010 1790 }; 2011 1791 2012 1792 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { ··· 2041 1817 .has_interface_timing_reg = true, 2042 1818 .enable_hs_mode_support = true, 2043 1819 .has_mutex = false, 1820 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1821 + .regs = &tegra20_i2c_regs, 2044 1822 }; 2045 1823 2046 1824 static const struct tegra_i2c_hw_feature tegra256_i2c_hw = { ··· 2075 1849 .has_interface_timing_reg = true, 2076 1850 .enable_hs_mode_support = true, 2077 1851 .has_mutex = true, 1852 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1853 + .regs = &tegra264_i2c_regs, 2078 1854 }; 2079 1855 2080 1856 static const struct tegra_i2c_hw_feature tegra264_i2c_hw = { ··· 2109 1881 .has_interface_timing_reg = true, 2110 1882 .enable_hs_mode_support = true, 2111 1883 .has_mutex = true, 1884 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1885 + .regs = &tegra264_i2c_regs, 1886 + }; 1887 + 1888 + static const struct tegra_i2c_hw_feature tegra410_i2c_hw = { 1889 + .has_continue_xfer_support = true, 1890 + .has_per_pkt_xfer_complete_irq = true, 1891 + .clk_divisor_hs_mode = 1, 1892 + .clk_divisor_std_mode = 0x3f, 1893 + .clk_divisor_fast_mode = 0x2c, 1894 + .clk_divisor_fast_plus_mode = 0x11, 1895 + .has_config_load_reg = true, 1896 + .has_multi_master_mode = true, 1897 + .has_slcg_override_reg = true, 1898 + .has_mst_fifo = true, 1899 + .has_mst_reset = true, 1900 + .quirks = &tegra194_i2c_quirks, 1901 + .supports_bus_clear = true, 1902 + .has_apb_dma = false, 1903 + .tlow_std_mode = 0x8, 1904 + .thigh_std_mode = 0x7, 1905 + .tlow_fast_mode = 0x2, 1906 + .thigh_fast_mode = 0x2, 1907 + .tlow_fastplus_mode = 0x2, 1908 + .thigh_fastplus_mode = 0x2, 1909 + .tlow_hs_mode = 0x8, 1910 + .thigh_hs_mode = 0x6, 1911 + .setup_hold_time_std_mode = 0x08080808, 1912 + .setup_hold_time_fast_mode = 0x02020202, 1913 + .setup_hold_time_fastplus_mode = 0x02020202, 1914 + .setup_hold_time_hs_mode = 0x0b0b0b, 1915 + .has_interface_timing_reg = true, 1916 + .enable_hs_mode_support = true, 1917 + .has_mutex = true, 1918 + .variant = TEGRA_I2C_VARIANT_DEFAULT, 1919 + .regs = &tegra410_i2c_regs, 2112 1920 }; 2113 1921 2114 1922 static const struct of_device_id tegra_i2c_of_match[] = { ··· 2153 1889 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 2154 1890 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 2155 1891 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 2156 - { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1892 + { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_vi_i2c_hw, }, 2157 1893 #endif 2158 1894 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 2159 1895 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, ··· 2161 1897 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 2162 1898 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 2163 1899 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) 2164 - { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1900 + { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_dvc_i2c_hw, }, 2165 1901 #endif 2166 1902 {}, 2167 1903 }; ··· 2169 1905 2170 1906 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 2171 1907 { 2172 - struct device_node *np = i2c_dev->dev->of_node; 2173 1908 bool multi_mode; 2174 1909 2175 1910 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 2176 1911 2177 1912 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 2178 1913 i2c_dev->multimaster_mode = multi_mode; 2179 - 2180 - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && 2181 - of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 2182 - i2c_dev->is_dvc = true; 2183 - 2184 - if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && 2185 - of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 2186 - i2c_dev->is_vi = true; 2187 1914 } 2188 1915 2189 1916 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) ··· 2460 2205 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 2461 2206 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 2462 2207 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 2208 + {.id = "NVDA2017", .driver_data = (kernel_ulong_t)&tegra410_i2c_hw}, 2463 2209 { } 2464 2210 }; 2465 2211 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);

+3 -10

drivers/i2c/busses/i2c-tiny-usb.c

··· 213 213 return ret; 214 214 } 215 215 216 - static void i2c_tiny_usb_free(struct i2c_tiny_usb *dev) 217 - { 218 - usb_put_dev(dev->usb_dev); 219 - kfree(dev); 220 - } 221 - 222 216 static int i2c_tiny_usb_probe(struct usb_interface *interface, 223 217 const struct usb_device_id *id) 224 218 { ··· 231 237 if (!dev) 232 238 goto error; 233 239 234 - dev->usb_dev = usb_get_dev(interface_to_usbdev(interface)); 240 + dev->usb_dev = interface_to_usbdev(interface); 235 241 dev->interface = interface; 236 242 237 243 /* save our data pointer in this interface device */ ··· 271 277 return 0; 272 278 273 279 error: 274 - if (dev) 275 - i2c_tiny_usb_free(dev); 280 + kfree(dev); 276 281 277 282 return retval; 278 283 } ··· 282 289 283 290 i2c_del_adapter(&dev->adapter); 284 291 usb_set_intfdata(interface, NULL); 285 - i2c_tiny_usb_free(dev); 292 + kfree(dev); 286 293 287 294 dev_dbg(&interface->dev, "disconnected\n"); 288 295 }

+1

drivers/i2c/busses/i2c-usbio.c

··· 29 29 { "INTC10B6" }, /* LNL */ 30 30 { "INTC10D2" }, /* MTL-CVF */ 31 31 { "INTC10E3" }, /* PTL */ 32 + { "INTC1118" }, /* NVL */ 32 33 { } 33 34 }; 34 35

+42 -55

drivers/i2c/busses/i2c-xiic.c

··· 27 27 #include <linux/platform_data/i2c-xiic.h> 28 28 #include <linux/io.h> 29 29 #include <linux/slab.h> 30 - #include <linux/of.h> 31 30 #include <linux/clk.h> 32 31 #include <linux/pm_runtime.h> 33 32 #include <linux/iopoll.h> ··· 1407 1408 .algo = &xiic_algorithm, 1408 1409 }; 1409 1410 1410 - #if defined(CONFIG_OF) 1411 1411 static const struct xiic_version_data xiic_2_00 = { 1412 1412 .quirks = DYNAMIC_MODE_READ_BROKEN_BIT, 1413 1413 }; ··· 1417 1419 {}, 1418 1420 }; 1419 1421 MODULE_DEVICE_TABLE(of, xiic_of_match); 1420 - #endif 1421 1422 1422 1423 static int xiic_i2c_probe(struct platform_device *pdev) 1423 1424 { 1425 + struct device *dev = &pdev->dev; 1426 + struct fwnode_handle *fwnode = dev_fwnode(dev); 1424 1427 struct xiic_i2c *i2c; 1425 1428 struct xiic_i2c_platform_data *pdata; 1426 - const struct of_device_id *match; 1429 + const struct xiic_version_data *data; 1427 1430 struct resource *res; 1428 1431 int ret, irq; 1429 1432 u8 i; 1430 1433 u32 sr; 1431 1434 1432 - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1435 + i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); 1433 1436 if (!i2c) 1434 1437 return -ENOMEM; 1435 1438 1436 - match = of_match_node(xiic_of_match, pdev->dev.of_node); 1437 - if (match && match->data) { 1438 - const struct xiic_version_data *data = match->data; 1439 - 1439 + data = device_get_match_data(dev); 1440 + if (data) 1440 1441 i2c->quirks = data->quirks; 1441 - } 1442 1442 1443 1443 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1444 1444 if (IS_ERR(i2c->base)) ··· 1446 1450 if (irq < 0) 1447 1451 return irq; 1448 1452 1449 - pdata = dev_get_platdata(&pdev->dev); 1453 + pdata = dev_get_platdata(dev); 1450 1454 1451 1455 /* hook up driver to tree */ 1452 1456 platform_set_drvdata(pdev, i2c); 1453 1457 i2c->adap = xiic_adapter; 1458 + i2c->adap.nr = pdev->id; 1454 1459 i2c_set_adapdata(&i2c->adap, i2c); 1455 1460 i2c->adap.dev.parent = &pdev->dev; 1456 - i2c->adap.dev.of_node = pdev->dev.of_node; 1461 + device_set_node(&i2c->adap.dev, fwnode); 1457 1462 snprintf(i2c->adap.name, sizeof(i2c->adap.name), 1458 1463 DRIVER_NAME " %s", pdev->name); 1459 1464 1460 - mutex_init(&i2c->lock); 1465 + ret = devm_mutex_init(dev, &i2c->lock); 1466 + if (ret) 1467 + return ret; 1468 + 1461 1469 spin_lock_init(&i2c->atomic_lock); 1462 1470 1463 - i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1464 - if (IS_ERR(i2c->clk)) 1465 - return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 1466 - "failed to enable input clock.\n"); 1471 + if (is_of_node(fwnode)) { 1472 + i2c->clk = devm_clk_get_enabled(dev, NULL); 1473 + if (IS_ERR(i2c->clk)) 1474 + return dev_err_probe(dev, PTR_ERR(i2c->clk), 1475 + "failed to enable input clock.\n"); 1476 + } 1467 1477 1468 - i2c->dev = &pdev->dev; 1469 - pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 1470 - pm_runtime_use_autosuspend(i2c->dev); 1471 - pm_runtime_set_active(i2c->dev); 1472 - pm_runtime_enable(i2c->dev); 1478 + i2c->dev = dev; 1479 + 1480 + pm_runtime_set_autosuspend_delay(dev, XIIC_PM_TIMEOUT); 1481 + pm_runtime_use_autosuspend(dev); 1482 + ret = devm_pm_runtime_set_active_enabled(dev); 1483 + if (ret) 1484 + return ret; 1473 1485 1474 1486 /* SCL frequency configuration */ 1475 1487 i2c->input_clk = clk_get_rate(i2c->clk); 1476 - ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1477 - &i2c->i2c_clk); 1488 + ret = device_property_read_u32(dev, "clock-frequency", &i2c->i2c_clk); 1478 1489 /* If clock-frequency not specified in DT, do not configure in SW */ 1479 1490 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ) 1480 1491 i2c->i2c_clk = 0; 1481 1492 1482 - ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1483 - xiic_process, IRQF_ONESHOT, 1484 - pdev->name, i2c); 1493 + ret = devm_request_threaded_irq(dev, irq, NULL, xiic_process, 1494 + IRQF_ONESHOT, pdev->name, i2c); 1495 + if (ret) 1496 + return ret; 1485 1497 1486 - if (ret < 0) { 1487 - dev_err_probe(&pdev->dev, ret, "Cannot claim IRQ\n"); 1488 - goto err_pm_disable; 1489 - } 1490 - 1491 - i2c->singlemaster = 1492 - of_property_read_bool(pdev->dev.of_node, "single-master"); 1498 + i2c->singlemaster = device_property_read_bool(dev, "single-master"); 1493 1499 1494 1500 /* 1495 1501 * Detect endianness ··· 1506 1508 i2c->endianness = BIG; 1507 1509 1508 1510 ret = xiic_reinit(i2c); 1509 - if (ret < 0) { 1510 - dev_err_probe(&pdev->dev, ret, "Cannot xiic_reinit\n"); 1511 - goto err_pm_disable; 1512 - } 1511 + if (ret) 1512 + return dev_err_probe(dev, ret, "Cannot xiic_reinit\n"); 1513 1513 1514 1514 /* add i2c adapter to i2c tree */ 1515 - ret = i2c_add_adapter(&i2c->adap); 1515 + ret = i2c_add_numbered_adapter(&i2c->adap); 1516 1516 if (ret) { 1517 1517 xiic_deinit(i2c); 1518 - goto err_pm_disable; 1518 + return ret; 1519 1519 } 1520 1520 1521 1521 if (pdata) { ··· 1522 1526 i2c_new_client_device(&i2c->adap, pdata->devices + i); 1523 1527 } 1524 1528 1525 - dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n", 1526 - (unsigned long)res->start, irq, i2c->i2c_clk); 1529 + dev_dbg(dev, "mmio %pR irq %d scl clock frequency %d\n", 1530 + res, irq, i2c->i2c_clk); 1527 1531 1528 1532 return 0; 1529 - 1530 - err_pm_disable: 1531 - pm_runtime_disable(&pdev->dev); 1532 - pm_runtime_set_suspended(&pdev->dev); 1533 - 1534 - return ret; 1535 1533 } 1536 1534 1537 1535 static void xiic_i2c_remove(struct platform_device *pdev) 1538 1536 { 1537 + struct device *dev = &pdev->dev; 1539 1538 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 1540 1539 int ret; 1541 1540 1542 1541 /* remove adapter & data */ 1543 1542 i2c_del_adapter(&i2c->adap); 1544 1543 1545 - ret = pm_runtime_get_sync(i2c->dev); 1546 - 1544 + ret = pm_runtime_get_sync(dev); 1547 1545 if (ret < 0) 1548 - dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n", 1546 + dev_warn(dev, "Failed to activate device for removal (%pe)\n", 1549 1547 ERR_PTR(ret)); 1550 1548 else 1551 1549 xiic_deinit(i2c); 1552 1550 1553 - pm_runtime_put_sync(i2c->dev); 1554 - pm_runtime_disable(&pdev->dev); 1555 - pm_runtime_set_suspended(&pdev->dev); 1556 - pm_runtime_dont_use_autosuspend(&pdev->dev); 1551 + pm_runtime_put_sync(dev); 1557 1552 } 1558 1553 1559 1554 static const struct dev_pm_ops xiic_dev_pm_ops = {

+4 -13

drivers/i2c/i2c-atr.c

··· 49 49 * @shared: Indicates if this alias pool is shared by multiple channels 50 50 * 51 51 * @lock: Lock protecting @aliases and @use_mask 52 - * @aliases: Array of aliases, must hold exactly @size elements 53 52 * @use_mask: Mask of used aliases 53 + * @aliases: Array of aliases, must hold exactly @size elements 54 54 */ 55 55 struct i2c_atr_alias_pool { 56 56 size_t size; ··· 58 58 59 59 /* Protects aliases and use_mask */ 60 60 spinlock_t lock; 61 - u16 *aliases; 62 61 unsigned long *use_mask; 62 + u16 aliases[] __counted_by(size); 63 63 }; 64 64 65 65 /** ··· 137 137 struct i2c_atr_alias_pool *alias_pool; 138 138 int ret; 139 139 140 - alias_pool = kzalloc_obj(*alias_pool); 140 + alias_pool = kzalloc_flex(*alias_pool, aliases, num_aliases); 141 141 if (!alias_pool) 142 142 return ERR_PTR(-ENOMEM); 143 143 144 144 alias_pool->size = num_aliases; 145 145 146 - alias_pool->aliases = kcalloc(num_aliases, sizeof(*alias_pool->aliases), GFP_KERNEL); 147 - if (!alias_pool->aliases) { 148 - ret = -ENOMEM; 149 - goto err_free_alias_pool; 150 - } 151 - 152 146 alias_pool->use_mask = bitmap_zalloc(num_aliases, GFP_KERNEL); 153 147 if (!alias_pool->use_mask) { 154 148 ret = -ENOMEM; 155 - goto err_free_aliases; 149 + goto err_free_alias_pool; 156 150 } 157 151 158 152 alias_pool->shared = shared; ··· 155 161 156 162 return alias_pool; 157 163 158 - err_free_aliases: 159 - kfree(alias_pool->aliases); 160 164 err_free_alias_pool: 161 165 kfree(alias_pool); 162 166 return ERR_PTR(ret); ··· 163 171 static void i2c_atr_free_alias_pool(struct i2c_atr_alias_pool *alias_pool) 164 172 { 165 173 bitmap_free(alias_pool->use_mask); 166 - kfree(alias_pool->aliases); 167 174 kfree(alias_pool); 168 175 } 169 176

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