drm/radeon: add ring and IB tests for CIK (v3)

+114

1 changed file

expand all

drivers

gpu

drm

radeon

cik.c

+114

drivers/gpu/drm/radeon/cik.c

··· 1518 1518 } 1519 1519 1520 1520 /** 1521 + * cik_ring_test - basic gfx ring test 1522 + * 1523 + * @rdev: radeon_device pointer 1524 + * @ring: radeon_ring structure holding ring information 1525 + * 1526 + * Allocate a scratch register and write to it using the gfx ring (CIK). 1527 + * Provides a basic gfx ring test to verify that the ring is working. 1528 + * Used by cik_cp_gfx_resume(); 1529 + * Returns 0 on success, error on failure. 1530 + */ 1531 + int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 1532 + { 1533 + uint32_t scratch; 1534 + uint32_t tmp = 0; 1535 + unsigned i; 1536 + int r; 1537 + 1538 + r = radeon_scratch_get(rdev, &scratch); 1539 + if (r) { 1540 + DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 1541 + return r; 1542 + } 1543 + WREG32(scratch, 0xCAFEDEAD); 1544 + r = radeon_ring_lock(rdev, ring, 3); 1545 + if (r) { 1546 + DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 1547 + radeon_scratch_free(rdev, scratch); 1548 + return r; 1549 + } 1550 + radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1551 + radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); 1552 + radeon_ring_write(ring, 0xDEADBEEF); 1553 + radeon_ring_unlock_commit(rdev, ring); 1554 + for (i = 0; i < rdev->usec_timeout; i++) { 1555 + tmp = RREG32(scratch); 1556 + if (tmp == 0xDEADBEEF) 1557 + break; 1558 + DRM_UDELAY(1); 1559 + } 1560 + if (i < rdev->usec_timeout) { 1561 + DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1562 + } else { 1563 + DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 1564 + ring->idx, scratch, tmp); 1565 + r = -EINVAL; 1566 + } 1567 + radeon_scratch_free(rdev, scratch); 1568 + return r; 1569 + } 1570 + 1571 + /** 1521 1572 * cik_fence_ring_emit - emit a fence on the gfx ring 1522 1573 * 1523 1574 * @rdev: radeon_device pointer ··· 1675 1624 (ib->gpu_addr & 0xFFFFFFFC)); 1676 1625 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1677 1626 radeon_ring_write(ring, control); 1627 + } 1628 + 1629 + /** 1630 + * cik_ib_test - basic gfx ring IB test 1631 + * 1632 + * @rdev: radeon_device pointer 1633 + * @ring: radeon_ring structure holding ring information 1634 + * 1635 + * Allocate an IB and execute it on the gfx ring (CIK). 1636 + * Provides a basic gfx ring test to verify that IBs are working. 1637 + * Returns 0 on success, error on failure. 1638 + */ 1639 + int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 1640 + { 1641 + struct radeon_ib ib; 1642 + uint32_t scratch; 1643 + uint32_t tmp = 0; 1644 + unsigned i; 1645 + int r; 1646 + 1647 + r = radeon_scratch_get(rdev, &scratch); 1648 + if (r) { 1649 + DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 1650 + return r; 1651 + } 1652 + WREG32(scratch, 0xCAFEDEAD); 1653 + r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 1654 + if (r) { 1655 + DRM_ERROR("radeon: failed to get ib (%d).\n", r); 1656 + return r; 1657 + } 1658 + ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 1659 + ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2); 1660 + ib.ptr[2] = 0xDEADBEEF; 1661 + ib.length_dw = 3; 1662 + r = radeon_ib_schedule(rdev, &ib, NULL); 1663 + if (r) { 1664 + radeon_scratch_free(rdev, scratch); 1665 + radeon_ib_free(rdev, &ib); 1666 + DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 1667 + return r; 1668 + } 1669 + r = radeon_fence_wait(ib.fence, false); 1670 + if (r) { 1671 + DRM_ERROR("radeon: fence wait failed (%d).\n", r); 1672 + return r; 1673 + } 1674 + for (i = 0; i < rdev->usec_timeout; i++) { 1675 + tmp = RREG32(scratch); 1676 + if (tmp == 0xDEADBEEF) 1677 + break; 1678 + DRM_UDELAY(1); 1679 + } 1680 + if (i < rdev->usec_timeout) { 1681 + DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 1682 + } else { 1683 + DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 1684 + scratch, tmp); 1685 + r = -EINVAL; 1686 + } 1687 + radeon_scratch_free(rdev, scratch); 1688 + radeon_ib_free(rdev, &ib); 1689 + return r; 1678 1690 } 1679 1691 1680 1692 /*

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