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drm/amd/display: Add NULL check for integrated_info in clk_mgr_construct

clk_mgr_construct() initializes display clock and memory bandwidth
settings during driver bring-up.

As part of this, the driver selects a watermark table based on the
memory type (DDR4, LPDDR4, LPDDR5) from ctx->dc_bios->integrated_info.

The display pipeline continuously reads pixel data from memory,
processes it (such as scaling, color conversion, and blending), and
sends it to the screen. To keep this pipeline running smoothly, the
driver must ensure there is enough memory bandwidth and that clocks are
increased when needed.

Watermark tables define when the GPU should increase clocks to ensure
there is enough bandwidth to feed pixel data without underflow.

However, ctx->dc_bios->integrated_info is dereferenced without checking
for NULL in multiple clk_mgr_construct() implementations. On some
platforms, BIOS may not provide this information, and accessing it
directly can cause a NULL pointer dereference during initialization.

Fix this by adding a NULL check before accessing integrated_info.

If integrated_info is not available, the driver safely falls back to
default watermark tables.

Fixes:
../dcn21/rn_clk_mgr.c:775 rn_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 743)
../dcn301/vg_clk_mgr.c:750 vg_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 736)
../dcn31/dcn31_clk_mgr.c:789 dcn31_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 728)
../dcn314/dcn314_clk_mgr.c:906 dcn314_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 845)
../dcn315/dcn315_clk_mgr.c:716 dcn315_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 655)
../dcn316/dcn316_clk_mgr.c:660 dcn316_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 639)
../dcn35/dcn35_clk_mgr.c:1540 dcn35_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 1467)

Fixes: 25879d7b4986 ("drm/amd/display: Clean FPGA code in dc")
Cc: Roman Li <roman.li@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Tom Chung <chiahsuan.chung@amd.com>
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Srinivasan Shanmugam and committed by
Alex Deucher fbe3a574 4ae3e16f

+24 -17
+2 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
··· 740 740 if (clk_mgr->base.dentist_vco_freq_khz == 0) 741 741 clk_mgr->base.dentist_vco_freq_khz = 3600000; 742 742 743 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { 743 + if (ctx->dc_bios->integrated_info && 744 + ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { 744 745 if (clk_mgr->periodic_retraining_disabled) { 745 746 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; 746 747 } else {
+4 -3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
··· 733 733 if (clk_mgr->base.base.dentist_vco_freq_khz == 0) 734 734 clk_mgr->base.base.dentist_vco_freq_khz = 3600000; 735 735 736 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 736 + if (ctx->dc_bios->integrated_info && 737 + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 737 738 vg_bw_params.wm_table = lpddr5_wm_table; 738 - } else { 739 + else 739 740 vg_bw_params.wm_table = ddr4_wm_table; 740 - } 741 + 741 742 /* Saved clocks configured at boot for debug purposes */ 742 743 vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); 743 744
+4 -3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
··· 725 725 /* TODO: Check we get what we expect during bringup */ 726 726 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 727 727 728 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 728 + if (ctx->dc_bios->integrated_info && 729 + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 729 730 dcn31_bw_params.wm_table = lpddr5_wm_table; 730 - } else { 731 + else 731 732 dcn31_bw_params.wm_table = ddr5_wm_table; 732 - } 733 + 733 734 /* Saved clocks configured at boot for debug purposes */ 734 735 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, 735 736 &clk_mgr->base.base, &log_info);
+2 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
··· 842 842 /* TODO: Check we get what we expect during bringup */ 843 843 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 844 844 845 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 845 + if (ctx->dc_bios->integrated_info && 846 + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 846 847 dcn314_bw_params.wm_table = lpddr5_wm_table; 847 848 else 848 849 dcn314_bw_params.wm_table = ddr5_wm_table;
+4 -3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
··· 652 652 if (clk_mgr->base.smu_ver > 0) 653 653 clk_mgr->base.smu_present = true; 654 654 655 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 655 + if (ctx->dc_bios->integrated_info && 656 + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 656 657 dcn315_bw_params.wm_table = lpddr5_wm_table; 657 - } else { 658 + else 658 659 dcn315_bw_params.wm_table = ddr5_wm_table; 659 - } 660 + 660 661 /* Saved clocks configured at boot for debug purposes */ 661 662 dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, 662 663 &clk_mgr->base.base, &log_info);
+4 -3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
··· 636 636 clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */ 637 637 638 638 639 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 639 + if (ctx->dc_bios->integrated_info && 640 + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 640 641 dcn316_bw_params.wm_table = lpddr5_wm_table; 641 - } else { 642 + else 642 643 dcn316_bw_params.wm_table = ddr4_wm_table; 643 - } 644 + 644 645 /* Saved clocks configured at boot for debug purposes */ 645 646 dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, 646 647 &clk_mgr->base.base, &log_info);
+4 -3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
··· 1464 1464 /* TODO: Check we get what we expect during bringup */ 1465 1465 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 1466 1466 1467 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 1467 + if (ctx->dc_bios->integrated_info && 1468 + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 1468 1469 dcn35_bw_params.wm_table = lpddr5_wm_table; 1469 - } else { 1470 + else 1470 1471 dcn35_bw_params.wm_table = ddr5_wm_table; 1471 - } 1472 + 1472 1473 /* Saved clocks configured at boot for debug purposes */ 1473 1474 dcn35_save_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); 1474 1475