Merge tag 'reset-for-v7.1' of https://git.pengutronix.de/git/pza/linux into soc/drivers

+8 -1

Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml

··· 17 17 compatible: 18 18 oneOf: 19 19 - items: 20 - - const: renesas,r9a09g056-usb2phy-reset # RZ/V2N 20 + - enum: 21 + - renesas,r9a09g047-usb2phy-reset # RZ/G3E 22 + - renesas,r9a09g056-usb2phy-reset # RZ/V2N 21 23 - const: renesas,r9a09g057-usb2phy-reset 22 24 23 25 - const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P) ··· 39 37 '#reset-cells': 40 38 const: 0 41 39 40 + '#mux-state-cells': 41 + const: 1 42 + 42 43 required: 43 44 - compatible 44 45 - reg ··· 49 44 - resets 50 45 - power-domains 51 46 - '#reset-cells' 47 + - '#mux-state-cells' 52 48 53 49 additionalProperties: false 54 50 ··· 64 58 resets = <&cpg 0xaf>; 65 59 power-domains = <&cpg>; 66 60 #reset-cells = <0>; 61 + #mux-state-cells = <1>; 67 62 };

+42

Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Cix Sky1 SoC system control register region 8 + 9 + maintainers: 10 + - Gary Yang <gary.yang@cixtech.com> 11 + 12 + description: 13 + An wide assortment of registers of the system controller on Sky1 SoC, 14 + including resets, usb, wakeup sources and so on. 15 + 16 + properties: 17 + compatible: 18 + items: 19 + - enum: 20 + - cix,sky1-system-control 21 + - cix,sky1-s5-system-control 22 + - const: syscon 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + '#reset-cells': 28 + const: 1 29 + 30 + required: 31 + - compatible 32 + - reg 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + syscon@4160000 { 39 + compatible = "cix,sky1-system-control", "syscon"; 40 + reg = <0x4160000 0x100>; 41 + #reset-cells = <1>; 42 + };

-1

Documentation/driver-api/reset.rst

··· 198 198 reset_control_rearm 199 199 reset_control_put 200 200 of_reset_control_get_count 201 - of_reset_control_array_get 202 201 devm_reset_control_array_get 203 202 reset_control_get_count 204 203

+9

drivers/reset/Kconfig

··· 257 257 config RESET_RZV2H_USB2PHY 258 258 tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" 259 259 depends on ARCH_RENESAS || COMPILE_TEST 260 + select AUXILIARY_BUS 261 + select REGMAP_MMIO 260 262 help 261 263 Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC 262 264 (and similar SoCs). ··· 292 290 - Allwinner SoCs 293 291 - SiFive FU740 SoCs 294 292 - Sophgo SoCs 293 + 294 + config RESET_SKY1 295 + bool "Cix Sky1 reset controller" 296 + depends on ARCH_CIX || COMPILE_TEST 297 + select REGMAP_MMIO 298 + help 299 + This enables the reset controller for Cix Sky1. 295 300 296 301 config RESET_SOCFPGA 297 302 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)

+1

drivers/reset/Makefile

··· 38 38 obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o 39 39 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o 40 40 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o 41 + obj-$(CONFIG_RESET_SKY1) += reset-sky1.o 41 42 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o 42 43 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o 43 44 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o

+342 -176

drivers/reset/core.c

··· 12 12 #include <linux/device.h> 13 13 #include <linux/err.h> 14 14 #include <linux/export.h> 15 + #include <linux/fwnode.h> 15 16 #include <linux/gpio/driver.h> 16 17 #include <linux/gpio/machine.h> 17 18 #include <linux/gpio/property.h> ··· 21 20 #include <linux/kref.h> 22 21 #include <linux/module.h> 23 22 #include <linux/of.h> 23 + #include <linux/property.h> 24 24 #include <linux/reset.h> 25 25 #include <linux/reset-controller.h> 26 26 #include <linux/slab.h> 27 + #include <linux/srcu.h> 27 28 28 29 static DEFINE_MUTEX(reset_list_mutex); 29 30 static LIST_HEAD(reset_controller_list); ··· 39 36 * struct reset_control - a reset control 40 37 * @rcdev: a pointer to the reset controller device 41 38 * this reset control belongs to 39 + * @srcu: protects the rcdev pointer from removal during consumer access 42 40 * @list: list entry for the rcdev's reset controller list 43 41 * @id: ID of the reset controller in the reset 44 42 * controller device ··· 51 47 * @triggered_count: Number of times this reset line has been reset. Currently 52 48 * only used for shared resets, which means that the value 53 49 * will be either 0 or 1. 50 + * @lock: serializes the internals of reset_control_acquire() 54 51 */ 55 52 struct reset_control { 56 - struct reset_controller_dev *rcdev; 53 + struct reset_controller_dev __rcu *rcdev; 54 + struct srcu_struct srcu; 57 55 struct list_head list; 58 56 unsigned int id; 59 57 struct kref refcnt; ··· 64 58 bool array; 65 59 atomic_t deassert_count; 66 60 atomic_t triggered_count; 61 + struct mutex lock; 67 62 }; 68 63 69 64 /** ··· 81 74 82 75 /** 83 76 * struct reset_gpio_lookup - lookup key for ad-hoc created reset-gpio devices 84 - * @of_args: phandle to the reset controller with all the args like GPIO number 77 + * @ref_args: Reference to the reset controller with all the args like GPIO number 85 78 * @swnode: Software node containing the reference to the GPIO provider 86 79 * @list: list entry for the reset_gpio_lookup_list 80 + * @adev: Auxiliary device representing the reset controller 87 81 */ 88 82 struct reset_gpio_lookup { 89 - struct of_phandle_args of_args; 83 + struct fwnode_reference_args ref_args; 90 84 struct fwnode_handle *swnode; 91 85 struct list_head list; 86 + struct auxiliary_device adev; 92 87 }; 93 88 94 89 static const char *rcdev_name(struct reset_controller_dev *rcdev) ··· 98 89 if (rcdev->dev) 99 90 return dev_name(rcdev->dev); 100 91 101 - if (rcdev->of_node) 102 - return rcdev->of_node->full_name; 103 - 104 - if (rcdev->of_args) 105 - return rcdev->of_args->np->full_name; 92 + if (rcdev->fwnode) 93 + return fwnode_get_name(rcdev->fwnode); 106 94 107 95 return NULL; 108 96 } 109 97 110 98 /** 111 - * of_reset_simple_xlate - translate reset_spec to the reset line number 99 + * fwnode_reset_simple_xlate - translate reset_spec to the reset line number 112 100 * @rcdev: a pointer to the reset controller device 113 - * @reset_spec: reset line specifier as found in the device tree 101 + * @reset_spec: reset line specifier as found in firmware 114 102 * 115 - * This static translation function is used by default if of_xlate in 116 - * :c:type:`reset_controller_dev` is not set. It is useful for all reset 117 - * controllers with 1:1 mapping, where reset lines can be indexed by number 118 - * without gaps. 103 + * This static translation function is used by default if neither fwnode_xlate 104 + * not of_xlate in :c:type:`reset_controller_dev` is not set. It is useful for 105 + * all reset controllers with 1:1 mapping, where reset lines can be indexed by 106 + * number without gaps. 119 107 */ 120 - static int of_reset_simple_xlate(struct reset_controller_dev *rcdev, 121 - const struct of_phandle_args *reset_spec) 108 + static int fwnode_reset_simple_xlate(struct reset_controller_dev *rcdev, 109 + const struct fwnode_reference_args *reset_spec) 122 110 { 123 111 if (reset_spec->args[0] >= rcdev->nr_resets) 124 112 return -EINVAL; ··· 129 123 */ 130 124 int reset_controller_register(struct reset_controller_dev *rcdev) 131 125 { 132 - if (rcdev->of_node && rcdev->of_args) 126 + if ((rcdev->of_node && rcdev->fwnode) || (rcdev->of_xlate && rcdev->fwnode_xlate)) 133 127 return -EINVAL; 134 128 135 - if (!rcdev->of_xlate) { 136 - rcdev->of_reset_n_cells = 1; 137 - rcdev->of_xlate = of_reset_simple_xlate; 129 + if (rcdev->of_node && !rcdev->fwnode) 130 + rcdev->fwnode = of_fwnode_handle(rcdev->of_node); 131 + 132 + if (!rcdev->fwnode) { 133 + rcdev->fwnode = dev_fwnode(rcdev->dev); 134 + if (!rcdev->fwnode) 135 + return -EINVAL; 136 + } 137 + 138 + if (rcdev->of_xlate) 139 + rcdev->fwnode_reset_n_cells = rcdev->of_reset_n_cells; 140 + 141 + if (!rcdev->fwnode_xlate && !rcdev->of_xlate) { 142 + rcdev->fwnode_xlate = fwnode_reset_simple_xlate; 143 + rcdev->fwnode_reset_n_cells = 1; 138 144 } 139 145 140 146 INIT_LIST_HEAD(&rcdev->reset_control_head); 147 + mutex_init(&rcdev->lock); 141 148 142 - mutex_lock(&reset_list_mutex); 149 + guard(mutex)(&reset_list_mutex); 150 + 143 151 list_add(&rcdev->list, &reset_controller_list); 144 - mutex_unlock(&reset_list_mutex); 145 152 146 153 return 0; 147 154 } 148 155 EXPORT_SYMBOL_GPL(reset_controller_register); 156 + 157 + static void reset_controller_remove(struct reset_controller_dev *rcdev, 158 + struct reset_control *rstc) 159 + { 160 + lockdep_assert_held(&rcdev->lock); 161 + 162 + list_del(&rstc->list); 163 + module_put(rcdev->owner); 164 + put_device(rcdev->dev); 165 + } 149 166 150 167 /** 151 168 * reset_controller_unregister - unregister a reset controller device ··· 176 147 */ 177 148 void reset_controller_unregister(struct reset_controller_dev *rcdev) 178 149 { 179 - mutex_lock(&reset_list_mutex); 180 - list_del(&rcdev->list); 181 - mutex_unlock(&reset_list_mutex); 150 + struct reset_control *rstc, *pos; 151 + 152 + scoped_guard(mutex, &reset_list_mutex) 153 + list_del(&rcdev->list); 154 + 155 + scoped_guard(mutex, &rcdev->lock) { 156 + /* 157 + * Numb but don't free the remaining reset control handles that are 158 + * still held by consumers. 159 + */ 160 + list_for_each_entry_safe(rstc, pos, &rcdev->reset_control_head, list) { 161 + rcu_assign_pointer(rstc->rcdev, NULL); 162 + synchronize_srcu(&rstc->srcu); 163 + reset_controller_remove(rcdev, rstc); 164 + } 165 + } 166 + 167 + mutex_destroy(&rcdev->lock); 182 168 } 183 169 EXPORT_SYMBOL_GPL(reset_controller_unregister); 184 170 ··· 370 326 */ 371 327 int reset_control_reset(struct reset_control *rstc) 372 328 { 329 + struct reset_controller_dev *rcdev; 373 330 int ret; 374 331 375 332 if (!rstc) ··· 382 337 if (reset_control_is_array(rstc)) 383 338 return reset_control_array_reset(rstc_to_array(rstc)); 384 339 385 - if (!rstc->rcdev->ops->reset) 340 + guard(srcu)(&rstc->srcu); 341 + 342 + rcdev = srcu_dereference(rstc->rcdev, &rstc->srcu); 343 + if (!rcdev) 344 + return -ENODEV; 345 + 346 + if (!rcdev->ops->reset) 386 347 return -ENOTSUPP; 387 348 388 349 if (rstc->shared) { ··· 402 351 return -EPERM; 403 352 } 404 353 405 - ret = rstc->rcdev->ops->reset(rstc->rcdev, rstc->id); 354 + ret = rcdev->ops->reset(rcdev, rstc->id); 406 355 if (rstc->shared && ret) 407 356 atomic_dec(&rstc->triggered_count); 408 357 ··· 435 384 EXPORT_SYMBOL_GPL(reset_control_bulk_reset); 436 385 437 386 /** 438 - * reset_control_rearm - allow shared reset line to be re-triggered" 387 + * reset_control_rearm - allow shared reset line to be re-triggered 439 388 * @rstc: reset controller 440 389 * 441 390 * On a shared reset line the actual reset pulse is only triggered once for the ··· 492 441 */ 493 442 int reset_control_assert(struct reset_control *rstc) 494 443 { 444 + struct reset_controller_dev *rcdev; 445 + 495 446 if (!rstc) 496 447 return 0; 497 448 ··· 502 449 503 450 if (reset_control_is_array(rstc)) 504 451 return reset_control_array_assert(rstc_to_array(rstc)); 452 + 453 + guard(srcu)(&rstc->srcu); 454 + 455 + rcdev = srcu_dereference(rstc->rcdev, &rstc->srcu); 456 + if (!rcdev) 457 + return -ENODEV; 505 458 506 459 if (rstc->shared) { 507 460 if (WARN_ON(atomic_read(&rstc->triggered_count) != 0)) ··· 523 464 * Shared reset controls allow the reset line to be in any state 524 465 * after this call, so doing nothing is a valid option. 525 466 */ 526 - if (!rstc->rcdev->ops->assert) 467 + if (!rcdev->ops->assert) 527 468 return 0; 528 469 } else { 529 470 /* ··· 531 472 * is no way to guarantee that the reset line is asserted after 532 473 * this call. 533 474 */ 534 - if (!rstc->rcdev->ops->assert) 475 + if (!rcdev->ops->assert) 535 476 return -ENOTSUPP; 536 477 537 478 if (!rstc->acquired) { 538 479 WARN(1, "reset %s (ID: %u) is not acquired\n", 539 - rcdev_name(rstc->rcdev), rstc->id); 480 + rcdev_name(rcdev), rstc->id); 540 481 return -EPERM; 541 482 } 542 483 } 543 484 544 - return rstc->rcdev->ops->assert(rstc->rcdev, rstc->id); 485 + return rcdev->ops->assert(rcdev, rstc->id); 545 486 } 546 487 EXPORT_SYMBOL_GPL(reset_control_assert); 547 488 ··· 588 529 */ 589 530 int reset_control_deassert(struct reset_control *rstc) 590 531 { 532 + struct reset_controller_dev *rcdev; 533 + 591 534 if (!rstc) 592 535 return 0; 593 536 ··· 598 537 599 538 if (reset_control_is_array(rstc)) 600 539 return reset_control_array_deassert(rstc_to_array(rstc)); 540 + 541 + guard(srcu)(&rstc->srcu); 542 + 543 + rcdev = srcu_dereference(rstc->rcdev, &rstc->srcu); 544 + if (!rcdev) 545 + return -ENODEV; 601 546 602 547 if (rstc->shared) { 603 548 if (WARN_ON(atomic_read(&rstc->triggered_count) != 0)) ··· 614 547 } else { 615 548 if (!rstc->acquired) { 616 549 WARN(1, "reset %s (ID: %u) is not acquired\n", 617 - rcdev_name(rstc->rcdev), rstc->id); 550 + rcdev_name(rcdev), rstc->id); 618 551 return -EPERM; 619 552 } 620 553 } ··· 626 559 * case, the reset controller driver should implement .deassert() and 627 560 * return -ENOTSUPP. 628 561 */ 629 - if (!rstc->rcdev->ops->deassert) 562 + if (!rcdev->ops->deassert) 630 563 return 0; 631 564 632 - return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->id); 565 + return rcdev->ops->deassert(rcdev, rstc->id); 633 566 } 634 567 EXPORT_SYMBOL_GPL(reset_control_deassert); 635 568 ··· 671 604 */ 672 605 int reset_control_status(struct reset_control *rstc) 673 606 { 607 + struct reset_controller_dev *rcdev; 608 + 674 609 if (!rstc) 675 610 return 0; 676 611 677 612 if (WARN_ON(IS_ERR(rstc)) || reset_control_is_array(rstc)) 678 613 return -EINVAL; 679 614 680 - if (rstc->rcdev->ops->status) 681 - return rstc->rcdev->ops->status(rstc->rcdev, rstc->id); 615 + guard(srcu)(&rstc->srcu); 616 + 617 + rcdev = srcu_dereference(rstc->rcdev, &rstc->srcu); 618 + if (!rcdev) 619 + return -ENODEV; 620 + 621 + if (rcdev->ops->status) 622 + return rcdev->ops->status(rcdev, rstc->id); 682 623 683 624 return -ENOTSUPP; 684 625 } ··· 714 639 */ 715 640 int reset_control_acquire(struct reset_control *rstc) 716 641 { 642 + struct reset_controller_dev *rcdev; 717 643 struct reset_control *rc; 718 644 719 645 if (!rstc) ··· 726 650 if (reset_control_is_array(rstc)) 727 651 return reset_control_array_acquire(rstc_to_array(rstc)); 728 652 729 - mutex_lock(&reset_list_mutex); 653 + guard(mutex)(&rstc->lock); 730 654 731 - if (rstc->acquired) { 732 - mutex_unlock(&reset_list_mutex); 655 + if (rstc->acquired) 733 656 return 0; 734 - } 735 657 736 - list_for_each_entry(rc, &rstc->rcdev->reset_control_head, list) { 737 - if (rstc != rc && rstc->id == rc->id) { 738 - if (rc->acquired) { 739 - mutex_unlock(&reset_list_mutex); 740 - return -EBUSY; 658 + guard(srcu)(&rstc->srcu); 659 + 660 + rcdev = srcu_dereference(rstc->rcdev, &rstc->srcu); 661 + if (!rcdev) 662 + return -ENODEV; 663 + 664 + scoped_guard(mutex, &rcdev->lock) { 665 + list_for_each_entry(rc, &rcdev->reset_control_head, list) { 666 + if (rstc != rc && rstc->id == rc->id) { 667 + if (rc->acquired) 668 + return -EBUSY; 741 669 } 742 670 } 743 671 } 744 672 745 673 rstc->acquired = true; 746 674 747 - mutex_unlock(&reset_list_mutex); 748 675 return 0; 749 676 } 750 677 EXPORT_SYMBOL_GPL(reset_control_acquire); ··· 831 752 bool shared = flags & RESET_CONTROL_FLAGS_BIT_SHARED; 832 753 bool acquired = flags & RESET_CONTROL_FLAGS_BIT_ACQUIRED; 833 754 struct reset_control *rstc; 755 + int ret; 834 756 835 - lockdep_assert_held(&reset_list_mutex); 757 + lockdep_assert_held(&rcdev->lock); 836 758 837 759 /* Expect callers to filter out OPTIONAL and DEASSERTED bits */ 838 760 if (WARN_ON(flags & ~(RESET_CONTROL_FLAGS_BIT_SHARED | ··· 862 782 if (!rstc) 863 783 return ERR_PTR(-ENOMEM); 864 784 785 + ret = init_srcu_struct(&rstc->srcu); 786 + if (ret) { 787 + kfree(rstc); 788 + return ERR_PTR(ret); 789 + } 790 + 865 791 if (!try_module_get(rcdev->owner)) { 792 + cleanup_srcu_struct(&rstc->srcu); 866 793 kfree(rstc); 867 794 return ERR_PTR(-ENODEV); 868 795 } 869 796 870 - rstc->rcdev = rcdev; 797 + rcu_assign_pointer(rstc->rcdev, rcdev); 871 798 list_add(&rstc->list, &rcdev->reset_control_head); 872 799 rstc->id = index; 873 800 kref_init(&rstc->refcnt); 801 + mutex_init(&rstc->lock); 874 802 rstc->acquired = acquired; 875 803 rstc->shared = shared; 876 804 get_device(rcdev->dev); ··· 890 802 { 891 803 struct reset_control *rstc = container_of(kref, struct reset_control, 892 804 refcnt); 805 + struct reset_controller_dev *rcdev; 893 806 894 - lockdep_assert_held(&reset_list_mutex); 807 + lockdep_assert_held(&rstc->srcu); 895 808 896 - module_put(rstc->rcdev->owner); 809 + rcdev = rcu_replace_pointer(rstc->rcdev, NULL, true); 810 + if (rcdev) { 811 + lockdep_assert_held(&rcdev->lock); 812 + reset_controller_remove(rcdev, rstc); 813 + } 897 814 898 - list_del(&rstc->list); 899 - put_device(rstc->rcdev->dev); 900 - kfree(rstc); 815 + mutex_destroy(&rstc->lock); 901 816 } 902 817 903 - static void __reset_control_put_internal(struct reset_control *rstc) 818 + static void reset_control_put_internal(struct reset_control *rstc) 904 819 { 905 - lockdep_assert_held(&reset_list_mutex); 820 + struct reset_controller_dev *rcdev; 821 + int ret = 0; 906 822 907 823 if (IS_ERR_OR_NULL(rstc)) 908 824 return; 909 825 910 - kref_put(&rstc->refcnt, __reset_control_release); 826 + scoped_guard(srcu, &rstc->srcu) { 827 + rcdev = srcu_dereference(rstc->rcdev, &rstc->srcu); 828 + if (!rcdev) 829 + /* Already released. */ 830 + return; 831 + 832 + guard(mutex)(&rcdev->lock); 833 + ret = kref_put(&rstc->refcnt, __reset_control_release); 834 + } 835 + 836 + if (ret) { 837 + synchronize_srcu(&rstc->srcu); 838 + cleanup_srcu_struct(&rstc->srcu); 839 + kfree(rstc); 840 + } 911 841 } 912 842 913 843 static void reset_gpio_aux_device_release(struct device *dev) 914 844 { 915 - struct auxiliary_device *adev = to_auxiliary_dev(dev); 916 - 917 - kfree(adev); 845 + WARN(1, "reset-gpio device %s should never have been removed", dev_name(dev)); 918 846 } 919 847 920 - static int reset_add_gpio_aux_device(struct device *parent, 921 - struct fwnode_handle *swnode, 922 - int id, void *pdata) 848 + static int reset_create_gpio_aux_device(struct reset_gpio_lookup *rgpio_dev, 849 + struct device *parent) 923 850 { 924 - struct auxiliary_device *adev; 925 - int ret; 851 + struct auxiliary_device *adev = &rgpio_dev->adev; 852 + int ret, id; 926 853 927 - adev = kzalloc_obj(*adev); 928 - if (!adev) 854 + id = ida_alloc(&reset_gpio_ida, GFP_KERNEL); 855 + if (id < 0) 929 856 return -ENOMEM; 930 857 931 858 adev->id = id; 932 859 adev->name = "gpio"; 933 860 adev->dev.parent = parent; 934 - adev->dev.platform_data = pdata; 861 + adev->dev.platform_data = &rgpio_dev->ref_args; 935 862 adev->dev.release = reset_gpio_aux_device_release; 936 - device_set_node(&adev->dev, swnode); 863 + device_set_node(&adev->dev, rgpio_dev->swnode); 937 864 938 865 ret = auxiliary_device_init(adev); 939 866 if (ret) { 940 - kfree(adev); 867 + ida_free(&reset_gpio_ida, id); 941 868 return ret; 942 869 } 943 870 944 871 ret = __auxiliary_device_add(adev, "reset"); 945 872 if (ret) { 946 873 auxiliary_device_uninit(adev); 947 - kfree(adev); 874 + ida_free(&reset_gpio_ida, id); 948 875 return ret; 949 876 } 950 877 951 - return ret; 878 + return 0; 879 + } 880 + 881 + static void reset_gpio_add_devlink(struct fwnode_handle *fwnode, 882 + struct reset_gpio_lookup *rgpio_dev) 883 + { 884 + struct device *consumer; 885 + 886 + /* 887 + * We must use get_dev_from_fwnode() and not ref_find_device_by_node() 888 + * because the latter only considers the platform bus while we want to 889 + * get consumers of any kind that can be associated with firmware 890 + * nodes: auxiliary, soundwire, etc. 891 + */ 892 + consumer = get_dev_from_fwnode(fwnode); 893 + if (consumer) { 894 + if (!device_link_add(consumer, &rgpio_dev->adev.dev, 895 + DL_FLAG_AUTOREMOVE_CONSUMER)) 896 + pr_warn("Failed to create a device link between reset-gpio and its consumer"); 897 + 898 + put_device(consumer); 899 + } 900 + /* 901 + * else { } 902 + * 903 + * TODO: If ever there's a case where we need to support shared 904 + * reset-gpios retrieved from a device node for which there's no 905 + * device present yet, this is where we'd set up a notifier waiting 906 + * for the device to appear in the system. This would be a lot of code 907 + * that would go unused for now so let's cross that bridge when and if 908 + * we get there. 909 + */ 910 + } 911 + 912 + /* TODO: move it out into drivers/base/ */ 913 + static bool fwnode_reference_args_equal(const struct fwnode_reference_args *left, 914 + const struct fwnode_reference_args *right) 915 + { 916 + return left->fwnode == right->fwnode && left->nargs == right->nargs && 917 + !memcmp(left->args, right->args, sizeof(left->args[0]) * left->nargs); 952 918 } 953 919 954 920 /* 955 - * @args: phandle to the GPIO provider with all the args like GPIO number 921 + * @np: OF-node associated with the consumer 922 + * @args: Reference to the GPIO provider with all the args like GPIO number 956 923 */ 957 - static int __reset_add_reset_gpio_device(const struct of_phandle_args *args) 924 + static int __reset_add_reset_gpio_device(struct fwnode_handle *fwnode, 925 + const struct fwnode_reference_args *args) 958 926 { 959 927 struct property_entry properties[3] = { }; 960 - unsigned int offset, of_flags, lflags; 928 + unsigned int offset, flags, lflags; 961 929 struct reset_gpio_lookup *rgpio_dev; 962 930 struct device *parent; 963 - int id, ret, prop = 0; 931 + int ret, prop = 0; 964 932 965 933 /* 966 934 * Currently only #gpio-cells=2 is supported with the meaning of: ··· 1024 880 * args[1]: GPIO flags 1025 881 * TODO: Handle other cases. 1026 882 */ 1027 - if (args->args_count != 2) 883 + if (args->nargs != 2) 1028 884 return -ENOENT; 1029 885 1030 886 /* ··· 1035 891 lockdep_assert_not_held(&reset_list_mutex); 1036 892 1037 893 offset = args->args[0]; 1038 - of_flags = args->args[1]; 894 + flags = args->args[1]; 1039 895 1040 896 /* 1041 897 * Later we map GPIO flags between OF and Linux, however not all ··· 1045 901 * FIXME: Find a better way of translating OF flags to GPIO lookup 1046 902 * flags. 1047 903 */ 1048 - if (of_flags > GPIO_ACTIVE_LOW) { 904 + if (flags > GPIO_ACTIVE_LOW) { 1049 905 pr_err("reset-gpio code does not support GPIO flags %u for GPIO %u\n", 1050 - of_flags, offset); 906 + flags, offset); 1051 907 return -EINVAL; 1052 908 } 1053 909 1054 910 struct gpio_device *gdev __free(gpio_device_put) = 1055 - gpio_device_find_by_fwnode(of_fwnode_handle(args->np)); 911 + gpio_device_find_by_fwnode(args->fwnode); 1056 912 if (!gdev) 1057 913 return -EPROBE_DEFER; 1058 914 1059 915 guard(mutex)(&reset_gpio_lookup_mutex); 1060 916 1061 917 list_for_each_entry(rgpio_dev, &reset_gpio_lookup_list, list) { 1062 - if (args->np == rgpio_dev->of_args.np) { 1063 - if (of_phandle_args_equal(args, &rgpio_dev->of_args)) 1064 - return 0; /* Already on the list, done */ 918 + if (fwnode_reference_args_equal(args, &rgpio_dev->ref_args)) { 919 + /* 920 + * Already on the list, create the device link 921 + * and stop here. 922 + */ 923 + reset_gpio_add_devlink(fwnode, rgpio_dev); 924 + return 0; 1065 925 } 1066 926 } 1067 927 1068 - lflags = GPIO_PERSISTENT | (of_flags & GPIO_ACTIVE_LOW); 928 + lflags = GPIO_PERSISTENT | (flags & GPIO_ACTIVE_LOW); 1069 929 parent = gpio_device_to_device(gdev); 1070 930 properties[prop++] = PROPERTY_ENTRY_STRING("compatible", "reset-gpio"); 1071 931 properties[prop++] = PROPERTY_ENTRY_GPIO("reset-gpios", parent->fwnode, offset, lflags); 1072 932 1073 - id = ida_alloc(&reset_gpio_ida, GFP_KERNEL); 1074 - if (id < 0) 1075 - return id; 1076 - 1077 933 /* Not freed on success, because it is persisent subsystem data. */ 1078 934 rgpio_dev = kzalloc_obj(*rgpio_dev); 1079 - if (!rgpio_dev) { 1080 - ret = -ENOMEM; 1081 - goto err_ida_free; 1082 - } 935 + if (!rgpio_dev) 936 + return -ENOMEM; 1083 937 1084 - rgpio_dev->of_args = *args; 938 + rgpio_dev->ref_args = *args; 1085 939 /* 1086 - * We keep the device_node reference, but of_args.np is put at the end 1087 - * of __of_reset_control_get(), so get it one more time. 940 + * We keep the fwnode_handle reference, but ref_args.fwnode is put at 941 + * the end of __fwnode_reset_control_get(), so get it one more time. 1088 942 * Hold reference as long as rgpio_dev memory is valid. 1089 943 */ 1090 - of_node_get(rgpio_dev->of_args.np); 944 + fwnode_handle_get(rgpio_dev->ref_args.fwnode); 1091 945 1092 946 rgpio_dev->swnode = fwnode_create_software_node(properties, NULL); 1093 947 if (IS_ERR(rgpio_dev->swnode)) { 1094 948 ret = PTR_ERR(rgpio_dev->swnode); 1095 - goto err_put_of_node; 949 + goto err_put_fwnode; 1096 950 } 1097 951 1098 - ret = reset_add_gpio_aux_device(parent, rgpio_dev->swnode, id, 1099 - &rgpio_dev->of_args); 952 + ret = reset_create_gpio_aux_device(rgpio_dev, parent); 1100 953 if (ret) 1101 954 goto err_del_swnode; 1102 955 956 + reset_gpio_add_devlink(fwnode, rgpio_dev); 1103 957 list_add(&rgpio_dev->list, &reset_gpio_lookup_list); 1104 958 1105 959 return 0; 1106 960 1107 961 err_del_swnode: 1108 962 fwnode_remove_software_node(rgpio_dev->swnode); 1109 - err_put_of_node: 1110 - of_node_put(rgpio_dev->of_args.np); 963 + err_put_fwnode: 964 + fwnode_handle_put(rgpio_dev->ref_args.fwnode); 1111 965 kfree(rgpio_dev); 1112 - err_ida_free: 1113 - ida_free(&reset_gpio_ida, id); 1114 966 1115 967 return ret; 1116 968 } 1117 969 1118 - static struct reset_controller_dev *__reset_find_rcdev(const struct of_phandle_args *args, 1119 - bool gpio_fallback) 970 + static struct reset_controller_dev * 971 + __reset_find_rcdev(const struct fwnode_reference_args *args, bool gpio_fallback) 1120 972 { 973 + struct fwnode_reference_args *rc_args; 1121 974 struct reset_controller_dev *rcdev; 1122 975 1123 976 lockdep_assert_held(&reset_list_mutex); 1124 977 1125 978 list_for_each_entry(rcdev, &reset_controller_list, list) { 1126 - if (gpio_fallback) { 1127 - if (rcdev->of_args && of_phandle_args_equal(args, 1128 - rcdev->of_args)) 979 + if (gpio_fallback && rcdev->dev && 980 + device_is_compatible(rcdev->dev, "reset-gpio")) { 981 + rc_args = dev_get_platdata(rcdev->dev); 982 + 983 + if (fwnode_reference_args_equal(args, rc_args)) 1129 984 return rcdev; 1130 985 } else { 1131 - if (args->np == rcdev->of_node) 986 + if (args->fwnode == rcdev->fwnode) 1132 987 return rcdev; 1133 988 } 1134 989 } ··· 1136 993 } 1137 994 1138 995 struct reset_control * 1139 - __of_reset_control_get(struct device_node *node, const char *id, int index, 1140 - enum reset_control_flags flags) 996 + __fwnode_reset_control_get(struct fwnode_handle *fwnode, const char *id, int index, 997 + enum reset_control_flags flags) 1141 998 { 1142 999 bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL; 1143 1000 bool gpio_fallback = false; 1144 - struct reset_control *rstc; 1001 + struct reset_control *rstc = ERR_PTR(-EINVAL); 1145 1002 struct reset_controller_dev *rcdev; 1146 - struct of_phandle_args args; 1147 - int rstc_id; 1003 + struct fwnode_reference_args args; 1004 + struct of_phandle_args of_args; 1005 + int rstc_id = -EINVAL; 1148 1006 int ret; 1149 1007 1150 - if (!node) 1008 + if (!fwnode) 1151 1009 return ERR_PTR(-EINVAL); 1152 1010 1153 1011 if (id) { 1154 - index = of_property_match_string(node, 1155 - "reset-names", id); 1012 + index = fwnode_property_match_string(fwnode, "reset-names", id); 1156 1013 if (index == -EILSEQ) 1157 1014 return ERR_PTR(index); 1158 1015 if (index < 0) 1159 1016 return optional ? NULL : ERR_PTR(-ENOENT); 1160 1017 } 1161 1018 1162 - ret = of_parse_phandle_with_args(node, "resets", "#reset-cells", 1163 - index, &args); 1019 + ret = fwnode_property_get_reference_args(fwnode, "resets", "#reset-cells", 1020 + 0, index, &args); 1164 1021 if (ret == -EINVAL) 1165 1022 return ERR_PTR(ret); 1166 1023 if (ret) { ··· 1171 1028 * There can be only one reset-gpio for regular devices, so 1172 1029 * don't bother with the "reset-gpios" phandle index. 1173 1030 */ 1174 - ret = of_parse_phandle_with_args(node, "reset-gpios", "#gpio-cells", 1175 - 0, &args); 1031 + ret = fwnode_property_get_reference_args(fwnode, "reset-gpios", 1032 + "#gpio-cells", 0, 0, &args); 1176 1033 if (ret) 1177 1034 return optional ? NULL : ERR_PTR(ret); 1178 1035 1179 1036 gpio_fallback = true; 1180 1037 1181 - ret = __reset_add_reset_gpio_device(&args); 1038 + ret = __reset_add_reset_gpio_device(fwnode, &args); 1039 + if (ret) { 1040 + fwnode_handle_put(args.fwnode); 1041 + return ERR_PTR(ret); 1042 + } 1043 + } 1044 + 1045 + guard(mutex)(&reset_list_mutex); 1046 + 1047 + rcdev = __reset_find_rcdev(&args, gpio_fallback); 1048 + if (!rcdev) { 1049 + rstc = ERR_PTR(-EPROBE_DEFER); 1050 + goto out_put; 1051 + } 1052 + 1053 + if (WARN_ON(args.nargs != rcdev->fwnode_reset_n_cells)) { 1054 + rstc = ERR_PTR(-EINVAL); 1055 + goto out_put; 1056 + } 1057 + 1058 + if (rcdev->of_xlate && is_of_node(fwnode)) { 1059 + ret = of_parse_phandle_with_args(to_of_node(fwnode), 1060 + gpio_fallback ? "reset-gpios" : "resets", 1061 + gpio_fallback ? "#gpio-cells" : "#reset-cells", 1062 + gpio_fallback ? 0 : index, 1063 + &of_args); 1182 1064 if (ret) { 1183 1065 rstc = ERR_PTR(ret); 1184 1066 goto out_put; 1185 1067 } 1186 - } 1187 1068 1188 - mutex_lock(&reset_list_mutex); 1189 - rcdev = __reset_find_rcdev(&args, gpio_fallback); 1190 - if (!rcdev) { 1191 - rstc = ERR_PTR(-EPROBE_DEFER); 1192 - goto out_unlock; 1069 + rstc_id = rcdev->of_xlate(rcdev, &of_args); 1070 + of_node_put(of_args.np); 1071 + } else if (rcdev->fwnode_xlate) { 1072 + rstc_id = rcdev->fwnode_xlate(rcdev, &args); 1193 1073 } 1194 - 1195 - if (WARN_ON(args.args_count != rcdev->of_reset_n_cells)) { 1196 - rstc = ERR_PTR(-EINVAL); 1197 - goto out_unlock; 1198 - } 1199 - 1200 - rstc_id = rcdev->of_xlate(rcdev, &args); 1201 1074 if (rstc_id < 0) { 1202 1075 rstc = ERR_PTR(rstc_id); 1203 - goto out_unlock; 1076 + goto out_put; 1204 1077 } 1205 1078 1206 1079 flags &= ~RESET_CONTROL_FLAGS_BIT_OPTIONAL; 1207 1080 1208 - /* reset_list_mutex also protects the rcdev's reset_control list */ 1209 - rstc = __reset_control_get_internal(rcdev, rstc_id, flags); 1081 + scoped_guard(mutex, &rcdev->lock) 1082 + rstc = __reset_control_get_internal(rcdev, rstc_id, flags); 1210 1083 1211 - out_unlock: 1212 - mutex_unlock(&reset_list_mutex); 1213 1084 out_put: 1214 - of_node_put(args.np); 1085 + fwnode_handle_put(args.fwnode); 1215 1086 1216 1087 return rstc; 1217 1088 } 1218 - EXPORT_SYMBOL_GPL(__of_reset_control_get); 1089 + EXPORT_SYMBOL_GPL(__fwnode_reset_control_get); 1219 1090 1220 1091 struct reset_control *__reset_control_get(struct device *dev, const char *id, 1221 1092 int index, enum reset_control_flags flags) ··· 1237 1080 bool shared = flags & RESET_CONTROL_FLAGS_BIT_SHARED; 1238 1081 bool acquired = flags & RESET_CONTROL_FLAGS_BIT_ACQUIRED; 1239 1082 bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL; 1083 + struct fwnode_handle *fwnode = dev_fwnode(dev); 1240 1084 1241 1085 if (WARN_ON(shared && acquired)) 1242 1086 return ERR_PTR(-EINVAL); 1243 1087 1244 - if (dev->of_node) 1245 - return __of_reset_control_get(dev->of_node, id, index, flags); 1088 + if (fwnode) 1089 + return __fwnode_reset_control_get(fwnode, id, index, flags); 1246 1090 1247 1091 return optional ? NULL : ERR_PTR(-ENOENT); 1248 1092 } ··· 1266 1108 return 0; 1267 1109 1268 1110 err: 1269 - mutex_lock(&reset_list_mutex); 1270 1111 while (i--) 1271 - __reset_control_put_internal(rstcs[i].rstc); 1272 - mutex_unlock(&reset_list_mutex); 1112 + reset_control_put_internal(rstcs[i].rstc); 1113 + 1273 1114 return ret; 1274 1115 } 1275 1116 EXPORT_SYMBOL_GPL(__reset_control_bulk_get); ··· 1277 1120 { 1278 1121 int i; 1279 1122 1280 - mutex_lock(&reset_list_mutex); 1281 1123 for (i = 0; i < resets->num_rstcs; i++) 1282 - __reset_control_put_internal(resets->rstc[i]); 1283 - mutex_unlock(&reset_list_mutex); 1124 + reset_control_put_internal(resets->rstc[i]); 1284 1125 kfree(resets); 1285 1126 } 1286 1127 ··· 1296 1141 return; 1297 1142 } 1298 1143 1299 - mutex_lock(&reset_list_mutex); 1300 - __reset_control_put_internal(rstc); 1301 - mutex_unlock(&reset_list_mutex); 1144 + reset_control_put_internal(rstc); 1302 1145 } 1303 1146 EXPORT_SYMBOL_GPL(reset_control_put); 1304 1147 ··· 1307 1154 */ 1308 1155 void reset_control_bulk_put(int num_rstcs, struct reset_control_bulk_data *rstcs) 1309 1156 { 1310 - mutex_lock(&reset_list_mutex); 1311 1157 while (num_rstcs--) 1312 - __reset_control_put_internal(rstcs[num_rstcs].rstc); 1313 - mutex_unlock(&reset_list_mutex); 1158 + reset_control_put_internal(rstcs[num_rstcs].rstc); 1314 1159 } 1315 1160 EXPORT_SYMBOL_GPL(reset_control_bulk_put); 1316 1161 ··· 1469 1318 */ 1470 1319 1471 1320 /** 1472 - * of_reset_control_get_count - Count number of resets available with a device 1321 + * fwnode_reset_control_get_count - Count number of resets available with a device 1473 1322 * 1474 - * @node: device node that contains 'resets'. 1323 + * @fwnode: firmware node that contains 'resets'. 1475 1324 * 1476 1325 * Returns positive reset count on success, or error number on failure and 1477 1326 * on count being zero. 1478 1327 */ 1479 - static int of_reset_control_get_count(struct device_node *node) 1328 + static int fwnode_reset_control_get_count(struct fwnode_handle *fwnode) 1480 1329 { 1481 - int count; 1330 + struct fwnode_reference_args args; 1331 + int count = 0, ret; 1482 1332 1483 - if (!node) 1333 + if (!fwnode) 1484 1334 return -EINVAL; 1485 1335 1486 - count = of_count_phandle_with_args(node, "resets", "#reset-cells"); 1336 + for (;;) { 1337 + ret = fwnode_property_get_reference_args(fwnode, "resets", "#reset-cells", 1338 + 0, count, &args); 1339 + if (ret) { 1340 + if (ret == -ENOENT) 1341 + break; 1342 + 1343 + return ret; 1344 + } 1345 + 1346 + fwnode_handle_put(args.fwnode); 1347 + count++; 1348 + } 1349 + 1487 1350 if (count == 0) 1488 1351 count = -ENOENT; 1489 1352 ··· 1505 1340 } 1506 1341 1507 1342 /** 1508 - * of_reset_control_array_get - Get a list of reset controls using 1509 - * device node. 1343 + * fwnode_reset_control_array_get - Get a list of reset controls using 1344 + * a firmware node. 1510 1345 * 1511 - * @np: device node for the device that requests the reset controls array 1346 + * @fwnode: firmware node for the device that requests the reset controls array 1512 1347 * @flags: whether reset controls are shared, optional, acquired 1513 1348 * 1514 1349 * Returns pointer to allocated reset_control on success or error on failure 1515 1350 */ 1516 1351 struct reset_control * 1517 - of_reset_control_array_get(struct device_node *np, enum reset_control_flags flags) 1352 + fwnode_reset_control_array_get(struct fwnode_handle *fwnode, 1353 + enum reset_control_flags flags) 1518 1354 { 1519 1355 bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL; 1520 1356 struct reset_control_array *resets; 1521 1357 struct reset_control *rstc; 1522 1358 int num, i; 1523 1359 1524 - num = of_reset_control_get_count(np); 1360 + num = fwnode_reset_control_get_count(fwnode); 1525 1361 if (num < 0) 1526 1362 return optional ? NULL : ERR_PTR(num); 1527 1363 ··· 1532 1366 resets->num_rstcs = num; 1533 1367 1534 1368 for (i = 0; i < num; i++) { 1535 - rstc = __of_reset_control_get(np, NULL, i, flags); 1369 + rstc = __fwnode_reset_control_get(fwnode, NULL, i, flags); 1536 1370 if (IS_ERR(rstc)) 1537 1371 goto err_rst; 1538 1372 resets->rstc[i] = rstc; ··· 1542 1376 return &resets->base; 1543 1377 1544 1378 err_rst: 1545 - mutex_lock(&reset_list_mutex); 1546 1379 while (--i >= 0) 1547 - __reset_control_put_internal(resets->rstc[i]); 1548 - mutex_unlock(&reset_list_mutex); 1380 + reset_control_put_internal(resets->rstc[i]); 1549 1381 1550 1382 kfree(resets); 1551 1383 1552 1384 return rstc; 1553 1385 } 1554 - EXPORT_SYMBOL_GPL(of_reset_control_array_get); 1386 + EXPORT_SYMBOL_GPL(fwnode_reset_control_array_get); 1555 1387 1556 1388 /** 1557 1389 * devm_reset_control_array_get - Resource managed reset control array get ··· 1573 1409 if (!ptr) 1574 1410 return ERR_PTR(-ENOMEM); 1575 1411 1576 - rstc = of_reset_control_array_get(dev->of_node, flags); 1412 + rstc = fwnode_reset_control_array_get(dev_fwnode(dev), flags); 1577 1413 if (IS_ERR_OR_NULL(rstc)) { 1578 1414 devres_free(ptr); 1579 1415 return rstc; ··· 1596 1432 */ 1597 1433 int reset_control_get_count(struct device *dev) 1598 1434 { 1599 - if (dev->of_node) 1600 - return of_reset_control_get_count(dev->of_node); 1435 + struct fwnode_handle *fwnode = dev_fwnode(dev); 1436 + 1437 + if (fwnode) 1438 + return fwnode_reset_control_get_count(fwnode); 1601 1439 1602 1440 return -ENOENT; 1603 1441 }

+3 -9

drivers/reset/reset-ath79.c

··· 15 15 16 16 struct ath79_reset { 17 17 struct reset_controller_dev rcdev; 18 - struct notifier_block restart_nb; 19 18 void __iomem *base; 20 19 spinlock_t lock; 21 20 }; ··· 71 72 .status = ath79_reset_status, 72 73 }; 73 74 74 - static int ath79_reset_restart_handler(struct notifier_block *nb, 75 - unsigned long action, void *data) 75 + static int ath79_reset_restart_handler(struct sys_off_data *data) 76 76 { 77 - struct ath79_reset *ath79_reset = 78 - container_of(nb, struct ath79_reset, restart_nb); 77 + struct ath79_reset *ath79_reset = data->cb_data; 79 78 80 79 ath79_reset_assert(&ath79_reset->rcdev, FULL_CHIP_RESET); 81 80 ··· 105 108 if (err) 106 109 return err; 107 110 108 - ath79_reset->restart_nb.notifier_call = ath79_reset_restart_handler; 109 - ath79_reset->restart_nb.priority = 128; 110 - 111 - err = register_restart_handler(&ath79_reset->restart_nb); 111 + err = devm_register_restart_handler(&pdev->dev, ath79_reset_restart_handler, ath79_reset); 112 112 if (err) 113 113 dev_warn(&pdev->dev, "Failed to register restart handler\n"); 114 114

+5 -22

drivers/reset/reset-gpio.c

··· 4 4 #include <linux/gpio/consumer.h> 5 5 #include <linux/mod_devicetable.h> 6 6 #include <linux/module.h> 7 - #include <linux/of.h> 7 + #include <linux/property.h> 8 8 #include <linux/reset-controller.h> 9 9 10 10 struct reset_gpio_priv { ··· 46 46 .status = reset_gpio_status, 47 47 }; 48 48 49 - static int reset_gpio_of_xlate(struct reset_controller_dev *rcdev, 50 - const struct of_phandle_args *reset_spec) 49 + static int reset_gpio_fwnode_xlate(struct reset_controller_dev *rcdev, 50 + const struct fwnode_reference_args *reset_spec) 51 51 { 52 52 return reset_spec->args[0]; 53 - } 54 - 55 - static void reset_gpio_of_node_put(void *data) 56 - { 57 - of_node_put(data); 58 53 } 59 54 60 55 static int reset_gpio_probe(struct auxiliary_device *adev, 61 56 const struct auxiliary_device_id *id) 62 57 { 63 58 struct device *dev = &adev->dev; 64 - struct of_phandle_args *platdata = dev_get_platdata(dev); 65 59 struct reset_gpio_priv *priv; 66 - int ret; 67 - 68 - if (!platdata) 69 - return -EINVAL; 70 60 71 61 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 72 62 if (!priv) 73 63 return -ENOMEM; 74 - 75 - auxiliary_set_drvdata(adev, &priv->rc); 76 64 77 65 priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 78 66 if (IS_ERR(priv->reset)) ··· 70 82 priv->rc.ops = &reset_gpio_ops; 71 83 priv->rc.owner = THIS_MODULE; 72 84 priv->rc.dev = dev; 73 - priv->rc.of_args = platdata; 74 - ret = devm_add_action_or_reset(dev, reset_gpio_of_node_put, 75 - priv->rc.of_node); 76 - if (ret) 77 - return ret; 78 85 79 86 /* Cells to match GPIO specifier, but it's not really used */ 80 - priv->rc.of_reset_n_cells = 2; 81 - priv->rc.of_xlate = reset_gpio_of_xlate; 87 + priv->rc.fwnode_reset_n_cells = 2; 88 + priv->rc.fwnode_xlate = reset_gpio_fwnode_xlate; 82 89 priv->rc.nr_resets = 1; 83 90 84 91 return devm_reset_controller_register(dev, &priv->rc);

+3 -8

drivers/reset/reset-intel-gw.c

··· 28 28 29 29 struct intel_reset_data { 30 30 struct reset_controller_dev rcdev; 31 - struct notifier_block restart_nb; 32 31 const struct intel_reset_soc *soc_data; 33 32 struct regmap *regmap; 34 33 struct device *dev; ··· 152 153 return id; 153 154 } 154 155 155 - static int intel_reset_restart_handler(struct notifier_block *nb, 156 - unsigned long action, void *data) 156 + static int intel_reset_restart_handler(struct sys_off_data *data) 157 157 { 158 - struct intel_reset_data *reset_data; 158 + struct intel_reset_data *reset_data = data->cb_data; 159 159 160 - reset_data = container_of(nb, struct intel_reset_data, restart_nb); 161 160 intel_assert_device(&reset_data->rcdev, reset_data->reboot_id); 162 161 163 162 return NOTIFY_DONE; ··· 212 215 if (data->soc_data->legacy) 213 216 data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, rb_id[2]); 214 217 215 - data->restart_nb.notifier_call = intel_reset_restart_handler; 216 - data->restart_nb.priority = 128; 217 - register_restart_handler(&data->restart_nb); 218 + devm_register_restart_handler(&pdev->dev, intel_reset_restart_handler, data); 218 219 219 220 return 0; 220 221 }

+4 -8

drivers/reset/reset-lpc18xx.c

··· 31 31 32 32 struct lpc18xx_rgu_data { 33 33 struct reset_controller_dev rcdev; 34 - struct notifier_block restart_nb; 35 34 struct clk *clk_delay; 36 35 struct clk *clk_reg; 37 36 void __iomem *base; ··· 40 41 41 42 #define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev) 42 43 43 - static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode, 44 - void *cmd) 44 + static int lpc18xx_rgu_restart(struct sys_off_data *data) 45 45 { 46 - struct lpc18xx_rgu_data *rc = container_of(nb, struct lpc18xx_rgu_data, 47 - restart_nb); 46 + struct lpc18xx_rgu_data *rc = data->cb_data; 48 47 49 48 writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0); 50 49 mdelay(2000); ··· 175 178 if (ret) 176 179 return dev_err_probe(&pdev->dev, ret, "unable to register device\n"); 177 180 178 - rc->restart_nb.priority = 192, 179 - rc->restart_nb.notifier_call = lpc18xx_rgu_restart, 180 - ret = register_restart_handler(&rc->restart_nb); 181 + ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, 192, 182 + lpc18xx_rgu_restart, rc); 181 183 if (ret) 182 184 dev_warn(&pdev->dev, "failed to register restart handler\n"); 183 185

+4 -7

drivers/reset/reset-ma35d1.c

··· 19 19 20 20 struct ma35d1_reset_data { 21 21 struct reset_controller_dev rcdev; 22 - struct notifier_block restart_handler; 23 22 void __iomem *base; 24 23 /* protect registers against concurrent read-modify-write */ 25 24 spinlock_t lock; ··· 124 125 [MA35D1_RESET_SSPCC] = {0x2C, 31} 125 126 }; 126 127 127 - static int ma35d1_restart_handler(struct notifier_block *this, unsigned long mode, void *cmd) 128 + static int ma35d1_restart_handler(struct sys_off_data *sys_off_data) 128 129 { 129 - struct ma35d1_reset_data *data = 130 - container_of(this, struct ma35d1_reset_data, restart_handler); 130 + struct ma35d1_reset_data *data = sys_off_data->cb_data; 131 131 u32 id = MA35D1_RESET_CHIP; 132 132 133 133 writel_relaxed(BIT(ma35d1_reset_map[id].bit), ··· 211 213 reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT; 212 214 reset_data->rcdev.ops = &ma35d1_reset_ops; 213 215 reset_data->rcdev.of_node = dev->of_node; 214 - reset_data->restart_handler.notifier_call = ma35d1_restart_handler; 215 - reset_data->restart_handler.priority = 192; 216 216 spin_lock_init(&reset_data->lock); 217 217 218 - err = register_restart_handler(&reset_data->restart_handler); 218 + err = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, 192, 219 + ma35d1_restart_handler, reset_data); 219 220 if (err) 220 221 dev_warn(&pdev->dev, "failed to register restart handler\n"); 221 222

+4 -8

drivers/reset/reset-npcm.c

··· 89 89 90 90 struct npcm_rc_data { 91 91 struct reset_controller_dev rcdev; 92 - struct notifier_block restart_nb; 93 92 const struct npcm_reset_info *info; 94 93 struct regmap *gcr_regmap; 95 94 u32 sw_reset_number; ··· 99 100 100 101 #define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev) 101 102 102 - static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode, 103 - void *cmd) 103 + static int npcm_rc_restart(struct sys_off_data *data) 104 104 { 105 - struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data, 106 - restart_nb); 105 + struct npcm_rc_data *rc = data->cb_data; 107 106 108 107 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); 109 108 mdelay(1000); ··· 469 472 if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number", 470 473 &rc->sw_reset_number)) { 471 474 if (rc->sw_reset_number && rc->sw_reset_number < 5) { 472 - rc->restart_nb.priority = 192; 473 - rc->restart_nb.notifier_call = npcm_rc_restart; 474 - ret = register_restart_handler(&rc->restart_nb); 475 + ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, 192, 476 + npcm_rc_restart, rc); 475 477 if (ret) { 476 478 dev_warn(&pdev->dev, "failed to register restart handler\n"); 477 479 return ret;

+4 -1

drivers/reset/reset-rzg2l-usbphy-ctrl.c

··· 136 136 { 137 137 u32 val = power_on ? 0 : 1; 138 138 139 + if (!pwrrdy) 140 + return 0; 141 + 139 142 /* The initialization path guarantees that the mask is 1 bit long. */ 140 143 return regmap_field_update_bits(pwrrdy, 1, val); 141 144 } ··· 350 347 351 348 MODULE_LICENSE("GPL v2"); 352 349 MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control"); 353 - MODULE_AUTHOR("biju.das.jz@bp.renesas.com>"); 350 + MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");

+102 -95

drivers/reset/reset-rzv2h-usb2phy.c

··· 5 5 * Copyright (C) 2025 Renesas Electronics Corporation 6 6 */ 7 7 8 - #include <linux/cleanup.h> 8 + #include <linux/auxiliary_bus.h> 9 9 #include <linux/delay.h> 10 + #include <linux/idr.h> 10 11 #include <linux/io.h> 11 12 #include <linux/module.h> 12 13 #include <linux/of.h> 13 14 #include <linux/platform_device.h> 14 15 #include <linux/pm_runtime.h> 16 + #include <linux/regmap.h> 15 17 #include <linux/reset.h> 16 18 #include <linux/reset-controller.h> 17 19 18 - struct rzv2h_usb2phy_regval { 19 - u16 reg; 20 - u16 val; 21 - }; 20 + static DEFINE_IDA(auxiliary_ids); 22 21 23 22 struct rzv2h_usb2phy_reset_of_data { 24 - const struct rzv2h_usb2phy_regval *init_vals; 25 - unsigned int init_val_count; 23 + const struct reg_sequence *init_seq; 24 + unsigned int init_nseq; 25 + 26 + const struct reg_sequence *assert_seq; 27 + unsigned int assert_nseq; 28 + 29 + const struct reg_sequence *deassert_seq; 30 + unsigned int deassert_nseq; 26 31 27 32 u16 reset_reg; 28 - u16 reset_assert_val; 29 - u16 reset_deassert_val; 30 33 u16 reset_status_bits; 31 - u16 reset_release_val; 32 - 33 - u16 reset2_reg; 34 - u16 reset2_acquire_val; 35 - u16 reset2_release_val; 36 34 }; 37 35 38 36 struct rzv2h_usb2phy_reset_priv { 39 37 const struct rzv2h_usb2phy_reset_of_data *data; 40 - void __iomem *base; 38 + struct regmap *regmap; 41 39 struct device *dev; 42 40 struct reset_controller_dev rcdev; 43 - spinlock_t lock; /* protects register accesses */ 44 41 }; 45 42 46 43 static inline struct rzv2h_usb2phy_reset_priv ··· 46 49 return container_of(rcdev, struct rzv2h_usb2phy_reset_priv, rcdev); 47 50 } 48 51 49 - /* This function must be called only after pm_runtime_resume_and_get() has been called */ 50 - static void rzv2h_usbphy_assert_helper(struct rzv2h_usb2phy_reset_priv *priv) 51 - { 52 - const struct rzv2h_usb2phy_reset_of_data *data = priv->data; 53 - 54 - scoped_guard(spinlock, &priv->lock) { 55 - writel(data->reset2_acquire_val, priv->base + data->reset2_reg); 56 - writel(data->reset_assert_val, priv->base + data->reset_reg); 57 - } 58 - 59 - usleep_range(11, 20); 60 - } 61 - 62 52 static int rzv2h_usbphy_reset_assert(struct reset_controller_dev *rcdev, 63 53 unsigned long id) 64 54 { 65 55 struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); 66 - struct device *dev = priv->dev; 67 - int ret; 68 56 69 - ret = pm_runtime_resume_and_get(dev); 70 - if (ret) { 71 - dev_err(dev, "pm_runtime_resume_and_get failed\n"); 72 - return ret; 73 - } 74 - 75 - rzv2h_usbphy_assert_helper(priv); 76 - 77 - pm_runtime_put(dev); 78 - 79 - return 0; 57 + return regmap_multi_reg_write(priv->regmap, priv->data->assert_seq, 58 + priv->data->assert_nseq); 80 59 } 81 60 82 61 static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev, 83 62 unsigned long id) 84 63 { 85 64 struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); 86 - const struct rzv2h_usb2phy_reset_of_data *data = priv->data; 87 - struct device *dev = priv->dev; 88 - int ret; 89 65 90 - ret = pm_runtime_resume_and_get(dev); 91 - if (ret) { 92 - dev_err(dev, "pm_runtime_resume_and_get failed\n"); 93 - return ret; 94 - } 95 - 96 - scoped_guard(spinlock, &priv->lock) { 97 - writel(data->reset_deassert_val, priv->base + data->reset_reg); 98 - writel(data->reset2_release_val, priv->base + data->reset2_reg); 99 - writel(data->reset_release_val, priv->base + data->reset_reg); 100 - } 101 - 102 - pm_runtime_put(dev); 103 - 104 - return 0; 66 + return regmap_multi_reg_write(priv->regmap, priv->data->deassert_seq, 67 + priv->data->deassert_nseq); 105 68 } 106 69 107 70 static int rzv2h_usbphy_reset_status(struct reset_controller_dev *rcdev, 108 71 unsigned long id) 109 72 { 110 73 struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); 111 - struct device *dev = priv->dev; 112 - int ret; 113 74 u32 reg; 114 75 115 - ret = pm_runtime_resume_and_get(dev); 116 - if (ret) { 117 - dev_err(dev, "pm_runtime_resume_and_get failed\n"); 118 - return ret; 119 - } 120 - 121 - reg = readl(priv->base + priv->data->reset_reg); 122 - 123 - pm_runtime_put(dev); 76 + regmap_read(priv->regmap, priv->data->reset_reg, &reg); 124 77 125 78 return (reg & priv->data->reset_status_bits) == priv->data->reset_status_bits; 126 79 } ··· 88 141 return 0; 89 142 } 90 143 144 + static void rzv2h_usb2phy_reset_ida_free(void *data) 145 + { 146 + struct auxiliary_device *adev = data; 147 + 148 + ida_free(&auxiliary_ids, adev->id); 149 + } 150 + 151 + static int rzv2h_usb2phy_reset_mux_register(struct device *dev, 152 + const char *mux_name) 153 + { 154 + struct auxiliary_device *adev; 155 + int id; 156 + 157 + id = ida_alloc(&auxiliary_ids, GFP_KERNEL); 158 + if (id < 0) 159 + return id; 160 + 161 + adev = __devm_auxiliary_device_create(dev, dev->driver->name, 162 + mux_name, NULL, id); 163 + if (!adev) { 164 + ida_free(&auxiliary_ids, id); 165 + return -ENOMEM; 166 + } 167 + 168 + return devm_add_action_or_reset(dev, rzv2h_usb2phy_reset_ida_free, adev); 169 + } 170 + 171 + static const struct regmap_config rzv2h_usb2phy_reset_regconf = { 172 + .reg_bits = 32, 173 + .val_bits = 32, 174 + .reg_stride = 4, 175 + .can_sleep = true, 176 + }; 177 + 178 + static void rzv2h_usb2phy_reset_pm_runtime_put(void *data) 179 + { 180 + pm_runtime_put(data); 181 + } 182 + 91 183 static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev) 92 184 { 93 185 const struct rzv2h_usb2phy_reset_of_data *data; 94 186 struct rzv2h_usb2phy_reset_priv *priv; 95 187 struct device *dev = &pdev->dev; 96 188 struct reset_control *rstc; 189 + void __iomem *base; 97 190 int error; 98 191 99 192 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 143 156 data = of_device_get_match_data(dev); 144 157 priv->data = data; 145 158 priv->dev = dev; 146 - priv->base = devm_platform_ioremap_resource(pdev, 0); 147 - if (IS_ERR(priv->base)) 148 - return PTR_ERR(priv->base); 159 + base = devm_platform_ioremap_resource(pdev, 0); 160 + if (IS_ERR(base)) 161 + return PTR_ERR(base); 162 + 163 + priv->regmap = devm_regmap_init_mmio(dev, base, &rzv2h_usb2phy_reset_regconf); 164 + if (IS_ERR(priv->regmap)) 165 + return PTR_ERR(priv->regmap); 149 166 150 167 rstc = devm_reset_control_get_shared_deasserted(dev, NULL); 151 168 if (IS_ERR(rstc)) 152 169 return dev_err_probe(dev, PTR_ERR(rstc), 153 170 "failed to get deasserted reset\n"); 154 - 155 - spin_lock_init(&priv->lock); 156 171 157 172 error = devm_pm_runtime_enable(dev); 158 173 if (error) ··· 164 175 if (error) 165 176 return dev_err_probe(dev, error, "pm_runtime_resume_and_get failed\n"); 166 177 167 - for (unsigned int i = 0; i < data->init_val_count; i++) 168 - writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg); 178 + error = devm_add_action_or_reset(dev, rzv2h_usb2phy_reset_pm_runtime_put, 179 + dev); 180 + if (error) 181 + return dev_err_probe(dev, error, "unable to register cleanup action\n"); 169 182 170 - /* keep usb2phy in asserted state */ 171 - rzv2h_usbphy_assert_helper(priv); 172 - 173 - pm_runtime_put(dev); 183 + error = regmap_multi_reg_write(priv->regmap, data->init_seq, data->init_nseq); 184 + if (error) 185 + return dev_err_probe(dev, error, "failed to initialize PHY registers\n"); 174 186 175 187 priv->rcdev.ops = &rzv2h_usbphy_reset_ops; 176 188 priv->rcdev.of_reset_n_cells = 0; ··· 180 190 priv->rcdev.of_node = dev->of_node; 181 191 priv->rcdev.dev = dev; 182 192 183 - return devm_reset_controller_register(dev, &priv->rcdev); 193 + error = devm_reset_controller_register(dev, &priv->rcdev); 194 + if (error) 195 + return dev_err_probe(dev, error, "could not register reset controller\n"); 196 + 197 + error = rzv2h_usb2phy_reset_mux_register(dev, "vbenctl"); 198 + if (error) 199 + return dev_err_probe(dev, error, "could not register aux mux\n"); 200 + 201 + return 0; 184 202 } 185 203 186 204 /* 187 205 * initialization values required to prepare the PHY to receive 188 206 * assert and deassert requests. 189 207 */ 190 - static const struct rzv2h_usb2phy_regval rzv2h_init_vals[] = { 191 - { .reg = 0xc10, .val = 0x67c }, 192 - { .reg = 0xc14, .val = 0x1f }, 193 - { .reg = 0x600, .val = 0x909 }, 208 + static const struct reg_sequence rzv2h_init_seq[] = { 209 + { .reg = 0xc10, .def = 0x67c }, 210 + { .reg = 0xc14, .def = 0x01f }, 211 + { .reg = 0x600, .def = 0x909 }, 212 + }; 213 + 214 + static const struct reg_sequence rzv2h_assert_seq[] = { 215 + { .reg = 0xb04, .def = 0x303 }, 216 + { .reg = 0x000, .def = 0x206, .delay_us = 11 }, 217 + }; 218 + 219 + static const struct reg_sequence rzv2h_deassert_seq[] = { 220 + { .reg = 0x000, .def = 0x200 }, 221 + { .reg = 0xb04, .def = 0x003 }, 222 + { .reg = 0x000, .def = 0x000 }, 194 223 }; 195 224 196 225 static const struct rzv2h_usb2phy_reset_of_data rzv2h_reset_of_data = { 197 - .init_vals = rzv2h_init_vals, 198 - .init_val_count = ARRAY_SIZE(rzv2h_init_vals), 226 + .init_seq = rzv2h_init_seq, 227 + .init_nseq = ARRAY_SIZE(rzv2h_init_seq), 228 + .assert_seq = rzv2h_assert_seq, 229 + .assert_nseq = ARRAY_SIZE(rzv2h_assert_seq), 230 + .deassert_seq = rzv2h_deassert_seq, 231 + .deassert_nseq = ARRAY_SIZE(rzv2h_deassert_seq), 199 232 .reset_reg = 0, 200 - .reset_assert_val = 0x206, 201 233 .reset_status_bits = BIT(2), 202 - .reset_deassert_val = 0x200, 203 - .reset_release_val = 0x0, 204 - .reset2_reg = 0xb04, 205 - .reset2_acquire_val = 0x303, 206 - .reset2_release_val = 0x3, 207 234 }; 208 235 209 236 static const struct of_device_id rzv2h_usb2phy_reset_of_match[] = {

+367

drivers/reset/reset-sky1.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * 4 + * CIX System Reset Controller (SRC) driver 5 + * 6 + * Author: Jerry Zhu <jerry.zhu@cixtech.com> 7 + */ 8 + 9 + #include <linux/delay.h> 10 + #include <linux/mfd/syscon.h> 11 + #include <linux/module.h> 12 + #include <linux/of.h> 13 + #include <linux/platform_device.h> 14 + #include <linux/regmap.h> 15 + #include <linux/reset-controller.h> 16 + 17 + #include <dt-bindings/reset/cix,sky1-system-control.h> 18 + #include <dt-bindings/reset/cix,sky1-s5-system-control.h> 19 + 20 + #define SKY1_RESET_SLEEP_MIN_US 50 21 + #define SKY1_RESET_SLEEP_MAX_US 100 22 + 23 + struct sky1_src_signal { 24 + unsigned int offset; 25 + unsigned int bit; 26 + }; 27 + 28 + struct sky1_src_variant { 29 + const struct sky1_src_signal *signals; 30 + unsigned int signals_num; 31 + }; 32 + 33 + struct sky1_src { 34 + struct reset_controller_dev rcdev; 35 + const struct sky1_src_signal *signals; 36 + struct regmap *regmap; 37 + }; 38 + 39 + enum { 40 + CSU_PM_RESET = 0x304, 41 + SENSORFUSION_RESET = 0x308, 42 + SENSORFUSION_NOC_RESET = 0x30c, 43 + RESET_GROUP0_S0_DOMAIN_0 = 0x400, 44 + RESET_GROUP0_S0_DOMAIN_1 = 0x404, 45 + RESET_GROUP1_USB_PHYS = 0x408, 46 + RESET_GROUP1_USB_CONTROLLERS = 0x40c, 47 + RESET_GROUP0_RCSU = 0x800, 48 + RESET_GROUP1_RCSU = 0x804, 49 + }; 50 + 51 + static const struct sky1_src_signal sky1_src_signals[] = { 52 + /* reset group1 for s0 domain modules */ 53 + [SKY1_CSU_PM_RESET_N] = { CSU_PM_RESET, BIT(0) }, 54 + [SKY1_SENSORFUSION_RESET_N] = { SENSORFUSION_RESET, BIT(0) }, 55 + [SKY1_SENSORFUSION_NOC_RESET_N] = { SENSORFUSION_NOC_RESET, BIT(0) }, 56 + [SKY1_DDRC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(0) }, 57 + [SKY1_GIC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(1) }, 58 + [SKY1_CI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(2) }, 59 + [SKY1_SYS_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(3) }, 60 + [SKY1_MM_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(4) }, 61 + [SKY1_PCIE_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(5) }, 62 + [SKY1_GPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(6) }, 63 + [SKY1_NPUTOP_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(7) }, 64 + [SKY1_NPUCORE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(8) }, 65 + [SKY1_NPUCORE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(9) }, 66 + [SKY1_NPUCORE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(10) }, 67 + [SKY1_VPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(11) }, 68 + [SKY1_ISP_SRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(12) }, 69 + [SKY1_ISP_ARESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(13) }, 70 + [SKY1_ISP_HRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(14) }, 71 + [SKY1_ISP_GDCRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(15) }, 72 + [SKY1_DPU_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(16) }, 73 + [SKY1_DPU_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(17) }, 74 + [SKY1_DPU_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(18) }, 75 + [SKY1_DPU_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(19) }, 76 + [SKY1_DPU_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(20) }, 77 + [SKY1_DP_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(21) }, 78 + [SKY1_DP_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(22) }, 79 + [SKY1_DP_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(23) }, 80 + [SKY1_DP_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(24) }, 81 + [SKY1_DP_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(25) }, 82 + [SKY1_DP_PHY_RST_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(26) }, 83 + 84 + /* reset group1 for s0 domain modules */ 85 + [SKY1_AUDIO_HIFI5_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(0) }, 86 + [SKY1_AUDIO_HIFI5_NOC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(1) }, 87 + [SKY1_CSIDPHY_PRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(2) }, 88 + [SKY1_CSIDPHY_CMNRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(3) }, 89 + [SKY1_CSI0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(4) }, 90 + [SKY1_CSIDPHY_PRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(5) }, 91 + [SKY1_CSIDPHY_CMNRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(6) }, 92 + [SKY1_CSI1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(7) }, 93 + [SKY1_CSI2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(8) }, 94 + [SKY1_CSI3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(9) }, 95 + [SKY1_CSIBRDGE0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(10) }, 96 + [SKY1_CSIBRDGE1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(11) }, 97 + [SKY1_CSIBRDGE2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(12) }, 98 + [SKY1_CSIBRDGE3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(13) }, 99 + [SKY1_GMAC0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(14) }, 100 + [SKY1_GMAC1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(15) }, 101 + [SKY1_PCIE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(16) }, 102 + [SKY1_PCIE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(17) }, 103 + [SKY1_PCIE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(18) }, 104 + [SKY1_PCIE3_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(19) }, 105 + [SKY1_PCIE4_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(20) }, 106 + 107 + /* reset group1 for usb phys */ 108 + [SKY1_USB_DP_PHY0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(0) }, 109 + [SKY1_USB_DP_PHY1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(1) }, 110 + [SKY1_USB_DP_PHY2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(2) }, 111 + [SKY1_USB_DP_PHY3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(3) }, 112 + [SKY1_USB_DP_PHY0_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(4) }, 113 + [SKY1_USB_DP_PHY1_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(5) }, 114 + [SKY1_USB_DP_PHY2_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(6) }, 115 + [SKY1_USB_DP_PHY3_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(7) }, 116 + [SKY1_USBPHY_SS_PST_N] = { RESET_GROUP1_USB_PHYS, BIT(8) }, 117 + [SKY1_USBPHY_SS_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(9) }, 118 + [SKY1_USBPHY_HS0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(10) }, 119 + [SKY1_USBPHY_HS1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(11) }, 120 + [SKY1_USBPHY_HS2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(12) }, 121 + [SKY1_USBPHY_HS3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(13) }, 122 + [SKY1_USBPHY_HS4_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(14) }, 123 + [SKY1_USBPHY_HS5_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(15) }, 124 + [SKY1_USBPHY_HS6_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(16) }, 125 + [SKY1_USBPHY_HS7_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(17) }, 126 + [SKY1_USBPHY_HS8_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(18) }, 127 + [SKY1_USBPHY_HS9_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(19) }, 128 + 129 + /* reset group1 for usb controllers */ 130 + [SKY1_USBC_SS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(0) }, 131 + [SKY1_USBC_SS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(1) }, 132 + [SKY1_USBC_SS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(2) }, 133 + [SKY1_USBC_SS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(3) }, 134 + [SKY1_USBC_SS4_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(4) }, 135 + [SKY1_USBC_SS5_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(5) }, 136 + [SKY1_USBC_SS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(6) }, 137 + [SKY1_USBC_SS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(7) }, 138 + [SKY1_USBC_SS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(8) }, 139 + [SKY1_USBC_SS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(9) }, 140 + [SKY1_USBC_SS4_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(10) }, 141 + [SKY1_USBC_SS5_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(11) }, 142 + [SKY1_USBC_HS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(12) }, 143 + [SKY1_USBC_HS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(13) }, 144 + [SKY1_USBC_HS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(14) }, 145 + [SKY1_USBC_HS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(15) }, 146 + [SKY1_USBC_HS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(16) }, 147 + [SKY1_USBC_HS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(17) }, 148 + [SKY1_USBC_HS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(18) }, 149 + [SKY1_USBC_HS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(19) }, 150 + 151 + /* reset group0 for rcsu */ 152 + [SKY1_AUDIO_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(0) }, 153 + [SKY1_CI700_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(1) }, 154 + [SKY1_CSI_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(2) }, 155 + [SKY1_CSI_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(3) }, 156 + [SKY1_CSU_PM_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(4) }, 157 + [SKY1_DDR_BROADCAST_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(5) }, 158 + [SKY1_DDR_CTRL_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(6) }, 159 + [SKY1_DDR_CTRL_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(7) }, 160 + [SKY1_DDR_CTRL_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(8) }, 161 + [SKY1_DDR_CTRL_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(9) }, 162 + [SKY1_DDR_TZC400_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(10) }, 163 + [SKY1_DDR_TZC400_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(11) }, 164 + [SKY1_DDR_TZC400_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(12) }, 165 + [SKY1_DDR_TZC400_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(13) }, 166 + [SKY1_DP0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(14) }, 167 + [SKY1_DP1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(15) }, 168 + [SKY1_DP2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(16) }, 169 + [SKY1_DP3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(17) }, 170 + [SKY1_DP4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(18) }, 171 + [SKY1_DPU0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(19) }, 172 + [SKY1_DPU1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(20) }, 173 + [SKY1_DPU2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(21) }, 174 + [SKY1_DPU3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(22) }, 175 + [SKY1_DPU4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(23) }, 176 + [SKY1_DSU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(24) }, 177 + [SKY1_FCH_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(25) }, 178 + [SKY1_GICD_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(26) }, 179 + [SKY1_GMAC_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(27) }, 180 + [SKY1_GPU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(28) }, 181 + [SKY1_ISP_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(29) }, 182 + [SKY1_ISP_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(30) }, 183 + [SKY1_NI700_MMHUB_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(31) }, 184 + 185 + /* reset group1 for rcsu */ 186 + [SKY1_NPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(0) }, 187 + [SKY1_NI700_PCIE_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(1) }, 188 + [SKY1_PCIE_X421_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(2) }, 189 + [SKY1_PCIE_X8_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(3) }, 190 + [SKY1_SF_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(4) }, 191 + [SKY1_RCSU_SMMU_MMHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(5) }, 192 + [SKY1_RCSU_SMMU_PCIEHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(6) }, 193 + [SKY1_RCSU_SYSHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(7) }, 194 + [SKY1_NI700_SMN_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(8) }, 195 + [SKY1_NI700_SYSHUB_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(9) }, 196 + [SKY1_RCSU_USB2_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(10) }, 197 + [SKY1_RCSU_USB2_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(11) }, 198 + [SKY1_RCSU_USB2_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(12) }, 199 + [SKY1_RCSU_USB2_HOST3_RESET_N] = { RESET_GROUP1_RCSU, BIT(13) }, 200 + [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(14) }, 201 + [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(15) }, 202 + [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(16) }, 203 + [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(17) }, 204 + [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(18) }, 205 + [SKY1_VPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(19) }, 206 + }; 207 + 208 + static const struct sky1_src_variant variant_sky1 = { 209 + .signals = sky1_src_signals, 210 + .signals_num = ARRAY_SIZE(sky1_src_signals), 211 + }; 212 + 213 + enum { 214 + FCH_SW_RST_FUNC = 0x8, 215 + FCH_SW_RST_BUS = 0xc, 216 + FCH_SW_XSPI = 0x10, 217 + }; 218 + 219 + static const struct sky1_src_signal sky1_src_fch_signals[] = { 220 + /* resets for fch_sw_rst_func */ 221 + [SW_I3C0_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(0) }, 222 + [SW_I3C0_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(1) }, 223 + [SW_I3C1_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(2) }, 224 + [SW_I3C1_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(3) }, 225 + [SW_UART0_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(4) }, 226 + [SW_UART1_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(5) }, 227 + [SW_UART2_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(6) }, 228 + [SW_UART3_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(7) }, 229 + [SW_TIMER_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(20) }, 230 + 231 + /* resets for fch_sw_rst_bus */ 232 + [SW_I3C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(0) }, 233 + [SW_I3C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(1) }, 234 + [SW_DMA_RST_AXI_N] = { FCH_SW_RST_BUS, BIT(2) }, 235 + [SW_UART0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(4) }, 236 + [SW_UART1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(5) }, 237 + [SW_UART2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(6) }, 238 + [SW_UART3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(7) }, 239 + [SW_SPI0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(8) }, 240 + [SW_SPI1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(9) }, 241 + [SW_I2C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(12) }, 242 + [SW_I2C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(13) }, 243 + [SW_I2C2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(14) }, 244 + [SW_I2C3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(15) }, 245 + [SW_I2C4_RST_APB_N] = { FCH_SW_RST_BUS, BIT(16) }, 246 + [SW_I2C5_RST_APB_N] = { FCH_SW_RST_BUS, BIT(17) }, 247 + [SW_I2C6_RST_APB_N] = { FCH_SW_RST_BUS, BIT(18) }, 248 + [SW_I2C7_RST_APB_N] = { FCH_SW_RST_BUS, BIT(19) }, 249 + [SW_GPIO_RST_APB_N] = { FCH_SW_RST_BUS, BIT(21) }, 250 + 251 + /* resets for fch_sw_xspi */ 252 + [SW_XSPI_REG_RST_N] = { FCH_SW_XSPI, BIT(0) }, 253 + [SW_XSPI_SYS_RST_N] = { FCH_SW_XSPI, BIT(1) }, 254 + }; 255 + 256 + static const struct sky1_src_variant variant_sky1_fch = { 257 + .signals = sky1_src_fch_signals, 258 + .signals_num = ARRAY_SIZE(sky1_src_fch_signals), 259 + }; 260 + 261 + static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev) 262 + { 263 + return container_of(rcdev, struct sky1_src, rcdev); 264 + } 265 + 266 + static int sky1_reset_set(struct reset_controller_dev *rcdev, 267 + unsigned long id, bool assert) 268 + { 269 + struct sky1_src *sky1src = to_sky1_src(rcdev); 270 + const struct sky1_src_signal *signal = &sky1src->signals[id]; 271 + unsigned int value = assert ? 0 : signal->bit; 272 + 273 + return regmap_update_bits(sky1src->regmap, 274 + signal->offset, signal->bit, value); 275 + } 276 + 277 + static int sky1_reset_assert(struct reset_controller_dev *rcdev, 278 + unsigned long id) 279 + { 280 + sky1_reset_set(rcdev, id, true); 281 + usleep_range(SKY1_RESET_SLEEP_MIN_US, 282 + SKY1_RESET_SLEEP_MAX_US); 283 + return 0; 284 + } 285 + 286 + static int sky1_reset_deassert(struct reset_controller_dev *rcdev, 287 + unsigned long id) 288 + { 289 + sky1_reset_set(rcdev, id, false); 290 + usleep_range(SKY1_RESET_SLEEP_MIN_US, 291 + SKY1_RESET_SLEEP_MAX_US); 292 + return 0; 293 + } 294 + 295 + static int sky1_reset(struct reset_controller_dev *rcdev, 296 + unsigned long id) 297 + { 298 + sky1_reset_assert(rcdev, id); 299 + sky1_reset_deassert(rcdev, id); 300 + return 0; 301 + } 302 + 303 + static int sky1_reset_status(struct reset_controller_dev *rcdev, 304 + unsigned long id) 305 + { 306 + unsigned int value = 0; 307 + struct sky1_src *sky1src = to_sky1_src(rcdev); 308 + const struct sky1_src_signal *signal = &sky1src->signals[id]; 309 + 310 + regmap_read(sky1src->regmap, signal->offset, &value); 311 + return !(value & signal->bit); 312 + } 313 + 314 + static const struct reset_control_ops sky1_src_ops = { 315 + .reset = sky1_reset, 316 + .assert = sky1_reset_assert, 317 + .deassert = sky1_reset_deassert, 318 + .status = sky1_reset_status 319 + }; 320 + 321 + static int sky1_reset_probe(struct platform_device *pdev) 322 + { 323 + struct sky1_src *sky1src; 324 + struct device *dev = &pdev->dev; 325 + const struct sky1_src_variant *variant; 326 + 327 + sky1src = devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL); 328 + if (!sky1src) 329 + return -ENOMEM; 330 + 331 + variant = of_device_get_match_data(dev); 332 + 333 + sky1src->regmap = device_node_to_regmap(dev->of_node); 334 + if (IS_ERR(sky1src->regmap)) { 335 + return dev_err_probe(dev, PTR_ERR(sky1src->regmap), 336 + "Unable to get sky1-src regmap"); 337 + } 338 + 339 + sky1src->signals = variant->signals; 340 + sky1src->rcdev.owner = THIS_MODULE; 341 + sky1src->rcdev.nr_resets = variant->signals_num; 342 + sky1src->rcdev.ops = &sky1_src_ops; 343 + sky1src->rcdev.of_node = dev->of_node; 344 + sky1src->rcdev.dev = dev; 345 + 346 + return devm_reset_controller_register(dev, &sky1src->rcdev); 347 + } 348 + 349 + static const struct of_device_id sky1_sysreg_of_match[] = { 350 + { .compatible = "cix,sky1-system-control", .data = &variant_sky1_fch}, 351 + { .compatible = "cix,sky1-s5-system-control", .data = &variant_sky1}, 352 + {}, 353 + }; 354 + MODULE_DEVICE_TABLE(of, sky1_sysreg_of_match); 355 + 356 + static struct platform_driver sky1_reset_driver = { 357 + .probe = sky1_reset_probe, 358 + .driver = { 359 + .name = "cix,sky1-rst", 360 + .of_match_table = sky1_sysreg_of_match, 361 + }, 362 + }; 363 + module_platform_driver(sky1_reset_driver) 364 + 365 + MODULE_AUTHOR("Jerry Zhu <jerry.zhu@cixtech.com>"); 366 + MODULE_DESCRIPTION("Cix Sky1 reset driver"); 367 + MODULE_LICENSE("GPL");

+4 -8

drivers/reset/reset-sunplus.c

··· 100 100 101 101 struct sp_reset { 102 102 struct reset_controller_dev rcdev; 103 - struct notifier_block notifier; 104 103 void __iomem *base; 105 104 }; 106 105 ··· 153 154 .status = sp_reset_status, 154 155 }; 155 156 156 - static int sp_restart(struct notifier_block *nb, unsigned long mode, 157 - void *cmd) 157 + static int sp_restart(struct sys_off_data *data) 158 158 { 159 - struct sp_reset *reset = container_of(nb, struct sp_reset, notifier); 159 + struct sp_reset *reset = data->cb_data; 160 160 161 161 sp_reset_assert(&reset->rcdev, 0); 162 162 sp_reset_deassert(&reset->rcdev, 0); ··· 187 189 if (ret) 188 190 return ret; 189 191 190 - reset->notifier.notifier_call = sp_restart; 191 - reset->notifier.priority = 192; 192 - 193 - return register_restart_handler(&reset->notifier); 192 + return devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, 193 + 192, sp_restart, reset); 194 194 } 195 195 196 196 static const struct of_device_id sp_reset_dt_ids[] = {

+36 -24

drivers/reset/spacemit/reset-spacemit-k3.c

··· 112 112 [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), 113 113 [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), 114 114 [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), 115 - [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 116 - BIT(1)|BIT(2)|BIT(3)), 117 - [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 118 - BIT(5)|BIT(6)|BIT(7)), 119 - [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 120 - BIT(9)|BIT(10)|BIT(11)), 121 - [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 122 - BIT(13)|BIT(14)|BIT(15)), 123 - [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 124 - BIT(17)|BIT(18)|BIT(19)), 115 + [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), 116 + [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), 117 + [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), 118 + [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), 119 + [RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)), 120 + [RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)), 121 + [RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)), 122 + [RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)), 123 + [RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)), 124 + [RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)), 125 + [RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)), 126 + [RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)), 127 + [RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)), 128 + [RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)), 129 + [RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)), 125 130 [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), 126 131 [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), 127 132 [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), ··· 156 151 [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), 157 152 [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), 158 153 [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), 159 - [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, 160 - BIT(1) | BIT(2) | BIT(3), 0), 161 - [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, 162 - BIT(3) | BIT(2) | BIT(0)), 154 + [RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0), 155 + [RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0), 156 + [RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0), 157 + [RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)), 158 + [RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)), 159 + [RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)), 163 160 [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), 164 161 [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), 165 162 [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), ··· 171 164 [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), 172 165 [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), 173 166 [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), 174 - [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, 175 - BIT(5) | BIT(4) | BIT(3)), 176 - [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, 177 - BIT(5) | BIT(4) | BIT(3)), 178 - [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, 179 - BIT(5) | BIT(4) | BIT(3)), 180 - [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, 181 - BIT(5) | BIT(4) | BIT(3)), 182 - [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, 183 - BIT(5) | BIT(4) | BIT(3)), 167 + [RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)), 168 + [RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)), 169 + [RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)), 170 + [RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)), 171 + [RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)), 172 + [RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)), 173 + [RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)), 174 + [RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)), 175 + [RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)), 176 + [RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)), 177 + [RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)), 178 + [RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)), 179 + [RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)), 180 + [RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)), 181 + [RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)), 184 182 [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), 185 183 [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), 186 184 [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)),

+2 -7

drivers/reset/sti/reset-syscfg.c

··· 41 41 struct syscfg_reset_controller { 42 42 struct reset_controller_dev rst; 43 43 bool active_low; 44 - struct syscfg_reset_channel *channels; 44 + struct syscfg_reset_channel channels[]; 45 45 }; 46 46 47 47 #define to_syscfg_reset_controller(_rst) \ ··· 135 135 struct syscfg_reset_controller *rc; 136 136 int i, err; 137 137 138 - rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL); 138 + rc = devm_kzalloc(dev, struct_size(rc, channels, data->nr_channels), GFP_KERNEL); 139 139 if (!rc) 140 - return -ENOMEM; 141 - 142 - rc->channels = devm_kcalloc(dev, data->nr_channels, 143 - sizeof(*rc->channels), GFP_KERNEL); 144 - if (!rc->channels) 145 140 return -ENOMEM; 146 141 147 142 rc->rst.ops = &syscfg_reset_ops;

+163

include/dt-bindings/reset/cix,sky1-s5-system-control.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* Author: Jerry Zhu <jerry.zhu@cixtech.com> */ 3 + #ifndef DT_BINDING_RESET_CIX_SKY1_S5_SYSTEM_CONTROL_H 4 + #define DT_BINDING_RESET_CIX_SKY1_S5_SYSTEM_CONTROL_H 5 + 6 + /* reset for csu_pm */ 7 + #define SKY1_CSU_PM_RESET_N 0 8 + #define SKY1_SENSORFUSION_RESET_N 1 9 + #define SKY1_SENSORFUSION_NOC_RESET_N 2 10 + 11 + /* reset group0 for s0 domain modules */ 12 + #define SKY1_DDRC_RESET_N 3 13 + #define SKY1_GIC_RESET_N 4 14 + #define SKY1_CI700_RESET_N 5 15 + #define SKY1_SYS_NI700_RESET_N 6 16 + #define SKY1_MM_NI700_RESET_N 7 17 + #define SKY1_PCIE_NI700_RESET_N 8 18 + #define SKY1_GPU_RESET_N 9 19 + #define SKY1_NPUTOP_RESET_N 10 20 + #define SKY1_NPUCORE0_RESET_N 11 21 + #define SKY1_NPUCORE1_RESET_N 12 22 + #define SKY1_NPUCORE2_RESET_N 13 23 + #define SKY1_VPU_RESET_N 14 24 + #define SKY1_ISP_SRESET_N 15 25 + #define SKY1_ISP_ARESET_N 16 26 + #define SKY1_ISP_HRESET_N 17 27 + #define SKY1_ISP_GDCRESET_N 18 28 + #define SKY1_DPU_RESET0_N 19 29 + #define SKY1_DPU_RESET1_N 20 30 + #define SKY1_DPU_RESET2_N 21 31 + #define SKY1_DPU_RESET3_N 22 32 + #define SKY1_DPU_RESET4_N 23 33 + #define SKY1_DP_RESET0_N 24 34 + #define SKY1_DP_RESET1_N 25 35 + #define SKY1_DP_RESET2_N 26 36 + #define SKY1_DP_RESET3_N 27 37 + #define SKY1_DP_RESET4_N 28 38 + #define SKY1_DP_PHY_RST_N 29 39 + 40 + /* reset group1 for s0 domain modules */ 41 + #define SKY1_AUDIO_HIFI5_RESET_N 30 42 + #define SKY1_AUDIO_HIFI5_NOC_RESET_N 31 43 + #define SKY1_CSIDPHY_PRST0_N 32 44 + #define SKY1_CSIDPHY_CMNRST0_N 33 45 + #define SKY1_CSI0_RST_N 34 46 + #define SKY1_CSIDPHY_PRST1_N 35 47 + #define SKY1_CSIDPHY_CMNRST1_N 36 48 + #define SKY1_CSI1_RST_N 37 49 + #define SKY1_CSI2_RST_N 38 50 + #define SKY1_CSI3_RST_N 39 51 + #define SKY1_CSIBRDGE0_RST_N 40 52 + #define SKY1_CSIBRDGE1_RST_N 41 53 + #define SKY1_CSIBRDGE2_RST_N 42 54 + #define SKY1_CSIBRDGE3_RST_N 43 55 + #define SKY1_GMAC0_RST_N 44 56 + #define SKY1_GMAC1_RST_N 45 57 + #define SKY1_PCIE0_RESET_N 46 58 + #define SKY1_PCIE1_RESET_N 47 59 + #define SKY1_PCIE2_RESET_N 48 60 + #define SKY1_PCIE3_RESET_N 49 61 + #define SKY1_PCIE4_RESET_N 50 62 + 63 + /* reset group1 for usb phys */ 64 + #define SKY1_USB_DP_PHY0_PRST_N 51 65 + #define SKY1_USB_DP_PHY1_PRST_N 52 66 + #define SKY1_USB_DP_PHY2_PRST_N 53 67 + #define SKY1_USB_DP_PHY3_PRST_N 54 68 + #define SKY1_USB_DP_PHY0_RST_N 55 69 + #define SKY1_USB_DP_PHY1_RST_N 56 70 + #define SKY1_USB_DP_PHY2_RST_N 57 71 + #define SKY1_USB_DP_PHY3_RST_N 58 72 + #define SKY1_USBPHY_SS_PST_N 59 73 + #define SKY1_USBPHY_SS_RST_N 60 74 + #define SKY1_USBPHY_HS0_PRST_N 61 75 + #define SKY1_USBPHY_HS1_PRST_N 62 76 + #define SKY1_USBPHY_HS2_PRST_N 63 77 + #define SKY1_USBPHY_HS3_PRST_N 64 78 + #define SKY1_USBPHY_HS4_PRST_N 65 79 + #define SKY1_USBPHY_HS5_PRST_N 66 80 + #define SKY1_USBPHY_HS6_PRST_N 67 81 + #define SKY1_USBPHY_HS7_PRST_N 68 82 + #define SKY1_USBPHY_HS8_PRST_N 69 83 + #define SKY1_USBPHY_HS9_PRST_N 70 84 + 85 + /* reset group1 for usb controllers */ 86 + #define SKY1_USBC_SS0_PRST_N 71 87 + #define SKY1_USBC_SS1_PRST_N 72 88 + #define SKY1_USBC_SS2_PRST_N 73 89 + #define SKY1_USBC_SS3_PRST_N 74 90 + #define SKY1_USBC_SS4_PRST_N 75 91 + #define SKY1_USBC_SS5_PRST_N 76 92 + #define SKY1_USBC_SS0_RST_N 77 93 + #define SKY1_USBC_SS1_RST_N 78 94 + #define SKY1_USBC_SS2_RST_N 79 95 + #define SKY1_USBC_SS3_RST_N 80 96 + #define SKY1_USBC_SS4_RST_N 81 97 + #define SKY1_USBC_SS5_RST_N 82 98 + #define SKY1_USBC_HS0_PRST_N 83 99 + #define SKY1_USBC_HS1_PRST_N 84 100 + #define SKY1_USBC_HS2_PRST_N 85 101 + #define SKY1_USBC_HS3_PRST_N 86 102 + #define SKY1_USBC_HS0_RST_N 87 103 + #define SKY1_USBC_HS1_RST_N 88 104 + #define SKY1_USBC_HS2_RST_N 89 105 + #define SKY1_USBC_HS3_RST_N 90 106 + 107 + /* reset group0 for rcsu */ 108 + #define SKY1_AUDIO_RCSU_RESET_N 91 109 + #define SKY1_CI700_RCSU_RESET_N 92 110 + #define SKY1_CSI_RCSU0_RESET_N 93 111 + #define SKY1_CSI_RCSU1_RESET_N 94 112 + #define SKY1_CSU_PM_RCSU_RESET_N 95 113 + #define SKY1_DDR_BROADCAST_RCSU_RESET_N 96 114 + #define SKY1_DDR_CTRL_RCSU_0_RESET_N 97 115 + #define SKY1_DDR_CTRL_RCSU_1_RESET_N 98 116 + #define SKY1_DDR_CTRL_RCSU_2_RESET_N 99 117 + #define SKY1_DDR_CTRL_RCSU_3_RESET_N 100 118 + #define SKY1_DDR_TZC400_RCSU_0_RESET_N 101 119 + #define SKY1_DDR_TZC400_RCSU_1_RESET_N 102 120 + #define SKY1_DDR_TZC400_RCSU_2_RESET_N 103 121 + #define SKY1_DDR_TZC400_RCSU_3_RESET_N 104 122 + #define SKY1_DP0_RCSU_RESET_N 105 123 + #define SKY1_DP1_RCSU_RESET_N 106 124 + #define SKY1_DP2_RCSU_RESET_N 107 125 + #define SKY1_DP3_RCSU_RESET_N 108 126 + #define SKY1_DP4_RCSU_RESET_N 109 127 + #define SKY1_DPU0_RCSU_RESET_N 110 128 + #define SKY1_DPU1_RCSU_RESET_N 111 129 + #define SKY1_DPU2_RCSU_RESET_N 112 130 + #define SKY1_DPU3_RCSU_RESET_N 113 131 + #define SKY1_DPU4_RCSU_RESET_N 114 132 + #define SKY1_DSU_RCSU_RESET_N 115 133 + #define SKY1_FCH_RCSU_RESET_N 116 134 + #define SKY1_GICD_RCSU_RESET_N 117 135 + #define SKY1_GMAC_RCSU_RESET_N 118 136 + #define SKY1_GPU_RCSU_RESET_N 119 137 + #define SKY1_ISP_RCSU0_RESET_N 120 138 + #define SKY1_ISP_RCSU1_RESET_N 121 139 + #define SKY1_NI700_MMHUB_RCSU_RESET_N 122 140 + 141 + /* reset group1 for rcsu */ 142 + #define SKY1_NPU_RCSU_RESET_N 123 143 + #define SKY1_NI700_PCIE_RCSU_RESET_N 124 144 + #define SKY1_PCIE_X421_RCSU_RESET_N 125 145 + #define SKY1_PCIE_X8_RCSU_RESET_N 126 146 + #define SKY1_SF_RCSU_RESET_N 127 147 + #define SKY1_RCSU_SMMU_MMHUB_RESET_N 128 148 + #define SKY1_RCSU_SMMU_PCIEHUB_RESET_N 129 149 + #define SKY1_RCSU_SYSHUB_RESET_N 130 150 + #define SKY1_NI700_SMN_RCSU_RESET_N 131 151 + #define SKY1_NI700_SYSHUB_RCSU_RESET_N 132 152 + #define SKY1_RCSU_USB2_HOST0_RESET_N 133 153 + #define SKY1_RCSU_USB2_HOST1_RESET_N 134 154 + #define SKY1_RCSU_USB2_HOST2_RESET_N 135 155 + #define SKY1_RCSU_USB2_HOST3_RESET_N 136 156 + #define SKY1_RCSU_USB3_TYPEA_DRD_RESET_N 137 157 + #define SKY1_RCSU_USB3_TYPEC_DRD_RESET_N 138 158 + #define SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N 139 159 + #define SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N 140 160 + #define SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N 141 161 + #define SKY1_VPU_RCSU_RESET_N 142 162 + 163 + #endif

+41

include/dt-bindings/reset/cix,sky1-system-control.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* Author: Jerry Zhu <jerry.zhu@cixtech.com> */ 3 + #ifndef DT_BINDING_RESET_CIX_SKY1_SYSTEM_CONTROL_H 4 + #define DT_BINDING_RESET_CIX_SKY1_SYSTEM_CONTROL_H 5 + 6 + /* func reset for sky1 fch */ 7 + #define SW_I3C0_RST_FUNC_G_N 0 8 + #define SW_I3C0_RST_FUNC_I_N 1 9 + #define SW_I3C1_RST_FUNC_G_N 2 10 + #define SW_I3C1_RST_FUNC_I_N 3 11 + #define SW_UART0_RST_FUNC_N 4 12 + #define SW_UART1_RST_FUNC_N 5 13 + #define SW_UART2_RST_FUNC_N 6 14 + #define SW_UART3_RST_FUNC_N 7 15 + #define SW_TIMER_RST_FUNC_N 8 16 + 17 + /* apb reset for sky1 fch */ 18 + #define SW_I3C0_RST_APB_N 9 19 + #define SW_I3C1_RST_APB_N 10 20 + #define SW_DMA_RST_AXI_N 11 21 + #define SW_UART0_RST_APB_N 12 22 + #define SW_UART1_RST_APB_N 13 23 + #define SW_UART2_RST_APB_N 14 24 + #define SW_UART3_RST_APB_N 15 25 + #define SW_SPI0_RST_APB_N 16 26 + #define SW_SPI1_RST_APB_N 17 27 + #define SW_I2C0_RST_APB_N 18 28 + #define SW_I2C1_RST_APB_N 19 29 + #define SW_I2C2_RST_APB_N 20 30 + #define SW_I2C3_RST_APB_N 21 31 + #define SW_I2C4_RST_APB_N 22 32 + #define SW_I2C5_RST_APB_N 23 33 + #define SW_I2C6_RST_APB_N 24 34 + #define SW_I2C7_RST_APB_N 25 35 + #define SW_GPIO_RST_APB_N 26 36 + 37 + /* fch rst for xspi */ 38 + #define SW_XSPI_REG_RST_N 27 39 + #define SW_XSPI_SYS_RST_N 28 40 + 41 + #endif

+36 -12

include/dt-bindings/reset/spacemit,k3-resets.h

··· 97 97 #define RESET_APMU_SDH0 13 98 98 #define RESET_APMU_SDH1 14 99 99 #define RESET_APMU_SDH2 15 100 - #define RESET_APMU_USB2 16 101 - #define RESET_APMU_USB3_PORTA 17 102 - #define RESET_APMU_USB3_PORTB 18 103 - #define RESET_APMU_USB3_PORTC 19 104 - #define RESET_APMU_USB3_PORTD 20 100 + #define RESET_APMU_USB2_AHB 16 101 + #define RESET_APMU_USB2_VCC 17 102 + #define RESET_APMU_USB2_PHY 18 103 + #define RESET_APMU_USB3_A_AHB 19 104 + #define RESET_APMU_USB3_A_VCC 20 105 105 #define RESET_APMU_QSPI 21 106 106 #define RESET_APMU_QSPI_BUS 22 107 107 #define RESET_APMU_DMA 23 ··· 132 132 #define RESET_APMU_CPU7_SW 48 133 133 #define RESET_APMU_C1_MPSUB_SW 49 134 134 #define RESET_APMU_MPSUB_DBG 50 135 - #define RESET_APMU_UCIE 51 136 - #define RESET_APMU_RCPU 52 135 + #define RESET_APMU_USB3_A_PHY 51 /* USB3 A */ 136 + #define RESET_APMU_USB3_B_AHB 52 137 137 #define RESET_APMU_DSI4LN2_ESCCLK 53 138 138 #define RESET_APMU_DSI4LN2_LCD_SW 54 139 139 #define RESET_APMU_DSI4LN2_LCD_MCLK 55 ··· 143 143 #define RESET_APMU_UFS_ACLK 59 144 144 #define RESET_APMU_EDP0 60 145 145 #define RESET_APMU_EDP1 61 146 - #define RESET_APMU_PCIE_PORTA 62 147 - #define RESET_APMU_PCIE_PORTB 63 148 - #define RESET_APMU_PCIE_PORTC 64 149 - #define RESET_APMU_PCIE_PORTD 65 150 - #define RESET_APMU_PCIE_PORTE 66 146 + #define RESET_APMU_USB3_B_VCC 62 /* USB3 B */ 147 + #define RESET_APMU_USB3_B_PHY 63 148 + #define RESET_APMU_USB3_C_AHB 64 149 + #define RESET_APMU_USB3_C_VCC 65 150 + #define RESET_APMU_USB3_C_PHY 66 151 151 #define RESET_APMU_EMAC0 67 152 152 #define RESET_APMU_EMAC1 68 153 153 #define RESET_APMU_EMAC2 69 154 154 #define RESET_APMU_ESPI_MCLK 70 155 155 #define RESET_APMU_ESPI_SCLK 71 156 + #define RESET_APMU_USB3_D_AHB 72 /* USB3 D */ 157 + #define RESET_APMU_USB3_D_VCC 73 158 + #define RESET_APMU_USB3_D_PHY 74 159 + #define RESET_APMU_UCIE_IP 75 160 + #define RESET_APMU_UCIE_HOT 76 161 + #define RESET_APMU_UCIE_MON 77 162 + #define RESET_APMU_RCPU_AUDIO_SYS 78 163 + #define RESET_APMU_RCPU_MCU_CORE 79 164 + #define RESET_APMU_RCPU_AUDIO_APMU 80 165 + #define RESET_APMU_PCIE_A_DBI 81 166 + #define RESET_APMU_PCIE_A_SLAVE 82 167 + #define RESET_APMU_PCIE_A_MASTER 83 168 + #define RESET_APMU_PCIE_B_DBI 84 169 + #define RESET_APMU_PCIE_B_SLAVE 85 170 + #define RESET_APMU_PCIE_B_MASTER 86 171 + #define RESET_APMU_PCIE_C_DBI 87 172 + #define RESET_APMU_PCIE_C_SLAVE 88 173 + #define RESET_APMU_PCIE_C_MASTER 89 174 + #define RESET_APMU_PCIE_D_DBI 90 175 + #define RESET_APMU_PCIE_D_SLAVE 91 176 + #define RESET_APMU_PCIE_D_MASTER 92 177 + #define RESET_APMU_PCIE_E_DBI 93 178 + #define RESET_APMU_PCIE_E_SLAVE 94 179 + #define RESET_APMU_PCIE_E_MASTER 95 156 180 157 181 /* DCIU resets*/ 158 182 #define RESET_DCIU_HDMA 0

+15 -6

include/linux/reset-controller.h

··· 3 3 #define _LINUX_RESET_CONTROLLER_H_ 4 4 5 5 #include <linux/list.h> 6 + #include <linux/mutex.h> 6 7 8 + struct fwnode_handle; 9 + struct fwnode_reference_args; 7 10 struct reset_controller_dev; 8 11 9 12 /** ··· 38 35 * @reset_control_head: head of internal list of requested reset controls 39 36 * @dev: corresponding driver model device struct 40 37 * @of_node: corresponding device tree node as phandle target 41 - * @of_args: for reset-gpios controllers: corresponding phandle args with 42 - * of_node and GPIO number complementing of_node; either this or 43 - * of_node should be present 44 38 * @of_reset_n_cells: number of cells in reset line specifiers 45 39 * @of_xlate: translation function to translate from specifier as found in the 46 - * device tree to id as given to the reset control ops, defaults 47 - * to :c:func:`of_reset_simple_xlate`. 40 + * device tree to id as given to the reset control ops 41 + * @fwnode: firmware node associated with this device 42 + * @fwnode_reset_n_cells: number of cells in reset line specifiers 43 + * @fwnode_xlate: translation function to translate from firmware specifier to 44 + * id as given to the reset control ops, defaults to 45 + * :c:func:`fwnode_reset_simple_xlate` 48 46 * @nr_resets: number of reset controls in this reset controller device 47 + * @lock: protects the reset control list from concurrent access 49 48 */ 50 49 struct reset_controller_dev { 51 50 const struct reset_control_ops *ops; ··· 56 51 struct list_head reset_control_head; 57 52 struct device *dev; 58 53 struct device_node *of_node; 59 - const struct of_phandle_args *of_args; 60 54 int of_reset_n_cells; 61 55 int (*of_xlate)(struct reset_controller_dev *rcdev, 62 56 const struct of_phandle_args *reset_spec); 57 + struct fwnode_handle *fwnode; 58 + int fwnode_reset_n_cells; 59 + int (*fwnode_xlate)(struct reset_controller_dev *rcdev, 60 + const struct fwnode_reference_args *reset_spec); 63 61 unsigned int nr_resets; 62 + struct mutex lock; 64 63 }; 65 64 66 65 #if IS_ENABLED(CONFIG_RESET_CONTROLLER)

+28 -15

include/linux/reset.h

··· 5 5 #include <linux/bits.h> 6 6 #include <linux/err.h> 7 7 #include <linux/errno.h> 8 + #include <linux/of.h> 8 9 #include <linux/types.h> 9 10 10 11 struct device; 11 12 struct device_node; 13 + struct fwnode_handle; 12 14 struct reset_control; 13 15 14 16 /** ··· 86 84 int reset_control_bulk_acquire(int num_rstcs, struct reset_control_bulk_data *rstcs); 87 85 void reset_control_bulk_release(int num_rstcs, struct reset_control_bulk_data *rstcs); 88 86 89 - struct reset_control *__of_reset_control_get(struct device_node *node, 87 + struct reset_control *__fwnode_reset_control_get(struct fwnode_handle *fwnode, 90 88 const char *id, int index, enum reset_control_flags flags); 91 89 struct reset_control *__reset_control_get(struct device *dev, const char *id, 92 90 int index, enum reset_control_flags flags); ··· 105 103 106 104 struct reset_control *devm_reset_control_array_get(struct device *dev, 107 105 enum reset_control_flags flags); 108 - struct reset_control *of_reset_control_array_get(struct device_node *np, enum reset_control_flags); 106 + struct reset_control *fwnode_reset_control_array_get(struct fwnode_handle *fwnode, 107 + enum reset_control_flags); 109 108 110 109 int reset_control_get_count(struct device *dev); 111 110 ··· 155 152 return optional ? 0 : -ENOTSUPP; 156 153 } 157 154 158 - static inline struct reset_control *__of_reset_control_get( 159 - struct device_node *node, 155 + static inline struct reset_control *__fwnode_reset_control_get( 156 + struct fwnode_handle *fwnode, 160 157 const char *id, int index, enum reset_control_flags flags) 161 158 { 162 159 bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL; ··· 245 242 } 246 243 247 244 static inline struct reset_control * 248 - of_reset_control_array_get(struct device_node *np, enum reset_control_flags flags) 245 + fwnode_reset_control_array_get(struct fwnode_handle *fwnode, enum reset_control_flags flags) 249 246 { 250 247 bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL; 251 248 ··· 503 500 static inline struct reset_control *of_reset_control_get_exclusive( 504 501 struct device_node *node, const char *id) 505 502 { 506 - return __of_reset_control_get(node, id, 0, RESET_CONTROL_EXCLUSIVE); 503 + return __fwnode_reset_control_get(of_fwnode_handle(node), id, 0, 504 + RESET_CONTROL_EXCLUSIVE); 507 505 } 508 506 509 507 /** ··· 524 520 static inline struct reset_control *of_reset_control_get_optional_exclusive( 525 521 struct device_node *node, const char *id) 526 522 { 527 - return __of_reset_control_get(node, id, 0, RESET_CONTROL_OPTIONAL_EXCLUSIVE); 523 + return __fwnode_reset_control_get(of_fwnode_handle(node), id, 0, 524 + RESET_CONTROL_OPTIONAL_EXCLUSIVE); 528 525 } 529 526 530 527 /** ··· 550 545 static inline struct reset_control *of_reset_control_get_shared( 551 546 struct device_node *node, const char *id) 552 547 { 553 - return __of_reset_control_get(node, id, 0, RESET_CONTROL_SHARED); 548 + return __fwnode_reset_control_get(of_fwnode_handle(node), id, 0, 549 + RESET_CONTROL_SHARED); 554 550 } 555 551 556 552 /** ··· 568 562 static inline struct reset_control *of_reset_control_get_exclusive_by_index( 569 563 struct device_node *node, int index) 570 564 { 571 - return __of_reset_control_get(node, NULL, index, RESET_CONTROL_EXCLUSIVE); 565 + return __fwnode_reset_control_get(of_fwnode_handle(node), NULL, index, 566 + RESET_CONTROL_EXCLUSIVE); 572 567 } 573 568 574 569 /** ··· 597 590 static inline struct reset_control *of_reset_control_get_shared_by_index( 598 591 struct device_node *node, int index) 599 592 { 600 - return __of_reset_control_get(node, NULL, index, RESET_CONTROL_SHARED); 593 + return __fwnode_reset_control_get(of_fwnode_handle(node), NULL, index, 594 + RESET_CONTROL_SHARED); 601 595 } 602 596 603 597 /** ··· 1040 1032 static inline struct reset_control * 1041 1033 of_reset_control_array_get_exclusive(struct device_node *node) 1042 1034 { 1043 - return of_reset_control_array_get(node, RESET_CONTROL_EXCLUSIVE); 1035 + return fwnode_reset_control_array_get(of_fwnode_handle(node), 1036 + RESET_CONTROL_EXCLUSIVE); 1044 1037 } 1045 1038 1046 1039 static inline struct reset_control * 1047 1040 of_reset_control_array_get_exclusive_released(struct device_node *node) 1048 1041 { 1049 - return of_reset_control_array_get(node, RESET_CONTROL_EXCLUSIVE_RELEASED); 1042 + return fwnode_reset_control_array_get(of_fwnode_handle(node), 1043 + RESET_CONTROL_EXCLUSIVE_RELEASED); 1050 1044 } 1051 1045 1052 1046 static inline struct reset_control * 1053 1047 of_reset_control_array_get_shared(struct device_node *node) 1054 1048 { 1055 - return of_reset_control_array_get(node, RESET_CONTROL_SHARED); 1049 + return fwnode_reset_control_array_get(of_fwnode_handle(node), 1050 + RESET_CONTROL_SHARED); 1056 1051 } 1057 1052 1058 1053 static inline struct reset_control * 1059 1054 of_reset_control_array_get_optional_exclusive(struct device_node *node) 1060 1055 { 1061 - return of_reset_control_array_get(node, RESET_CONTROL_OPTIONAL_EXCLUSIVE); 1056 + return fwnode_reset_control_array_get(of_fwnode_handle(node), 1057 + RESET_CONTROL_OPTIONAL_EXCLUSIVE); 1062 1058 } 1063 1059 1064 1060 static inline struct reset_control * 1065 1061 of_reset_control_array_get_optional_shared(struct device_node *node) 1066 1062 { 1067 - return of_reset_control_array_get(node, RESET_CONTROL_OPTIONAL_SHARED); 1063 + return fwnode_reset_control_array_get(of_fwnode_handle(node), 1064 + RESET_CONTROL_OPTIONAL_SHARED); 1068 1065 } 1069 1066 #endif

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