Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: octeontx2 - Rework how engine group number is obtained
By default, otx2_cpt_get_kcrypto_eng_grp_num() returns the engine group
number of SE engine type. Add an engine type parameter to support
retrieving the engine group number for different engine types.
Since otx2_cpt_get_kcrypto_eng_grp_num() always returns the kernel crypto
engine group number, rename it to otx2_cpt_get_eng_grp_num().
Signed-off-by: Amit Singh Tomar <amitsinght@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Amit Singh Tomar
and committed by
Herbert Xu
fbfe4f47
71203f68
+28
-13
+2
-1
drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
+2
-1
drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
···
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int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
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int cpu_num);
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void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe);
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-
int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev);
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+
int otx2_cpt_get_eng_grp_num(struct pci_dev *pdev,
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enum otx2_cpt_eng_type);
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#endif /* __OTX2_CPT_REQMGR_H */
+1
-1
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+1
-1
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
···
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struct cpt_hw_ops *ops;
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u8 are_lfs_attached; /* Whether CPT LFs are attached */
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u8 lfs_num; /* Number of CPT LFs */
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-
u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */
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u8 kcrypto_se_eng_grp_num; /* Crypto symmetric engine group number */
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u8 kvf_limits; /* Kernel crypto limits */
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atomic_t state; /* LF's state. started/reset */
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int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */
+4
-2
drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c
+4
-2
drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c
···
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req_info->req_type = OTX2_CPT_ENC_DEC_REQ;
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req_info->is_enc = enc;
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req_info->is_trunc_hmac = false;
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-
req_info->ctrl.s.grp = otx2_cpt_get_kcrypto_eng_grp_num(pdev);
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+
req_info->ctrl.s.grp = otx2_cpt_get_eng_grp_num(pdev,
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OTX2_CPT_SE_TYPES);
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req_info->req.cptr = ctx->er_ctx.hw_ctx;
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req_info->req.cptr_dma = ctx->er_ctx.cptr_dma;
···
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if (status)
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return status;
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-
req_info->ctrl.s.grp = otx2_cpt_get_kcrypto_eng_grp_num(pdev);
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+
req_info->ctrl.s.grp = otx2_cpt_get_eng_grp_num(pdev,
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+
OTX2_CPT_SE_TYPES);
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/*
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* We perform an asynchronous send and once
+7
-6
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+7
-6
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
···
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u8 eng_grp_msk;
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/* Get engine group number for symmetric crypto */
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-
cptvf->lfs.kcrypto_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;
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+
cptvf->lfs.kcrypto_se_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;
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ret = otx2_cptvf_send_eng_grp_num_msg(cptvf, OTX2_CPT_SE_TYPES);
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if (ret)
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return ret;
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-
if (cptvf->lfs.kcrypto_eng_grp_num == OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {
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-
dev_err(dev, "Engine group for kernel crypto not available\n");
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-
ret = -ENOENT;
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-
return ret;
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+
if (cptvf->lfs.kcrypto_se_eng_grp_num ==
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OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {
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dev_err(dev,
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"Symmetric Engine group for crypto not available\n");
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return -ENOENT;
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}
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-
eng_grp_msk = 1 << cptvf->lfs.kcrypto_eng_grp_num;
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eng_grp_msk = 1 << cptvf->lfs.kcrypto_se_eng_grp_num;
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ret = otx2_cptvf_send_kvf_limits_msg(cptvf);
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if (ret)
+4
-1
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
+4
-1
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
···
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struct otx2_cpt_caps_rsp *eng_caps;
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struct cpt_rd_wr_reg_msg *rsp_reg;
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struct msix_offset_rsp *rsp_msix;
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+
u8 grp_num;
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int i;
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if (msg->id >= MBOX_MSG_MAX) {
···
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break;
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case MBOX_MSG_GET_ENG_GRP_NUM:
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rsp_grp = (struct otx2_cpt_egrp_num_rsp *) msg;
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-
cptvf->lfs.kcrypto_eng_grp_num = rsp_grp->eng_grp_num;
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+
grp_num = rsp_grp->eng_grp_num;
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if (rsp_grp->eng_type == OTX2_CPT_SE_TYPES)
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cptvf->lfs.kcrypto_se_eng_grp_num = grp_num;
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break;
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case MBOX_MSG_GET_KVF_LIMITS:
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rsp_limits = (struct otx2_cpt_kvf_limits_rsp *) msg;
+10
-2
drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
+10
-2
drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
···
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&wqe->lfs->lf[wqe->lf_num].pqueue);
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}
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-
int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev)
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+
int otx2_cpt_get_eng_grp_num(struct pci_dev *pdev,
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enum otx2_cpt_eng_type eng_type)
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{
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struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev);
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-
return cptvf->lfs.kcrypto_eng_grp_num;
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switch (eng_type) {
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case OTX2_CPT_SE_TYPES:
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return cptvf->lfs.kcrypto_se_eng_grp_num;
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default:
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dev_err(&cptvf->pdev->dev, "Unsupported engine type");
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break;
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}
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return -ENXIO;
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}