Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
regmap: reg_default_cb for flat cache defaults
Merge series from "Sheetal ." <sheetal@nvidia.com>:
This series adds a reg_default_cb callback for REGCACHE_FLAT to provide
defaults for registers not listed in reg_defaults. Defaults are loaded
eagerly during regcache init and the callback can use writeable_reg to
filter valid addresses and avoid holes.
Tegra ASoC drivers set reg_default_cb and add writeable_reg filtering for
AHUB RX holes to prevent invalid addresses from being marked valid.
+240
-1
+3
drivers/base/regmap/internal.h
+3
drivers/base/regmap/internal.h
···
117
117
void *val_buf, size_t val_size);
118
118
int (*write)(void *context, const void *data, size_t count);
119
119
120
+
int (*reg_default_cb)(struct device *dev, unsigned int reg,
121
+
unsigned int *val);
122
+
120
123
unsigned long read_flag_mask;
121
124
unsigned long write_flag_mask;
122
125
+19
drivers/base/regmap/regcache-flat.c
+19
drivers/base/regmap/regcache-flat.c
···
79
79
__set_bit(index, cache->valid);
80
80
}
81
81
82
+
if (map->reg_default_cb) {
83
+
dev_dbg(map->dev,
84
+
"Populating regcache_flat using reg_default_cb callback\n");
85
+
86
+
for (i = 0; i <= map->max_register; i += map->reg_stride) {
87
+
unsigned int index = regcache_flat_get_index(map, i);
88
+
unsigned int value;
89
+
90
+
if (test_bit(index, cache->valid))
91
+
continue;
92
+
93
+
if (map->reg_default_cb(map->dev, i, &value))
94
+
continue;
95
+
96
+
cache->data[index] = value;
97
+
__set_bit(index, cache->valid);
98
+
}
99
+
}
100
+
82
101
return 0;
83
102
}
84
103
+2
-1
drivers/base/regmap/regcache.c
+2
-1
drivers/base/regmap/regcache.c
···
223
223
goto err_free;
224
224
}
225
225
226
-
if (map->num_reg_defaults && map->cache_ops->populate) {
226
+
if (map->cache_ops->populate &&
227
+
(map->num_reg_defaults || map->reg_default_cb)) {
227
228
dev_dbg(map->dev, "Populating %s cache\n", map->cache_ops->name);
228
229
map->lock(map->lock_arg);
229
230
ret = map->cache_ops->populate(map);
+91
drivers/base/regmap/regmap-kunit.c
+91
drivers/base/regmap/regmap-kunit.c
···
15
15
16
16
struct regmap_test_priv {
17
17
struct device *dev;
18
+
bool *reg_default_called;
19
+
unsigned int reg_default_max;
18
20
};
19
21
20
22
struct regmap_test_param {
···
119
117
};
120
118
121
119
KUNIT_ARRAY_PARAM(real_cache_types_only, real_cache_types_only_list, param_to_desc);
120
+
121
+
static const struct regmap_test_param flat_cache_types_list[] = {
122
+
{ .cache = REGCACHE_FLAT, .from_reg = 0 },
123
+
{ .cache = REGCACHE_FLAT, .from_reg = 0, .fast_io = true },
124
+
{ .cache = REGCACHE_FLAT, .from_reg = 0x2001 },
125
+
};
126
+
127
+
KUNIT_ARRAY_PARAM(flat_cache_types, flat_cache_types_list, param_to_desc);
122
128
123
129
static const struct regmap_test_param real_cache_types_list[] = {
124
130
{ .cache = REGCACHE_FLAT, .from_reg = 0 },
···
256
246
const struct regmap_test_param *param = test->param_value;
257
247
258
248
return reg != (param->from_reg + 5);
249
+
}
250
+
251
+
static unsigned int reg_default_expected(unsigned int reg)
252
+
{
253
+
return 0x5a5a0000 | (reg & 0xffff);
254
+
}
255
+
256
+
static int reg_default_test_cb(struct device *dev, unsigned int reg,
257
+
unsigned int *def)
258
+
{
259
+
struct kunit *test = dev_get_drvdata(dev);
260
+
struct regmap_test_priv *priv = test->priv;
261
+
262
+
if (priv && priv->reg_default_called && reg <= priv->reg_default_max)
263
+
priv->reg_default_called[reg] = true;
264
+
265
+
*def = reg_default_expected(reg);
266
+
return 0;
267
+
}
268
+
269
+
static void expect_reg_default_value(struct kunit *test, struct regmap *map,
270
+
struct regmap_ram_data *data,
271
+
struct regmap_test_priv *priv,
272
+
unsigned int reg)
273
+
{
274
+
unsigned int val;
275
+
276
+
KUNIT_EXPECT_TRUE(test, priv->reg_default_called[reg]);
277
+
KUNIT_EXPECT_EQ(test, 0, regmap_read(map, reg, &val));
278
+
KUNIT_EXPECT_EQ(test, reg_default_expected(reg), val);
279
+
KUNIT_EXPECT_FALSE(test, data->read[reg]);
259
280
}
260
281
261
282
static void basic_read_write(struct kunit *test)
···
667
626
/* The data should have been read from cache if there was one */
668
627
for (i = 0; i < BLOCK_TEST_SIZE; i++)
669
628
KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
629
+
}
630
+
631
+
static void reg_default_callback_populates_flat_cache(struct kunit *test)
632
+
{
633
+
const struct regmap_test_param *param = test->param_value;
634
+
struct regmap_test_priv *priv = test->priv;
635
+
struct regmap *map;
636
+
struct regmap_config config;
637
+
struct regmap_ram_data *data;
638
+
unsigned int reg, val;
639
+
unsigned int defaults_end;
640
+
641
+
config = test_regmap_config;
642
+
config.num_reg_defaults = 3;
643
+
config.max_register = param->from_reg + BLOCK_TEST_SIZE - 1;
644
+
config.reg_default_cb = reg_default_test_cb;
645
+
646
+
priv->reg_default_max = config.max_register;
647
+
priv->reg_default_called = kunit_kcalloc(test, config.max_register + 1,
648
+
sizeof(*priv->reg_default_called),
649
+
GFP_KERNEL);
650
+
KUNIT_ASSERT_NOT_NULL(test, priv->reg_default_called);
651
+
652
+
map = gen_regmap(test, &config, &data);
653
+
KUNIT_ASSERT_FALSE(test, IS_ERR(map));
654
+
if (IS_ERR(map))
655
+
return;
656
+
657
+
for (reg = 0; reg <= config.max_register; reg++)
658
+
data->read[reg] = false;
659
+
660
+
defaults_end = param->from_reg + config.num_reg_defaults - 1;
661
+
662
+
for (reg = param->from_reg; reg <= defaults_end; reg++) {
663
+
KUNIT_EXPECT_FALSE(test, priv->reg_default_called[reg]);
664
+
KUNIT_EXPECT_EQ(test, 0, regmap_read(map, reg, &val));
665
+
KUNIT_EXPECT_EQ(test, data->vals[reg], val);
666
+
KUNIT_EXPECT_FALSE(test, data->read[reg]);
667
+
}
668
+
669
+
if (param->from_reg > 0)
670
+
expect_reg_default_value(test, map, data, priv, 0);
671
+
672
+
if (defaults_end + 1 <= config.max_register)
673
+
expect_reg_default_value(test, map, data, priv, defaults_end + 1);
674
+
675
+
if (config.max_register > defaults_end + 1)
676
+
expect_reg_default_value(test, map, data, priv, config.max_register);
670
677
}
671
678
672
679
static void reg_defaults_read_dev(struct kunit *test)
···
2147
2058
KUNIT_CASE_PARAM(write_readonly, regcache_types_gen_params),
2148
2059
KUNIT_CASE_PARAM(read_writeonly, regcache_types_gen_params),
2149
2060
KUNIT_CASE_PARAM(reg_defaults, regcache_types_gen_params),
2061
+
KUNIT_CASE_PARAM(reg_default_callback_populates_flat_cache,
2062
+
flat_cache_types_gen_params),
2150
2063
KUNIT_CASE_PARAM(reg_defaults_read_dev, regcache_types_gen_params),
2151
2064
KUNIT_CASE_PARAM(register_patch, regcache_types_gen_params),
2152
2065
KUNIT_CASE_PARAM(stride, regcache_types_gen_params),
+2
drivers/base/regmap/regmap.c
+2
drivers/base/regmap/regmap.c
···
813
813
map->precious_reg = config->precious_reg;
814
814
map->writeable_noinc_reg = config->writeable_noinc_reg;
815
815
map->readable_noinc_reg = config->readable_noinc_reg;
816
+
map->reg_default_cb = config->reg_default_cb;
816
817
map->cache_type = config->cache_type;
817
818
818
819
spin_lock_init(&map->async_lock);
···
1436
1435
map->precious_reg = config->precious_reg;
1437
1436
map->writeable_noinc_reg = config->writeable_noinc_reg;
1438
1437
map->readable_noinc_reg = config->readable_noinc_reg;
1438
+
map->reg_default_cb = config->reg_default_cb;
1439
1439
map->cache_type = config->cache_type;
1440
1440
1441
1441
ret = regmap_set_name(map, config);
+14
include/linux/regmap.h
+14
include/linux/regmap.h
···
359
359
* @reg_defaults: Power on reset values for registers (for use with
360
360
* register cache support).
361
361
* @num_reg_defaults: Number of elements in reg_defaults.
362
+
* @reg_default_cb: Optional callback to return default values for registers
363
+
* not listed in reg_defaults. This is only used for
364
+
* REGCACHE_FLAT population; drivers must ensure the readable_reg/
365
+
* writeable_reg callbacks are defined to handle holes.
362
366
*
363
367
* @read_flag_mask: Mask to be set in the top bytes of the register when doing
364
368
* a read.
···
453
449
const struct regmap_access_table *rd_noinc_table;
454
450
const struct reg_default *reg_defaults;
455
451
unsigned int num_reg_defaults;
452
+
int (*reg_default_cb)(struct device *dev, unsigned int reg,
453
+
unsigned int *def);
456
454
enum regcache_type cache_type;
457
455
const void *reg_defaults_raw;
458
456
unsigned int num_reg_defaults_raw;
···
1353
1347
unsigned int mask, unsigned int val)
1354
1348
{
1355
1349
return regmap_update_bits_base(map, reg, mask, val, NULL, false, true);
1350
+
}
1351
+
1352
+
static inline int regmap_default_zero_cb(struct device *dev,
1353
+
unsigned int reg,
1354
+
unsigned int *def)
1355
+
{
1356
+
*def = 0;
1357
+
return 0;
1356
1358
}
1357
1359
1358
1360
int regmap_get_val_bytes(struct regmap *map);
+1
sound/soc/tegra/tegra186_asrc.c
+1
sound/soc/tegra/tegra186_asrc.c
+1
sound/soc/tegra/tegra186_dspk.c
+1
sound/soc/tegra/tegra186_dspk.c
+3
sound/soc/tegra/tegra210_admaif.c
+3
sound/soc/tegra/tegra210_admaif.c
···
241
241
.volatile_reg = tegra_admaif_volatile_reg,
242
242
.reg_defaults = tegra210_admaif_reg_defaults,
243
243
.num_reg_defaults = TEGRA210_ADMAIF_CHANNEL_COUNT * 6 + 1,
244
+
.reg_default_cb = regmap_default_zero_cb,
244
245
.cache_type = REGCACHE_FLAT,
245
246
};
246
247
···
255
254
.volatile_reg = tegra_admaif_volatile_reg,
256
255
.reg_defaults = tegra186_admaif_reg_defaults,
257
256
.num_reg_defaults = TEGRA186_ADMAIF_CHANNEL_COUNT * 6 + 1,
257
+
.reg_default_cb = regmap_default_zero_cb,
258
258
.cache_type = REGCACHE_FLAT,
259
259
};
260
260
···
269
267
.volatile_reg = tegra_admaif_volatile_reg,
270
268
.reg_defaults = tegra264_admaif_reg_defaults,
271
269
.num_reg_defaults = TEGRA264_ADMAIF_CHANNEL_COUNT * 6 + 1,
270
+
.reg_default_cb = regmap_default_zero_cb,
272
271
.cache_type = REGCACHE_FLAT,
273
272
};
274
273
+2
sound/soc/tegra/tegra210_adx.c
+2
sound/soc/tegra/tegra210_adx.c
···
625
625
.volatile_reg = tegra210_adx_volatile_reg,
626
626
.reg_defaults = tegra210_adx_reg_defaults,
627
627
.num_reg_defaults = ARRAY_SIZE(tegra210_adx_reg_defaults),
628
+
.reg_default_cb = regmap_default_zero_cb,
628
629
.cache_type = REGCACHE_FLAT,
629
630
};
630
631
···
639
638
.volatile_reg = tegra264_adx_volatile_reg,
640
639
.reg_defaults = tegra264_adx_reg_defaults,
641
640
.num_reg_defaults = ARRAY_SIZE(tegra264_adx_reg_defaults),
641
+
.reg_default_cb = regmap_default_zero_cb,
642
642
.cache_type = REGCACHE_FLAT,
643
643
};
644
644
+60
sound/soc/tegra/tegra210_ahub.c
+60
sound/soc/tegra/tegra210_ahub.c
···
2049
2049
.num_dapm_routes = ARRAY_SIZE(tegra264_ahub_routes),
2050
2050
};
2051
2051
2052
+
static bool tegra210_ahub_wr_reg(struct device *dev, unsigned int reg)
2053
+
{
2054
+
int part;
2055
+
2056
+
if (reg % TEGRA210_XBAR_RX_STRIDE)
2057
+
return false;
2058
+
2059
+
for (part = 0; part < TEGRA210_XBAR_UPDATE_MAX_REG; part++) {
2060
+
switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) {
2061
+
case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0:
2062
+
case TEGRA210_AXBAR_PART_0_I2S1_RX1_0 ... TEGRA210_AXBAR_PART_0_I2S5_RX1_0:
2063
+
case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0:
2064
+
case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0:
2065
+
case TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 ... TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0:
2066
+
case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0:
2067
+
case TEGRA210_AXBAR_PART_0_OPE1_RX1_0 ... TEGRA210_AXBAR_PART_0_OPE2_RX1_0:
2068
+
case TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0:
2069
+
case TEGRA210_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA210_AXBAR_PART_0_MVC2_RX1_0:
2070
+
case TEGRA210_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA210_AXBAR_PART_0_ADX2_RX1_0:
2071
+
return true;
2072
+
default:
2073
+
break;
2074
+
}
2075
+
}
2076
+
2077
+
return false;
2078
+
}
2079
+
2080
+
static bool tegra186_ahub_wr_reg(struct device *dev, unsigned int reg)
2081
+
{
2082
+
int part;
2083
+
2084
+
if (reg % TEGRA210_XBAR_RX_STRIDE)
2085
+
return false;
2086
+
2087
+
for (part = 0; part < TEGRA186_XBAR_UPDATE_MAX_REG; part++) {
2088
+
switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) {
2089
+
case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA186_AXBAR_PART_0_I2S6_RX1_0:
2090
+
case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0:
2091
+
case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0:
2092
+
case TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 ... TEGRA186_AXBAR_PART_0_DSPK2_RX1_0:
2093
+
case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0:
2094
+
case TEGRA210_AXBAR_PART_0_OPE1_RX1_0:
2095
+
case TEGRA186_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA186_AXBAR_PART_0_MVC2_RX1_0:
2096
+
case TEGRA186_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA186_AXBAR_PART_0_AMX3_RX4_0:
2097
+
case TEGRA210_AXBAR_PART_0_ADX1_RX1_0 ... TEGRA186_AXBAR_PART_0_ASRC1_RX7_0:
2098
+
return true;
2099
+
default:
2100
+
break;
2101
+
}
2102
+
}
2103
+
2104
+
return false;
2105
+
}
2106
+
2052
2107
static bool tegra264_ahub_wr_reg(struct device *dev, unsigned int reg)
2053
2108
{
2054
2109
int part;
···
2131
2076
.reg_bits = 32,
2132
2077
.val_bits = 32,
2133
2078
.reg_stride = 4,
2079
+
.writeable_reg = tegra210_ahub_wr_reg,
2134
2080
.max_register = TEGRA210_MAX_REGISTER_ADDR,
2081
+
.reg_default_cb = regmap_default_zero_cb,
2135
2082
.cache_type = REGCACHE_FLAT,
2136
2083
};
2137
2084
···
2141
2084
.reg_bits = 32,
2142
2085
.val_bits = 32,
2143
2086
.reg_stride = 4,
2087
+
.writeable_reg = tegra186_ahub_wr_reg,
2144
2088
.max_register = TEGRA186_MAX_REGISTER_ADDR,
2089
+
.reg_default_cb = regmap_default_zero_cb,
2145
2090
.cache_type = REGCACHE_FLAT,
2146
2091
};
2147
2092
···
2153
2094
.reg_stride = 4,
2154
2095
.writeable_reg = tegra264_ahub_wr_reg,
2155
2096
.max_register = TEGRA264_MAX_REGISTER_ADDR,
2097
+
.reg_default_cb = regmap_default_zero_cb,
2156
2098
.cache_type = REGCACHE_FLAT,
2157
2099
};
2158
2100
+30
sound/soc/tegra/tegra210_ahub.h
+30
sound/soc/tegra/tegra210_ahub.h
···
68
68
#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \
69
69
(TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
70
70
71
+
/* AXBAR register offsets */
72
+
#define TEGRA186_AXBAR_PART_0_AMX1_RX1_0 0x120
73
+
#define TEGRA186_AXBAR_PART_0_AMX3_RX4_0 0x14c
74
+
#define TEGRA186_AXBAR_PART_0_ASRC1_RX7_0 0x1a8
75
+
#define TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 0xc0
76
+
#define TEGRA186_AXBAR_PART_0_DSPK2_RX1_0 0xc4
77
+
#define TEGRA186_AXBAR_PART_0_I2S6_RX1_0 0x54
78
+
#define TEGRA186_AXBAR_PART_0_MVC1_RX1_0 0x110
79
+
#define TEGRA186_AXBAR_PART_0_MVC2_RX1_0 0x114
80
+
#define TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0 0x24
81
+
#define TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 0x0
82
+
#define TEGRA210_AXBAR_PART_0_ADX1_RX1_0 0x160
83
+
#define TEGRA210_AXBAR_PART_0_ADX2_RX1_0 0x164
84
+
#define TEGRA210_AXBAR_PART_0_AFC1_RX1_0 0xd0
85
+
#define TEGRA210_AXBAR_PART_0_AFC6_RX1_0 0xe4
86
+
#define TEGRA210_AXBAR_PART_0_AMX1_RX1_0 0x140
87
+
#define TEGRA210_AXBAR_PART_0_I2S1_RX1_0 0x40
88
+
#define TEGRA210_AXBAR_PART_0_I2S5_RX1_0 0x50
89
+
#define TEGRA210_AXBAR_PART_0_MIXER1_RX10_0 0xa4
90
+
#define TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 0x80
91
+
#define TEGRA210_AXBAR_PART_0_MVC1_RX1_0 0x120
92
+
#define TEGRA210_AXBAR_PART_0_MVC2_RX1_0 0x124
93
+
#define TEGRA210_AXBAR_PART_0_OPE1_RX1_0 0x100
94
+
#define TEGRA210_AXBAR_PART_0_OPE2_RX1_0 0x104
95
+
#define TEGRA210_AXBAR_PART_0_SFC1_RX1_0 0x60
96
+
#define TEGRA210_AXBAR_PART_0_SFC4_RX1_0 0x6c
97
+
#define TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 0xc0
98
+
#define TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0 0xc4
99
+
#define TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0 0x110
100
+
71
101
#define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
72
102
73
103
#define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
+3
sound/soc/tegra/tegra210_amx.c
+3
sound/soc/tegra/tegra210_amx.c
···
654
654
.volatile_reg = tegra210_amx_volatile_reg,
655
655
.reg_defaults = tegra210_amx_reg_defaults,
656
656
.num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
657
+
.reg_default_cb = regmap_default_zero_cb,
657
658
.cache_type = REGCACHE_FLAT,
658
659
};
659
660
···
668
667
.volatile_reg = tegra210_amx_volatile_reg,
669
668
.reg_defaults = tegra210_amx_reg_defaults,
670
669
.num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
670
+
.reg_default_cb = regmap_default_zero_cb,
671
671
.cache_type = REGCACHE_FLAT,
672
672
};
673
673
···
682
680
.volatile_reg = tegra264_amx_volatile_reg,
683
681
.reg_defaults = tegra264_amx_reg_defaults,
684
682
.num_reg_defaults = ARRAY_SIZE(tegra264_amx_reg_defaults),
683
+
.reg_default_cb = regmap_default_zero_cb,
685
684
.cache_type = REGCACHE_FLAT,
686
685
};
687
686
+1
sound/soc/tegra/tegra210_dmic.c
+1
sound/soc/tegra/tegra210_dmic.c
+2
sound/soc/tegra/tegra210_i2s.c
+2
sound/soc/tegra/tegra210_i2s.c
···
997
997
.volatile_reg = tegra210_i2s_volatile_reg,
998
998
.reg_defaults = tegra210_i2s_reg_defaults,
999
999
.num_reg_defaults = ARRAY_SIZE(tegra210_i2s_reg_defaults),
1000
+
.reg_default_cb = regmap_default_zero_cb,
1000
1001
.cache_type = REGCACHE_FLAT,
1001
1002
};
1002
1003
···
1045
1044
.volatile_reg = tegra264_i2s_volatile_reg,
1046
1045
.reg_defaults = tegra264_i2s_reg_defaults,
1047
1046
.num_reg_defaults = ARRAY_SIZE(tegra264_i2s_reg_defaults),
1047
+
.reg_default_cb = regmap_default_zero_cb,
1048
1048
.cache_type = REGCACHE_FLAT,
1049
1049
};
1050
1050
+1
sound/soc/tegra/tegra210_mbdrc.c
+1
sound/soc/tegra/tegra210_mbdrc.c
+1
sound/soc/tegra/tegra210_mixer.c
+1
sound/soc/tegra/tegra210_mixer.c
+1
sound/soc/tegra/tegra210_mvc.c
+1
sound/soc/tegra/tegra210_mvc.c
+1
sound/soc/tegra/tegra210_ope.c
+1
sound/soc/tegra/tegra210_ope.c
+1
sound/soc/tegra/tegra210_peq.c
+1
sound/soc/tegra/tegra210_peq.c
+1
sound/soc/tegra/tegra210_sfc.c
+1
sound/soc/tegra/tegra210_sfc.c