Merge tag 'char-misc-5.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

+7 -7

drivers/android/binder.c

··· 4686 4686 4687 4687 static void binder_free_proc(struct binder_proc *proc) 4688 4688 { 4689 + struct binder_device *device; 4690 + 4689 4691 BUG_ON(!list_empty(&proc->todo)); 4690 4692 BUG_ON(!list_empty(&proc->delivered_death)); 4693 + device = container_of(proc->context, struct binder_device, context); 4694 + if (refcount_dec_and_test(&device->ref)) { 4695 + kfree(proc->context->name); 4696 + kfree(device); 4697 + } 4691 4698 binder_alloc_deferred_release(&proc->alloc); 4692 4699 put_task_struct(proc->tsk); 4693 4700 binder_stats_deleted(BINDER_STAT_PROC); ··· 5413 5406 static void binder_deferred_release(struct binder_proc *proc) 5414 5407 { 5415 5408 struct binder_context *context = proc->context; 5416 - struct binder_device *device; 5417 5409 struct rb_node *n; 5418 5410 int threads, nodes, incoming_refs, outgoing_refs, active_transactions; 5419 5411 ··· 5429 5423 context->binder_context_mgr_node = NULL; 5430 5424 } 5431 5425 mutex_unlock(&context->context_mgr_node_lock); 5432 - device = container_of(proc->context, struct binder_device, context); 5433 - if (refcount_dec_and_test(&device->ref)) { 5434 - kfree(context->name); 5435 - kfree(device); 5436 - } 5437 - proc->context = NULL; 5438 5426 binder_inner_proc_lock(proc); 5439 5427 /* 5440 5428 * Make sure proc stays alive after we

+1 -1

drivers/fpga/Kconfig

··· 208 208 209 209 config FPGA_MGR_ZYNQMP_FPGA 210 210 tristate "Xilinx ZynqMP FPGA" 211 - depends on ARCH_ZYNQMP || COMPILE_TEST 211 + depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) 212 212 help 213 213 FPGA manager driver support for Xilinx ZynqMP FPGAs. 214 214 This driver uses the processor configuration port(PCAP)

+13

drivers/misc/habanalabs/command_submission.c

··· 62 62 container_of(fence, struct hl_cs_compl, base_fence); 63 63 struct hl_device *hdev = hl_cs_cmpl->hdev; 64 64 65 + /* EBUSY means the CS was never submitted and hence we don't have 66 + * an attached hw_sob object that we should handle here 67 + */ 68 + if (fence->error == -EBUSY) 69 + goto free; 70 + 65 71 if ((hl_cs_cmpl->type == CS_TYPE_SIGNAL) || 66 72 (hl_cs_cmpl->type == CS_TYPE_WAIT)) { 67 73 ··· 98 92 kref_put(&hl_cs_cmpl->hw_sob->kref, hl_sob_reset); 99 93 } 100 94 95 + free: 101 96 kfree_rcu(hl_cs_cmpl, base_fence.rcu); 102 97 } 103 98 ··· 335 328 336 329 hl_ctx_put(cs->ctx); 337 330 331 + /* We need to mark an error for not submitted because in that case 332 + * the dma fence release flow is different. Mainly, we don't need 333 + * to handle hw_sob for signal/wait 334 + */ 338 335 if (cs->timedout) 339 336 dma_fence_set_error(cs->fence, -ETIMEDOUT); 340 337 else if (cs->aborted) 341 338 dma_fence_set_error(cs->fence, -EIO); 339 + else if (!cs->submitted) 340 + dma_fence_set_error(cs->fence, -EBUSY); 342 341 343 342 dma_fence_signal(cs->fence); 344 343 dma_fence_put(cs->fence);

+2 -2

drivers/misc/habanalabs/debugfs.c

··· 480 480 return 0; 481 481 } 482 482 483 - static ssize_t mmu_write(struct file *file, const char __user *buf, 483 + static ssize_t mmu_asid_va_write(struct file *file, const char __user *buf, 484 484 size_t count, loff_t *f_pos) 485 485 { 486 486 struct seq_file *s = file->private_data; ··· 1125 1125 {"command_submission_jobs", command_submission_jobs_show, NULL}, 1126 1126 {"userptr", userptr_show, NULL}, 1127 1127 {"vm", vm_show, NULL}, 1128 - {"mmu", mmu_show, mmu_write}, 1128 + {"mmu", mmu_show, mmu_asid_va_write}, 1129 1129 {"engines", engines_show, NULL} 1130 1130 }; 1131 1131

+35 -2

drivers/misc/habanalabs/gaudi/gaudi.c

··· 96 96 97 97 #define GAUDI_NUM_OF_QM_ARB_ERR_CAUSE 3 98 98 99 - #define GAUDI_ARB_WDT_TIMEOUT 0x400000 99 + #define GAUDI_ARB_WDT_TIMEOUT 0x1000000 100 100 101 101 static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = { 102 102 "gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3", ··· 1893 1893 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo); 1894 1894 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi); 1895 1895 1896 + WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100); 1897 + 1896 1898 /* The following configuration is needed only once per QMAN */ 1897 1899 if (qman_id == 0) { 1898 1900 /* Configure RAZWI IRQ */ ··· 2726 2724 2727 2725 WREG32(mmSTLB_HOP_CONFIGURATION, 2728 2726 hdev->mmu_huge_page_opt ? 0x30440 : 0x40440); 2727 + 2728 + /* 2729 + * The H/W expects the first PI after init to be 1. After wraparound 2730 + * we'll write 0. 2731 + */ 2732 + gaudi->mmu_cache_inv_pi = 1; 2729 2733 2730 2734 gaudi->hw_cap_initialized |= HW_CAP_MMU; 2731 2735 ··· 3798 3790 src_in_host); 3799 3791 } 3800 3792 3793 + static int gaudi_validate_load_and_exe_pkt(struct hl_device *hdev, 3794 + struct hl_cs_parser *parser, 3795 + struct packet_load_and_exe *user_pkt) 3796 + { 3797 + u32 cfg; 3798 + 3799 + cfg = le32_to_cpu(user_pkt->cfg); 3800 + 3801 + if (cfg & GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK) { 3802 + dev_err(hdev->dev, 3803 + "User not allowed to use Load and Execute\n"); 3804 + return -EPERM; 3805 + } 3806 + 3807 + parser->patched_cb_size += sizeof(struct packet_load_and_exe); 3808 + 3809 + return 0; 3810 + } 3811 + 3801 3812 static int gaudi_validate_cb(struct hl_device *hdev, 3802 3813 struct hl_cs_parser *parser, bool is_mmu) 3803 3814 { ··· 3865 3838 rc = -EPERM; 3866 3839 break; 3867 3840 3841 + case PACKET_LOAD_AND_EXE: 3842 + rc = gaudi_validate_load_and_exe_pkt(hdev, parser, 3843 + (struct packet_load_and_exe *) user_pkt); 3844 + break; 3845 + 3868 3846 case PACKET_LIN_DMA: 3869 3847 parser->contains_dma_pkt = true; 3870 3848 if (is_mmu) ··· 3887 3855 case PACKET_FENCE: 3888 3856 case PACKET_NOP: 3889 3857 case PACKET_ARB_POINT: 3890 - case PACKET_LOAD_AND_EXE: 3891 3858 parser->patched_cb_size += pkt_size; 3892 3859 break; 3893 3860 ··· 6025 5994 mutex_lock(&hdev->mmu_cache_lock); 6026 5995 6027 5996 /* L0 & L1 invalidation */ 5997 + WREG32(mmSTLB_INV_PS, 3); 5998 + WREG32(mmSTLB_CACHE_INV, gaudi->mmu_cache_inv_pi++); 6028 5999 WREG32(mmSTLB_INV_PS, 2); 6029 6000 6030 6001 rc = hl_poll_timeout(

+3

drivers/misc/habanalabs/gaudi/gaudiP.h

··· 229 229 * @multi_msi_mode: whether we are working in multi MSI single MSI mode. 230 230 * Multi MSI is possible only with IOMMU enabled. 231 231 * @ext_queue_idx: helper index for external queues initialization. 232 + * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an 233 + * 8-bit value so use u8. 232 234 */ 233 235 struct gaudi_device { 234 236 int (*armcp_info_get)(struct hl_device *hdev); ··· 250 248 u32 hw_cap_initialized; 251 249 u8 multi_msi_mode; 252 250 u8 ext_queue_idx; 251 + u8 mmu_cache_inv_pi; 253 252 }; 254 253 255 254 void gaudi_init_security(struct hl_device *hdev);

+3

drivers/misc/habanalabs/include/gaudi/gaudi_packets.h

··· 197 197 __le32 ctl; 198 198 }; 199 199 200 + #define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_SHIFT 0 201 + #define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK 0x00000001 202 + 200 203 struct packet_load_and_exe { 201 204 __le32 cfg; 202 205 __le32 ctl;

+3

drivers/misc/mei/hw-me-regs.h

··· 94 94 #define MEI_DEV_ID_JSP_N 0x4DE0 /* Jasper Lake Point N */ 95 95 96 96 #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */ 97 + #define MEI_DEV_ID_TGP_H 0x43E0 /* Tiger Lake Point H */ 97 98 98 99 #define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */ 99 100 #define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */ ··· 108 107 # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000 109 108 #define PCI_CFG_HFS_2 0x48 110 109 #define PCI_CFG_HFS_3 0x60 110 + # define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070 111 + # define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060 111 112 #define PCI_CFG_HFS_4 0x64 112 113 #define PCI_CFG_HFS_5 0x68 113 114 #define PCI_CFG_HFS_6 0x6C

+64 -6

drivers/misc/mei/hw-me.c

··· 1366 1366 #define MEI_CFG_FW_NM \ 1367 1367 .quirk_probe = mei_me_fw_type_nm 1368 1368 1369 - static bool mei_me_fw_type_sps(struct pci_dev *pdev) 1369 + static bool mei_me_fw_type_sps_4(struct pci_dev *pdev) 1370 1370 { 1371 1371 u32 reg; 1372 1372 unsigned int devfn; ··· 1382 1382 return (reg & 0xf0000) == 0xf0000; 1383 1383 } 1384 1384 1385 - #define MEI_CFG_FW_SPS \ 1385 + #define MEI_CFG_FW_SPS_4 \ 1386 + .quirk_probe = mei_me_fw_type_sps_4 1387 + 1388 + /** 1389 + * mei_me_fw_sku_sps() - check for sps sku 1390 + * 1391 + * Read ME FW Status register to check for SPS Firmware. 1392 + * The SPS FW is only signaled in pci function 0 1393 + * 1394 + * @pdev: pci device 1395 + * 1396 + * Return: true in case of SPS firmware 1397 + */ 1398 + static bool mei_me_fw_type_sps(struct pci_dev *pdev) 1399 + { 1400 + u32 reg; 1401 + u32 fw_type; 1402 + unsigned int devfn; 1403 + 1404 + devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); 1405 + pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_3, &reg); 1406 + trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg); 1407 + fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK); 1408 + 1409 + dev_dbg(&pdev->dev, "fw type is %d\n", fw_type); 1410 + 1411 + return fw_type == PCI_CFG_HFS_3_FW_SKU_SPS; 1412 + } 1413 + 1414 + #define MEI_CFG_FW_SPS \ 1386 1415 .quirk_probe = mei_me_fw_type_sps 1387 1416 1388 1417 #define MEI_CFG_FW_VER_SUPP \ ··· 1481 1452 }; 1482 1453 1483 1454 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ 1484 - static const struct mei_cfg mei_me_pch8_sps_cfg = { 1455 + static const struct mei_cfg mei_me_pch8_sps_4_cfg = { 1485 1456 MEI_CFG_PCH8_HFS, 1486 1457 MEI_CFG_FW_VER_SUPP, 1487 - MEI_CFG_FW_SPS, 1458 + MEI_CFG_FW_SPS_4, 1459 + }; 1460 + 1461 + /* LBG with quirk for SPS (4.0) Firmware exclusion */ 1462 + static const struct mei_cfg mei_me_pch12_sps_4_cfg = { 1463 + MEI_CFG_PCH8_HFS, 1464 + MEI_CFG_FW_VER_SUPP, 1465 + MEI_CFG_FW_SPS_4, 1488 1466 }; 1489 1467 1490 1468 /* Cannon Lake and newer devices */ ··· 1501 1465 MEI_CFG_DMA_128, 1502 1466 }; 1503 1467 1504 - /* LBG with quirk for SPS Firmware exclusion */ 1468 + /* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */ 1505 1469 static const struct mei_cfg mei_me_pch12_sps_cfg = { 1470 + MEI_CFG_PCH8_HFS, 1471 + MEI_CFG_FW_VER_SUPP, 1472 + MEI_CFG_DMA_128, 1473 + MEI_CFG_FW_SPS, 1474 + }; 1475 + 1476 + /* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion 1477 + * w/o DMA support 1478 + */ 1479 + static const struct mei_cfg mei_me_pch12_nodma_sps_cfg = { 1506 1480 MEI_CFG_PCH8_HFS, 1507 1481 MEI_CFG_FW_VER_SUPP, 1508 1482 MEI_CFG_FW_SPS, ··· 1524 1478 MEI_CFG_FW_VER_SUPP, 1525 1479 MEI_CFG_DMA_128, 1526 1480 MEI_CFG_TRC, 1481 + }; 1482 + 1483 + /* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */ 1484 + static const struct mei_cfg mei_me_pch15_sps_cfg = { 1485 + MEI_CFG_PCH8_HFS, 1486 + MEI_CFG_FW_VER_SUPP, 1487 + MEI_CFG_DMA_128, 1488 + MEI_CFG_TRC, 1489 + MEI_CFG_FW_SPS, 1527 1490 }; 1528 1491 1529 1492 /* ··· 1547 1492 [MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg, 1548 1493 [MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg, 1549 1494 [MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg, 1550 - [MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg, 1495 + [MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg, 1551 1496 [MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg, 1497 + [MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg, 1552 1498 [MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg, 1499 + [MEI_ME_PCH12_SPS_NODMA_CFG] = &mei_me_pch12_nodma_sps_cfg, 1553 1500 [MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg, 1501 + [MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg, 1554 1502 }; 1555 1503 1556 1504 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)

+13 -4

drivers/misc/mei/hw-me.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 2 /* 3 - * Copyright (c) 2012-2019, Intel Corporation. All rights reserved. 3 + * Copyright (c) 2012-2020, Intel Corporation. All rights reserved. 4 4 * Intel Management Engine Interface (Intel MEI) Linux driver 5 5 */ 6 6 ··· 76 76 * with quirk for Node Manager exclusion. 77 77 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer 78 78 * client platforms. 79 - * @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer 79 + * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer 80 80 * servers platforms with quirk for 81 81 * SPS firmware exclusion. 82 82 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer 83 - * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 and newer 83 + * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0 84 + * servers platforms with quirk for 85 + * SPS firmware exclusion. 86 + * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer 84 87 * servers platforms with quirk for 85 88 * SPS firmware exclusion. 86 89 * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer 90 + * @MEI_ME_PCH15_SPS_CFG: Platform Controller Hub Gen15 and newer 91 + * servers platforms with quirk for 92 + * SPS firmware exclusion. 87 93 * @MEI_ME_NUM_CFG: Upper Sentinel. 88 94 */ 89 95 enum mei_cfg_idx { ··· 100 94 MEI_ME_PCH7_CFG, 101 95 MEI_ME_PCH_CPT_PBG_CFG, 102 96 MEI_ME_PCH8_CFG, 103 - MEI_ME_PCH8_SPS_CFG, 97 + MEI_ME_PCH8_SPS_4_CFG, 104 98 MEI_ME_PCH12_CFG, 99 + MEI_ME_PCH12_SPS_4_CFG, 105 100 MEI_ME_PCH12_SPS_CFG, 101 + MEI_ME_PCH12_SPS_NODMA_CFG, 106 102 MEI_ME_PCH15_CFG, 103 + MEI_ME_PCH15_SPS_CFG, 107 104 MEI_ME_NUM_CFG, 108 105 }; 109 106

+9 -8

drivers/misc/mei/pci-me.c

··· 59 59 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, 60 60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, 61 61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, 62 - {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, 63 - {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, 62 + {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 63 + {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, 64 64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, 65 - {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, 65 + {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, 66 66 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, 67 67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, 68 68 69 69 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, 70 70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, 71 - {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, 72 - {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, 73 - {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_CFG)}, 71 + {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, 72 + {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, 73 + {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, 74 74 75 75 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, 76 76 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, ··· 84 84 85 85 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, 86 86 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)}, 87 - {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, 88 - {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH8_CFG)}, 87 + {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, 88 + {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_NODMA_CFG)}, 89 89 90 90 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, 91 91 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, ··· 96 96 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, 97 97 98 98 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, 99 + {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, 99 100 100 101 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, 101 102

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