Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mmc-v4.10-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC host fix from Ulf Hansson:
"mmci: Fix hang while waiting for busy-end interrupt"
* tag 'mmc-v4.10-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: mmci: avoid clearing ST Micro busy end interrupt mistakenly
+25
-7
+25
-7
drivers/mmc/host/mmci.c
+25
-7
drivers/mmc/host/mmci.c
···
1023
1023
if (!host->busy_status && busy_resp &&
1024
1024
!(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1025
1025
(readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1026
-
/* Unmask the busy IRQ */
1026
+
1027
+
/* Clear the busy start IRQ */
1028
+
writel(host->variant->busy_detect_mask,
1029
+
host->base + MMCICLEAR);
1030
+
1031
+
/* Unmask the busy end IRQ */
1027
1032
writel(readl(base + MMCIMASK0) |
1028
1033
host->variant->busy_detect_mask,
1029
1034
base + MMCIMASK0);
···
1043
1038
1044
1039
/*
1045
1040
* At this point we are not busy with a command, we have
1046
-
* not received a new busy request, mask the busy IRQ and
1047
-
* fall through to process the IRQ.
1041
+
* not received a new busy request, clear and mask the busy
1042
+
* end IRQ and fall through to process the IRQ.
1048
1043
*/
1049
1044
if (host->busy_status) {
1045
+
1046
+
writel(host->variant->busy_detect_mask,
1047
+
host->base + MMCICLEAR);
1048
+
1050
1049
writel(readl(base + MMCIMASK0) &
1051
1050
~host->variant->busy_detect_mask,
1052
1051
base + MMCIMASK0);
···
1292
1283
}
1293
1284
1294
1285
/*
1295
-
* We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1296
-
* enabled) since the HW seems to be triggering the IRQ on both
1297
-
* edges while monitoring DAT0 for busy completion.
1286
+
* We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1287
+
* enabled) in mmci_cmd_irq() function where ST Micro busy
1288
+
* detection variant is handled. Considering the HW seems to be
1289
+
* triggering the IRQ on both edges while monitoring DAT0 for
1290
+
* busy completion and that same status bit is used to monitor
1291
+
* start and end of busy detection, special care must be taken
1292
+
* to make sure that both start and end interrupts are always
1293
+
* cleared one after the other.
1298
1294
*/
1299
1295
status &= readl(host->base + MMCIMASK0);
1300
-
writel(status, host->base + MMCICLEAR);
1296
+
if (host->variant->busy_detect)
1297
+
writel(status & ~host->variant->busy_detect_mask,
1298
+
host->base + MMCICLEAR);
1299
+
else
1300
+
writel(status, host->base + MMCICLEAR);
1301
1301
1302
1302
dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1303
1303