Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2020-11-06-1' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"It's Friday here so that means another installment of drm fixes to
distract you from the counting process.
Changes all over the place, the amdgpu changes contain support for a
new GPU that is close to current one already in the tree (Green
Sardine) so it shouldn't have much side effects.
Otherwise imx has a few cleanup patches and fixes, amdgpu and i915
have around the usual smattering of fixes, fonts got constified, and
vc4/panfrost has some minor fixes. All in all a fairly regular rc3.
We have an outstanding nouveau regression, but the author is looking
into the fix, so should be here next week.
I now return you to counting.
fonts:
- constify font structures.
MAINTAINERS:
- Fix path for amdgpu power management
amdgpu:
- Add support for more navi1x SKUs
- Fix for suspend on CI dGPUs
- VCN DPG fix for Picasso
- Sienna Cichlid fixes
- Polaris DPM fix
- Add support for Green Sardine
amdkfd:
- Fix an allocation failure check
i915:
- Fix set domain's cache coherency
- Fixes around breadcrumbs
- Fix encoder lookup during PSR atomic
- Hold onto an explicit ref to i915_vma_work.pinned
- gvt: HWSP reset handling fix
- gvt: flush workaround
- gvt: vGPU context pin/unpin
- gvt: mmio cmd access fix for bxt/apl
imx:
- drop unused functions and callbacks
- reuse imx_drm_encoder_parse_of
- spinlock rework
- memory leak fix
- minor cleanups
vc4:
- resource cleanup fix
panfrost:
- madvise/shrinker fix"
* tag 'drm-fixes-2020-11-06-1' of git://anongit.freedesktop.org/drm/drm: (55 commits)
drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE
drm/amd/display: Add green_sardine support to DM
drm/amd/display: Add green_sardine support to DC
drm/amdgpu: enable vcn support for green_sardine (v2)
drm/amdgpu: enable green_sardine_asd.bin loading (v2)
drm/amdgpu/sdma: add sdma engine support for green_sardine (v2)
drm/amdgpu: add gfx support for green_sardine (v2)
drm/amdgpu: add soc15 common ip block support for green_sardine (v3)
drm/amdgpu: add green_sardine support for gpu_info and ip block setting (v2)
drm/amdgpu: add Green_Sardine APU flag
drm/amdgpu: resolved ASD loading issue on sienna
amdkfd: Check kvmalloc return before memcpy
drm/amdgpu: update golden setting for sienna_cichlid
amd/amdgpu: Disable VCN DPG mode for Picasso
drm/amdgpu/swsmu: remove duplicate call to smu_set_default_dpm_table
drm/i915: Hold onto an explicit ref to i915_vma_work.pinned
drm/i915/gt: Flush xcs before tgl breadcrumbs
drm/i915/gt: Expose more parameters for emitting writes into the ring
drm/i915: Fix encoder lookup during PSR atomic check
drm/i915/gt: Use the local HWSP offset during submission
...
+439
-370
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
934
934
L: amd-gfx@lists.freedesktop.org
935
935
S: Supported
936
936
T: git git://people.freedesktop.org/~agd5f/linux
937
-
F: drivers/gpu/drm/amd/powerplay/
937
+
F: drivers/gpu/drm/amd/pm/powerplay/
938
938
939
939
AMD SEATTLE DEVICE TREE SUPPORT
940
940
M: Brijesh Singh <brijeshkumar.singh@amd.com>
+5
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+5
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
80
80
MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
81
81
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
82
82
MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83
+
MODULE_FIRMWARE("amdgpu/green_sardine_gpu_info.bin");
83
84
84
85
#define AMDGPU_RESUME_MS 2000
85
86
···
1806
1805
chip_name = "arcturus";
1807
1806
break;
1808
1807
case CHIP_RENOIR:
1809
-
chip_name = "renoir";
1808
+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
1809
+
chip_name = "renoir";
1810
+
else
1811
+
chip_name = "green_sardine";
1810
1812
break;
1811
1813
case CHIP_NAVI10:
1812
1814
chip_name = "navi10";
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
2524
2524
psp->asd_feature_version = le32_to_cpu(desc->fw_version);
2525
2525
psp->asd_ucode_size = le32_to_cpu(desc->size_bytes);
2526
2526
psp->asd_start_addr = ucode_start_addr;
2527
+
psp->asd_fw = psp->ta_fw;
2527
2528
break;
2528
2529
case TA_FW_TYPE_PSP_XGMI:
2529
2530
psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
+7
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+7
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
···
39
39
#define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
40
40
#define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
41
41
#define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
42
+
#define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
42
43
#define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
43
44
#define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
44
45
#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
···
51
50
MODULE_FIRMWARE(FIRMWARE_RAVEN2);
52
51
MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
53
52
MODULE_FIRMWARE(FIRMWARE_RENOIR);
53
+
MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
54
54
MODULE_FIRMWARE(FIRMWARE_NAVI10);
55
55
MODULE_FIRMWARE(FIRMWARE_NAVI14);
56
56
MODULE_FIRMWARE(FIRMWARE_NAVI12);
···
91
89
adev->vcn.indirect_sram = true;
92
90
break;
93
91
case CHIP_RENOIR:
94
-
fw_name = FIRMWARE_RENOIR;
92
+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
93
+
fw_name = FIRMWARE_RENOIR;
94
+
else
95
+
fw_name = FIRMWARE_GREEN_SARDINE;
96
+
95
97
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
96
98
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
97
99
adev->vcn.indirect_sram = true;
+3
-1
drivers/gpu/drm/amd/amdgpu/cik.c
+3
-1
drivers/gpu/drm/amd/amdgpu/cik.c
···
1336
1336
1337
1337
switch (adev->asic_type) {
1338
1338
case CHIP_BONAIRE:
1339
-
case CHIP_HAWAII:
1340
1339
/* disable baco reset until it works */
1341
1340
/* smu7_asic_get_baco_capability(adev, &baco_reset); */
1342
1341
baco_reset = false;
1342
+
break;
1343
+
case CHIP_HAWAII:
1344
+
baco_reset = cik_asic_supports_baco(adev);
1343
1345
break;
1344
1346
default:
1345
1347
baco_reset = false;
+12
-15
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+12
-15
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
···
1071
1071
{
1072
1072
u32 srbm_soft_reset = 0;
1073
1073
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074
-
u32 tmp = RREG32(mmSRBM_STATUS2);
1074
+
u32 tmp;
1075
1075
1076
-
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1077
-
/* sdma0 */
1078
-
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1079
-
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1080
-
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1081
-
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1082
-
}
1083
-
if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1084
-
/* sdma1 */
1085
-
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1086
-
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1087
-
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1088
-
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1089
-
}
1076
+
/* sdma0 */
1077
+
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1078
+
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1079
+
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1080
+
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1081
+
1082
+
/* sdma1 */
1083
+
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1084
+
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1085
+
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1086
+
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1090
1087
1091
1088
if (srbm_soft_reset) {
1092
1089
tmp = RREG32(mmSRBM_SOFT_RESET);
+4
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+4
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
128
128
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
129
129
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
130
130
131
+
#define mmCGTT_SPI_CS_CLK_CTRL 0x507c
132
+
#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
133
+
131
134
MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
132
135
MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
133
136
MODULE_FIRMWARE("amdgpu/navi10_me.bin");
···
3097
3094
3098
3095
static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3099
3096
{
3097
+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3100
3098
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3101
3099
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3102
3100
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
+11
-1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+11
-1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
117
117
MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
118
118
MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
119
119
120
+
MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin");
121
+
MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin");
122
+
MODULE_FIRMWARE("amdgpu/green_sardine_me.bin");
123
+
MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin");
124
+
MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin");
125
+
MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin");
126
+
120
127
#define mmTCP_CHAN_STEER_0_ARCT 0x0b03
121
128
#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0
122
129
#define mmTCP_CHAN_STEER_1_ARCT 0x0b04
···
1637
1630
chip_name = "arcturus";
1638
1631
break;
1639
1632
case CHIP_RENOIR:
1640
-
chip_name = "renoir";
1633
+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
1634
+
chip_name = "renoir";
1635
+
else
1636
+
chip_name = "green_sardine";
1641
1637
break;
1642
1638
default:
1643
1639
BUG();
+6
-5
drivers/gpu/drm/amd/amdgpu/nv.c
+6
-5
drivers/gpu/drm/amd/amdgpu/nv.c
···
455
455
adev->virt.ops = &xgpu_nv_virt_ops;
456
456
}
457
457
458
-
static bool nv_is_blockchain_sku(struct pci_dev *pdev)
458
+
static bool nv_is_headless_sku(struct pci_dev *pdev)
459
459
{
460
-
if (pdev->device == 0x731E &&
461
-
(pdev->revision == 0xC6 || pdev->revision == 0xC7))
460
+
if ((pdev->device == 0x731E &&
461
+
(pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
462
+
(pdev->device == 0x7340 && pdev->revision == 0xC9))
462
463
return true;
463
464
return false;
464
465
}
···
493
492
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
494
493
#if defined(CONFIG_DRM_AMD_DC)
495
494
else if (amdgpu_device_has_dc_support(adev) &&
496
-
!nv_is_blockchain_sku(adev->pdev))
495
+
!nv_is_headless_sku(adev->pdev))
497
496
amdgpu_device_ip_block_add(adev, &dm_ip_block);
498
497
#endif
499
498
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
···
501
500
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
502
501
!amdgpu_sriov_vf(adev))
503
502
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
504
-
if (!nv_is_blockchain_sku(adev->pdev))
503
+
if (!nv_is_headless_sku(adev->pdev))
505
504
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
506
505
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
507
506
if (adev->enable_mes)
+5
-1
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+5
-1
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
···
39
39
40
40
MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41
41
MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
42
+
MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
42
43
43
44
/* address block */
44
45
#define smnMP1_FIRMWARE_FLAGS 0x3010024
···
55
54
56
55
switch (adev->asic_type) {
57
56
case CHIP_RENOIR:
58
-
chip_name = "renoir";
57
+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
58
+
chip_name = "renoir";
59
+
else
60
+
chip_name = "green_sardine";
59
61
break;
60
62
default:
61
63
BUG();
+5
-1
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+5
-1
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
···
69
69
MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70
70
MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71
71
MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
72
+
MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
72
73
73
74
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
74
75
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
···
620
619
chip_name = "arcturus";
621
620
break;
622
621
case CHIP_RENOIR:
623
-
chip_name = "renoir";
622
+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
623
+
chip_name = "renoir";
624
+
else
625
+
chip_name = "green_sardine";
624
626
break;
625
627
default:
626
628
BUG();
+10
-4
drivers/gpu/drm/amd/amdgpu/soc15.c
+10
-4
drivers/gpu/drm/amd/amdgpu/soc15.c
···
1195
1195
1196
1196
adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1197
1197
AMD_PG_SUPPORT_MMHUB |
1198
-
AMD_PG_SUPPORT_VCN |
1199
-
AMD_PG_SUPPORT_VCN_DPG;
1198
+
AMD_PG_SUPPORT_VCN;
1200
1199
} else {
1201
1200
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1202
1201
AMD_CG_SUPPORT_GFX_MGLS |
···
1242
1243
break;
1243
1244
case CHIP_RENOIR:
1244
1245
adev->asic_funcs = &soc15_asic_funcs;
1245
-
adev->apu_flags |= AMD_APU_IS_RENOIR;
1246
+
if (adev->pdev->device == 0x1636)
1247
+
adev->apu_flags |= AMD_APU_IS_RENOIR;
1248
+
else
1249
+
adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1250
+
1251
+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
1252
+
adev->external_rev_id = adev->rev_id + 0x91;
1253
+
else
1254
+
adev->external_rev_id = adev->rev_id + 0xa1;
1246
1255
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1247
1256
AMD_CG_SUPPORT_GFX_MGLS |
1248
1257
AMD_CG_SUPPORT_GFX_3D_CGCG |
···
1275
1268
AMD_PG_SUPPORT_VCN |
1276
1269
AMD_PG_SUPPORT_JPEG |
1277
1270
AMD_PG_SUPPORT_VCN_DPG;
1278
-
adev->external_rev_id = adev->rev_id + 0x91;
1279
1271
break;
1280
1272
default:
1281
1273
/* FIXME: not supported yet */
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
···
798
798
}
799
799
800
800
pcrat_image = kvmalloc(crat_table->length, GFP_KERNEL);
801
-
memcpy(pcrat_image, crat_table, crat_table->length);
802
801
if (!pcrat_image)
803
802
return -ENOMEM;
804
803
804
+
memcpy(pcrat_image, crat_table, crat_table->length);
805
805
*crat_image = pcrat_image;
806
806
*size = crat_table->length;
807
807
+6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
100
100
#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
101
101
MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
102
102
#endif
103
+
#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
104
+
MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
103
105
104
106
#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
105
107
MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
···
975
973
case CHIP_RAVEN:
976
974
case CHIP_RENOIR:
977
975
init_data.flags.gpu_vm_support = true;
976
+
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
977
+
init_data.flags.disable_dmcu = true;
978
978
break;
979
979
default:
980
980
break;
···
1271
1267
case CHIP_RENOIR:
1272
1268
dmub_asic = DMUB_ASIC_DCN21;
1273
1269
fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1270
+
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1271
+
fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1274
1272
break;
1275
1273
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1276
1274
case CHIP_SIENNA_CICHLID:
+5
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+5
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
···
166
166
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
167
167
break;
168
168
}
169
+
170
+
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
171
+
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
172
+
break;
173
+
}
169
174
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
170
175
rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
171
176
break;
+2
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+2
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+4
drivers/gpu/drm/amd/display/include/dal_asic_id.h
+4
drivers/gpu/drm/amd/display/include/dal_asic_id.h
···
205
205
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
206
206
#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
207
207
#endif
208
+
#define GREEN_SARDINE_A0 0xA1
209
+
#ifndef ASICREV_IS_GREEN_SARDINE
210
+
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
211
+
#endif
208
212
209
213
/*
210
214
* ASIC chip ID
+1
drivers/gpu/drm/amd/pm/inc/hwmgr.h
+1
drivers/gpu/drm/amd/pm/inc/hwmgr.h
···
229
229
bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
230
230
int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
231
231
int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
232
+
int (*stop_smc)(struct pp_hwmgr *hwmgr);
232
233
};
233
234
234
235
struct pp_hwmgr_func {
+2
drivers/gpu/drm/amd/pm/inc/smumgr.h
+2
drivers/gpu/drm/amd/pm/inc/smumgr.h
+4
-3
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
+4
-3
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
···
142
142
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
143
143
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
144
144
{ CMD_DELAY_MS, 0, 0, 0, 20, 0 },
145
-
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x20 },
145
+
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
146
146
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
147
-
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
147
+
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
148
148
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
149
149
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
150
-
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x10 },
150
+
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
151
151
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
152
152
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
153
153
};
···
155
155
static const struct baco_cmd_entry clean_baco_tbl[] =
156
156
{
157
157
{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
158
+
{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
158
159
{ CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
159
160
};
160
161
+22
-12
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+22
-12
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
···
1541
1541
PP_ASSERT_WITH_CODE((tmp_result == 0),
1542
1542
"Failed to reset to default!", result = tmp_result);
1543
1543
1544
+
tmp_result = smum_stop_smc(hwmgr);
1545
+
PP_ASSERT_WITH_CODE((tmp_result == 0),
1546
+
"Failed to stop smc!", result = tmp_result);
1547
+
1544
1548
tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1545
1549
PP_ASSERT_WITH_CODE((tmp_result == 0),
1546
1550
"Failed to force to switch arbf0!", result = tmp_result);
···
1589
1585
data->current_profile_setting.sclk_down_hyst = 100;
1590
1586
data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1591
1587
data->current_profile_setting.bupdate_mclk = 1;
1592
-
if (adev->gmc.vram_width == 256) {
1593
-
data->current_profile_setting.mclk_up_hyst = 10;
1594
-
data->current_profile_setting.mclk_down_hyst = 60;
1595
-
data->current_profile_setting.mclk_activity = 25;
1596
-
} else if (adev->gmc.vram_width == 128) {
1597
-
data->current_profile_setting.mclk_up_hyst = 5;
1598
-
data->current_profile_setting.mclk_down_hyst = 16;
1599
-
data->current_profile_setting.mclk_activity = 20;
1600
-
} else if (adev->gmc.vram_width == 64) {
1601
-
data->current_profile_setting.mclk_up_hyst = 3;
1602
-
data->current_profile_setting.mclk_down_hyst = 16;
1603
-
data->current_profile_setting.mclk_activity = 20;
1588
+
if (hwmgr->chip_id >= CHIP_POLARIS10) {
1589
+
if (adev->gmc.vram_width == 256) {
1590
+
data->current_profile_setting.mclk_up_hyst = 10;
1591
+
data->current_profile_setting.mclk_down_hyst = 60;
1592
+
data->current_profile_setting.mclk_activity = 25;
1593
+
} else if (adev->gmc.vram_width == 128) {
1594
+
data->current_profile_setting.mclk_up_hyst = 5;
1595
+
data->current_profile_setting.mclk_down_hyst = 16;
1596
+
data->current_profile_setting.mclk_activity = 20;
1597
+
} else if (adev->gmc.vram_width == 64) {
1598
+
data->current_profile_setting.mclk_up_hyst = 3;
1599
+
data->current_profile_setting.mclk_down_hyst = 16;
1600
+
data->current_profile_setting.mclk_activity = 20;
1601
+
}
1602
+
} else {
1603
+
data->current_profile_setting.mclk_up_hyst = 0;
1604
+
data->current_profile_setting.mclk_down_hyst = 100;
1605
+
data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1604
1606
}
1605
1607
hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1606
1608
hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+25
-4
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
+25
-4
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
···
2726
2726
2727
2727
static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
2728
2728
{
2729
-
return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2730
-
CGS_IND_REG__SMC, FEATURE_STATUS,
2731
-
VOLTAGE_CONTROLLER_ON))
2732
-
? true : false;
2729
+
return ci_is_smc_ram_running(hwmgr);
2733
2730
}
2734
2731
2735
2732
static int ci_smu_init(struct pp_hwmgr *hwmgr)
···
2936
2939
return 0;
2937
2940
}
2938
2941
2942
+
static void ci_reset_smc(struct pp_hwmgr *hwmgr)
2943
+
{
2944
+
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2945
+
SMC_SYSCON_RESET_CNTL,
2946
+
rst_reg, 1);
2947
+
}
2948
+
2949
+
2950
+
static void ci_stop_smc_clock(struct pp_hwmgr *hwmgr)
2951
+
{
2952
+
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2953
+
SMC_SYSCON_CLOCK_CNTL_0,
2954
+
ck_disable, 1);
2955
+
}
2956
+
2957
+
static int ci_stop_smc(struct pp_hwmgr *hwmgr)
2958
+
{
2959
+
ci_reset_smc(hwmgr);
2960
+
ci_stop_smc_clock(hwmgr);
2961
+
2962
+
return 0;
2963
+
}
2964
+
2939
2965
const struct pp_smumgr_func ci_smu_funcs = {
2940
2966
.name = "ci_smu",
2941
2967
.smu_init = ci_smu_init,
···
2984
2964
.is_dpm_running = ci_is_dpm_running,
2985
2965
.update_dpm_settings = ci_update_dpm_settings,
2986
2966
.update_smc_table = ci_update_smc_table,
2967
+
.stop_smc = ci_stop_smc,
2987
2968
};
+8
drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
+8
drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
-11
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
-11
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
1029
1029
return ret;
1030
1030
}
1031
1031
1032
-
/*
1033
-
* Set initialized values (get from vbios) to dpm tables context such as
1034
-
* gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1035
-
* type of clks.
1036
-
*/
1037
-
ret = smu_set_default_dpm_table(smu);
1038
-
if (ret) {
1039
-
dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1040
-
return ret;
1041
-
}
1042
-
1043
1032
ret = smu_notify_display_change(smu);
1044
1033
if (ret)
1045
1034
return ret;
+1
-1
drivers/gpu/drm/i915/display/intel_psr.c
+1
-1
drivers/gpu/drm/i915/display/intel_psr.c
···
1754
1754
return;
1755
1755
1756
1756
intel_connector = to_intel_connector(connector);
1757
-
dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector));
1757
+
dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder));
1758
1758
if (dev_priv->psr.dp != &dig_port->dp)
1759
1759
return;
1760
1760
+13
-15
drivers/gpu/drm/i915/gem/i915_gem_domain.c
+13
-15
drivers/gpu/drm/i915/gem/i915_gem_domain.c
···
509
509
return -ENOENT;
510
510
511
511
/*
512
-
* Already in the desired write domain? Nothing for us to do!
513
-
*
514
-
* We apply a little bit of cunning here to catch a broader set of
515
-
* no-ops. If obj->write_domain is set, we must be in the same
516
-
* obj->read_domains, and only that domain. Therefore, if that
517
-
* obj->write_domain matches the request read_domains, we are
518
-
* already in the same read/write domain and can skip the operation,
519
-
* without having to further check the requested write_domain.
520
-
*/
521
-
if (READ_ONCE(obj->write_domain) == read_domains) {
522
-
err = 0;
523
-
goto out;
524
-
}
525
-
526
-
/*
527
512
* Try to flush the object off the GPU without holding the lock.
528
513
* We will repeat the flush holding the lock in the normal manner
529
514
* to catch cases where we are gazumped.
···
544
559
err = i915_gem_object_pin_pages(obj);
545
560
if (err)
546
561
goto out;
562
+
563
+
/*
564
+
* Already in the desired write domain? Nothing for us to do!
565
+
*
566
+
* We apply a little bit of cunning here to catch a broader set of
567
+
* no-ops. If obj->write_domain is set, we must be in the same
568
+
* obj->read_domains, and only that domain. Therefore, if that
569
+
* obj->write_domain matches the request read_domains, we are
570
+
* already in the same read/write domain and can skip the operation,
571
+
* without having to further check the requested write_domain.
572
+
*/
573
+
if (READ_ONCE(obj->write_domain) == read_domains)
574
+
goto out_unpin;
547
575
548
576
err = i915_gem_object_lock_interruptible(obj, NULL);
549
577
if (err)
+35
-20
drivers/gpu/drm/i915/gt/intel_engine.h
+35
-20
drivers/gpu/drm/i915/gt/intel_engine.h
···
245
245
}
246
246
247
247
static inline u32 *
248
-
__gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
248
+
__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
249
249
{
250
-
/* We're using qword write, offset should be aligned to 8 bytes. */
251
-
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
252
-
253
-
/* w/a for post sync ops following a GPGPU operation we
254
-
* need a prior CS_STALL, which is emitted by the flush
255
-
* following the batch.
256
-
*/
257
250
*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
258
-
*cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
259
-
*cs++ = gtt_offset;
251
+
*cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
252
+
*cs++ = offset;
260
253
*cs++ = 0;
261
254
*cs++ = value;
262
-
/* We're thrashing one dword of HWS. */
263
-
*cs++ = 0;
255
+
*cs++ = 0; /* We're thrashing one extra dword. */
264
256
265
257
return cs;
266
258
}
···
260
268
static inline u32*
261
269
gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
262
270
{
263
-
return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
271
+
/* We're using qword write, offset should be aligned to 8 bytes. */
272
+
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
273
+
274
+
return __gen8_emit_write_rcs(cs,
275
+
value,
276
+
gtt_offset,
277
+
0,
278
+
flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
264
279
}
265
280
266
281
static inline u32*
267
282
gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
268
283
{
269
-
return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, flags0, flags1);
284
+
/* We're using qword write, offset should be aligned to 8 bytes. */
285
+
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
286
+
287
+
return __gen8_emit_write_rcs(cs,
288
+
value,
289
+
gtt_offset,
290
+
flags0,
291
+
flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
292
+
}
293
+
294
+
static inline u32 *
295
+
__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
296
+
{
297
+
*cs++ = (MI_FLUSH_DW + 1) | flags;
298
+
*cs++ = gtt_offset;
299
+
*cs++ = 0;
300
+
*cs++ = value;
301
+
302
+
return cs;
270
303
}
271
304
272
305
static inline u32 *
···
302
285
/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
303
286
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
304
287
305
-
*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
306
-
*cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
307
-
*cs++ = 0;
308
-
*cs++ = value;
309
-
310
-
return cs;
288
+
return __gen8_emit_flush_dw(cs,
289
+
value,
290
+
gtt_offset | MI_FLUSH_DW_USE_GTT,
291
+
flags | MI_FLUSH_DW_OP_STOREDW);
311
292
}
312
293
313
294
static inline void __intel_engine_reset(struct intel_engine_cs *engine,
+22
-9
drivers/gpu/drm/i915/gt/intel_lrc.c
+22
-9
drivers/gpu/drm/i915/gt/intel_lrc.c
···
3547
3547
.destroy = execlists_context_destroy,
3548
3548
};
3549
3549
3550
+
static u32 hwsp_offset(const struct i915_request *rq)
3551
+
{
3552
+
const struct intel_timeline_cacheline *cl;
3553
+
3554
+
/* Before the request is executed, the timeline/cachline is fixed */
3555
+
3556
+
cl = rcu_dereference_protected(rq->hwsp_cacheline, 1);
3557
+
if (cl)
3558
+
return cl->ggtt_offset;
3559
+
3560
+
return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
3561
+
}
3562
+
3550
3563
static int gen8_emit_init_breadcrumb(struct i915_request *rq)
3551
3564
{
3552
3565
u32 *cs;
···
3582
3569
*cs++ = MI_NOOP;
3583
3570
3584
3571
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
3585
-
*cs++ = i915_request_timeline(rq)->hwsp_offset;
3572
+
*cs++ = hwsp_offset(rq);
3586
3573
*cs++ = 0;
3587
3574
*cs++ = rq->fence.seqno - 1;
3588
3575
···
4899
4886
return gen8_emit_wa_tail(request, cs);
4900
4887
}
4901
4888
4902
-
static u32 *emit_xcs_breadcrumb(struct i915_request *request, u32 *cs)
4889
+
static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
4903
4890
{
4904
-
u32 addr = i915_request_active_timeline(request)->hwsp_offset;
4905
-
4906
-
return gen8_emit_ggtt_write(cs, request->fence.seqno, addr, 0);
4891
+
return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
4907
4892
}
4908
4893
4909
4894
static u32 *gen8_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
···
4920
4909
/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
4921
4910
cs = gen8_emit_ggtt_write_rcs(cs,
4922
4911
request->fence.seqno,
4923
-
i915_request_active_timeline(request)->hwsp_offset,
4912
+
hwsp_offset(request),
4924
4913
PIPE_CONTROL_FLUSH_ENABLE |
4925
4914
PIPE_CONTROL_CS_STALL);
4926
4915
···
4932
4921
{
4933
4922
cs = gen8_emit_ggtt_write_rcs(cs,
4934
4923
request->fence.seqno,
4935
-
i915_request_active_timeline(request)->hwsp_offset,
4924
+
hwsp_offset(request),
4936
4925
PIPE_CONTROL_CS_STALL |
4937
4926
PIPE_CONTROL_TILE_CACHE_FLUSH |
4938
4927
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
···
4994
4983
4995
4984
static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
4996
4985
{
4997
-
return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
4986
+
/* XXX Stalling flush before seqno write; post-sync not */
4987
+
cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
4988
+
return gen12_emit_fini_breadcrumb_tail(rq, cs);
4998
4989
}
4999
4990
5000
4991
static u32 *
···
5004
4991
{
5005
4992
cs = gen12_emit_ggtt_write_rcs(cs,
5006
4993
request->fence.seqno,
5007
-
i915_request_active_timeline(request)->hwsp_offset,
4994
+
hwsp_offset(request),
5008
4995
PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
5009
4996
PIPE_CONTROL_CS_STALL |
5010
4997
PIPE_CONTROL_TILE_CACHE_FLUSH |
+10
-8
drivers/gpu/drm/i915/gt/intel_timeline.c
+10
-8
drivers/gpu/drm/i915/gt/intel_timeline.c
···
188
188
return cl;
189
189
}
190
190
191
-
static void cacheline_acquire(struct intel_timeline_cacheline *cl)
191
+
static void cacheline_acquire(struct intel_timeline_cacheline *cl,
192
+
u32 ggtt_offset)
192
193
{
193
-
if (cl)
194
-
i915_active_acquire(&cl->active);
194
+
if (!cl)
195
+
return;
196
+
197
+
cl->ggtt_offset = ggtt_offset;
198
+
i915_active_acquire(&cl->active);
195
199
}
196
200
197
201
static void cacheline_release(struct intel_timeline_cacheline *cl)
···
344
340
GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
345
341
tl->fence_context, tl->hwsp_offset);
346
342
347
-
cacheline_acquire(tl->hwsp_cacheline);
343
+
cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
348
344
if (atomic_fetch_inc(&tl->pin_count)) {
349
345
cacheline_release(tl->hwsp_cacheline);
350
346
__i915_vma_unpin(tl->hwsp_ggtt);
···
519
515
GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
520
516
tl->fence_context, tl->hwsp_offset);
521
517
522
-
cacheline_acquire(cl);
518
+
cacheline_acquire(cl, tl->hwsp_offset);
523
519
tl->hwsp_cacheline = cl;
524
520
525
521
*seqno = timeline_advance(tl);
···
577
573
if (err)
578
574
goto out;
579
575
580
-
*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
581
-
ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES;
582
-
576
+
*hwsp = cl->ggtt_offset;
583
577
out:
584
578
i915_active_release(&cl->active);
585
579
return err;
+2
drivers/gpu/drm/i915/gt/intel_timeline_types.h
+2
drivers/gpu/drm/i915/gt/intel_timeline_types.h
+44
-3
drivers/gpu/drm/i915/gvt/handlers.c
+44
-3
drivers/gpu/drm/i915/gvt/handlers.c
···
1489
1489
const struct intel_engine_cs *engine =
1490
1490
intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1491
1491
1492
-
if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1492
+
if (value != 0 &&
1493
+
!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1493
1494
gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1494
1495
offset, value);
1495
1496
return -EINVAL;
···
1648
1647
unsigned int offset, void *p_data, unsigned int bytes)
1649
1648
{
1650
1649
vgpu_vreg(vgpu, offset) = 0;
1650
+
return 0;
1651
+
}
1652
+
1653
+
/**
1654
+
* FixMe:
1655
+
* If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
1656
+
* 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
1657
+
* Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
1658
+
* these MI_BATCH_BUFFER.
1659
+
* Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
1660
+
* PML4 PTE: PAT(0) PCD(1) PWT(1).
1661
+
* The performance is still expected to be low, will need further improvement.
1662
+
*/
1663
+
static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
1664
+
void *p_data, unsigned int bytes)
1665
+
{
1666
+
u64 pat =
1667
+
GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1668
+
GEN8_PPAT(1, 0) |
1669
+
GEN8_PPAT(2, 0) |
1670
+
GEN8_PPAT(3, CHV_PPAT_SNOOP) |
1671
+
GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1672
+
GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1673
+
GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1674
+
GEN8_PPAT(7, CHV_PPAT_SNOOP);
1675
+
1676
+
vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
1677
+
1651
1678
return 0;
1652
1679
}
1653
1680
···
2841
2812
2842
2813
MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2843
2814
2844
-
MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2815
+
MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
2845
2816
MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2846
2817
2847
2818
MMIO_D(GAMTARBMODE, D_BDW_PLUS);
···
3168
3139
NULL, NULL);
3169
3140
3170
3141
MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
3171
-
MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
3142
+
MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
3172
3143
3173
3144
return 0;
3174
3145
}
···
3342
3313
MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3343
3314
MMIO_D(GEN6_GFXPAUSE, D_BXT);
3344
3315
MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
3316
+
MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3317
+
MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
3318
+
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3319
+
0, 0, D_BXT, NULL, NULL);
3320
+
MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3321
+
0, 0, D_BXT, NULL, NULL);
3322
+
MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3323
+
0, 0, D_BXT, NULL, NULL);
3324
+
MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
3325
+
0, 0, D_BXT, NULL, NULL);
3345
3326
3346
3327
MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3328
+
3329
+
MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
3347
3330
3348
3331
return 0;
3349
3332
}
+8
-7
drivers/gpu/drm/i915/gvt/scheduler.c
+8
-7
drivers/gpu/drm/i915/gvt/scheduler.c
···
1277
1277
1278
1278
i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
1279
1279
for_each_engine(engine, vgpu->gvt->gt, id)
1280
-
intel_context_unpin(s->shadow[id]);
1280
+
intel_context_put(s->shadow[id]);
1281
1281
1282
1282
kmem_cache_destroy(s->workloads);
1283
1283
}
···
1369
1369
ce->ring = __intel_context_ring_size(ring_size);
1370
1370
}
1371
1371
1372
-
ret = intel_context_pin(ce);
1373
-
intel_context_put(ce);
1374
-
if (ret)
1375
-
goto out_shadow_ctx;
1376
-
1377
1372
s->shadow[i] = ce;
1378
1373
}
1379
1374
···
1400
1405
if (IS_ERR(s->shadow[i]))
1401
1406
break;
1402
1407
1403
-
intel_context_unpin(s->shadow[i]);
1404
1408
intel_context_put(s->shadow[i]);
1405
1409
}
1406
1410
i915_vm_put(&ppgtt->vm);
···
1473
1479
{
1474
1480
struct intel_vgpu_submission *s = &workload->vgpu->submission;
1475
1481
1482
+
intel_context_unpin(s->shadow[workload->engine->id]);
1476
1483
release_shadow_batch_buffer(workload);
1477
1484
release_shadow_wa_ctx(&workload->wa_ctx);
1478
1485
···
1715
1720
if (ret) {
1716
1721
if (vgpu_is_vm_unhealthy(ret))
1717
1722
enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1723
+
intel_vgpu_destroy_workload(workload);
1724
+
return ERR_PTR(ret);
1725
+
}
1726
+
1727
+
ret = intel_context_pin(s->shadow[engine->id]);
1728
+
if (ret) {
1718
1729
intel_vgpu_destroy_workload(workload);
1719
1730
return ERR_PTR(ret);
1720
1731
}
+4
-2
drivers/gpu/drm/i915/i915_vma.c
+4
-2
drivers/gpu/drm/i915/i915_vma.c
···
314
314
{
315
315
struct i915_vma_work *vw = container_of(work, typeof(*vw), base);
316
316
317
-
if (vw->pinned)
317
+
if (vw->pinned) {
318
318
__i915_gem_object_unpin_pages(vw->pinned);
319
+
i915_gem_object_put(vw->pinned);
320
+
}
319
321
320
322
i915_vm_free_pt_stash(vw->vm, &vw->stash);
321
323
i915_vm_put(vw->vm);
···
433
431
434
432
if (vma->obj) {
435
433
__i915_gem_object_pin_pages(vma->obj);
436
-
work->pinned = vma->obj;
434
+
work->pinned = i915_gem_object_get(vma->obj);
437
435
}
438
436
} else {
439
437
vma->ops->bind_vma(vma->vm, NULL, vma, cache_level, bind_flags);
+3
-14
drivers/gpu/drm/imx/dw_hdmi-imx.c
+3
-14
drivers/gpu/drm/imx/dw_hdmi-imx.c
···
111
111
return 0;
112
112
}
113
113
114
-
static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
115
-
{
116
-
}
117
-
118
114
static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
119
115
{
120
116
struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
···
136
140
137
141
static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
138
142
.enable = dw_hdmi_imx_encoder_enable,
139
-
.disable = dw_hdmi_imx_encoder_disable,
140
143
.atomic_check = dw_hdmi_imx_atomic_check,
141
144
};
142
145
···
214
219
hdmi->dev = &pdev->dev;
215
220
encoder = &hdmi->encoder;
216
221
217
-
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
218
-
/*
219
-
* If we failed to find the CRTC(s) which this encoder is
220
-
* supposed to be connected to, it's because the CRTC has
221
-
* not been registered yet. Defer probing, and hope that
222
-
* the required CRTC is added later.
223
-
*/
224
-
if (encoder->possible_crtcs == 0)
225
-
return -EPROBE_DEFER;
222
+
ret = imx_drm_encoder_parse_of(drm, encoder, dev->of_node);
223
+
if (ret)
224
+
return ret;
226
225
227
226
ret = dw_hdmi_imx_parse_dt(hdmi);
228
227
if (ret < 0)
+5
-5
drivers/gpu/drm/imx/imx-drm-core.c
+5
-5
drivers/gpu/drm/imx/imx-drm-core.c
···
20
20
#include <drm/drm_fb_helper.h>
21
21
#include <drm/drm_gem_cma_helper.h>
22
22
#include <drm/drm_gem_framebuffer_helper.h>
23
+
#include <drm/drm_managed.h>
23
24
#include <drm/drm_of.h>
24
25
#include <drm/drm_plane_helper.h>
25
26
#include <drm/drm_probe_helper.h>
···
213
212
drm->mode_config.allow_fb_modifiers = true;
214
213
drm->mode_config.normalize_zpos = true;
215
214
216
-
drm_mode_config_init(drm);
215
+
ret = drmm_mode_config_init(drm);
216
+
if (ret)
217
+
return ret;
217
218
218
219
ret = drm_vblank_init(drm, MAX_CRTC);
219
220
if (ret)
···
254
251
drm_kms_helper_poll_fini(drm);
255
252
component_unbind_all(drm->dev, drm);
256
253
err_kms:
257
-
drm_mode_config_cleanup(drm);
258
254
drm_dev_put(drm);
259
255
260
256
return ret;
···
269
267
270
268
component_unbind_all(drm->dev, drm);
271
269
272
-
drm_mode_config_cleanup(drm);
270
+
drm_dev_put(drm);
273
271
274
272
dev_set_drvdata(dev, NULL);
275
-
276
-
drm_dev_put(drm);
277
273
}
278
274
279
275
static const struct component_master_ops imx_drm_ops = {
+4
-6
drivers/gpu/drm/imx/imx-ldb.c
+4
-6
drivers/gpu/drm/imx/imx-ldb.c
···
62
62
struct i2c_adapter *ddc;
63
63
int chno;
64
64
void *edid;
65
-
int edid_len;
66
65
struct drm_display_mode mode;
67
66
int mode_valid;
68
67
u32 bus_format;
···
535
536
}
536
537
537
538
if (!channel->ddc) {
539
+
int edid_len;
540
+
538
541
/* if no DDC available, fallback to hardcoded EDID */
539
542
dev_dbg(dev, "no ddc available\n");
540
543
541
-
edidp = of_get_property(child, "edid",
542
-
&channel->edid_len);
544
+
edidp = of_get_property(child, "edid", &edid_len);
543
545
if (edidp) {
544
-
channel->edid = kmemdup(edidp,
545
-
channel->edid_len,
546
-
GFP_KERNEL);
546
+
channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
547
547
} else if (!channel->panel) {
548
548
/* fallback to display-timings node */
549
549
ret = of_get_drm_display_mode(child,
+6
-34
drivers/gpu/drm/imx/imx-tve.c
+6
-34
drivers/gpu/drm/imx/imx-tve.c
···
13
13
#include <linux/platform_device.h>
14
14
#include <linux/regmap.h>
15
15
#include <linux/regulator/consumer.h>
16
-
#include <linux/spinlock.h>
17
16
#include <linux/videodev2.h>
18
17
19
18
#include <video/imx-ipu-v3.h>
···
103
104
struct drm_connector connector;
104
105
struct drm_encoder encoder;
105
106
struct device *dev;
106
-
spinlock_t lock; /* register lock */
107
-
bool enabled;
108
107
int mode;
109
108
int di_hsync_pin;
110
109
int di_vsync_pin;
···
126
129
return container_of(e, struct imx_tve, encoder);
127
130
}
128
131
129
-
static void tve_lock(void *__tve)
130
-
__acquires(&tve->lock)
131
-
{
132
-
struct imx_tve *tve = __tve;
133
-
134
-
spin_lock(&tve->lock);
135
-
}
136
-
137
-
static void tve_unlock(void *__tve)
138
-
__releases(&tve->lock)
139
-
{
140
-
struct imx_tve *tve = __tve;
141
-
142
-
spin_unlock(&tve->lock);
143
-
}
144
-
145
132
static void tve_enable(struct imx_tve *tve)
146
133
{
147
-
if (!tve->enabled) {
148
-
tve->enabled = true;
149
-
clk_prepare_enable(tve->clk);
150
-
regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
151
-
TVE_EN, TVE_EN);
152
-
}
134
+
clk_prepare_enable(tve->clk);
135
+
regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
153
136
154
137
/* clear interrupt status register */
155
138
regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
···
146
169
147
170
static void tve_disable(struct imx_tve *tve)
148
171
{
149
-
if (tve->enabled) {
150
-
tve->enabled = false;
151
-
regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
152
-
clk_disable_unprepare(tve->clk);
153
-
}
172
+
regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
173
+
clk_disable_unprepare(tve->clk);
154
174
}
155
175
156
176
static int tve_setup_tvout(struct imx_tve *tve)
···
474
500
475
501
.readable_reg = imx_tve_readable_reg,
476
502
477
-
.lock = tve_lock,
478
-
.unlock = tve_unlock,
503
+
.fast_io = true,
479
504
480
505
.max_register = 0xdc,
481
506
};
···
484
511
[TVE_MODE_VGA] = "vga",
485
512
};
486
513
487
-
static const int of_get_tve_mode(struct device_node *np)
514
+
static int of_get_tve_mode(struct device_node *np)
488
515
{
489
516
const char *bm;
490
517
int ret, i;
···
517
544
memset(tve, 0, sizeof(*tve));
518
545
519
546
tve->dev = dev;
520
-
spin_lock_init(&tve->lock);
521
547
522
548
ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
523
549
if (ddc_node) {
+3
-17
drivers/gpu/drm/imx/parallel-display.c
+3
-17
drivers/gpu/drm/imx/parallel-display.c
···
28
28
struct drm_bridge bridge;
29
29
struct device *dev;
30
30
void *edid;
31
-
int edid_len;
32
31
u32 bus_format;
33
32
u32 bus_flags;
34
33
struct drm_display_mode mode;
···
38
39
static inline struct imx_parallel_display *con_to_imxpd(struct drm_connector *c)
39
40
{
40
41
return container_of(c, struct imx_parallel_display, connector);
41
-
}
42
-
43
-
static inline struct imx_parallel_display *enc_to_imxpd(struct drm_encoder *e)
44
-
{
45
-
return container_of(e, struct imx_parallel_display, encoder);
46
42
}
47
43
48
44
static inline struct imx_parallel_display *bridge_to_imxpd(struct drm_bridge *b)
···
304
310
struct device_node *np = dev->of_node;
305
311
const u8 *edidp;
306
312
struct imx_parallel_display *imxpd;
313
+
int edid_len;
307
314
int ret;
308
315
u32 bus_format = 0;
309
316
const char *fmt;
···
318
323
if (ret && ret != -ENODEV)
319
324
return ret;
320
325
321
-
edidp = of_get_property(np, "edid", &imxpd->edid_len);
326
+
edidp = of_get_property(np, "edid", &edid_len);
322
327
if (edidp)
323
-
imxpd->edid = kmemdup(edidp, imxpd->edid_len, GFP_KERNEL);
328
+
imxpd->edid = devm_kmemdup(dev, edidp, edid_len, GFP_KERNEL);
324
329
325
330
ret = of_property_read_string(np, "interface-pix-fmt", &fmt);
326
331
if (!ret) {
···
344
349
return 0;
345
350
}
346
351
347
-
static void imx_pd_unbind(struct device *dev, struct device *master,
348
-
void *data)
349
-
{
350
-
struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
351
-
352
-
kfree(imxpd->edid);
353
-
}
354
-
355
352
static const struct component_ops imx_pd_ops = {
356
353
.bind = imx_pd_bind,
357
-
.unbind = imx_pd_unbind,
358
354
};
359
355
360
356
static int imx_pd_probe(struct platform_device *pdev)
+3
-2
drivers/gpu/drm/panfrost/panfrost_drv.c
+3
-2
drivers/gpu/drm/panfrost/panfrost_drv.c
···
626
626
err_out1:
627
627
pm_runtime_disable(pfdev->dev);
628
628
panfrost_device_fini(pfdev);
629
+
pm_runtime_set_suspended(pfdev->dev);
629
630
err_out0:
630
631
drm_dev_put(ddev);
631
632
return err;
···
641
640
panfrost_gem_shrinker_cleanup(ddev);
642
641
643
642
pm_runtime_get_sync(pfdev->dev);
644
-
panfrost_device_fini(pfdev);
645
-
pm_runtime_put_sync_suspend(pfdev->dev);
646
643
pm_runtime_disable(pfdev->dev);
644
+
panfrost_device_fini(pfdev);
645
+
pm_runtime_set_suspended(pfdev->dev);
647
646
648
647
drm_dev_put(ddev);
649
648
return 0;
+1
-3
drivers/gpu/drm/panfrost/panfrost_gem.c
+1
-3
drivers/gpu/drm/panfrost/panfrost_gem.c
···
105
105
kref_put(&mapping->refcount, panfrost_gem_mapping_release);
106
106
}
107
107
108
-
void panfrost_gem_teardown_mappings(struct panfrost_gem_object *bo)
108
+
void panfrost_gem_teardown_mappings_locked(struct panfrost_gem_object *bo)
109
109
{
110
110
struct panfrost_gem_mapping *mapping;
111
111
112
-
mutex_lock(&bo->mappings.lock);
113
112
list_for_each_entry(mapping, &bo->mappings.list, node)
114
113
panfrost_gem_teardown_mapping(mapping);
115
-
mutex_unlock(&bo->mappings.lock);
116
114
}
117
115
118
116
int panfrost_gem_open(struct drm_gem_object *obj, struct drm_file *file_priv)
+1
-1
drivers/gpu/drm/panfrost/panfrost_gem.h
+1
-1
drivers/gpu/drm/panfrost/panfrost_gem.h
···
82
82
panfrost_gem_mapping_get(struct panfrost_gem_object *bo,
83
83
struct panfrost_file_priv *priv);
84
84
void panfrost_gem_mapping_put(struct panfrost_gem_mapping *mapping);
85
-
void panfrost_gem_teardown_mappings(struct panfrost_gem_object *bo);
85
+
void panfrost_gem_teardown_mappings_locked(struct panfrost_gem_object *bo);
86
86
87
87
void panfrost_gem_shrinker_init(struct drm_device *dev);
88
88
void panfrost_gem_shrinker_cleanup(struct drm_device *dev);
+11
-3
drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c
+11
-3
drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c
···
40
40
{
41
41
struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
42
42
struct panfrost_gem_object *bo = to_panfrost_bo(obj);
43
+
bool ret = false;
43
44
44
45
if (atomic_read(&bo->gpu_usecount))
45
46
return false;
46
47
47
-
if (!mutex_trylock(&shmem->pages_lock))
48
+
if (!mutex_trylock(&bo->mappings.lock))
48
49
return false;
49
50
50
-
panfrost_gem_teardown_mappings(bo);
51
+
if (!mutex_trylock(&shmem->pages_lock))
52
+
goto unlock_mappings;
53
+
54
+
panfrost_gem_teardown_mappings_locked(bo);
51
55
drm_gem_shmem_purge_locked(obj);
56
+
ret = true;
52
57
53
58
mutex_unlock(&shmem->pages_lock);
54
-
return true;
59
+
60
+
unlock_mappings:
61
+
mutex_unlock(&bo->mappings.lock);
62
+
return ret;
55
63
}
56
64
57
65
static unsigned long
+5
-4
drivers/gpu/drm/vc4/vc4_bo.c
+5
-4
drivers/gpu/drm/vc4/vc4_bo.c
···
449
449
}
450
450
451
451
if (IS_ERR(cma_obj)) {
452
-
struct drm_printer p = drm_info_printer(vc4->dev->dev);
452
+
struct drm_printer p = drm_info_printer(vc4->base.dev);
453
453
DRM_ERROR("Failed to allocate from CMA:\n");
454
454
vc4_bo_stats_print(&p, vc4);
455
455
return ERR_PTR(-ENOMEM);
···
590
590
{
591
591
struct vc4_dev *vc4 =
592
592
container_of(work, struct vc4_dev, bo_cache.time_work);
593
-
struct drm_device *dev = vc4->dev;
593
+
struct drm_device *dev = &vc4->base;
594
594
595
595
mutex_lock(&vc4->bo_lock);
596
596
vc4_bo_cache_free_old(dev);
···
1005
1005
return 0;
1006
1006
}
1007
1007
1008
+
static void vc4_bo_cache_destroy(struct drm_device *dev, void *unused);
1008
1009
int vc4_bo_cache_init(struct drm_device *dev)
1009
1010
{
1010
1011
struct vc4_dev *vc4 = to_vc4_dev(dev);
···
1034
1033
INIT_WORK(&vc4->bo_cache.time_work, vc4_bo_cache_time_work);
1035
1034
timer_setup(&vc4->bo_cache.time_timer, vc4_bo_cache_time_timer, 0);
1036
1035
1037
-
return 0;
1036
+
return drmm_add_action_or_reset(dev, vc4_bo_cache_destroy, NULL);
1038
1037
}
1039
1038
1040
-
void vc4_bo_cache_destroy(struct drm_device *dev)
1039
+
static void vc4_bo_cache_destroy(struct drm_device *dev, void *unused)
1041
1040
{
1042
1041
struct vc4_dev *vc4 = to_vc4_dev(dev);
1043
1042
int i;
+14
-27
drivers/gpu/drm/vc4/vc4_drv.c
+14
-27
drivers/gpu/drm/vc4/vc4_drv.c
···
257
257
258
258
dev->coherent_dma_mask = DMA_BIT_MASK(32);
259
259
260
-
vc4 = devm_kzalloc(dev, sizeof(*vc4), GFP_KERNEL);
261
-
if (!vc4)
262
-
return -ENOMEM;
263
-
264
260
/* If VC4 V3D is missing, don't advertise render nodes. */
265
261
node = of_find_matching_node_and_match(NULL, vc4_v3d_dt_match, NULL);
266
262
if (!node || !of_device_is_available(node))
267
263
vc4_drm_driver.driver_features &= ~DRIVER_RENDER;
268
264
of_node_put(node);
269
265
270
-
drm = drm_dev_alloc(&vc4_drm_driver, dev);
271
-
if (IS_ERR(drm))
272
-
return PTR_ERR(drm);
266
+
vc4 = devm_drm_dev_alloc(dev, &vc4_drm_driver, struct vc4_dev, base);
267
+
if (IS_ERR(vc4))
268
+
return PTR_ERR(vc4);
269
+
270
+
drm = &vc4->base;
273
271
platform_set_drvdata(pdev, drm);
274
-
vc4->dev = drm;
275
-
drm->dev_private = vc4;
276
272
INIT_LIST_HEAD(&vc4->debugfs_list);
277
273
278
274
mutex_init(&vc4->bin_bo_lock);
279
275
280
276
ret = vc4_bo_cache_init(drm);
281
277
if (ret)
282
-
goto dev_put;
278
+
return ret;
283
279
284
-
drm_mode_config_init(drm);
280
+
ret = drmm_mode_config_init(drm);
281
+
if (ret)
282
+
return ret;
285
283
286
-
vc4_gem_init(drm);
284
+
ret = vc4_gem_init(drm);
285
+
if (ret)
286
+
return ret;
287
287
288
288
ret = component_bind_all(dev, drm);
289
289
if (ret)
290
-
goto gem_destroy;
290
+
return ret;
291
291
292
292
ret = vc4_plane_create_additional_planes(drm);
293
293
if (ret)
···
312
312
313
313
unbind_all:
314
314
component_unbind_all(dev, drm);
315
-
gem_destroy:
316
-
vc4_gem_destroy(drm);
317
-
drm_mode_config_cleanup(drm);
318
-
vc4_bo_cache_destroy(drm);
319
-
dev_put:
320
-
drm_dev_put(drm);
315
+
321
316
return ret;
322
317
}
323
318
324
319
static void vc4_drm_unbind(struct device *dev)
325
320
{
326
321
struct drm_device *drm = dev_get_drvdata(dev);
327
-
struct vc4_dev *vc4 = to_vc4_dev(drm);
328
322
329
323
drm_dev_unregister(drm);
330
324
331
325
drm_atomic_helper_shutdown(drm);
332
-
333
-
drm_mode_config_cleanup(drm);
334
-
335
-
drm_atomic_private_obj_fini(&vc4->load_tracker);
336
-
drm_atomic_private_obj_fini(&vc4->ctm_manager);
337
-
338
-
drm_dev_put(drm);
339
326
}
340
327
341
328
static const struct component_master_ops vc4_drm_ops = {
+4
-5
drivers/gpu/drm/vc4/vc4_drv.h
+4
-5
drivers/gpu/drm/vc4/vc4_drv.h
···
14
14
#include <drm/drm_device.h>
15
15
#include <drm/drm_encoder.h>
16
16
#include <drm/drm_gem_cma_helper.h>
17
+
#include <drm/drm_managed.h>
17
18
#include <drm/drm_mm.h>
18
19
#include <drm/drm_modeset_lock.h>
19
20
···
72
71
};
73
72
74
73
struct vc4_dev {
75
-
struct drm_device *dev;
74
+
struct drm_device base;
76
75
77
76
struct vc4_hvs *hvs;
78
77
struct vc4_v3d *v3d;
···
235
234
static inline struct vc4_dev *
236
235
to_vc4_dev(struct drm_device *dev)
237
236
{
238
-
return (struct vc4_dev *)dev->dev_private;
237
+
return container_of(dev, struct vc4_dev, base);
239
238
}
240
239
241
240
struct vc4_bo {
···
810
809
struct sg_table *sgt);
811
810
void *vc4_prime_vmap(struct drm_gem_object *obj);
812
811
int vc4_bo_cache_init(struct drm_device *dev);
813
-
void vc4_bo_cache_destroy(struct drm_device *dev);
814
812
int vc4_bo_inc_usecnt(struct vc4_bo *bo);
815
813
void vc4_bo_dec_usecnt(struct vc4_bo *bo);
816
814
void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
···
874
874
extern const struct dma_fence_ops vc4_fence_ops;
875
875
876
876
/* vc4_gem.c */
877
-
void vc4_gem_init(struct drm_device *dev);
878
-
void vc4_gem_destroy(struct drm_device *dev);
877
+
int vc4_gem_init(struct drm_device *dev);
879
878
int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
880
879
struct drm_file *file_priv);
881
880
int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
+10
-9
drivers/gpu/drm/vc4/vc4_gem.c
+10
-9
drivers/gpu/drm/vc4/vc4_gem.c
···
314
314
struct vc4_dev *vc4 =
315
315
container_of(work, struct vc4_dev, hangcheck.reset_work);
316
316
317
-
vc4_save_hang_state(vc4->dev);
317
+
vc4_save_hang_state(&vc4->base);
318
318
319
-
vc4_reset(vc4->dev);
319
+
vc4_reset(&vc4->base);
320
320
}
321
321
322
322
static void
323
323
vc4_hangcheck_elapsed(struct timer_list *t)
324
324
{
325
325
struct vc4_dev *vc4 = from_timer(vc4, t, hangcheck.timer);
326
-
struct drm_device *dev = vc4->dev;
326
+
struct drm_device *dev = &vc4->base;
327
327
uint32_t ct0ca, ct1ca;
328
328
unsigned long irqflags;
329
329
struct vc4_exec_info *bin_exec, *render_exec;
···
1000
1000
list_del(&exec->head);
1001
1001
1002
1002
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
1003
-
vc4_complete_exec(vc4->dev, exec);
1003
+
vc4_complete_exec(&vc4->base, exec);
1004
1004
spin_lock_irqsave(&vc4->job_lock, irqflags);
1005
1005
}
1006
1006
···
1258
1258
return 0;
1259
1259
1260
1260
fail:
1261
-
vc4_complete_exec(vc4->dev, exec);
1261
+
vc4_complete_exec(&vc4->base, exec);
1262
1262
1263
1263
return ret;
1264
1264
}
1265
1265
1266
-
void
1267
-
vc4_gem_init(struct drm_device *dev)
1266
+
static void vc4_gem_destroy(struct drm_device *dev, void *unused);
1267
+
int vc4_gem_init(struct drm_device *dev)
1268
1268
{
1269
1269
struct vc4_dev *vc4 = to_vc4_dev(dev);
1270
1270
···
1285
1285
1286
1286
INIT_LIST_HEAD(&vc4->purgeable.list);
1287
1287
mutex_init(&vc4->purgeable.lock);
1288
+
1289
+
return drmm_add_action_or_reset(dev, vc4_gem_destroy, NULL);
1288
1290
}
1289
1291
1290
-
void
1291
-
vc4_gem_destroy(struct drm_device *dev)
1292
+
static void vc4_gem_destroy(struct drm_device *dev, void *unused)
1292
1293
{
1293
1294
struct vc4_dev *vc4 = to_vc4_dev(dev);
1294
1295
+2
-2
drivers/gpu/drm/vc4/vc4_hvs.c
+2
-2
drivers/gpu/drm/vc4/vc4_hvs.c
···
560
560
{
561
561
struct platform_device *pdev = to_platform_device(dev);
562
562
struct drm_device *drm = dev_get_drvdata(master);
563
-
struct vc4_dev *vc4 = drm->dev_private;
563
+
struct vc4_dev *vc4 = to_vc4_dev(drm);
564
564
struct vc4_hvs *hvs = NULL;
565
565
int ret;
566
566
u32 dispctrl;
···
679
679
void *data)
680
680
{
681
681
struct drm_device *drm = dev_get_drvdata(master);
682
-
struct vc4_dev *vc4 = drm->dev_private;
682
+
struct vc4_dev *vc4 = to_vc4_dev(drm);
683
683
struct vc4_hvs *hvs = vc4->hvs;
684
684
685
685
if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
+58
-22
drivers/gpu/drm/vc4/vc4_kms.c
+58
-22
drivers/gpu/drm/vc4/vc4_kms.c
···
51
51
struct drm_private_obj *manager)
52
52
{
53
53
struct drm_device *dev = state->dev;
54
-
struct vc4_dev *vc4 = dev->dev_private;
54
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
55
55
struct drm_private_state *priv_state;
56
56
int ret;
57
57
···
92
92
.atomic_duplicate_state = vc4_ctm_duplicate_state,
93
93
.atomic_destroy_state = vc4_ctm_destroy_state,
94
94
};
95
+
96
+
static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
97
+
{
98
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
99
+
100
+
drm_atomic_private_obj_fini(&vc4->ctm_manager);
101
+
}
102
+
103
+
static int vc4_ctm_obj_init(struct vc4_dev *vc4)
104
+
{
105
+
struct vc4_ctm_state *ctm_state;
106
+
107
+
drm_modeset_lock_init(&vc4->ctm_state_lock);
108
+
109
+
ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
110
+
if (!ctm_state)
111
+
return -ENOMEM;
112
+
113
+
drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
114
+
&vc4_ctm_state_funcs);
115
+
116
+
return drmm_add_action(&vc4->base, vc4_ctm_obj_fini, NULL);
117
+
}
95
118
96
119
/* Converts a DRM S31.32 value to the HW S0.9 format. */
97
120
static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
···
632
609
.atomic_destroy_state = vc4_load_tracker_destroy_state,
633
610
};
634
611
612
+
static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
613
+
{
614
+
struct vc4_dev *vc4 = to_vc4_dev(dev);
615
+
616
+
if (!vc4->load_tracker_available)
617
+
return;
618
+
619
+
drm_atomic_private_obj_fini(&vc4->load_tracker);
620
+
}
621
+
622
+
static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
623
+
{
624
+
struct vc4_load_tracker_state *load_state;
625
+
626
+
if (!vc4->load_tracker_available)
627
+
return 0;
628
+
629
+
load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
630
+
if (!load_state)
631
+
return -ENOMEM;
632
+
633
+
drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
634
+
&load_state->base,
635
+
&vc4_load_tracker_state_funcs);
636
+
637
+
return drmm_add_action(&vc4->base, vc4_load_tracker_obj_fini, NULL);
638
+
}
639
+
635
640
#define NUM_OUTPUTS 6
636
641
#define NUM_CHANNELS 3
637
642
···
762
711
int vc4_kms_load(struct drm_device *dev)
763
712
{
764
713
struct vc4_dev *vc4 = to_vc4_dev(dev);
765
-
struct vc4_ctm_state *ctm_state;
766
-
struct vc4_load_tracker_state *load_state;
767
714
bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
768
715
"brcm,bcm2711-vc5");
769
716
int ret;
···
800
751
dev->mode_config.async_page_flip = true;
801
752
dev->mode_config.allow_fb_modifiers = true;
802
753
803
-
drm_modeset_lock_init(&vc4->ctm_state_lock);
754
+
ret = vc4_ctm_obj_init(vc4);
755
+
if (ret)
756
+
return ret;
804
757
805
-
ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
806
-
if (!ctm_state)
807
-
return -ENOMEM;
808
-
809
-
drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base,
810
-
&vc4_ctm_state_funcs);
811
-
812
-
if (vc4->load_tracker_available) {
813
-
load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
814
-
if (!load_state) {
815
-
drm_atomic_private_obj_fini(&vc4->ctm_manager);
816
-
return -ENOMEM;
817
-
}
818
-
819
-
drm_atomic_private_obj_init(dev, &vc4->load_tracker,
820
-
&load_state->base,
821
-
&vc4_load_tracker_state_funcs);
822
-
}
758
+
ret = vc4_load_tracker_obj_init(vc4);
759
+
if (ret)
760
+
return ret;
823
761
824
762
drm_mode_config_reset(dev);
825
763
+6
-6
drivers/gpu/drm/vc4/vc4_v3d.c
+6
-6
drivers/gpu/drm/vc4/vc4_v3d.c
···
168
168
169
169
int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
170
170
{
171
-
struct drm_device *dev = vc4->dev;
171
+
struct drm_device *dev = &vc4->base;
172
172
unsigned long irqflags;
173
173
int slot;
174
174
uint64_t seqno = 0;
···
246
246
INIT_LIST_HEAD(&list);
247
247
248
248
while (true) {
249
-
struct vc4_bo *bo = vc4_bo_create(vc4->dev, size, true,
249
+
struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true,
250
250
VC4_BO_TYPE_BIN);
251
251
252
252
if (IS_ERR(bo)) {
···
361
361
struct vc4_v3d *v3d = dev_get_drvdata(dev);
362
362
struct vc4_dev *vc4 = v3d->vc4;
363
363
364
-
vc4_irq_uninstall(vc4->dev);
364
+
vc4_irq_uninstall(&vc4->base);
365
365
366
366
clk_disable_unprepare(v3d->clk);
367
367
···
378
378
if (ret != 0)
379
379
return ret;
380
380
381
-
vc4_v3d_init_hw(vc4->dev);
381
+
vc4_v3d_init_hw(&vc4->base);
382
382
383
383
/* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */
384
-
enable_irq(vc4->dev->irq);
385
-
vc4_irq_postinstall(vc4->dev);
384
+
enable_irq(vc4->base.irq);
385
+
vc4_irq_postinstall(&vc4->base);
386
386
387
387
return 0;
388
388
}
-67
drivers/gpu/ipu-v3/ipu-common.c
-67
drivers/gpu/ipu-v3/ipu-common.c
···
133
133
}
134
134
EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
135
135
136
-
bool ipu_pixelformat_is_planar(u32 pixelformat)
137
-
{
138
-
switch (pixelformat) {
139
-
case V4L2_PIX_FMT_YUV420:
140
-
case V4L2_PIX_FMT_YVU420:
141
-
case V4L2_PIX_FMT_YUV422P:
142
-
case V4L2_PIX_FMT_NV12:
143
-
case V4L2_PIX_FMT_NV21:
144
-
case V4L2_PIX_FMT_NV16:
145
-
case V4L2_PIX_FMT_NV61:
146
-
return true;
147
-
}
148
-
149
-
return false;
150
-
}
151
-
EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
152
-
153
-
enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
154
-
{
155
-
switch (mbus_code & 0xf000) {
156
-
case 0x1000:
157
-
return IPUV3_COLORSPACE_RGB;
158
-
case 0x2000:
159
-
return IPUV3_COLORSPACE_YUV;
160
-
default:
161
-
return IPUV3_COLORSPACE_UNKNOWN;
162
-
}
163
-
}
164
-
EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
165
-
166
-
int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
167
-
{
168
-
switch (pixelformat) {
169
-
case V4L2_PIX_FMT_YUV420:
170
-
case V4L2_PIX_FMT_YVU420:
171
-
case V4L2_PIX_FMT_YUV422P:
172
-
case V4L2_PIX_FMT_NV12:
173
-
case V4L2_PIX_FMT_NV21:
174
-
case V4L2_PIX_FMT_NV16:
175
-
case V4L2_PIX_FMT_NV61:
176
-
/*
177
-
* for the planar YUV formats, the stride passed to
178
-
* cpmem must be the stride in bytes of the Y plane.
179
-
* And all the planar YUV formats have an 8-bit
180
-
* Y component.
181
-
*/
182
-
return (8 * pixel_stride) >> 3;
183
-
case V4L2_PIX_FMT_RGB565:
184
-
case V4L2_PIX_FMT_YUYV:
185
-
case V4L2_PIX_FMT_UYVY:
186
-
return (16 * pixel_stride) >> 3;
187
-
case V4L2_PIX_FMT_BGR24:
188
-
case V4L2_PIX_FMT_RGB24:
189
-
return (24 * pixel_stride) >> 3;
190
-
case V4L2_PIX_FMT_BGR32:
191
-
case V4L2_PIX_FMT_RGB32:
192
-
case V4L2_PIX_FMT_XBGR32:
193
-
case V4L2_PIX_FMT_XRGB32:
194
-
return (32 * pixel_stride) >> 3;
195
-
default:
196
-
break;
197
-
}
198
-
199
-
return -EINVAL;
200
-
}
201
-
EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
202
-
203
136
int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
204
137
bool hflip, bool vflip)
205
138
{
-3
include/video/imx-ipu-v3.h
-3
include/video/imx-ipu-v3.h
···
484
484
485
485
enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
486
486
enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
487
-
enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
488
-
int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
489
-
bool ipu_pixelformat_is_planar(u32 pixelformat);
490
487
int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
491
488
bool hflip, bool vflip);
492
489
int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
+1
-1
lib/fonts/font_10x18.c
+1
-1
lib/fonts/font_10x18.c
+1
-1
lib/fonts/font_6x10.c
+1
-1
lib/fonts/font_6x10.c
+1
-1
lib/fonts/font_6x11.c
+1
-1
lib/fonts/font_6x11.c
+1
-1
lib/fonts/font_6x8.c
+1
-1
lib/fonts/font_6x8.c
+1
-1
lib/fonts/font_7x14.c
+1
-1
lib/fonts/font_7x14.c
+1
-1
lib/fonts/font_8x16.c
+1
-1
lib/fonts/font_8x16.c
+1
-1
lib/fonts/font_8x8.c
+1
-1
lib/fonts/font_8x8.c
+1
-1
lib/fonts/font_acorn_8x8.c
+1
-1
lib/fonts/font_acorn_8x8.c
···
5
5
6
6
#define FONTDATAMAX 2048
7
7
8
-
static struct font_data acorndata_8x8 = {
8
+
static const struct font_data acorndata_8x8 = {
9
9
{ 0, 0, FONTDATAMAX, 0 }, {
10
10
/* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^@ */
11
11
/* 01 */ 0x7e, 0x81, 0xa5, 0x81, 0xbd, 0x99, 0x81, 0x7e, /* ^A */
+1
-1
lib/fonts/font_mini_4x6.c
+1
-1
lib/fonts/font_mini_4x6.c
+1
-1
lib/fonts/font_pearl_8x8.c
+1
-1
lib/fonts/font_pearl_8x8.c
+1
-1
lib/fonts/font_sun12x22.c
+1
-1
lib/fonts/font_sun12x22.c
+1
-1
lib/fonts/font_sun8x16.c
+1
-1
lib/fonts/font_sun8x16.c
···
3
3
4
4
#define FONTDATAMAX 4096
5
5
6
-
static struct font_data fontdata_sun8x16 = {
6
+
static const struct font_data fontdata_sun8x16 = {
7
7
{ 0, 0, FONTDATAMAX, 0 }, {
8
8
/* */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
9
9
/* */ 0x00,0x00,0x7e,0x81,0xa5,0x81,0x81,0xbd,0x99,0x81,0x81,0x7e,0x00,0x00,0x00,0x00,
+1
-1
lib/fonts/font_ter16x32.c
+1
-1
lib/fonts/font_ter16x32.c