Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
Add a wrapper on cx0 powerdown change sequence for LT Phy usage,
as the sequence remains unchanged when going from SNPS Phy to
LT Phy.
Bspec: 74495
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
+18
-3
+3
-3
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+3
-3
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
2802
2802
return val;
2803
2803
}
2804
2804
2805
-
static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
2806
-
u8 lane_mask, u8 state)
2805
+
void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
2806
+
u8 lane_mask, u8 state)
2807
2807
{
2808
2808
struct intel_display *display = to_intel_display(encoder);
2809
2809
enum port port = encoder->port;
···
2833
2833
/* Update Timeout Value */
2834
2834
if (intel_de_wait_custom(display, buf_ctl2_reg,
2835
2835
intel_cx0_get_powerdown_update(lane_mask), 0,
2836
-
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
2836
+
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
2837
2837
drm_warn(display->drm,
2838
2838
"PHY %c failed to bring out of Lane reset after %dus.\n",
2839
2839
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
+2
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+2
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
41
41
const struct intel_cx0pll_state *b);
42
42
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
43
43
const struct intel_crtc_state *crtc_state);
44
+
void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
45
+
u8 lane_mask, u8 state);
44
46
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
45
47
void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
46
48
bool intel_cx0_is_hdmi_frl(u32 clock);
+13
drivers/gpu/drm/i915/display/intel_lt_phy.c
+13
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
44
44
}
45
45
46
46
static void
47
+
intel_lt_phy_powerdown_change_sequence(struct intel_encoder *encoder,
48
+
u8 lane_mask, u8 state)
49
+
{
50
+
intel_cx0_powerdown_change_sequence(encoder, lane_mask, state);
51
+
}
52
+
53
+
static void
47
54
intel_lt_phy_lane_reset(struct intel_encoder *encoder,
48
55
u8 lane_count)
49
56
{
···
77
70
XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP);
78
71
79
72
intel_lt_phy_setup_powerdown(encoder, lane_count);
73
+
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
74
+
XELPDP_P2_STATE_RESET);
80
75
81
76
intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
82
77
XE3PLPD_MACCLK_RESET_0, 0);
···
154
145
{
155
146
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
156
147
bool lane_reversal = dig_port->lane_reversal;
148
+
u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
157
149
158
150
/* 1. Enable MacCLK at default 162 MHz frequency. */
159
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intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
···
163
153
intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
164
154
165
155
/* 3. Change owned PHY lanes power to Ready state. */
156
+
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
157
+
XELPDP_P2_STATE_READY);
158
+
166
159
/*
167
160
* 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
168
161
* encoded rate and encoded mode.