Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'gpio-updates-for-v6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio updates from Bartosz Golaszewski:
"There's one new driver (Apple SMC) and extensions to existing drivers
for supporting new HW models. A lot of different impovements across
drivers and in core GPIO code. Details on that are in the signed tag
as usual.
We managed to remove some of the legacy APIs. Arnd Bergmann started to
work on making the legacy bits optional so that we may compile them
only for older platforms that still really need them.
Rob Herring has done a lot of work to convert legacy .txt dt-bindings
for GPIO controllers to YAML. There are only a few left now in the
GPIO tree.
A big part of the commits in this PR concern the conversion of GPIO
drivers to using the new line value setter callbacks. This conversion
is now complete treewide (unless I've missed something) and once all
the changes from different trees land in mainline, I'll send you
another PR containing a commit dropping the legacy callbacks from the
tree.
As the quest to pay back technical dept never really ends, we're
starting another set of interface conversions, this time it's about
moving fields specific to only a handful of drivers using the
gpio-mmio helper out of the core gpio_chip structure that every
controller implements and uses. This cycle we introduce a new set of
APIs and convert a few drivers under drivers/gpio/, next cycle we'll
convert remaining modules treewide (in gpio, pinctrl and mfd trees)
and finally remove the old interfaces and move the gpio-mmio fields
into their own structure wrapping gpio_chip.
One last change I should mention here is the rework of the sysfs
interface. In 2016, we introduced the GPIO character device as the
preferred alternative to the sysfs class under /sys/class/gpio. While
it has seen a wide adoption with the help of its user-space
counterpart - libgpiod - there are still users who prefer the
simplicity of sysfs.
As far as the GPIO subsystem is concerned, the problem is not the
existince of the GPIO class as such but rather the fact that it
exposes the global GPIO numbers to the user-space, stopping us from
ever being able to remove the numberspace from the kernel. To that
end, this release we introduced a parallel, limited sysfs interface
that doesn't expose these numbers and only implements a subset of
features that are relevant to the existing users. This is a result of
several discussions over the course of last year and should allow us
to remove the legacy part some time in the future.
Summary:
GPIOLIB core:
- introduce a parallel, limited sysfs user ABI that doesn't expose
the global GPIO numbers to user-space while maintaining backward
compatibility with the end goal of it completely replacing the
existing interface, allowing us to remove it
- remove the legacy devm_gpio_request() routine which has no more
users
- start the process of allowing to compile-out the legacy parts of
the GPIO core for users who don't need it by introducing a new
Kconfig option: GPIOLIB_LEGACY
- don't use global GPIO numbers in debugfs output from the core code
(drivers still do it, the work is ongoing)
- start the process of moving the fields specific to the gpio-mmio
helper out of the core struct gpio_chip into their own structure
that wraps it: create a new header with modern interfaces and
convert several drivers to using it
- remove the platform data structure associated with the gpio-mmio
helper from the kernel after having converted all remaining users
to generic device properties
- remove legacy struct gpio definition as it has no more users
New drivers:
- add the GPIO driver for the Apple System Management Controller
Driver improvements:
- add support for new models to gpio-adp5585, gpio-tps65219 and
gpio-pca953x
- extend the interrupt support in gpio-loongson-64bit
- allow to mark the simulated GPIO lines as invalid in gpio-sim
- convert all remaining GPIO drivers to using the new GPIO value
setter callbacks
- convert gpio-rcar to using simple device power management ops
callbacks
- don't check if current direction of a line is output before setting
the value in gpio-pisosr and ti-fpc202: the GPIO core already
handles that
- also drop unneeded GPIO range checks in drivers, the core already
makes sure we're within bounds when calling driver callbacks
- use dev_fwnode() where applicable across GPIO drivers
- set line value in gpio-zynqmp-modepin and gpio-twl6040 when the
user wants to change direction of the pin to output even though
these drivers don't need to do anything else to actually set the
direction, otherwise a call like gpiod_direction_output(d, 1) will
not result in the line driver high
- remove the reduntant call to pm_runtime_mark_last_busy() from
gpio-arizona
- use lock guards in gpio-cadence and gpio-mxc
- check the return values of regmap functions in gpio-wcd934x and
gpio-tps65912
- use better regmap interfaces in gpio-wcove and gpio-pca953x
- remove dummy GPIO chip callbacks from several drivers in cases
where the GPIO core can already handle their absence
- allow building gpio-palmas as a module
Fixes:
- use correct bit widths (according to the documentation) in
gpio-virtio
Device-tree bindings:
- convert several of the legacy .txt documents for many different
devices to YAML, improving automatic validation
- create a "trivial" GPIO DT schema that covers a wide range of
simple hardware that share a set of basic GPIO properties
- document new HW: Apple MAC SMC GPIO block and adp5589 I/O expander
- document a new model for pca95xx
- add and/or remove properties in YAML documents for gpio-rockchip,
fsl,qoriq-gpio, arm,pl061 and gpio-xilinx
Misc:
- some minor refactoring in several places, adding/removing forward
declarations, moving defines to better places, constify the
arguments in some functions, remove duplicate includes, etc.
- documentation updates"
* tag 'gpio-updates-for-v6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (202 commits)
MIPS: alchemy: gpio: use new GPIO line value setter callbacks for the remaining chips
gpiolib: enable CONFIG_GPIOLIB_LEGACY even for !GPIOLIB
gpio: virtio: Fix config space reading.
gpiolib: make legacy interfaces optional
dt-bindings: gpio: rockchip: Allow use of a power-domain
gpiolib: of: add forward declaration for struct device_node
power: reset: macsmc-reboot: Add driver for rebooting via Apple SMC
gpio: Add new gpio-macsmc driver for Apple Macs
mfd: Add Apple Silicon System Management Controller
soc: apple: rtkit: Make shmem_destroy optional
dt-bindings: mfd: Add Apple Mac System Management Controller
dt-bindings: power: reboot: Add Apple Mac SMC Reboot Controller
dt-bindings: gpio: Add Apple Mac SMC GPIO block
gpio: cadence: Remove duplicated include in gpio-cadence.c
gpio: tps65219: Add support for TI TPS65214 PMIC
gpio: tps65219: Update _IDX & _OFFSET macro prefix
gpio: sysfs: Fix an end of loop test in gpiod_unexport()
dt-bindings: gpio: Convert qca,ar7100-gpio to DT schema
dt-bindings: gpio: Convert maxim,max3191x to DT schema
dt-bindings: gpio: fsl,qoriq-gpio: Add missing mpc8xxx compatibles
...
+6499
-3708
+10
-2
Documentation/ABI/obsolete/sysfs-gpio
+10
-2
Documentation/ABI/obsolete/sysfs-gpio
···
19
19
/export ... asks the kernel to export a GPIO to userspace
20
20
/unexport ... to return a GPIO to the kernel
21
21
/gpioN ... for each exported GPIO #N OR
22
-
/<LINE-NAME> ... for a properly named GPIO line
23
22
/value ... always readable, writes fail for input GPIOs
24
23
/direction ... r/w as: in, out (default low); write: high, low
25
24
/edge ... r/w as: none, falling, rising, both
25
+
/active_low ... r/w as: 0, 1
26
26
/gpiochipN ... for each gpiochip; #N is its first GPIO
27
27
/base ... (r/o) same as N
28
-
/label ... (r/o) descriptive, not necessarily unique
28
+
/label ... (r/o) descriptive chip name
29
29
/ngpio ... (r/o) number of GPIOs; numbered N to N + (ngpio - 1)
30
+
/gpio<OFFSET>
31
+
/value ... always readable, writes fail for input GPIOs
32
+
/direction ... r/w as: in, out (default low); write: high, low
33
+
/chipX ... for each gpiochip; #X is the gpio device ID
34
+
/export ... asks the kernel to export a GPIO at HW offset X to userspace
35
+
/unexport ... to return a GPIO at HW offset X to the kernel
36
+
/label ... (r/o) descriptive chip name
37
+
/ngpio ... (r/o) number of GPIOs exposed by the chip
30
38
31
39
This ABI is obsoleted by Documentation/ABI/testing/gpio-cdev and will be
32
40
removed after 2020.
+5
-2
Documentation/admin-guide/gpio/gpio-sim.rst
+5
-2
Documentation/admin-guide/gpio/gpio-sim.rst
···
50
50
51
51
**Attribute:** ``/config/gpio-sim/gpio-device/gpio-bankX/lineY/name``
52
52
53
-
This group represents a single line at the offset Y. The 'name' attribute
54
-
allows to set the line name as represented by the 'gpio-line-names' property.
53
+
**Attribute:** ``/config/gpio-sim/gpio-device/gpio-bankX/lineY/valid``
54
+
55
+
This group represents a single line at the offset Y. The ``valid`` attribute
56
+
indicates whether the line can be used as GPIO. The ``name`` attribute allows
57
+
to set the line name as represented by the 'gpio-line-names' property.
55
58
56
59
**Item:** ``/config/gpio-sim/gpio-device/gpio-bankX/lineY/hog``
57
60
+1
Documentation/devicetree/bindings/fpga/fpga-region.yaml
+1
Documentation/devicetree/bindings/fpga/fpga-region.yaml
-72
Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
-72
Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
···
1
-
GPIO controllers on MPC8xxx SoCs
2
-
3
-
This is for the non-QE/CPM/GUTs GPIO controllers as found on
4
-
8349, 8572, 8610 and compatible.
5
-
6
-
Every GPIO controller node must have #gpio-cells property defined,
7
-
this information will be used to translate gpio-specifiers.
8
-
See bindings/gpio/gpio.txt for details of how to specify GPIO
9
-
information for devices.
10
-
11
-
The GPIO module usually is connected to the SoC's internal interrupt
12
-
controller, see bindings/interrupt-controller/interrupts.txt (the
13
-
interrupt client nodes section) for details how to specify this GPIO
14
-
module's interrupt.
15
-
16
-
The GPIO module may serve as another interrupt controller (cascaded to
17
-
the SoC's internal interrupt controller). See the interrupt controller
18
-
nodes section in bindings/interrupt-controller/interrupts.txt for
19
-
details.
20
-
21
-
Required properties:
22
-
- compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23
-
for 83xx, "fsl,mpc8572-gpio" for 85xx, or
24
-
"fsl,mpc8610-gpio" for 86xx.
25
-
- #gpio-cells: Should be two. The first cell is the pin number
26
-
and the second cell is used to specify optional
27
-
parameters (currently unused).
28
-
- interrupts: Interrupt mapping for GPIO IRQ.
29
-
- gpio-controller: Marks the port as GPIO controller.
30
-
31
-
Optional properties:
32
-
- interrupt-controller: Empty boolean property which marks the GPIO
33
-
module as an IRQ controller.
34
-
- #interrupt-cells: Should be two. Defines the number of integer
35
-
cells required to specify an interrupt within
36
-
this interrupt controller. The first cell
37
-
defines the pin number, the second cell
38
-
defines additional flags (trigger type,
39
-
trigger polarity). Note that the available
40
-
set of trigger conditions supported by the
41
-
GPIO module depends on the actual SoC.
42
-
43
-
Example of gpio-controller nodes for a MPC8347 SoC:
44
-
45
-
gpio1: gpio-controller@c00 {
46
-
#gpio-cells = <2>;
47
-
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
48
-
reg = <0xc00 0x100>;
49
-
interrupt-parent = <&ipic>;
50
-
interrupts = <74 0x8>;
51
-
gpio-controller;
52
-
interrupt-controller;
53
-
#interrupt-cells = <2>;
54
-
};
55
-
56
-
gpio2: gpio-controller@d00 {
57
-
#gpio-cells = <2>;
58
-
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
59
-
reg = <0xd00 0x100>;
60
-
interrupt-parent = <&ipic>;
61
-
interrupts = <75 0x8>;
62
-
gpio-controller;
63
-
};
64
-
65
-
Example of a peripheral using the GPIO module as an IRQ controller:
66
-
67
-
funkyfpga@0 {
68
-
compatible = "funky-fpga";
69
-
...
70
-
interrupt-parent = <&gpio1>;
71
-
interrupts = <4 3>;
72
-
};
-35
Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt
-35
Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt
···
1
-
* Abilis TB10x GPIO controller
2
-
3
-
Required Properties:
4
-
- compatible: Should be "abilis,tb10x-gpio"
5
-
- reg: Address and length of the register set for the device
6
-
- gpio-controller: Marks the device node as a gpio controller.
7
-
- #gpio-cells: Should be <2>. The first cell is the pin number and the
8
-
second cell is used to specify optional parameters:
9
-
- bit 0 specifies polarity (0 for normal, 1 for inverted).
10
-
- abilis,ngpio: the number of GPIO pins this driver controls.
11
-
12
-
Optional Properties:
13
-
- interrupt-controller: Marks the device node as an interrupt controller.
14
-
- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
15
-
- interrupts: Defines the interrupt line connecting this GPIO controller to
16
-
its parent interrupt controller.
17
-
18
-
GPIO ranges are specified as described in
19
-
Documentation/devicetree/bindings/gpio/gpio.txt
20
-
21
-
Example:
22
-
23
-
gpioa: gpio@ff140000 {
24
-
compatible = "abilis,tb10x-gpio";
25
-
interrupt-controller;
26
-
#interrupt-cells = <1>;
27
-
interrupt-parent = <&tb10x_ictl>;
28
-
interrupts = <27 2>;
29
-
reg = <0xFF140000 0x1000>;
30
-
gpio-controller;
31
-
#gpio-cells = <2>;
32
-
abilis,ngpio = <3>;
33
-
gpio-ranges = <&iomux 0 0 0>;
34
-
gpio-ranges-group-names = "gpioa_pins";
35
-
};
+63
Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.yaml
+63
Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/abilis,tb10x-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Abilis TB10x GPIO controller
8
+
9
+
maintainers:
10
+
- Christian Ruppert <christian.ruppert@abilis.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: abilis,tb10x-gpio
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
gpio-controller: true
20
+
21
+
'#gpio-cells':
22
+
const: 2
23
+
24
+
gpio-ranges: true
25
+
26
+
gpio-ranges-group-names: true
27
+
28
+
interrupt-controller: true
29
+
30
+
'#interrupt-cells':
31
+
const: 1
32
+
description: Interrupts are triggered on both edges
33
+
34
+
interrupts:
35
+
maxItems: 1
36
+
37
+
abilis,ngpio:
38
+
description: Number of GPIO pins this driver controls
39
+
$ref: /schemas/types.yaml#/definitions/uint32
40
+
41
+
required:
42
+
- compatible
43
+
- reg
44
+
- gpio-controller
45
+
- '#gpio-cells'
46
+
- abilis,ngpio
47
+
48
+
additionalProperties: false
49
+
50
+
examples:
51
+
- |
52
+
gpio@ff140000 {
53
+
compatible = "abilis,tb10x-gpio";
54
+
interrupt-controller;
55
+
#interrupt-cells = <1>;
56
+
interrupts = <27 2>;
57
+
reg = <0xff140000 0x1000>;
58
+
gpio-controller;
59
+
#gpio-cells = <2>;
60
+
abilis,ngpio = <3>;
61
+
gpio-ranges = <&iomux 0 0 0>;
62
+
gpio-ranges-group-names = "gpioa_pins";
63
+
};
+75
Documentation/devicetree/bindings/gpio/altr-pio-1.0.yaml
+75
Documentation/devicetree/bindings/gpio/altr-pio-1.0.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/altr-pio-1.0.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Altera GPIO controller
8
+
9
+
maintainers:
10
+
- Dinh Nguyen <dinguyen@kernel.org>
11
+
- Marek Vasut <marex@denx.de>
12
+
- Mathieu Malaterre <malat@debian.org>
13
+
- Tien Hock Loh <thloh@altera.com>
14
+
15
+
properties:
16
+
compatible:
17
+
const: altr,pio-1.0
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
gpio-controller: true
23
+
24
+
"#gpio-cells":
25
+
const: 2
26
+
description:
27
+
First cell is the GPIO offset number. Second cell is reserved and
28
+
currently unused.
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
interrupt-controller: true
34
+
35
+
"#interrupt-cells":
36
+
const: 2
37
+
38
+
altr,ngpio:
39
+
$ref: /schemas/types.yaml#/definitions/uint32
40
+
description: Width of the GPIO bank.
41
+
default: 32
42
+
43
+
altr,interrupt-type:
44
+
$ref: /schemas/types.yaml#/definitions/uint32
45
+
description: >
46
+
Specifies the interrupt trigger type synthesized by hardware.
47
+
Values defined in <dt-bindings/interrupt-controller/irq.h>.
48
+
enum: [1, 2, 3, 4]
49
+
50
+
required:
51
+
- compatible
52
+
- reg
53
+
- gpio-controller
54
+
- "#gpio-cells"
55
+
- interrupts
56
+
- interrupt-controller
57
+
- "#interrupt-cells"
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/interrupt-controller/irq.h>
64
+
65
+
gpio@ff200000 {
66
+
compatible = "altr,pio-1.0";
67
+
reg = <0xff200000 0x10>;
68
+
interrupts = <45 4>;
69
+
interrupt-controller;
70
+
#interrupt-cells = <2>;
71
+
gpio-controller;
72
+
#gpio-cells = <2>;
73
+
altr,ngpio = <32>;
74
+
altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
75
+
};
+94
Documentation/devicetree/bindings/gpio/apm,xgene-gpio-sb.yaml
+94
Documentation/devicetree/bindings/gpio/apm,xgene-gpio-sb.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/apm,xgene-gpio-sb.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: APM X-Gene Standby GPIO controller
8
+
9
+
maintainers:
10
+
- Khuong Dinh <khuong@os.amperecomputing.com>
11
+
12
+
description: |
13
+
This is a gpio controller in the standby domain. It also supports interrupt in
14
+
some particular pins which are sourced to its parent interrupt controller
15
+
as diagram below:
16
+
+-----------------+
17
+
| X-Gene standby |
18
+
| GPIO controller +------ GPIO_0
19
+
+------------+ | | ...
20
+
| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
21
+
| controller | (SPI40) | | ...
22
+
| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
23
+
| | ... | |
24
+
| | EXT_INT_N | +------ GPIO_[N+9]
25
+
| | (SPI[40 + N])| | ...
26
+
| +--------------+ +------ GPIO_MAX
27
+
+------------+ +-----------------+
28
+
29
+
properties:
30
+
compatible:
31
+
const: apm,xgene-gpio-sb
32
+
33
+
reg:
34
+
maxItems: 1
35
+
36
+
'#gpio-cells':
37
+
const: 2
38
+
39
+
gpio-controller: true
40
+
41
+
interrupts:
42
+
description:
43
+
List of interrupt specifiers for EXT_INT_0 through EXT_INT_N. The first
44
+
entry must correspond to EXT_INT_0.
45
+
46
+
'#interrupt-cells':
47
+
const: 2
48
+
description:
49
+
First cell selects EXT_INT_N (0-N), second cell specifies flags
50
+
51
+
interrupt-controller: true
52
+
53
+
apm,nr-gpios:
54
+
$ref: /schemas/types.yaml#/definitions/uint32
55
+
description: Number of GPIO pins
56
+
57
+
apm,nr-irqs:
58
+
$ref: /schemas/types.yaml#/definitions/uint32
59
+
description: Number of interrupt pins
60
+
61
+
apm,irq-start:
62
+
$ref: /schemas/types.yaml#/definitions/uint32
63
+
description: Lowest GPIO pin supporting interrupts
64
+
65
+
required:
66
+
- compatible
67
+
- reg
68
+
- '#gpio-cells'
69
+
- gpio-controller
70
+
- interrupts
71
+
- '#interrupt-cells'
72
+
- interrupt-controller
73
+
74
+
additionalProperties: false
75
+
76
+
examples:
77
+
- |
78
+
gpio@17001000 {
79
+
compatible = "apm,xgene-gpio-sb";
80
+
reg = <0x17001000 0x400>;
81
+
#gpio-cells = <2>;
82
+
gpio-controller;
83
+
interrupts = <0x0 0x28 0x1>,
84
+
<0x0 0x29 0x1>,
85
+
<0x0 0x2a 0x1>,
86
+
<0x0 0x2b 0x1>,
87
+
<0x0 0x2c 0x1>,
88
+
<0x0 0x2d 0x1>;
89
+
#interrupt-cells = <2>;
90
+
interrupt-controller;
91
+
apm,nr-gpios = <22>;
92
+
apm,nr-irqs = <6>;
93
+
apm,irq-start = <8>;
94
+
};
+29
Documentation/devicetree/bindings/gpio/apple,smc-gpio.yaml
+29
Documentation/devicetree/bindings/gpio/apple,smc-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/apple,smc-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Apple Mac System Management Controller GPIO
8
+
9
+
maintainers:
10
+
- Sven Peter <sven@kernel.org>
11
+
12
+
description:
13
+
Apple Mac System Management Controller GPIO block.
14
+
15
+
properties:
16
+
compatible:
17
+
const: apple,smc-gpio
18
+
19
+
gpio-controller: true
20
+
21
+
'#gpio-cells':
22
+
const: 2
23
+
24
+
required:
25
+
- compatible
26
+
- gpio-controller
27
+
- '#gpio-cells'
28
+
29
+
additionalProperties: false
+62
Documentation/devicetree/bindings/gpio/cavium,octeon-3860-gpio.yaml
+62
Documentation/devicetree/bindings/gpio/cavium,octeon-3860-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/cavium,octeon-3860-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cavium Octeon 3860 GPIO controller
8
+
9
+
maintainers:
10
+
- Bartosz Golaszewski <brgl@bgdev.pl>
11
+
12
+
properties:
13
+
compatible:
14
+
const: cavium,octeon-3860-gpio
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
gpio-controller: true
20
+
21
+
'#gpio-cells':
22
+
const: 2
23
+
24
+
interrupt-controller: true
25
+
26
+
'#interrupt-cells':
27
+
const: 2
28
+
29
+
interrupts:
30
+
maxItems: 16
31
+
32
+
required:
33
+
- compatible
34
+
- reg
35
+
- gpio-controller
36
+
- '#gpio-cells'
37
+
- interrupt-controller
38
+
- '#interrupt-cells'
39
+
- interrupts
40
+
41
+
additionalProperties: false
42
+
43
+
examples:
44
+
- |
45
+
bus {
46
+
#address-cells = <2>;
47
+
#size-cells = <2>;
48
+
49
+
gpio@1070000000800 {
50
+
compatible = "cavium,octeon-3860-gpio";
51
+
reg = <0x10700 0x00000800 0x0 0x100>;
52
+
gpio-controller;
53
+
#gpio-cells = <2>;
54
+
interrupt-controller;
55
+
#interrupt-cells = <2>;
56
+
/* The GPIO pin connect to 16 consecutive CUI bits */
57
+
interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
58
+
<0 20>, <0 21>, <0 22>, <0 23>,
59
+
<0 24>, <0 25>, <0 26>, <0 27>,
60
+
<0 28>, <0 29>, <0 30>, <0 31>;
61
+
};
62
+
};
-49
Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
-49
Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
···
1
-
* General Purpose Input Output (GPIO) bus.
2
-
3
-
Properties:
4
-
- compatible: "cavium,octeon-3860-gpio"
5
-
6
-
Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
7
-
8
-
- reg: The base address of the GPIO unit's register bank.
9
-
10
-
- gpio-controller: This is a GPIO controller.
11
-
12
-
- #gpio-cells: Must be <2>. The first cell is the GPIO pin.
13
-
14
-
- interrupt-controller: The GPIO controller is also an interrupt
15
-
controller, many of its pins may be configured as an interrupt
16
-
source.
17
-
18
-
- #interrupt-cells: Must be <2>. The first cell is the GPIO pin
19
-
connected to the interrupt source. The second cell is the interrupt
20
-
triggering protocol and may have one of four values:
21
-
1 - edge triggered on the rising edge.
22
-
2 - edge triggered on the falling edge
23
-
4 - level triggered active high.
24
-
8 - level triggered active low.
25
-
26
-
- interrupts: Interrupt routing for each pin.
27
-
28
-
Example:
29
-
30
-
gpio-controller@1070000000800 {
31
-
#gpio-cells = <2>;
32
-
compatible = "cavium,octeon-3860-gpio";
33
-
reg = <0x10700 0x00000800 0x0 0x100>;
34
-
gpio-controller;
35
-
/* Interrupts are specified by two parts:
36
-
* 1) GPIO pin number (0..15)
37
-
* 2) Triggering (1 - edge rising
38
-
* 2 - edge falling
39
-
* 4 - level active high
40
-
* 8 - level active low)
41
-
*/
42
-
interrupt-controller;
43
-
#interrupt-cells = <2>;
44
-
/* The GPIO pin connect to 16 consecutive CUI bits */
45
-
interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
46
-
<0 20>, <0 21>, <0 22>, <0 23>,
47
-
<0 24>, <0 25>, <0 26>, <0 27>,
48
-
<0 28>, <0 29>, <0 30>, <0 31>;
49
-
};
-17
Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
-17
Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
···
1
-
* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs
2
-
3
-
Required properties:
4
-
- compatible: Should contain "cirrus,ep7209-mctrl-gpio".
5
-
- gpio-controller: Marks the device node as a gpio controller.
6
-
- #gpio-cells: Should be two. The first cell is the pin number and
7
-
the second cell is used to specify the gpio polarity:
8
-
0 = Active high,
9
-
1 = Active low.
10
-
11
-
Example:
12
-
sysgpio: sysgpio {
13
-
compatible = "cirrus,ep7312-mctrl-gpio",
14
-
"cirrus,ep7209-mctrl-gpio";
15
-
gpio-controller;
16
-
#gpio-cells = <2>;
17
-
};
+49
Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.yaml
+49
Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/cirrus,clps711x-mctrl-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs
8
+
9
+
maintainers:
10
+
- Alexander Shiyan <shc_work@mail.ru>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- items:
16
+
- const: cirrus,ep7312-mctrl-gpio
17
+
- const: cirrus,ep7209-mctrl-gpio
18
+
- const: cirrus,ep7209-mctrl-gpio
19
+
20
+
gpio-controller: true
21
+
22
+
'#gpio-cells':
23
+
const: 2
24
+
25
+
gpio,syscon-dev:
26
+
description:
27
+
Phandle and offset of device's specific registers within the syscon state
28
+
control registers
29
+
$ref: /schemas/types.yaml#/definitions/phandle-array
30
+
items:
31
+
- items:
32
+
- description: phandle to syscon
33
+
- description: register offset within state control registers
34
+
35
+
required:
36
+
- compatible
37
+
- gpio-controller
38
+
- '#gpio-cells'
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
sysgpio: sysgpio {
45
+
compatible = "cirrus,ep7312-mctrl-gpio",
46
+
"cirrus,ep7209-mctrl-gpio";
47
+
gpio-controller;
48
+
#gpio-cells = <2>;
49
+
};
+75
Documentation/devicetree/bindings/gpio/exar,xra1403.yaml
+75
Documentation/devicetree/bindings/gpio/exar,xra1403.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/exar,xra1403.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: XRA1403 16-bit GPIO Expander with Reset Input
8
+
9
+
maintainers:
10
+
- Nandor Han <nandor.han@ge.com>
11
+
12
+
description: >
13
+
The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features
14
+
available:
15
+
16
+
- Individually programmable inputs:
17
+
- Internal pull-up resistors
18
+
- Polarity inversion
19
+
- Individual interrupt enable
20
+
- Rising edge and/or Falling edge interrupt
21
+
- Input filter
22
+
- Individually programmable outputs:
23
+
- Output Level Control
24
+
- Output Three-State Control
25
+
26
+
properties:
27
+
compatible:
28
+
const: exar,xra1403
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
gpio-controller: true
34
+
35
+
'#gpio-cells':
36
+
const: 2
37
+
38
+
interrupt-controller: true
39
+
40
+
'#interrupt-cells':
41
+
const: 2
42
+
43
+
reset-gpios:
44
+
description: Control line for the device reset.
45
+
46
+
required:
47
+
- compatible
48
+
- reg
49
+
- gpio-controller
50
+
- '#gpio-cells'
51
+
52
+
allOf:
53
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
54
+
55
+
unevaluatedProperties: false
56
+
57
+
examples:
58
+
- |
59
+
#include <dt-bindings/gpio/gpio.h>
60
+
61
+
spi {
62
+
#address-cells = <1>;
63
+
#size-cells = <0>;
64
+
65
+
gpio@2 {
66
+
compatible = "exar,xra1403";
67
+
reg = <2>;
68
+
spi-max-frequency = <1000000>;
69
+
gpio-controller;
70
+
#gpio-cells = <2>;
71
+
interrupt-controller;
72
+
#interrupt-cells = <2>;
73
+
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
74
+
};
75
+
};
-59
Documentation/devicetree/bindings/gpio/fcs,fxl6408.yaml
-59
Documentation/devicetree/bindings/gpio/fcs,fxl6408.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/gpio/fcs,fxl6408.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Fairchild FXL6408 I2C GPIO Expander
8
-
9
-
maintainers:
10
-
- Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
11
-
12
-
properties:
13
-
compatible:
14
-
enum:
15
-
- fcs,fxl6408
16
-
17
-
reg:
18
-
maxItems: 1
19
-
20
-
"#gpio-cells":
21
-
const: 2
22
-
23
-
gpio-controller: true
24
-
25
-
gpio-line-names:
26
-
minItems: 1
27
-
maxItems: 8
28
-
29
-
patternProperties:
30
-
"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
31
-
type: object
32
-
required:
33
-
- gpio-hog
34
-
35
-
required:
36
-
- compatible
37
-
- reg
38
-
- gpio-controller
39
-
- "#gpio-cells"
40
-
41
-
additionalProperties: false
42
-
43
-
examples:
44
-
- |
45
-
i2c {
46
-
#address-cells = <1>;
47
-
#size-cells = <0>;
48
-
49
-
gpio_expander_43: gpio-expander@43 {
50
-
compatible = "fcs,fxl6408";
51
-
reg = <0x43>;
52
-
gpio-controller;
53
-
#gpio-cells = <2>;
54
-
gpio-line-names = "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_WLAN",
55
-
"PWR_EN_+V3.3_WiFi_N", "PCIe_REF_CLK_EN",
56
-
"USB_RESET_N", "USB_BYPASS_N", "Wi-Fi_PDn",
57
-
"Wi-Fi_WKUP_BT";
58
-
};
59
-
};
+7
Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml
+7
Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml
-19
Documentation/devicetree/bindings/gpio/gateworks,pld-gpio.txt
-19
Documentation/devicetree/bindings/gpio/gateworks,pld-gpio.txt
···
1
-
Gateworks PLD GPIO controller bindings
2
-
3
-
The GPIO controller should be a child node on an I2C bus.
4
-
5
-
Required properties:
6
-
- compatible: Should be "gateworks,pld-gpio"
7
-
- reg: I2C slave address
8
-
- gpio-controller: Marks the device node as a GPIO controller.
9
-
- #gpio-cells: Should be <2>. The first cell is the gpio number and
10
-
the second cell is used to specify optional parameters.
11
-
12
-
Example:
13
-
14
-
pld@56 {
15
-
compatible = "gateworks,pld-gpio";
16
-
reg = <0x56>;
17
-
gpio-controller;
18
-
#gpio-cells = <2>;
19
-
};
-30
Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt
-30
Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt
···
1
-
* 74XX MMIO GPIO driver
2
-
3
-
Required properties:
4
-
- compatible: Should contain one of the following:
5
-
"ti,741g125": for 741G125 (1-bit Input),
6
-
"ti,741g174": for 741G74 (1-bit Output),
7
-
"ti,742g125": for 742G125 (2-bit Input),
8
-
"ti,7474" : for 7474 (2-bit Output),
9
-
"ti,74125" : for 74125 (4-bit Input),
10
-
"ti,74175" : for 74175 (4-bit Output),
11
-
"ti,74365" : for 74365 (6-bit Input),
12
-
"ti,74174" : for 74174 (6-bit Output),
13
-
"ti,74244" : for 74244 (8-bit Input),
14
-
"ti,74273" : for 74273 (8-bit Output),
15
-
"ti,741624" : for 741624 (16-bit Input),
16
-
"ti,7416374": for 7416374 (16-bit Output).
17
-
- reg: Physical base address and length where IC resides.
18
-
- gpio-controller: Marks the device node as a gpio controller.
19
-
- #gpio-cells: Should be two. The first cell is the pin number and
20
-
the second cell is used to specify the GPIO polarity:
21
-
0 = Active High,
22
-
1 = Active Low.
23
-
24
-
Example:
25
-
ctrl: gpio@30008004 {
26
-
compatible = "ti,74174";
27
-
reg = <0x30008004 0x1>;
28
-
gpio-controller;
29
-
#gpio-cells = <2>;
30
-
};
-44
Documentation/devicetree/bindings/gpio/gpio-altera.txt
-44
Documentation/devicetree/bindings/gpio/gpio-altera.txt
···
1
-
Altera GPIO controller bindings
2
-
3
-
Required properties:
4
-
- compatible:
5
-
- "altr,pio-1.0"
6
-
- reg: Physical base address and length of the controller's registers.
7
-
- #gpio-cells : Should be 2
8
-
- The first cell is the gpio offset number.
9
-
- The second cell is reserved and is currently unused.
10
-
- gpio-controller : Marks the device node as a GPIO controller.
11
-
- interrupt-controller: Mark the device node as an interrupt controller
12
-
- #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
13
-
- The first cell is the GPIO offset number within the GPIO controller.
14
-
- The second cell is the interrupt trigger type and level flags.
15
-
- interrupts: Specify the interrupt.
16
-
- altr,interrupt-type: Specifies the interrupt trigger type the GPIO
17
-
hardware is synthesized. This field is required if the Altera GPIO controller
18
-
used has IRQ enabled as the interrupt type is not software controlled,
19
-
but hardware synthesized. Required if GPIO is used as an interrupt
20
-
controller. The value is defined in <dt-bindings/interrupt-controller/irq.h>
21
-
Only the following flags are supported:
22
-
IRQ_TYPE_EDGE_RISING
23
-
IRQ_TYPE_EDGE_FALLING
24
-
IRQ_TYPE_EDGE_BOTH
25
-
IRQ_TYPE_LEVEL_HIGH
26
-
27
-
Optional properties:
28
-
- altr,ngpio: Width of the GPIO bank. This defines how many pins the
29
-
GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
30
-
specified.
31
-
32
-
Example:
33
-
34
-
gpio_altr: gpio@ff200000 {
35
-
compatible = "altr,pio-1.0";
36
-
reg = <0xff200000 0x10>;
37
-
interrupts = <0 45 4>;
38
-
altr,ngpio = <32>;
39
-
altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
40
-
#gpio-cells = <2>;
41
-
gpio-controller;
42
-
#interrupt-cells = <2>;
43
-
interrupt-controller;
44
-
};
-37
Documentation/devicetree/bindings/gpio/gpio-ath79.txt
-37
Documentation/devicetree/bindings/gpio/gpio-ath79.txt
···
1
-
Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller
2
-
3
-
Required properties:
4
-
- compatible: has to be "qca,<soctype>-gpio" and one of the following
5
-
fallbacks:
6
-
- "qca,ar7100-gpio"
7
-
- "qca,ar9340-gpio"
8
-
- reg: Base address and size of the controllers memory area
9
-
- gpio-controller : Marks the device node as a GPIO controller.
10
-
- #gpio-cells : Should be two. The first cell is the pin number and the
11
-
second cell is used to specify optional parameters.
12
-
- ngpios: Should be set to the number of GPIOs available on the SoC.
13
-
14
-
Optional properties:
15
-
- interrupts: Interrupt specifier for the controllers interrupt.
16
-
- interrupt-controller : Identifies the node as an interrupt controller
17
-
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
18
-
source, should be 2
19
-
20
-
Please refer to interrupts.txt in this directory for details of the common
21
-
Interrupt Controllers bindings used by client devices.
22
-
23
-
Example:
24
-
25
-
gpio@18040000 {
26
-
compatible = "qca,ar9132-gpio", "qca,ar7100-gpio";
27
-
reg = <0x18040000 0x30>;
28
-
interrupts = <2>;
29
-
30
-
ngpios = <22>;
31
-
32
-
gpio-controller;
33
-
#gpio-cells = <2>;
34
-
35
-
interrupt-controller;
36
-
#interrupt-cells = <2>;
37
-
};
-28
Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
-28
Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
···
1
-
Cirrus Logic CLPS711X GPIO controller
2
-
3
-
Required properties:
4
-
- compatible: Should be "cirrus,ep7209-gpio"
5
-
- reg: Physical base GPIO controller registers location and length.
6
-
There should be two registers, first is DATA register, the second
7
-
is DIRECTION.
8
-
- gpio-controller: Marks the device node as a gpio controller.
9
-
- #gpio-cells: Should be two. The first cell is the pin number and
10
-
the second cell is used to specify the gpio polarity:
11
-
0 = active high
12
-
1 = active low
13
-
14
-
Note: Each GPIO port should have an alias correctly numbered in "aliases"
15
-
node.
16
-
17
-
Example:
18
-
19
-
aliases {
20
-
gpio0 = &porta;
21
-
};
22
-
23
-
porta: gpio@80000000 {
24
-
compatible = "cirrus,ep7312-gpio","cirrus,ep7209-gpio";
25
-
reg = <0x80000000 0x1>, <0x80000040 0x1>;
26
-
gpio-controller;
27
-
#gpio-cells = <2>;
28
-
};
-39
Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
-39
Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
···
1
-
Keystone 2 DSP GPIO controller bindings
2
-
3
-
HOST OS userland running on ARM can send interrupts to DSP cores using
4
-
the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
5
-
This is one of the component used by the IPC mechanism used on Keystone SOCs.
6
-
7
-
For example TCI6638K2K SoC has 8 DSP GPIO controllers:
8
-
- 8 for C66x CorePacx CPUs 0-7
9
-
10
-
Keystone 2 DSP GPIO controller has specific features:
11
-
- each GPIO can be configured only as output pin;
12
-
- setting GPIO value to 1 causes IRQ generation on target DSP core;
13
-
- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
14
-
pending.
15
-
16
-
Required Properties:
17
-
- compatible: should be "ti,keystone-dsp-gpio"
18
-
- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
19
-
access device state control registers and the offset of device's specific
20
-
registers within device state control registers range.
21
-
- gpio-controller: Marks the device node as a gpio controller.
22
-
- #gpio-cells: Should be 2.
23
-
24
-
Please refer to gpio.txt in this directory for details of the common GPIO
25
-
bindings used by client devices.
26
-
27
-
Example:
28
-
dspgpio0: keystone_dsp_gpio@2620240 {
29
-
compatible = "ti,keystone-dsp-gpio";
30
-
ti,syscon-dev = <&devctrl 0x240>;
31
-
gpio-controller;
32
-
#gpio-cells = <2>;
33
-
};
34
-
35
-
dsp0: dsp0 {
36
-
compatible = "linux,rproc-user";
37
-
...
38
-
kick-gpio = <&dspgpio0 27>;
39
-
};
-37
Documentation/devicetree/bindings/gpio/gpio-lp3943.txt
-37
Documentation/devicetree/bindings/gpio/gpio-lp3943.txt
···
1
-
TI/National Semiconductor LP3943 GPIO controller
2
-
3
-
Required properties:
4
-
- compatible: "ti,lp3943-gpio"
5
-
- gpio-controller: Marks the device node as a GPIO controller.
6
-
- #gpio-cells: Should be 2. See gpio.txt in this directory for a
7
-
description of the cells format.
8
-
9
-
Example:
10
-
Simple LED controls with LP3943 GPIO controller
11
-
12
-
&i2c4 {
13
-
lp3943@60 {
14
-
compatible = "ti,lp3943";
15
-
reg = <0x60>;
16
-
17
-
gpioex: gpio {
18
-
compatible = "ti,lp3943-gpio";
19
-
gpio-controller;
20
-
#gpio-cells = <2>;
21
-
};
22
-
};
23
-
};
24
-
25
-
leds {
26
-
compatible = "gpio-leds";
27
-
indicator1 {
28
-
label = "indi1";
29
-
gpios = <&gpioex 9 GPIO_ACTIVE_LOW>;
30
-
};
31
-
32
-
indicator2 {
33
-
label = "indi2";
34
-
gpios = <&gpioex 10 GPIO_ACTIVE_LOW>;
35
-
default-state = "off";
36
-
};
37
-
};
-59
Documentation/devicetree/bindings/gpio/gpio-max3191x.txt
-59
Documentation/devicetree/bindings/gpio/gpio-max3191x.txt
···
1
-
GPIO driver for Maxim MAX3191x industrial serializer
2
-
3
-
Required properties:
4
-
- compatible: Must be one of:
5
-
"maxim,max31910"
6
-
"maxim,max31911"
7
-
"maxim,max31912"
8
-
"maxim,max31913"
9
-
"maxim,max31953"
10
-
"maxim,max31963"
11
-
- reg: Chip select number.
12
-
- gpio-controller: Marks the device node as a GPIO controller.
13
-
- #gpio-cells: Should be two. For consumer use see gpio.txt.
14
-
15
-
Optional properties:
16
-
- #daisy-chained-devices:
17
-
Number of chips in the daisy-chain (default is 1).
18
-
- maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
19
-
The number of GPIOs must equal "#daisy-chained-devices"
20
-
(if each chip is driven by a separate pin) or 1
21
-
(if all chips are wired to the same pin).
22
-
- maxim,fault-gpios: GPIO pins to read fault of each chip.
23
-
The number of GPIOs must equal "#daisy-chained-devices"
24
-
or 1.
25
-
- maxim,db0-gpios: GPIO pins to configure debounce of each chip.
26
-
The number of GPIOs must equal "#daisy-chained-devices"
27
-
or 1.
28
-
- maxim,db1-gpios: GPIO pins to configure debounce of each chip.
29
-
The number of GPIOs must equal "maxim,db0-gpios".
30
-
- maxim,modesel-8bit: Boolean whether the modesel pin of the chips is
31
-
pulled high (8-bit mode). Use this if the modesel pin
32
-
is hardwired and consequently "maxim,modesel-gpios"
33
-
cannot be specified. By default if neither this nor
34
-
"maxim,modesel-gpios" is given, the driver assumes
35
-
that modesel is pulled low (16-bit mode).
36
-
- maxim,ignore-undervoltage:
37
-
Boolean whether to ignore undervoltage alarms signaled
38
-
by the "maxim,fault-gpios" or by the status byte
39
-
(in 16-bit mode). Use this if the chips are powered
40
-
through 5VOUT instead of VCC24V, in which case they
41
-
will constantly signal undervoltage.
42
-
43
-
For other required and optional properties of SPI slave nodes please refer to
44
-
../spi/spi-bus.txt.
45
-
46
-
Example:
47
-
gpio@0 {
48
-
compatible = "maxim,max31913";
49
-
reg = <0>;
50
-
gpio-controller;
51
-
#gpio-cells = <2>;
52
-
53
-
maxim,modesel-gpios = <&gpio2 23>;
54
-
maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
55
-
maxim,db0-gpios = <&gpio2 25>;
56
-
maxim,db1-gpios = <&gpio2 26>;
57
-
58
-
spi-max-frequency = <25000000>;
59
-
};
-25
Documentation/devicetree/bindings/gpio/gpio-max77620.txt
-25
Documentation/devicetree/bindings/gpio/gpio-max77620.txt
···
1
-
GPIO driver for MAX77620 Power management IC from Maxim Semiconductor.
2
-
3
-
Device has 8 GPIO pins which can be configured as GPIO as well as the
4
-
special IO functions.
5
-
6
-
Required properties:
7
-
-------------------
8
-
- gpio-controller : Marks the device node as a gpio controller.
9
-
- #gpio-cells : Should be two. The first cell is the pin number and
10
-
the second cell is used to specify the gpio polarity:
11
-
0 = active high
12
-
1 = active low
13
-
For more details, please refer generic GPIO DT binding document
14
-
<devicetree/bindings/gpio/gpio.txt>.
15
-
16
-
Example:
17
-
--------
18
-
#include <dt-bindings/mfd/max77620.h>
19
-
...
20
-
max77620@3c {
21
-
compatible = "maxim,max77620";
22
-
23
-
gpio-controller;
24
-
#gpio-cells = <2>;
25
-
};
-38
Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt
-38
Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt
···
1
-
Lantiq SoC External Bus memory mapped GPIO controller
2
-
3
-
By attaching hardware latches to the EBU it is possible to create output
4
-
only gpios. This driver configures a special memory address, which when
5
-
written to outputs 16 bit to the latches.
6
-
7
-
The node describing the memory mapped GPIOs needs to be a child of the node
8
-
describing the "lantiq,localbus".
9
-
10
-
Required properties:
11
-
- compatible : Should be "lantiq,gpio-mm-lantiq"
12
-
- reg : Address and length of the register set for the device
13
-
- #gpio-cells : Should be two. The first cell is the pin number and
14
-
the second cell is used to specify optional parameters (currently
15
-
unused).
16
-
- gpio-controller : Marks the device node as a gpio controller.
17
-
18
-
Optional properties:
19
-
- lantiq,shadow : The default value that we shall assume as already set on the
20
-
shift register cascade.
21
-
22
-
Example:
23
-
24
-
localbus@0 {
25
-
#address-cells = <2>;
26
-
#size-cells = <1>;
27
-
ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
28
-
1 0 0x4000000 0x4000010>; /* addsel1 */
29
-
compatible = "lantiq,localbus", "simple-bus";
30
-
31
-
gpio_mm0: gpio@4000000 {
32
-
compatible = "lantiq,gpio-mm";
33
-
reg = <1 0x0 0x10>;
34
-
gpio-controller;
35
-
#gpio-cells = <2>;
36
-
lantiq,shadow = <0x77f>
37
-
};
38
-
}
-18
Documentation/devicetree/bindings/gpio/gpio-moxtet.txt
-18
Documentation/devicetree/bindings/gpio/gpio-moxtet.txt
···
1
-
Turris Mox Moxtet GPIO expander via Moxtet bus
2
-
3
-
Required properties:
4
-
- compatible : Should be "cznic,moxtet-gpio".
5
-
- gpio-controller : Marks the device node as a GPIO controller.
6
-
- #gpio-cells : Should be two. For consumer use see gpio.txt.
7
-
8
-
Other properties are required for a Moxtet bus device, please refer to
9
-
Documentation/devicetree/bindings/bus/moxtet.txt.
10
-
11
-
Example:
12
-
13
-
moxtet_sfp: gpio@0 {
14
-
compatible = "cznic,moxtet-gpio";
15
-
gpio-controller;
16
-
#gpio-cells = <2>;
17
-
reg = <0>;
18
-
}
-27
Documentation/devicetree/bindings/gpio/gpio-palmas.txt
-27
Documentation/devicetree/bindings/gpio/gpio-palmas.txt
···
1
-
Palmas GPIO controller bindings
2
-
3
-
Required properties:
4
-
- compatible:
5
-
- "ti,palams-gpio" for palma series of the GPIO controller
6
-
- "ti,tps80036-gpio" for Palma series device TPS80036.
7
-
- "ti,tps65913-gpio" for palma series device TPS65913.
8
-
- "ti,tps65914-gpio" for palma series device TPS65914.
9
-
- #gpio-cells : Should be two.
10
-
- first cell is the gpio pin number
11
-
- second cell is used to specify the gpio polarity:
12
-
0 = active high
13
-
1 = active low
14
-
- gpio-controller : Marks the device node as a GPIO controller.
15
-
16
-
Note: This gpio node will be sub node of palmas node.
17
-
18
-
Example:
19
-
palmas: tps65913@58 {
20
-
:::::::::::
21
-
palmas_gpio: palmas_gpio {
22
-
compatible = "ti,palmas-gpio";
23
-
gpio-controller;
24
-
#gpio-cells = <2>;
25
-
};
26
-
:::::::::::
27
-
};
-56
Documentation/devicetree/bindings/gpio/gpio-pca9570.yaml
-56
Documentation/devicetree/bindings/gpio/gpio-pca9570.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/gpio/gpio-pca9570.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: PCA9570 I2C GPO expander
8
-
9
-
maintainers:
10
-
- Sungbo Eo <mans0n@gorani.run>
11
-
12
-
properties:
13
-
compatible:
14
-
enum:
15
-
- dlg,slg7xl45106
16
-
- nxp,pca9570
17
-
- nxp,pca9571
18
-
19
-
reg:
20
-
maxItems: 1
21
-
22
-
gpio-controller: true
23
-
24
-
'#gpio-cells':
25
-
const: 2
26
-
27
-
gpio-line-names:
28
-
minItems: 4
29
-
maxItems: 8
30
-
31
-
label:
32
-
description: A descriptive name for this device.
33
-
34
-
required:
35
-
- compatible
36
-
- reg
37
-
- gpio-controller
38
-
- "#gpio-cells"
39
-
40
-
additionalProperties: false
41
-
42
-
examples:
43
-
- |
44
-
i2c {
45
-
#address-cells = <1>;
46
-
#size-cells = <0>;
47
-
48
-
gpio@24 {
49
-
compatible = "nxp,pca9570";
50
-
reg = <0x24>;
51
-
gpio-controller;
52
-
#gpio-cells = <2>;
53
-
};
54
-
};
55
-
56
-
...
+1
Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml
+1
Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml
-34
Documentation/devicetree/bindings/gpio/gpio-pisosr.txt
-34
Documentation/devicetree/bindings/gpio/gpio-pisosr.txt
···
1
-
Generic Parallel-in/Serial-out Shift Register GPIO Driver
2
-
3
-
This binding describes generic parallel-in/serial-out shift register
4
-
devices that can be used for GPI (General Purpose Input). This includes
5
-
SN74165 serial-out shift registers and the SN65HVS88x series of
6
-
industrial serializers.
7
-
8
-
Required properties:
9
-
- compatible : Should be "pisosr-gpio".
10
-
- gpio-controller : Marks the device node as a GPIO controller.
11
-
- #gpio-cells : Should be two. For consumer use see gpio.txt.
12
-
13
-
Optional properties:
14
-
- ngpios : Number of used GPIO lines (0..n-1), default is 8.
15
-
- load-gpios : GPIO pin specifier attached to load enable, this
16
-
pin is pulsed before reading from the device to
17
-
load input pin values into the device.
18
-
19
-
For other required and optional properties of SPI slave
20
-
nodes please refer to ../spi/spi-bus.txt.
21
-
22
-
Example:
23
-
24
-
gpio@0 {
25
-
compatible = "ti,sn65hvs882", "pisosr-gpio";
26
-
gpio-controller;
27
-
#gpio-cells = <2>;
28
-
29
-
load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
30
-
31
-
reg = <0>;
32
-
spi-max-frequency = <1000000>;
33
-
spi-cpol;
34
-
};
-51
Documentation/devicetree/bindings/gpio/gpio-tpic2810.yaml
-51
Documentation/devicetree/bindings/gpio/gpio-tpic2810.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/gpio/gpio-tpic2810.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: TPIC2810 GPIO controller
8
-
9
-
maintainers:
10
-
- Aswath Govindraju <a-govindraju@ti.com>
11
-
12
-
properties:
13
-
compatible:
14
-
enum:
15
-
- ti,tpic2810
16
-
17
-
reg:
18
-
maxItems: 1
19
-
20
-
gpio-controller: true
21
-
22
-
"#gpio-cells":
23
-
const: 2
24
-
25
-
gpio-line-names:
26
-
minItems: 1
27
-
maxItems: 32
28
-
29
-
required:
30
-
- compatible
31
-
- reg
32
-
- gpio-controller
33
-
- "#gpio-cells"
34
-
35
-
additionalProperties: false
36
-
37
-
examples:
38
-
- |
39
-
#include <dt-bindings/gpio/gpio.h>
40
-
41
-
i2c {
42
-
#address-cells = <1>;
43
-
#size-cells = <0>;
44
-
gpio@60 {
45
-
compatible = "ti,tpic2810";
46
-
reg = <0x60>;
47
-
gpio-controller;
48
-
#gpio-cells = <2>;
49
-
gpio-line-names = "LED A", "LED B", "LED C";
50
-
};
51
-
};
-20
Documentation/devicetree/bindings/gpio/gpio-ts4800.txt
-20
Documentation/devicetree/bindings/gpio/gpio-ts4800.txt
···
1
-
* TS-4800 FPGA's GPIO controller bindings
2
-
3
-
Required properties:
4
-
- compatible: Must be "technologic,ts4800-gpio".
5
-
- #gpio-cells: Should be two. The first cell is the pin number.
6
-
- reg: Physical base address of the controller and length
7
-
of memory mapped region.
8
-
9
-
Optional property:
10
-
- ngpios: See "gpio.txt"
11
-
12
-
Example:
13
-
14
-
gpio1: gpio {
15
-
compatible = "technologic,ts4800-gpio";
16
-
reg = <0x10020 0x6>;
17
-
ngpios = <8>;
18
-
gpio-controller;
19
-
#gpio-cells = <2>;
20
-
};
-30
Documentation/devicetree/bindings/gpio/gpio-ts4900.txt
-30
Documentation/devicetree/bindings/gpio/gpio-ts4900.txt
···
1
-
* Technologic Systems I2C-FPGA's GPIO controller bindings
2
-
3
-
This bindings describes the GPIO controller for Technologic's FPGA core.
4
-
TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
5
-
uses 2 bits: it doesn't use a dedicated input bit.
6
-
7
-
Required properties:
8
-
- compatible: Should be one of the following
9
-
"technologic,ts4900-gpio"
10
-
"technologic,ts7970-gpio"
11
-
- reg: Physical base address of the controller and length
12
-
of memory mapped region.
13
-
- #gpio-cells: Should be two. The first cell is the pin number.
14
-
- gpio-controller: Marks the device node as a gpio controller.
15
-
16
-
Optional property:
17
-
- ngpios: Number of GPIOs this controller is instantiated with,
18
-
the default is 32. See gpio.txt for more details.
19
-
20
-
Example:
21
-
22
-
&i2c2 {
23
-
gpio8: gpio@28 {
24
-
compatible = "technologic,ts4900-gpio";
25
-
reg = <0x28>;
26
-
#gpio-cells = <2>;
27
-
gpio-controller;
28
-
ngpios = <32>;
29
-
};
30
-
};
-29
Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
-29
Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
···
1
-
twl4030 GPIO controller bindings
2
-
3
-
Required properties:
4
-
- compatible:
5
-
- "ti,twl4030-gpio" for twl4030 GPIO controller
6
-
- #gpio-cells : Should be two.
7
-
- first cell is the pin number
8
-
- second cell is used to specify optional parameters (unused)
9
-
- gpio-controller : Marks the device node as a GPIO controller.
10
-
- #interrupt-cells : Should be 2.
11
-
- interrupt-controller: Mark the device node as an interrupt controller
12
-
The first cell is the GPIO number.
13
-
The second cell is not used.
14
-
- ti,use-leds : Enables LEDA and LEDB outputs if set
15
-
- ti,debounce : if n-th bit is set, debounces GPIO-n
16
-
- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
17
-
- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
18
-
- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
19
-
20
-
Example:
21
-
22
-
twl_gpio: gpio {
23
-
compatible = "ti,twl4030-gpio";
24
-
#gpio-cells = <2>;
25
-
gpio-controller;
26
-
#interrupt-cells = <2>;
27
-
interrupt-controller;
28
-
ti,use-leds;
29
-
};
-64
Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt
-64
Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt
···
1
-
APM X-Gene Standby GPIO controller bindings
2
-
3
-
This is a gpio controller in the standby domain. It also supports interrupt in
4
-
some particular pins which are sourced to its parent interrupt controller
5
-
as diagram below:
6
-
+-----------------+
7
-
| X-Gene standby |
8
-
| GPIO controller +------ GPIO_0
9
-
+------------+ | | ...
10
-
| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
11
-
| controller | (SPI40) | | ...
12
-
| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
13
-
| | ... | |
14
-
| | EXT_INT_N | +------ GPIO_[N+9]
15
-
| | (SPI[40 + N])| | ...
16
-
| +--------------+ +------ GPIO_MAX
17
-
+------------+ +-----------------+
18
-
19
-
Required properties:
20
-
- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
21
-
- reg: Physical base address and size of the controller's registers
22
-
- #gpio-cells: Should be two.
23
-
- first cell is the pin number
24
-
- second cell is used to specify the gpio polarity:
25
-
0 = active high
26
-
1 = active low
27
-
- gpio-controller: Marks the device node as a GPIO controller.
28
-
- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
29
-
- interrupt-cells: Should be two.
30
-
- first cell is 0-N corresponding for EXT_INT_0 to EXT_INT_N.
31
-
- second cell is used to specify flags.
32
-
- interrupt-controller: Marks the device node as an interrupt controller.
33
-
- apm,nr-gpios: Optional, specify number of gpios pin.
34
-
- apm,nr-irqs: Optional, specify number of interrupt pins.
35
-
- apm,irq-start: Optional, specify lowest gpio pin support interrupt.
36
-
37
-
Example:
38
-
sbgpio: gpio@17001000{
39
-
compatible = "apm,xgene-gpio-sb";
40
-
reg = <0x0 0x17001000 0x0 0x400>;
41
-
#gpio-cells = <2>;
42
-
gpio-controller;
43
-
interrupts = <0x0 0x28 0x1>,
44
-
<0x0 0x29 0x1>,
45
-
<0x0 0x2a 0x1>,
46
-
<0x0 0x2b 0x1>,
47
-
<0x0 0x2c 0x1>,
48
-
<0x0 0x2d 0x1>;
49
-
interrupt-parent = <&gic>;
50
-
#interrupt-cells = <2>;
51
-
interrupt-controller;
52
-
apm,nr-gpios = <22>;
53
-
apm,nr-irqs = <6>;
54
-
apm,irq-start = <8>;
55
-
};
56
-
57
-
testuser {
58
-
compatible = "example,testuser";
59
-
/* Use the GPIO_13/EXT_INT_5 line as an active high triggered
60
-
* level interrupt
61
-
*/
62
-
interrupts = <5 4>;
63
-
interrupt-parent = <&sbgpio>;
64
-
};
-22
Documentation/devicetree/bindings/gpio/gpio-xgene.txt
-22
Documentation/devicetree/bindings/gpio/gpio-xgene.txt
···
1
-
APM X-Gene SoC GPIO controller bindings
2
-
3
-
This is a gpio controller that is part of the flash controller.
4
-
This gpio controller controls a total of 48 gpios.
5
-
6
-
Required properties:
7
-
- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
8
-
- reg: Physical base address and size of the controller's registers
9
-
- #gpio-cells: Should be two.
10
-
- first cell is the pin number
11
-
- second cell is used to specify the gpio polarity:
12
-
0 = active high
13
-
1 = active low
14
-
- gpio-controller: Marks the device node as a GPIO controller.
15
-
16
-
Example:
17
-
gpio0: gpio0@1701c000 {
18
-
compatible = "apm,xgene-gpio";
19
-
reg = <0x0 0x1701c000 0x0 0x40>;
20
-
gpio-controller;
21
-
#gpio-cells = <2>;
22
-
};
-46
Documentation/devicetree/bindings/gpio/gpio-xra1403.txt
-46
Documentation/devicetree/bindings/gpio/gpio-xra1403.txt
···
1
-
GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
2
-
3
-
The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
4
-
- Individually programmable inputs:
5
-
- Internal pull-up resistors
6
-
- Polarity inversion
7
-
- Individual interrupt enable
8
-
- Rising edge and/or Falling edge interrupt
9
-
- Input filter
10
-
- Individually programmable outputs
11
-
- Output Level Control
12
-
- Output Three-State Control
13
-
14
-
Properties
15
-
----------
16
-
Check documentation for SPI and GPIO controllers regarding properties needed to configure the node.
17
-
18
-
- compatible = "exar,xra1403".
19
-
- reg - SPI id of the device.
20
-
- gpio-controller - marks the node as gpio.
21
-
- #gpio-cells - should be two where the first cell is the pin number
22
-
and the second one is used for optional parameters.
23
-
24
-
Optional properties:
25
-
-------------------
26
-
- reset-gpios: in case available used to control the device reset line.
27
-
- interrupt-controller - marks the node as interrupt controller.
28
-
- #interrupt-cells - should be two and represents the number of cells
29
-
needed to encode interrupt source.
30
-
31
-
Example
32
-
--------
33
-
34
-
gpioxra0: gpio@2 {
35
-
compatible = "exar,xra1403";
36
-
reg = <2>;
37
-
38
-
gpio-controller;
39
-
#gpio-cells = <2>;
40
-
41
-
interrupt-controller;
42
-
#interrupt-cells = <2>;
43
-
44
-
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
45
-
spi-max-frequency = <1000000>;
46
-
};
-24
Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt
-24
Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt
···
1
-
* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs
2
-
3
-
All GPIOs are pin-shared with other functions. DCRs control whether a
4
-
particular pin that has GPIO capabilities acts as a GPIO or is used for
5
-
another purpose. GPIO outputs are separately programmable to emulate
6
-
an open-drain driver.
7
-
8
-
Required properties:
9
-
- compatible: must be "ibm,ppc4xx-gpio"
10
-
- reg: address and length of the register set for the device
11
-
- #gpio-cells: must be set to 2. The first cell is the pin number
12
-
and the second cell is used to specify the gpio polarity:
13
-
0 = active high
14
-
1 = active low
15
-
- gpio-controller: marks the device node as a gpio controller.
16
-
17
-
Example:
18
-
19
-
GPIO0: gpio@ef600b00 {
20
-
compatible = "ibm,ppc4xx-gpio";
21
-
reg = <0xef600b00 0x00000048>;
22
-
#gpio-cells = <2>;
23
-
gpio-controller;
24
-
};
+60
Documentation/devicetree/bindings/gpio/lacie,netxbig-gpio-ext.yaml
+60
Documentation/devicetree/bindings/gpio/lacie,netxbig-gpio-ext.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/lacie,netxbig-gpio-ext.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NetxBig GPIO extension bus
8
+
9
+
maintainers:
10
+
- Simon Guinot <simon.guinot@sequanux.org>
11
+
12
+
description: >
13
+
GPIO extension bus found on some LaCie/Seagate boards
14
+
(Example: 2Big/5Big Network v2, 2Big NAS).
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- const: lacie,netxbig-gpio-ext
20
+
21
+
addr-gpios:
22
+
description: GPIOs representing the address register (LSB->MSB).
23
+
items:
24
+
- description: bit 0 (LSB)
25
+
- description: bit 1
26
+
- description: bit 2 (MSB)
27
+
28
+
data-gpios:
29
+
description: GPIOs representing the data register (LSB->MSB).
30
+
items:
31
+
- description: bit 0 (LSB)
32
+
- description: bit 1
33
+
- description: bit 2 (MSB)
34
+
35
+
enable-gpio:
36
+
description: Latches the new configuration (address, data) on raising edge.
37
+
maxItems: 1
38
+
39
+
required:
40
+
- compatible
41
+
- addr-gpios
42
+
- data-gpios
43
+
- enable-gpio
44
+
45
+
additionalProperties: false
46
+
47
+
examples:
48
+
- |
49
+
#include <dt-bindings/gpio/gpio.h>
50
+
51
+
gpio {
52
+
compatible = "lacie,netxbig-gpio-ext";
53
+
addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
54
+
&gpio1 16 GPIO_ACTIVE_HIGH
55
+
&gpio1 17 GPIO_ACTIVE_HIGH>;
56
+
data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
57
+
&gpio1 13 GPIO_ACTIVE_HIGH
58
+
&gpio1 14 GPIO_ACTIVE_HIGH>;
59
+
enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
60
+
};
+54
Documentation/devicetree/bindings/gpio/lantiq,gpio-mm-lantiq.yaml
+54
Documentation/devicetree/bindings/gpio/lantiq,gpio-mm-lantiq.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/lantiq,gpio-mm-lantiq.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Lantiq SoC External Bus memory mapped GPIO controller
8
+
9
+
maintainers:
10
+
- John Crispin <john@phrozen.org>
11
+
12
+
description: |
13
+
By attaching hardware latches to the EBU it is possible to create output
14
+
only gpios. This driver configures a special memory address, which when
15
+
written to outputs 16 bit to the latches.
16
+
17
+
The node describing the memory mapped GPIOs needs to be a child of the node
18
+
describing the "lantiq,localbus".
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
- lantiq,gpio-mm-lantiq
24
+
- lantiq,gpio-mm
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
'#gpio-cells':
30
+
const: 2
31
+
32
+
gpio-controller: true
33
+
34
+
lantiq,shadow:
35
+
description: The default value that we shall assume as already set on the shift register cascade.
36
+
$ref: /schemas/types.yaml#/definitions/uint32
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- '#gpio-cells'
42
+
- gpio-controller
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
gpio@4000000 {
49
+
compatible = "lantiq,gpio-mm-lantiq";
50
+
reg = <0x4000000 0x10>;
51
+
gpio-controller;
52
+
#gpio-cells = <2>;
53
+
lantiq,shadow = <0x77f>;
54
+
};
-49
Documentation/devicetree/bindings/gpio/loongson,ls1x-gpio.yaml
-49
Documentation/devicetree/bindings/gpio/loongson,ls1x-gpio.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/gpio/loongson,ls1x-gpio.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Loongson-1 GPIO controller
8
-
9
-
maintainers:
10
-
- Keguang Zhang <keguang.zhang@gmail.com>
11
-
12
-
properties:
13
-
compatible:
14
-
const: loongson,ls1x-gpio
15
-
16
-
reg:
17
-
maxItems: 1
18
-
19
-
gpio-controller: true
20
-
21
-
"#gpio-cells":
22
-
const: 2
23
-
24
-
ngpios:
25
-
minimum: 1
26
-
maximum: 32
27
-
28
-
required:
29
-
- compatible
30
-
- reg
31
-
- gpio-controller
32
-
- "#gpio-cells"
33
-
- ngpios
34
-
35
-
additionalProperties: false
36
-
37
-
examples:
38
-
- |
39
-
gpio0: gpio@1fd010c0 {
40
-
compatible = "loongson,ls1x-gpio";
41
-
reg = <0x1fd010c0 0x4>;
42
-
43
-
gpio-controller;
44
-
#gpio-cells = <2>;
45
-
46
-
ngpios = <32>;
47
-
};
48
-
49
-
...
+104
Documentation/devicetree/bindings/gpio/maxim,max31910.yaml
+104
Documentation/devicetree/bindings/gpio/maxim,max31910.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/maxim,max31910.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Maxim MAX3191x GPIO serializer
8
+
9
+
maintainers:
10
+
- Lukas Wunner <lukas@wunner.de>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- maxim,max31910
16
+
- maxim,max31911
17
+
- maxim,max31912
18
+
- maxim,max31913
19
+
- maxim,max31953
20
+
- maxim,max31963
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
gpio-controller: true
26
+
27
+
'#gpio-cells':
28
+
const: 2
29
+
30
+
'#daisy-chained-devices':
31
+
description: Number of chips in the daisy-chain.
32
+
default: 1
33
+
34
+
maxim,modesel-gpios:
35
+
description:
36
+
GPIO pins to configure modesel of each chip. The number of GPIOs must
37
+
equal "#daisy-chained-devices" (if each chip is driven by a separate pin)
38
+
or 1 (if all chips are wired to the same pin).
39
+
40
+
maxim,fault-gpios:
41
+
description:
42
+
GPIO pins to read fault of each chip. The number of GPIOs must equal
43
+
"#daisy-chained-devices" or 1.
44
+
45
+
maxim,db0-gpios:
46
+
description:
47
+
GPIO pins to configure debounce of each chip. The number of GPIOs must
48
+
equal "#daisy-chained-devices" or 1.
49
+
50
+
maxim,db1-gpios:
51
+
description:
52
+
GPIO pins to configure debounce of each chip. The number of GPIOs must
53
+
equal "maxim,db0-gpios".
54
+
55
+
maxim,modesel-8bit:
56
+
description:
57
+
Boolean whether the modesel pin of the chips is pulled high (8-bit mode).
58
+
Use this if the modesel pin is hardwired and consequently
59
+
"maxim,modesel-gpios" cannot be specified. By default if neither this nor
60
+
"maxim,modesel-gpios" is given, the driver assumes that modesel is pulled
61
+
low (16-bit mode).
62
+
type: boolean
63
+
64
+
maxim,ignore-undervoltage:
65
+
description:
66
+
Boolean whether to ignore undervoltage alarms signaled by the
67
+
"maxim,fault-gpios" or by the status byte (in 16-bit mode). Use this if
68
+
the chips are powered through 5VOUT instead of VCC24V, in which case they
69
+
will constantly signal undervoltage.
70
+
type: boolean
71
+
72
+
required:
73
+
- compatible
74
+
- reg
75
+
- gpio-controller
76
+
- '#gpio-cells'
77
+
78
+
allOf:
79
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
80
+
81
+
unevaluatedProperties: false
82
+
83
+
examples:
84
+
- |
85
+
#include <dt-bindings/gpio/gpio.h>
86
+
87
+
spi {
88
+
#address-cells = <1>;
89
+
#size-cells = <0>;
90
+
91
+
gpio@0 {
92
+
compatible = "maxim,max31913";
93
+
reg = <0>;
94
+
gpio-controller;
95
+
#gpio-cells = <2>;
96
+
97
+
maxim,modesel-gpios = <&gpio2 23>;
98
+
maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
99
+
maxim,db0-gpios = <&gpio2 25>;
100
+
maxim,db1-gpios = <&gpio2 26>;
101
+
102
+
spi-max-frequency = <25000000>;
103
+
};
104
+
};
-49
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
-49
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
···
1
-
* Microchip PIC32 GPIO devices (PIO).
2
-
3
-
Required properties:
4
-
- compatible: "microchip,pic32mzda-gpio"
5
-
- reg: Base address and length for the device.
6
-
- interrupts: The port interrupt shared by all pins.
7
-
- gpio-controller: Marks the port as GPIO controller.
8
-
- #gpio-cells: Two. The first cell is the pin number and
9
-
the second cell is used to specify the gpio polarity as defined in
10
-
defined in <dt-bindings/gpio/gpio.h>:
11
-
0 = GPIO_ACTIVE_HIGH
12
-
1 = GPIO_ACTIVE_LOW
13
-
2 = GPIO_OPEN_DRAIN
14
-
- interrupt-controller: Marks the device node as an interrupt controller.
15
-
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
16
-
is used to specify the trigger type as defined in
17
-
<dt-bindings/interrupt-controller/irq.h>:
18
-
IRQ_TYPE_EDGE_RISING
19
-
IRQ_TYPE_EDGE_FALLING
20
-
IRQ_TYPE_EDGE_BOTH
21
-
- clocks: Clock specifier (see clock bindings for details).
22
-
- microchip,gpio-bank: Specifies which bank a controller owns.
23
-
- gpio-ranges: Interaction with the PINCTRL subsystem.
24
-
25
-
Example:
26
-
27
-
/* PORTA */
28
-
gpio0: gpio0@1f860000 {
29
-
compatible = "microchip,pic32mzda-gpio";
30
-
reg = <0x1f860000 0x100>;
31
-
interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
32
-
#gpio-cells = <2>;
33
-
gpio-controller;
34
-
interrupt-controller;
35
-
#interrupt-cells = <2>;
36
-
clocks = <&rootclk PB4CLK>;
37
-
microchip,gpio-bank = <0>;
38
-
gpio-ranges = <&pic32_pinctrl 0 0 16>;
39
-
};
40
-
41
-
keys {
42
-
...
43
-
44
-
button@sw1 {
45
-
label = "ESC";
46
-
linux,code = <1>;
47
-
gpios = <&gpio0 12 0>;
48
-
};
49
-
};
+71
Documentation/devicetree/bindings/gpio/microchip,pic32mzda-gpio.yaml
+71
Documentation/devicetree/bindings/gpio/microchip,pic32mzda-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/microchip,pic32mzda-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Microchip PIC32 GPIO controller
8
+
9
+
maintainers:
10
+
- Joshua Henderson <joshua.henderson@microchip.com>
11
+
- Purna Chandra Mandal <purna.mandal@microchip.com>
12
+
13
+
properties:
14
+
compatible:
15
+
const: microchip,pic32mzda-gpio
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
gpio-controller: true
21
+
22
+
gpio-ranges: true
23
+
24
+
"#gpio-cells":
25
+
const: 2
26
+
27
+
interrupts:
28
+
maxItems: 1
29
+
30
+
interrupt-controller: true
31
+
32
+
"#interrupt-cells":
33
+
const: 2
34
+
35
+
clocks:
36
+
maxItems: 1
37
+
38
+
microchip,gpio-bank:
39
+
description: Bank index owned by the controller
40
+
$ref: /schemas/types.yaml#/definitions/uint32
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- gpio-controller
46
+
- gpio-ranges
47
+
- "#gpio-cells"
48
+
- interrupts
49
+
- interrupt-controller
50
+
- "#interrupt-cells"
51
+
- clocks
52
+
- microchip,gpio-bank
53
+
54
+
additionalProperties: false
55
+
56
+
examples:
57
+
- |
58
+
#include <dt-bindings/interrupt-controller/irq.h>
59
+
60
+
gpio@1f860000 {
61
+
compatible = "microchip,pic32mzda-gpio";
62
+
reg = <0x1f860000 0x100>;
63
+
interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
64
+
#gpio-cells = <2>;
65
+
gpio-controller;
66
+
interrupt-controller;
67
+
#interrupt-cells = <2>;
68
+
clocks = <&rootclk 11>;
69
+
microchip,gpio-bank = <0>;
70
+
gpio-ranges = <&pic32_pinctrl 0 0 16>;
71
+
};
-22
Documentation/devicetree/bindings/gpio/netxbig-gpio-ext.txt
-22
Documentation/devicetree/bindings/gpio/netxbig-gpio-ext.txt
···
1
-
Binding for the GPIO extension bus found on some LaCie/Seagate boards
2
-
(Example: 2Big/5Big Network v2, 2Big NAS).
3
-
4
-
Required properties:
5
-
- compatible: "lacie,netxbig-gpio-ext".
6
-
- addr-gpios: GPIOs representing the address register (LSB -> MSB).
7
-
- data-gpios: GPIOs representing the data register (LSB -> MSB).
8
-
- enable-gpio: latches the new configuration (address, data) on raising edge.
9
-
10
-
Example:
11
-
12
-
netxbig_gpio_ext: netxbig-gpio-ext {
13
-
compatible = "lacie,netxbig-gpio-ext";
14
-
15
-
addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
16
-
&gpio1 16 GPIO_ACTIVE_HIGH
17
-
&gpio1 17 GPIO_ACTIVE_HIGH>;
18
-
data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
19
-
&gpio1 13 GPIO_ACTIVE_HIGH
20
-
&gpio1 14 GPIO_ACTIVE_HIGH>;
21
-
enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
22
-
};
-26
Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt
-26
Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt
···
1
-
Nintendo Wii (Hollywood) GPIO controller
2
-
3
-
Required properties:
4
-
- compatible: "nintendo,hollywood-gpio"
5
-
- reg: Physical base address and length of the controller's registers.
6
-
- gpio-controller: Marks the device node as a GPIO controller.
7
-
- #gpio-cells: Should be <2>. The first cell is the pin number and the
8
-
second cell is used to specify optional parameters:
9
-
- bit 0 specifies polarity (0 for normal, 1 for inverted).
10
-
11
-
Optional properties:
12
-
- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt
13
-
- interrupt-controller: Marks the device node as an interrupt controller.
14
-
- #interrupt-cells: Should be two.
15
-
- interrupts: Interrupt specifier for the controller's Broadway (PowerPC)
16
-
interrupt.
17
-
18
-
Example:
19
-
20
-
GPIO: gpio@d8000c0 {
21
-
#gpio-cells = <2>;
22
-
compatible = "nintendo,hollywood-gpio";
23
-
reg = <0x0d8000c0 0x40>;
24
-
gpio-controller;
25
-
ngpios = <24>;
26
-
}
-59
Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt
-59
Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt
···
1
-
NXP LPC18xx/43xx GPIO controller Device Tree Bindings
2
-
-----------------------------------------------------
3
-
4
-
Required properties:
5
-
- compatible : Should be "nxp,lpc1850-gpio"
6
-
- reg : List of addresses and lengths of the GPIO controller
7
-
register sets
8
-
- reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
9
-
"gpio-gpoup1-ic"
10
-
- clocks : Phandle and clock specifier pair for GPIO controller
11
-
- resets : Phandle and reset specifier pair for GPIO controller
12
-
- gpio-controller : Marks the device node as a GPIO controller
13
-
- #gpio-cells : Should be two:
14
-
- The first cell is the GPIO line number
15
-
- The second cell is used to specify polarity
16
-
- interrupt-controller : Marks the device node as an interrupt controller
17
-
- #interrupt-cells : Should be two:
18
-
- The first cell is an interrupt number within
19
-
0..9 range, for GPIO pin interrupts it is equal
20
-
to 'nxp,gpio-pin-interrupt' property value of
21
-
GPIO pin configuration, 8 is for GPIO GROUP0
22
-
interrupt, 9 is for GPIO GROUP1 interrupt
23
-
- The second cell is used to specify interrupt type
24
-
25
-
Optional properties:
26
-
- gpio-ranges : Mapping between GPIO and pinctrl
27
-
28
-
Example:
29
-
#define LPC_GPIO(port, pin) (port * 32 + pin)
30
-
#define LPC_PIN(port, pin) (0x##port * 32 + pin)
31
-
32
-
gpio: gpio@400f4000 {
33
-
compatible = "nxp,lpc1850-gpio";
34
-
reg = <0x400f4000 0x4000>, <0x40087000 0x1000>,
35
-
<0x40088000 0x1000>, <0x40089000 0x1000>;
36
-
reg-names = "gpio", "gpio-pin-ic",
37
-
"gpio-group0-ic", "gpio-gpoup1-ic";
38
-
clocks = <&ccu1 CLK_CPU_GPIO>;
39
-
resets = <&rgu 28>;
40
-
gpio-controller;
41
-
#gpio-cells = <2>;
42
-
interrupt-controller;
43
-
#interrupt-cells = <2>;
44
-
gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
45
-
...
46
-
<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
47
-
};
48
-
49
-
gpio_joystick {
50
-
compatible = "gpio-keys";
51
-
...
52
-
53
-
button0 {
54
-
...
55
-
interrupt-parent = <&gpio>;
56
-
interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
57
-
gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
58
-
};
59
-
};
+78
Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.yaml
+78
Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/nxp,lpc1850-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP LPC18xx/43xx GPIO controller
8
+
9
+
maintainers:
10
+
- Frank Li <Frank.Li@nxp.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: nxp,lpc1850-gpio
15
+
16
+
reg:
17
+
minItems: 1
18
+
maxItems: 4
19
+
20
+
reg-names:
21
+
minItems: 1
22
+
items:
23
+
- const: gpio
24
+
- const: gpio-pin-ic
25
+
- const: gpio-group0-ic
26
+
- const: gpio-gpoup1-ic
27
+
28
+
clocks:
29
+
maxItems: 1
30
+
31
+
resets:
32
+
maxItems: 1
33
+
34
+
gpio-controller: true
35
+
36
+
'#gpio-cells':
37
+
const: 2
38
+
39
+
interrupt-controller: true
40
+
41
+
'#interrupt-cells':
42
+
const: 2
43
+
description: |
44
+
- The first cell is an interrupt number within
45
+
0..9 range, for GPIO pin interrupts it is equal
46
+
to 'nxp,gpio-pin-interrupt' property value of
47
+
GPIO pin configuration, 8 is for GPIO GROUP0
48
+
interrupt, 9 is for GPIO GROUP1 interrupt
49
+
- The second cell is used to specify interrupt type
50
+
51
+
gpio-ranges: true
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
- clocks
57
+
- gpio-controller
58
+
- '#gpio-cells'
59
+
60
+
additionalProperties: false
61
+
62
+
examples:
63
+
- |
64
+
#include <dt-bindings/clock/lpc18xx-ccu.h>
65
+
66
+
gpio@400f4000 {
67
+
compatible = "nxp,lpc1850-gpio";
68
+
reg = <0x400f4000 0x4000>, <0x40087000 0x1000>,
69
+
<0x40088000 0x1000>, <0x40089000 0x1000>;
70
+
reg-names = "gpio", "gpio-pin-ic", "gpio-group0-ic", "gpio-gpoup1-ic";
71
+
clocks = <&ccu1 CLK_CPU_GPIO>;
72
+
resets = <&rgu 28>;
73
+
gpio-controller;
74
+
#gpio-cells = <2>;
75
+
interrupt-controller;
76
+
#interrupt-cells = <2>;
77
+
};
78
+
+67
Documentation/devicetree/bindings/gpio/pisosr-gpio.yaml
+67
Documentation/devicetree/bindings/gpio/pisosr-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/pisosr-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Generic Parallel-in/Serial-out Shift Register GPIO Driver
8
+
9
+
description:
10
+
This binding describes generic parallel-in/serial-out shift register
11
+
devices that can be used for GPI (General Purpose Input). This includes
12
+
SN74165 serial-out shift registers and the SN65HVS88x series of
13
+
industrial serializers.
14
+
15
+
maintainers:
16
+
- Frank Li <Frank.Li@nxp.com>
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- pisosr-gpio
22
+
23
+
gpio-controller: true
24
+
25
+
'#gpio-cells':
26
+
const: 2
27
+
28
+
ngpios:
29
+
maximum: 32
30
+
default: 8
31
+
32
+
load-gpios:
33
+
description:
34
+
GPIO pin specifier attached to load enable, this
35
+
pin is pulsed before reading from the device to
36
+
load input pin values into the device.
37
+
38
+
spi-cpol: true
39
+
40
+
required:
41
+
- compatible
42
+
- gpio-controller
43
+
- '#gpio-cells'
44
+
45
+
allOf:
46
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
47
+
48
+
unevaluatedProperties: false
49
+
50
+
examples:
51
+
- |
52
+
#include <dt-bindings/gpio/gpio.h>
53
+
54
+
spi {
55
+
#address-cells = <1>;
56
+
#size-cells = <0>;
57
+
58
+
gpio@0 {
59
+
compatible = "pisosr-gpio";
60
+
reg = <0>;
61
+
gpio-controller;
62
+
#gpio-cells = <2>;
63
+
load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
64
+
spi-max-frequency = <1000000>;
65
+
spi-cpol;
66
+
};
67
+
};
-3
Documentation/devicetree/bindings/gpio/pl061-gpio.yaml
-3
Documentation/devicetree/bindings/gpio/pl061-gpio.yaml
+60
Documentation/devicetree/bindings/gpio/qca,ar7100-gpio.yaml
+60
Documentation/devicetree/bindings/gpio/qca,ar7100-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/qca,ar7100-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Atheros AR7xxx/AR9xxx GPIO controller
8
+
9
+
maintainers:
10
+
- Alban Bedel <albeu@free.fr>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- items:
16
+
- const: qca,ar9132-gpio
17
+
- const: qca,ar7100-gpio
18
+
- enum:
19
+
- qca,ar7100-gpio
20
+
- qca,ar9340-gpio
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
gpio-controller: true
26
+
27
+
'#gpio-cells':
28
+
const: 2
29
+
30
+
ngpios: true
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
interrupt-controller: true
36
+
37
+
'#interrupt-cells':
38
+
const: 2
39
+
40
+
required:
41
+
- compatible
42
+
- reg
43
+
- gpio-controller
44
+
- '#gpio-cells'
45
+
- ngpios
46
+
47
+
additionalProperties: false
48
+
49
+
examples:
50
+
- |
51
+
gpio@18040000 {
52
+
compatible = "qca,ar9132-gpio", "qca,ar7100-gpio";
53
+
reg = <0x18040000 0x30>;
54
+
interrupts = <2>;
55
+
ngpios = <22>;
56
+
gpio-controller;
57
+
#gpio-cells = <2>;
58
+
interrupt-controller;
59
+
#interrupt-cells = <2>;
60
+
};
+3
Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
+3
Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
-50
Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.yaml
-50
Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.yaml
···
1
-
# SPDX-License-Identifier: GPL-2.0
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Rockchip RK3328 General Register Files GPIO controller
8
-
9
-
description:
10
-
The Rockchip RK3328 General Register File (GRF) outputs only the
11
-
GPIO_MUTE pin, originally for codec mute control, but it can also be used
12
-
for general purpose. It is manipulated by the GRF_SOC_CON10 register.
13
-
If needed in the future support for the HDMI pins can also be added.
14
-
The GPIO node should be declared as the child of the GRF node.
15
-
16
-
The GPIO_MUTE pin is referred to in the format
17
-
18
-
<&grf_gpio 0 GPIO_ACTIVE_LOW>
19
-
20
-
The first cell is the pin number and
21
-
the second cell is used to specify the GPIO polarity
22
-
0 = Active high
23
-
1 = Active low
24
-
25
-
maintainers:
26
-
- Heiko Stuebner <heiko@sntech.de>
27
-
28
-
properties:
29
-
compatible:
30
-
const: rockchip,rk3328-grf-gpio
31
-
32
-
gpio-controller: true
33
-
34
-
"#gpio-cells":
35
-
const: 2
36
-
37
-
required:
38
-
- compatible
39
-
- gpio-controller
40
-
- "#gpio-cells"
41
-
42
-
additionalProperties: false
43
-
44
-
examples:
45
-
- |
46
-
grf_gpio: gpio {
47
-
compatible = "rockchip,rk3328-grf-gpio";
48
-
gpio-controller;
49
-
#gpio-cells = <2>;
50
-
};
-21
Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
-21
Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
···
1
-
Synopsys GPIO via CREG (Control REGisters) driver
2
-
3
-
Required properties:
4
-
- compatible : "snps,creg-gpio-hsdk" or "snps,creg-gpio-axs10x".
5
-
- reg : Exactly one register range with length 0x4.
6
-
- #gpio-cells : Since the generic GPIO binding is used, the
7
-
amount of cells must be specified as 2. The first cell is the
8
-
pin number, the second cell is used to specify optional parameters:
9
-
See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
10
-
- gpio-controller : Marks the device node as a GPIO controller.
11
-
- ngpios: Number of GPIO pins.
12
-
13
-
Example:
14
-
15
-
gpio: gpio@f00014b0 {
16
-
compatible = "snps,creg-gpio-hsdk";
17
-
reg = <0xf00014b0 0x4>;
18
-
gpio-controller;
19
-
#gpio-cells = <2>;
20
-
ngpios = <2>;
21
-
};
-49
Documentation/devicetree/bindings/gpio/spear_spics.txt
-49
Documentation/devicetree/bindings/gpio/spear_spics.txt
···
1
-
=== ST Microelectronics SPEAr SPI CS Driver ===
2
-
3
-
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
4
-
Cell spi controller through its system registers, which otherwise remains under
5
-
PL022 control. If chipselect remain under PL022 control then they would be
6
-
released as soon as transfer is over and TxFIFO becomes empty. This is not
7
-
desired by some of the device protocols above spi which expect (multiple)
8
-
transfers without releasing their chipselects.
9
-
10
-
Chipselects can be controlled by software by turning them as GPIOs. SPEAr
11
-
provides another interface through system registers through which software can
12
-
directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
13
-
the control of this interface as gpio.
14
-
15
-
Required properties:
16
-
17
-
* compatible: should be defined as "st,spear-spics-gpio"
18
-
* reg: mentioning address range of spics controller
19
-
* st-spics,peripcfg-reg: peripheral configuration register offset
20
-
* st-spics,sw-enable-bit: bit offset to enable sw control
21
-
* st-spics,cs-value-bit: bit offset to drive chipselect low or high
22
-
* st-spics,cs-enable-mask: chip select number bit mask
23
-
* st-spics,cs-enable-shift: chip select number program offset
24
-
* gpio-controller: Marks the device node as gpio controller
25
-
* #gpio-cells: should be 1 and will mention chip select number
26
-
27
-
All the above bit offsets are within peripcfg register.
28
-
29
-
Example:
30
-
-------
31
-
spics: spics@e0700000{
32
-
compatible = "st,spear-spics-gpio";
33
-
reg = <0xe0700000 0x1000>;
34
-
st-spics,peripcfg-reg = <0x3b0>;
35
-
st-spics,sw-enable-bit = <12>;
36
-
st-spics,cs-value-bit = <11>;
37
-
st-spics,cs-enable-mask = <3>;
38
-
st-spics,cs-enable-shift = <8>;
39
-
gpio-controller;
40
-
#gpio-cells = <2>;
41
-
};
42
-
43
-
44
-
spi0: spi@e0100000 {
45
-
num-cs = <3>;
46
-
cs-gpios = <&gpio1 7 0>, <&spics 0>,
47
-
<&spics 1>;
48
-
...
49
-
}
+82
Documentation/devicetree/bindings/gpio/st,spear-spics-gpio.yaml
+82
Documentation/devicetree/bindings/gpio/st,spear-spics-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ST Microelectronics SPEAr SPI CS GPIO Controller
8
+
9
+
maintainers:
10
+
- Viresh Kumar <vireshk@kernel.org>
11
+
12
+
description: >
13
+
SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
14
+
Cell spi controller through its system registers, which otherwise remains
15
+
under PL022 control. If chipselect remain under PL022 control then they would
16
+
be released as soon as transfer is over and TxFIFO becomes empty. This is not
17
+
desired by some of the device protocols above spi which expect (multiple)
18
+
transfers without releasing their chipselects.
19
+
20
+
Chipselects can be controlled by software by turning them as GPIOs. SPEAr
21
+
provides another interface through system registers through which software can
22
+
directly control each PL022 chipselect. Hence, it is natural for SPEAr to
23
+
export the control of this interface as gpio.
24
+
25
+
properties:
26
+
compatible:
27
+
const: st,spear-spics-gpio
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
gpio-controller: true
33
+
34
+
'#gpio-cells':
35
+
const: 2
36
+
37
+
st-spics,peripcfg-reg:
38
+
description: Offset of the peripcfg register.
39
+
$ref: /schemas/types.yaml#/definitions/uint32
40
+
41
+
st-spics,sw-enable-bit:
42
+
description: Bit offset to enable software chipselect control.
43
+
$ref: /schemas/types.yaml#/definitions/uint32
44
+
45
+
st-spics,cs-value-bit:
46
+
description: Bit offset to drive chipselect low or high.
47
+
$ref: /schemas/types.yaml#/definitions/uint32
48
+
49
+
st-spics,cs-enable-mask:
50
+
description: Bitmask selecting which chipselects to enable.
51
+
$ref: /schemas/types.yaml#/definitions/uint32
52
+
53
+
st-spics,cs-enable-shift:
54
+
description: Bit shift for programming chipselect number.
55
+
$ref: /schemas/types.yaml#/definitions/uint32
56
+
57
+
required:
58
+
- compatible
59
+
- reg
60
+
- gpio-controller
61
+
- '#gpio-cells'
62
+
- st-spics,peripcfg-reg
63
+
- st-spics,sw-enable-bit
64
+
- st-spics,cs-value-bit
65
+
- st-spics,cs-enable-mask
66
+
- st-spics,cs-enable-shift
67
+
68
+
additionalProperties: false
69
+
70
+
examples:
71
+
- |
72
+
gpio@e0700000 {
73
+
compatible = "st,spear-spics-gpio";
74
+
reg = <0xe0700000 0x1000>;
75
+
st-spics,peripcfg-reg = <0x3b0>;
76
+
st-spics,sw-enable-bit = <12>;
77
+
st-spics,cs-value-bit = <11>;
78
+
st-spics,cs-enable-mask = <3>;
79
+
st-spics,cs-enable-shift = <8>;
80
+
gpio-controller;
81
+
#gpio-cells = <2>;
82
+
};
+65
Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml
+65
Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Keystone 2 DSP GPIO controller
8
+
9
+
maintainers:
10
+
- Grygorii Strashko <grygorii.strashko@ti.com>
11
+
12
+
description: |
13
+
HOST OS userland running on ARM can send interrupts to DSP cores using
14
+
the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
15
+
This is one of the component used by the IPC mechanism used on Keystone SOCs.
16
+
17
+
For example TCI6638K2K SoC has 8 DSP GPIO controllers:
18
+
- 8 for C66x CorePacx CPUs 0-7
19
+
20
+
Keystone 2 DSP GPIO controller has specific features:
21
+
- each GPIO can be configured only as output pin;
22
+
- setting GPIO value to 1 causes IRQ generation on target DSP core;
23
+
- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
24
+
pending.
25
+
26
+
properties:
27
+
compatible:
28
+
const: ti,keystone-dsp-gpio
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
gpio-controller: true
34
+
35
+
'#gpio-cells':
36
+
const: 2
37
+
38
+
gpio,syscon-dev:
39
+
description:
40
+
Phandle and offset of device's specific registers within the syscon state
41
+
control registers
42
+
$ref: /schemas/types.yaml#/definitions/phandle-array
43
+
items:
44
+
- items:
45
+
- description: phandle to syscon
46
+
- description: register offset within state control registers
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
- gpio-controller
52
+
- '#gpio-cells'
53
+
- gpio,syscon-dev
54
+
55
+
additionalProperties: false
56
+
57
+
examples:
58
+
- |
59
+
gpio@240 {
60
+
compatible = "ti,keystone-dsp-gpio";
61
+
reg = <0x240 0x4>;
62
+
gpio-controller;
63
+
#gpio-cells = <2>;
64
+
gpio,syscon-dev = <&devctrl 0x240>;
65
+
};
+61
Documentation/devicetree/bindings/gpio/ti,twl4030-gpio.yaml
+61
Documentation/devicetree/bindings/gpio/ti,twl4030-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ti,twl4030-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI TWL4030 GPIO controller
8
+
9
+
maintainers:
10
+
- Aaro Koskinen <aaro.koskinen@iki.fi>
11
+
- Andreas Kemnade <andreas@kemnade.info>
12
+
- Kevin Hilman <khilman@baylibre.com>
13
+
- Roger Quadros <rogerq@kernel.org>
14
+
- Tony Lindgren <tony@atomide.com>
15
+
16
+
properties:
17
+
compatible:
18
+
const: ti,twl4030-gpio
19
+
20
+
'#gpio-cells':
21
+
const: 2
22
+
23
+
gpio-controller: true
24
+
25
+
'#interrupt-cells':
26
+
const: 1
27
+
28
+
interrupt-controller: true
29
+
30
+
ti,debounce:
31
+
description: Debounce control bits. Each bit corresponds to a GPIO pin.
32
+
$ref: /schemas/types.yaml#/definitions/uint32
33
+
34
+
ti,mmc-cd:
35
+
description: MMC card detect control bits. Each bit corresponds to a GPIO pin for VMMC(n+1).
36
+
$ref: /schemas/types.yaml#/definitions/uint32
37
+
38
+
ti,pullups:
39
+
description: Pull-up control bits. Each bit corresponds to a GPIO pin.
40
+
$ref: /schemas/types.yaml#/definitions/uint32
41
+
42
+
ti,pulldowns:
43
+
description: Pull-down control bits. Each bit corresponds to a GPIO pin.
44
+
$ref: /schemas/types.yaml#/definitions/uint32
45
+
46
+
ti,use-leds:
47
+
type: boolean
48
+
description: Enables LEDA and LEDB outputs if set
49
+
50
+
additionalProperties: false
51
+
52
+
examples:
53
+
- |
54
+
gpio {
55
+
compatible = "ti,twl4030-gpio";
56
+
#gpio-cells = <2>;
57
+
gpio-controller;
58
+
#interrupt-cells = <1>;
59
+
interrupt-controller;
60
+
ti,use-leds;
61
+
};
+110
Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
+110
Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/trivial-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Trivial 2-cell GPIO controllers
8
+
9
+
maintainers:
10
+
- Bartosz Golaszewski <brgl@bgdev.pl>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- items:
16
+
- enum:
17
+
- cirrus,ep7312-gpio
18
+
- const: cirrus,ep7209-gpio
19
+
- enum:
20
+
- apm,xgene-gpio
21
+
- cirrus,ep7209-gpio
22
+
- cznic,moxtet-gpio
23
+
- dlg,slg7xl45106
24
+
- fcs,fxl6408
25
+
- gateworks,pld-gpio
26
+
- ibm,ppc4xx-gpio
27
+
- loongson,ls1x-gpio
28
+
- maxim,max77620
29
+
- nintendo,hollywood-gpio
30
+
- nxp,pca9570
31
+
- nxp,pca9571
32
+
- rockchip,rk3328-grf-gpio
33
+
- snps,creg-gpio-hsdk
34
+
- technologic,ts4800-gpio
35
+
- technologic,ts4900-gpio
36
+
- technologic,ts7970-gpio
37
+
- ti,741g125 # for 741G125 (1-bit Input),
38
+
- ti,741g174 # for 741G74 (1-bit Output),
39
+
- ti,742g125 # for 742G125 (2-bit Input),
40
+
- ti,7474 # for 7474 (2-bit Output),
41
+
- ti,74125 # for 74125 (4-bit Input),
42
+
- ti,74175 # for 74175 (4-bit Output),
43
+
- ti,74365 # for 74365 (6-bit Input),
44
+
- ti,74174 # for 74174 (6-bit Output),
45
+
- ti,74244 # for 74244 (8-bit Input),
46
+
- ti,74273 # for 74273 (8-bit Output),
47
+
- ti,741624 # for 741624 (16-bit Input),
48
+
- ti,7416374 # for 7416374 (16-bit Output).
49
+
- ti,lp3943-gpio
50
+
- ti,palmas-gpio
51
+
- ti,tpic2810
52
+
- ti,tps80036-gpio
53
+
- ti,tps65913-gpio
54
+
- ti,tps65914-gpio
55
+
56
+
reg:
57
+
maxItems: 1
58
+
59
+
'#gpio-cells':
60
+
const: 2
61
+
62
+
gpio-controller: true
63
+
64
+
gpio-line-names: true
65
+
66
+
ngpios: true
67
+
68
+
# Don't add more properties
69
+
70
+
patternProperties:
71
+
"^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
72
+
type: object
73
+
required:
74
+
- gpio-hog
75
+
76
+
required:
77
+
- compatible
78
+
- '#gpio-cells'
79
+
- gpio-controller
80
+
81
+
allOf:
82
+
- if:
83
+
properties:
84
+
compatible:
85
+
contains:
86
+
enum:
87
+
- maxim,max77620
88
+
- rockchip,rk3328-grf-gpio
89
+
- ti,lp3943-gpio
90
+
- ti,palmas-gpio
91
+
- ti,tps80036-gpio
92
+
- ti,tps65913-gpio
93
+
- ti,tps65914-gpio
94
+
then:
95
+
properties:
96
+
reg: false
97
+
else:
98
+
required:
99
+
- reg
100
+
101
+
additionalProperties: false
102
+
103
+
examples:
104
+
- |
105
+
gpio@1701c000 {
106
+
compatible = "apm,xgene-gpio";
107
+
reg = <0x1701c000 0x40>;
108
+
gpio-controller;
109
+
#gpio-cells = <2>;
110
+
};
+1
Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
+1
Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
+227
-13
Documentation/devicetree/bindings/mfd/adi,adp5585.yaml
+227
-13
Documentation/devicetree/bindings/mfd/adi,adp5585.yaml
···
15
15
16
16
properties:
17
17
compatible:
18
-
items:
19
-
- enum:
20
-
- adi,adp5585-00 # Default
21
-
- adi,adp5585-01 # 11 GPIOs
22
-
- adi,adp5585-02 # No pull-up resistors by default on special pins
23
-
- adi,adp5585-03 # Alternate I2C address
24
-
- adi,adp5585-04 # Pull-down resistors on all pins by default
25
-
- const: adi,adp5585
18
+
oneOf:
19
+
- items:
20
+
- enum:
21
+
- adi,adp5585-00 # Default
22
+
- adi,adp5585-01 # 11 GPIOs
23
+
- adi,adp5585-02 # No pull-up resistors by default on special pins
24
+
- adi,adp5585-03 # Alternate I2C address
25
+
- adi,adp5585-04 # Pull-down resistors on all pins by default
26
+
- const: adi,adp5585
27
+
- items:
28
+
- enum:
29
+
- adi,adp5589-00 # Default
30
+
- adi,adp5589-01 # R4 defaulted to RESET1 output
31
+
- adi,adp5589-02 # Pull-down resistors by default on special pins
32
+
- const: adi,adp5589
26
33
27
34
reg:
28
35
maxItems: 1
···
38
31
maxItems: 1
39
32
40
33
vdd-supply: true
34
+
35
+
reset-gpios:
36
+
maxItems: 1
41
37
42
38
gpio-controller: true
43
39
···
52
42
"#pwm-cells":
53
43
const: 3
54
44
45
+
interrupt-controller: true
46
+
47
+
'#interrupt-cells':
48
+
const: 2
49
+
50
+
poll-interval:
51
+
enum: [10, 20, 30, 40]
52
+
default: 10
53
+
54
+
adi,keypad-pins:
55
+
description: Specifies the pins used for the keypad matrix.
56
+
$ref: /schemas/types.yaml#/definitions/uint32-array
57
+
58
+
adi,unlock-events:
59
+
description:
60
+
Specifies a maximum of 2 events that can be used to unlock the keypad.
61
+
If this property is set, the keyboard will be locked and only unlocked
62
+
after these keys/gpis are pressed. The value 127 serves as a wildcard which
63
+
means any key can be used for unlocking.
64
+
$ref: /schemas/types.yaml#/definitions/uint32-array
65
+
minItems: 1
66
+
maxItems: 2
67
+
items:
68
+
anyOf:
69
+
- minimum: 1
70
+
maximum: 88
71
+
- minimum: 97
72
+
maximum: 115
73
+
- const: 127
74
+
75
+
adi,unlock-trigger-sec:
76
+
description:
77
+
Defines the time in which the second unlock event must occur after the
78
+
first unlock event has occurred.
79
+
maximum: 7
80
+
default: 0
81
+
82
+
adi,reset1-events:
83
+
description:
84
+
Defines the trigger events (key/gpi presses) that can generate reset
85
+
conditions one the reset1 block.
86
+
$ref: /schemas/types.yaml#/definitions/uint32-array
87
+
minItems: 1
88
+
maxItems: 3
89
+
90
+
adi,reset2-events:
91
+
description:
92
+
Defines the trigger events (key/gpi presses) that can generate reset
93
+
conditions one the reset2 block.
94
+
$ref: /schemas/types.yaml#/definitions/uint32-array
95
+
minItems: 1
96
+
maxItems: 2
97
+
98
+
adi,reset1-active-high:
99
+
description: Sets the reset1 signal as active high.
100
+
type: boolean
101
+
102
+
adi,reset2-active-high:
103
+
description: Sets the reset2 signal as active high.
104
+
type: boolean
105
+
106
+
adi,rst-passthrough-enable:
107
+
description: Allows the RST pin to override (OR with) the reset1 signal.
108
+
type: boolean
109
+
110
+
adi,reset-trigger-ms:
111
+
description:
112
+
Defines the length of time that the reset events must be active before a
113
+
reset signal is generated. All events must be active at the same time for
114
+
the same duration.
115
+
enum: [0, 1000, 1500, 2000, 2500, 3000, 3500, 4000]
116
+
default: 0
117
+
118
+
adi,reset-pulse-width-us:
119
+
description: Defines the pulse width of the reset signals.
120
+
enum: [500, 1000, 2000, 10000]
121
+
default: 500
122
+
55
123
patternProperties:
56
124
"-hog(-[0-9]+)?$":
57
125
type: object
···
137
49
required:
138
50
- gpio-hog
139
51
52
+
dependencies:
53
+
linux,keymap:
54
+
- adi,keypad-pins
55
+
- interrupts
56
+
interrupt-controller:
57
+
- interrupts
58
+
adi,unlock-trigger-sec:
59
+
- adi,unlock-events
60
+
adi,reset1-active-high:
61
+
- adi,reset1-events
62
+
adi,rst-passtrough-enable:
63
+
- adi,reset1-events
64
+
adi,reset2-active-high:
65
+
- adi,reset2-events
66
+
140
67
required:
141
68
- compatible
142
69
- reg
143
-
- gpio-controller
144
-
- "#gpio-cells"
145
-
- "#pwm-cells"
146
70
147
71
allOf:
72
+
- $ref: /schemas/input/matrix-keymap.yaml#
73
+
- $ref: /schemas/input/input.yaml#
148
74
- if:
149
75
properties:
150
76
compatible:
···
166
64
const: adi,adp5585-01
167
65
then:
168
66
properties:
67
+
adi,unlock-events: false
68
+
adi,unlock-trigger-sec: false
169
69
gpio-reserved-ranges: false
170
-
else:
70
+
reset-gpios: false
71
+
adi,keypad-pins:
72
+
minItems: 2
73
+
maxItems: 11
74
+
items:
75
+
minimum: 0
76
+
maximum: 10
77
+
adi,reset1-events:
78
+
items:
79
+
anyOf:
80
+
- minimum: 1
81
+
maximum: 30
82
+
- minimum: 37
83
+
maximum: 47
84
+
adi,reset2-events:
85
+
items:
86
+
anyOf:
87
+
- minimum: 1
88
+
maximum: 30
89
+
- minimum: 37
90
+
maximum: 47
91
+
- if:
171
92
properties:
93
+
compatible:
94
+
contains:
95
+
enum:
96
+
- adi,adp5585-00
97
+
- adi,adp5585-02
98
+
- adi,adp5585-03
99
+
- adi,adp5585-04
100
+
then:
101
+
properties:
102
+
adi,unlock-events: false
103
+
adi,unlock-trigger-sec: false
104
+
adi,keypad-pins:
105
+
minItems: 2
106
+
maxItems: 10
107
+
items:
108
+
enum: [0, 1, 2, 3, 4, 6, 7, 8, 9, 10]
109
+
adi,reset1-events:
110
+
items:
111
+
anyOf:
112
+
- minimum: 1
113
+
maximum: 25
114
+
- enum: [37, 38, 39, 40, 41, 43, 44, 45, 46, 47]
115
+
adi,reset2-events:
116
+
items:
117
+
anyOf:
118
+
- minimum: 1
119
+
maximum: 25
120
+
- enum: [37, 38, 39, 40, 41, 43, 44, 45, 46, 47]
172
121
gpio-reserved-ranges:
173
122
maxItems: 1
174
123
items:
···
227
74
- const: 5
228
75
- const: 1
229
76
230
-
additionalProperties: false
77
+
- if:
78
+
properties:
79
+
compatible:
80
+
contains:
81
+
enum:
82
+
- adi,adp5589-00
83
+
- adi,adp5589-01
84
+
- adi,adp5589-02
85
+
then:
86
+
properties:
87
+
gpio-reserved-ranges: false
88
+
adi,keypad-pins:
89
+
minItems: 2
90
+
maxItems: 19
91
+
items:
92
+
minimum: 0
93
+
maximum: 18
94
+
adi,reset1-events:
95
+
items:
96
+
anyOf:
97
+
- minimum: 1
98
+
maximum: 88
99
+
- minimum: 97
100
+
maximum: 115
101
+
adi,reset2-events:
102
+
items:
103
+
anyOf:
104
+
- minimum: 1
105
+
maximum: 88
106
+
- minimum: 97
107
+
maximum: 115
108
+
109
+
unevaluatedProperties: false
231
110
232
111
examples:
233
112
- |
113
+
#include <dt-bindings/input/input.h>
114
+
#include <dt-bindings/interrupt-controller/irq.h>
234
115
i2c {
235
116
#address-cells = <1>;
236
117
#size-cells = <0>;
···
280
93
gpio-reserved-ranges = <5 1>;
281
94
282
95
#pwm-cells = <3>;
96
+
97
+
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
98
+
interrupt-parent = <&gpio>;
99
+
100
+
adi,reset1-events = <1 43>;
101
+
adi,reset2-events = <2 3>;
102
+
adi,reset-trigger-ms = <2000>;
103
+
104
+
/*
105
+
* col0, col1, col2
106
+
* row0, row1, row2
107
+
*/
108
+
adi,keypad-pins = <0 1 2 6 7 8>;
109
+
110
+
linux,keymap = <
111
+
MATRIX_KEY(0x00, 0x00, KEY_1)
112
+
MATRIX_KEY(0x00, 0x01, KEY_2)
113
+
MATRIX_KEY(0x00, 0x02, KEY_3)
114
+
115
+
MATRIX_KEY(0x01, 0x00, KEY_A)
116
+
MATRIX_KEY(0x01, 0x01, KEY_B)
117
+
MATRIX_KEY(0x01, 0x02, KEY_C)
118
+
119
+
MATRIX_KEY(0x02, 0x00, BTN_1)
120
+
MATRIX_KEY(0x02, 0x01, BTN_2)
121
+
MATRIX_KEY(0x02, 0x02, BTN_3)
122
+
>;
283
123
};
284
124
};
285
125
+79
Documentation/devicetree/bindings/mfd/apple,smc.yaml
+79
Documentation/devicetree/bindings/mfd/apple,smc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/apple,smc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Apple Mac System Management Controller
8
+
9
+
maintainers:
10
+
- Sven Peter <sven@kernel.org>
11
+
12
+
description:
13
+
Apple Mac System Management Controller implements various functions
14
+
such as GPIO, RTC, power, reboot.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- enum:
20
+
- apple,t6000-smc
21
+
- apple,t8103-smc
22
+
- apple,t8112-smc
23
+
- const: apple,smc
24
+
25
+
reg:
26
+
items:
27
+
- description: SMC area
28
+
- description: SRAM area
29
+
30
+
reg-names:
31
+
items:
32
+
- const: smc
33
+
- const: sram
34
+
35
+
mboxes:
36
+
maxItems: 1
37
+
38
+
gpio:
39
+
$ref: /schemas/gpio/apple,smc-gpio.yaml
40
+
41
+
reboot:
42
+
$ref: /schemas/power/reset/apple,smc-reboot.yaml
43
+
44
+
additionalProperties: false
45
+
46
+
required:
47
+
- compatible
48
+
- reg
49
+
- reg-names
50
+
- mboxes
51
+
52
+
examples:
53
+
- |
54
+
soc {
55
+
#address-cells = <2>;
56
+
#size-cells = <2>;
57
+
58
+
smc@23e400000 {
59
+
compatible = "apple,t8103-smc", "apple,smc";
60
+
reg = <0x2 0x3e400000 0x0 0x4000>,
61
+
<0x2 0x3fe00000 0x0 0x100000>;
62
+
reg-names = "smc", "sram";
63
+
mboxes = <&smc_mbox>;
64
+
65
+
smc_gpio: gpio {
66
+
compatible = "apple,smc-gpio";
67
+
gpio-controller;
68
+
#gpio-cells = <2>;
69
+
};
70
+
71
+
reboot {
72
+
compatible = "apple,smc-reboot";
73
+
nvmem-cells = <&shutdown_flag>, <&boot_stage>,
74
+
<&boot_error_count>, <&panic_count>;
75
+
nvmem-cell-names = "shutdown_flag", "boot_stage",
76
+
"boot_error_count", "panic_count";
77
+
};
78
+
};
79
+
};
+1
-1
Documentation/devicetree/bindings/mfd/lp3943.txt
+1
-1
Documentation/devicetree/bindings/mfd/lp3943.txt
···
7
7
LP3943 consists of two sub-devices, lp3943-gpio and lp3943-pwm.
8
8
9
9
For the LP3943 GPIO properties please refer to:
10
-
Documentation/devicetree/bindings/gpio/gpio-lp3943.txt
10
+
Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
11
11
12
12
For the LP3943 PWM properties please refer to:
13
13
Documentation/devicetree/bindings/pwm/pwm-lp3943.txt
+40
Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml
+40
Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/power/reset/apple,smc-reboot.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Apple SMC Reboot Controller
8
+
9
+
description:
10
+
The Apple System Management Controller (SMC) provides reboot functionality
11
+
on Apple Silicon SoCs. It uses NVMEM cells to store and track various
12
+
system state information related to boot, shutdown, and panic events.
13
+
14
+
maintainers:
15
+
- Sven Peter <sven@kernel.org>
16
+
17
+
properties:
18
+
compatible:
19
+
const: apple,smc-reboot
20
+
21
+
nvmem-cells:
22
+
items:
23
+
- description: Flag indicating shutdown (as opposed to reboot)
24
+
- description: Stage at which the boot process stopped (0x30 for normal boot)
25
+
- description: Counter for boot errors
26
+
- description: Counter for system panics
27
+
28
+
nvmem-cell-names:
29
+
items:
30
+
- const: shutdown_flag
31
+
- const: boot_stage
32
+
- const: boot_error_count
33
+
- const: panic_count
34
+
35
+
required:
36
+
- compatible
37
+
- nvmem-cells
38
+
- nvmem-cell-names
39
+
40
+
additionalProperties: false
-4
Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
-4
Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
···
139
139
- interrupt-controller
140
140
- interrupts : should contain the cascade interrupt of the "flipper" pic
141
141
142
-
1.l) The General Purpose I/O (GPIO) controller node
143
-
144
-
see Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt
145
-
146
142
1.m) The control node
147
143
148
144
Represents the control interface used to setup several miscellaneous
+5
-3
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+5
-3
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
···
179
179
properties:
180
180
gpio:
181
181
type: object
182
+
properties:
183
+
compatible:
184
+
contains:
185
+
const: rockchip,rk3328-grf-gpio
182
186
183
-
$ref: /schemas/gpio/rockchip,rk3328-grf-gpio.yaml#
184
-
185
-
unevaluatedProperties: false
187
+
additionalProperties: true
186
188
187
189
power-controller:
188
190
type: object
-2
Documentation/devicetree/bindings/trivial-devices.yaml
-2
Documentation/devicetree/bindings/trivial-devices.yaml
···
39
39
- ad,adm9240
40
40
# AD5110 - Nonvolatile Digital Potentiometer
41
41
- adi,ad5110
42
-
# Analog Devices ADP5589 Keypad Decoder and I/O Expansion
43
-
- adi,adp5589
44
42
# Analog Devices LT7182S Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher
45
43
- adi,lt7182s
46
44
# AMS iAQ-Core VOC Sensor
-1
Documentation/driver-api/driver-model/devres.rst
-1
Documentation/driver-api/driver-model/devres.rst
+9
-3
MAINTAINERS
+9
-3
MAINTAINERS
···
551
551
S: Maintained
552
552
F: Documentation/devicetree/bindings/*/adi,adp5585*.yaml
553
553
F: drivers/gpio/gpio-adp5585.c
554
+
F: drivers/input/keyboard/adp5585-keys.c
554
555
F: drivers/mfd/adp5585.c
555
556
F: drivers/pwm/pwm-adp5585.c
556
557
F: include/linux/mfd/adp5585.h
···
2332
2331
F: Documentation/devicetree/bindings/clock/apple,nco.yaml
2333
2332
F: Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
2334
2333
F: Documentation/devicetree/bindings/dma/apple,admac.yaml
2334
+
F: Documentation/devicetree/bindings/gpio/apple,smc-gpio.yaml
2335
2335
F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
2336
2336
F: Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml
2337
2337
F: Documentation/devicetree/bindings/interrupt-controller/apple,*
···
2340
2338
F: Documentation/devicetree/bindings/iommu/apple,sart.yaml
2341
2339
F: Documentation/devicetree/bindings/leds/backlight/apple,dwi-bl.yaml
2342
2340
F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
2341
+
F: Documentation/devicetree/bindings/mfd/apple,smc.yaml
2343
2342
F: Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml
2344
2343
F: Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml
2345
2344
F: Documentation/devicetree/bindings/nvmem/apple,efuses.yaml
···
2348
2345
F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
2349
2346
F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
2350
2347
F: Documentation/devicetree/bindings/power/apple*
2348
+
F: Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml
2351
2349
F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
2352
2350
F: Documentation/devicetree/bindings/spi/apple,spi.yaml
2353
2351
F: Documentation/devicetree/bindings/spmi/apple,spmi.yaml
···
2358
2354
F: drivers/clk/clk-apple-nco.c
2359
2355
F: drivers/cpufreq/apple-soc-cpufreq.c
2360
2356
F: drivers/dma/apple-admac.c
2357
+
F: drivers/gpio/gpio-macsmc.c
2361
2358
F: drivers/pmdomain/apple/
2362
2359
F: drivers/i2c/busses/i2c-pasemi-core.c
2363
2360
F: drivers/i2c/busses/i2c-pasemi-platform.c
···
2366
2361
F: drivers/iommu/apple-dart.c
2367
2362
F: drivers/iommu/io-pgtable-dart.c
2368
2363
F: drivers/irqchip/irq-apple-aic.c
2364
+
F: drivers/mfd/macsmc.c
2369
2365
F: drivers/nvme/host/apple.c
2370
2366
F: drivers/nvmem/apple-efuses.c
2371
2367
F: drivers/nvmem/apple-spmi-nvmem.c
2372
2368
F: drivers/pinctrl/pinctrl-apple-gpio.c
2369
+
F: drivers/power/reset/macsmc-reboot.c
2373
2370
F: drivers/pwm/pwm-apple.c
2374
2371
F: drivers/soc/apple/*
2375
2372
F: drivers/spi/spi-apple.c
···
2380
2373
F: drivers/watchdog/apple_wdt.c
2381
2374
F: include/dt-bindings/interrupt-controller/apple-aic.h
2382
2375
F: include/dt-bindings/pinctrl/apple.h
2376
+
F: include/linux/mfd/macsmc.h
2383
2377
F: include/linux/soc/apple/*
2384
2378
F: include/uapi/drm/asahi_drm.h
2385
2379
···
2553
2545
F: Documentation/devicetree/bindings/bus/moxtet.txt
2554
2546
F: Documentation/devicetree/bindings/firmware/cznic,turris-mox-rwtm.txt
2555
2547
F: Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml
2556
-
F: Documentation/devicetree/bindings/gpio/gpio-moxtet.txt
2557
2548
F: Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml
2558
2549
F: Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml
2559
2550
F: Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt
···
3822
3815
S: Maintained
3823
3816
W: https://github.com/AlbanBedel/linux
3824
3817
T: git git://github.com/AlbanBedel/linux
3825
-
F: Documentation/devicetree/bindings/gpio/gpio-ath79.txt
3818
+
F: Documentation/devicetree/bindings/gpio/qca,ar7100-gpio.yaml
3826
3819
F: drivers/gpio/gpio-ath79.c
3827
3820
3828
3821
ATHEROS 71XX/9XXX USB PHY DRIVER
···
24046
24039
SYNOPSYS CREG GPIO DRIVER
24047
24040
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
24048
24041
S: Maintained
24049
-
F: Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
24050
24042
F: drivers/gpio/gpio-creg-snps.c
24051
24043
24052
24044
SYNOPSYS DESIGNWARE 8250 UART DRIVER
+20
-22
arch/arm/mach-omap1/board-ams-delta.c
+20
-22
arch/arm/mach-omap1/board-ams-delta.c
···
19
19
#include <linux/mtd/nand-gpio.h>
20
20
#include <linux/mtd/partitions.h>
21
21
#include <linux/platform_device.h>
22
+
#include <linux/property.h>
22
23
#include <linux/regulator/consumer.h>
23
24
#include <linux/regulator/fixed.h>
24
25
#include <linux/regulator/machine.h>
···
176
175
177
176
#define LATCH1_LABEL "latch1"
178
177
179
-
static struct bgpio_pdata latch1_pdata = {
180
-
.label = LATCH1_LABEL,
181
-
.base = -1,
182
-
.ngpio = LATCH1_NGPIO,
178
+
static const struct property_entry latch1_gpio_props[] = {
179
+
PROPERTY_ENTRY_STRING("label", LATCH1_LABEL),
180
+
PROPERTY_ENTRY_U32("ngpios", LATCH1_NGPIO),
181
+
{ }
183
182
};
184
183
185
-
static struct platform_device latch1_gpio_device = {
184
+
static const struct platform_device_info latch1_gpio_devinfo = {
186
185
.name = "basic-mmio-gpio",
187
186
.id = 0,
188
-
.resource = latch1_resources,
189
-
.num_resources = ARRAY_SIZE(latch1_resources),
190
-
.dev = {
191
-
.platform_data = &latch1_pdata,
192
-
},
187
+
.res = latch1_resources,
188
+
.num_res = ARRAY_SIZE(latch1_resources),
189
+
.properties = latch1_gpio_props,
193
190
};
194
191
195
192
#define LATCH1_PIN_LED_CAMERA 0
···
212
213
213
214
#define LATCH2_LABEL "latch2"
214
215
215
-
static struct bgpio_pdata latch2_pdata = {
216
-
.label = LATCH2_LABEL,
217
-
.base = -1,
218
-
.ngpio = LATCH2_NGPIO,
216
+
static const struct property_entry latch2_gpio_props[] = {
217
+
PROPERTY_ENTRY_STRING("label", LATCH2_LABEL),
218
+
PROPERTY_ENTRY_U32("ngpios", LATCH2_NGPIO),
219
+
{ }
219
220
};
220
221
221
-
static struct platform_device latch2_gpio_device = {
222
+
static struct platform_device_info latch2_gpio_devinfo = {
222
223
.name = "basic-mmio-gpio",
223
224
.id = 1,
224
-
.resource = latch2_resources,
225
-
.num_resources = ARRAY_SIZE(latch2_resources),
226
-
.dev = {
227
-
.platform_data = &latch2_pdata,
228
-
},
225
+
.res = latch2_resources,
226
+
.num_res = ARRAY_SIZE(latch2_resources),
227
+
.properties = latch2_gpio_props,
229
228
};
230
229
231
230
#define LATCH2_PIN_LCD_VBLEN 0
···
539
542
};
540
543
541
544
static struct platform_device *ams_delta_devices[] __initdata = {
542
-
&latch1_gpio_device,
543
-
&latch2_gpio_device,
544
545
&ams_delta_kp_device,
545
546
&ams_delta_audio_device,
546
547
&ams_delta_serio_device,
···
691
696
692
697
omap1_usb_init(&ams_delta_usb_config);
693
698
platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
699
+
700
+
platform_device_register_full(&latch1_gpio_devinfo);
701
+
platform_device_register_full(&latch2_gpio_devinfo);
694
702
695
703
/*
696
704
* As soon as regulator consumers have been registered, assign their
+10
-7
arch/arm/mach-s3c/mach-crag6410.c
+10
-7
arch/arm/mach-s3c/mach-crag6410.c
···
252
252
[0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"),
253
253
};
254
254
255
-
static struct platform_device crag6410_mmgpio = {
255
+
static const struct property_entry crag6410_mmgpio_props[] = {
256
+
PROPERTY_ENTRY_U32("gpio-mmio,base", MMGPIO_GPIO_BASE),
257
+
{ }
258
+
};
259
+
260
+
static struct platform_device_info crag6410_mmgpio_devinfo = {
256
261
.name = "basic-mmio-gpio",
257
262
.id = -1,
258
-
.resource = crag6410_mmgpio_resource,
259
-
.num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
260
-
.dev.platform_data = &(struct bgpio_pdata) {
261
-
.base = MMGPIO_GPIO_BASE,
262
-
},
263
+
.res = crag6410_mmgpio_resource,
264
+
.num_res = ARRAY_SIZE(crag6410_mmgpio_resource),
265
+
.properties = crag6410_mmgpio_props,
263
266
};
264
267
265
268
static struct platform_device speyside_device = {
···
376
373
&crag6410_gpio_keydev,
377
374
&crag6410_dm9k_device,
378
375
&s3c64xx_device_spi0,
379
-
&crag6410_mmgpio,
380
376
&crag6410_lcd_powerdev,
381
377
&crag6410_backlight_device,
382
378
&speyside_device,
···
873
871
874
872
pwm_add_table(crag6410_pwm_lookup, ARRAY_SIZE(crag6410_pwm_lookup));
875
873
platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
874
+
platform_device_register_full(&crag6410_mmgpio_devinfo);
876
875
877
876
gpio_led_register_device(-1, &gpio_leds_pdata);
878
877
+1
-1
arch/arm/mach-sa1100/assabet.c
+1
-1
arch/arm/mach-sa1100/assabet.c
+1
-1
arch/arm/mach-sa1100/neponset.c
+1
-1
arch/arm/mach-sa1100/neponset.c
+8
-4
arch/mips/alchemy/common/gpiolib.c
+8
-4
arch/mips/alchemy/common/gpiolib.c
···
40
40
return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
41
41
}
42
42
43
-
static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
43
+
static int gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
44
44
{
45
45
alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
46
+
47
+
return 0;
46
48
}
47
49
48
50
static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
···
70
68
return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
71
69
}
72
70
73
-
static void gpio1_set(struct gpio_chip *chip,
71
+
static int gpio1_set(struct gpio_chip *chip,
74
72
unsigned offset, int value)
75
73
{
76
74
alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
75
+
76
+
return 0;
77
77
}
78
78
79
79
static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
···
101
97
.direction_input = gpio1_direction_input,
102
98
.direction_output = gpio1_direction_output,
103
99
.get = gpio1_get,
104
-
.set = gpio1_set,
100
+
.set_rv = gpio1_set,
105
101
.to_irq = gpio1_to_irq,
106
102
.base = ALCHEMY_GPIO1_BASE,
107
103
.ngpio = ALCHEMY_GPIO1_NUM,
···
111
107
.direction_input = gpio2_direction_input,
112
108
.direction_output = gpio2_direction_output,
113
109
.get = gpio2_get,
114
-
.set = gpio2_set,
110
+
.set_rv = gpio2_set,
115
111
.to_irq = gpio2_to_irq,
116
112
.base = ALCHEMY_GPIO2_BASE,
117
113
.ngpio = ALCHEMY_GPIO2_NUM,
+23
-1
drivers/gpio/Kconfig
+23
-1
drivers/gpio/Kconfig
···
12
12
13
13
If unsure, say N.
14
14
15
+
config GPIOLIB_LEGACY
16
+
def_bool y
17
+
15
18
if GPIOLIB
16
19
17
20
config GPIOLIB_FASTPATH_LIMIT
···
71
68
This ABI is deprecated. If you want to use GPIO from userspace,
72
69
use the character device /dev/gpiochipN with the appropriate
73
70
ioctl() operations instead.
71
+
72
+
config GPIO_SYSFS_LEGACY
73
+
bool "Enable legacy functionalities of the sysfs interface"
74
+
depends on GPIO_SYSFS
75
+
default y if GPIO_SYSFS
76
+
help
77
+
Say Y here if you want to enable the legacy, global GPIO
78
+
numberspace-based functionalities of the sysfs interface.
74
79
75
80
config GPIO_CDEV
76
81
bool "Character device (/dev/gpiochipN) support" if EXPERT
···
1274
1263
config GPIO_ADP5585
1275
1264
tristate "GPIO Support for ADP5585"
1276
1265
depends on MFD_ADP5585
1266
+
select GPIOLIB_IRQCHIP
1277
1267
help
1278
1268
This option enables support for the GPIO function found in the Analog
1279
1269
Devices ADP5585.
···
1476
1464
This driver can also be built as a module. If so, the module will be
1477
1465
called gpio-lp87565.
1478
1466
1467
+
config GPIO_MACSMC
1468
+
tristate "Apple Mac SMC GPIO"
1469
+
depends on MFD_MACSMC
1470
+
help
1471
+
Support for GPIOs controlled by the SMC microcontroller on Apple Mac
1472
+
systems.
1473
+
1474
+
This driver can also be built as a module. If so, the module will be
1475
+
called gpio-macsmc.
1476
+
1479
1477
config GPIO_MADERA
1480
1478
tristate "Cirrus Logic Madera class codecs"
1481
1479
depends on PINCTRL_MADERA
···
1523
1501
called gpio-max77759.
1524
1502
1525
1503
config GPIO_PALMAS
1526
-
bool "TI PALMAS series PMICs GPIO"
1504
+
tristate "TI PALMAS series PMICs GPIO"
1527
1505
depends on MFD_PALMAS
1528
1506
help
1529
1507
Select this option to enable GPIO driver for the TI PALMAS
+2
-1
drivers/gpio/Makefile
+2
-1
drivers/gpio/Makefile
···
5
5
6
6
obj-$(CONFIG_GPIOLIB) += gpiolib.o
7
7
obj-$(CONFIG_GPIOLIB) += gpiolib-devres.o
8
-
obj-$(CONFIG_GPIOLIB) += gpiolib-legacy.o
8
+
obj-$(CONFIG_GPIOLIB_LEGACY) += gpiolib-legacy.o
9
9
obj-$(CONFIG_OF_GPIO) += gpiolib-of.o
10
10
obj-$(CONFIG_GPIO_CDEV) += gpiolib-cdev.o
11
11
obj-$(CONFIG_GPIO_SYSFS) += gpiolib-sysfs.o
···
99
99
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
100
100
obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
101
101
obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
102
+
obj-$(CONFIG_GPIO_MACSMC) += gpio-macsmc.o
102
103
obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
103
104
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
104
105
obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
+10
-9
drivers/gpio/TODO
+10
-9
drivers/gpio/TODO
···
131
131
helpers (x86 inb()/outb()) and convert port-mapped I/O drivers to use
132
132
this with dry-coding and sending to maintainers to test
133
133
134
+
- Move the MMIO GPIO specific fields out of struct gpio_chip into a
135
+
dedicated structure. Currently every GPIO chip has them if gpio-mmio is
136
+
enabled in Kconfig even if it itself doesn't register with the helper
137
+
library.
138
+
134
139
-------------------------------------------------------------------------------
135
140
136
141
Generic regmap GPIO
···
188
183
189
184
-------------------------------------------------------------------------------
190
185
191
-
Extend the sysfs ABI to allow exporting lines by their HW offsets
186
+
Remove legacy sysfs features
192
187
193
-
The need to support the sysfs GPIO class is one of the main obstacles to
194
-
removing the global GPIO numberspace from the kernel. In order to wean users
195
-
off using global numbers from user-space, extend the existing interface with
196
-
new per-gpiochip export/unexport attributes that allow to refer to GPIOs using
197
-
their hardware offsets within the chip.
198
-
199
-
Encourage users to switch to using them and eventually remove the existing
200
-
global export/unexport attribues.
188
+
We have two parallel per-chip class devices and per-exported-line attribute
189
+
groups in sysfs. One is using the obsolete global GPIO numberspace and the
190
+
second relies on hardware offsets of pins within the chip. Remove the former
191
+
once user-space has switched to using the latter.
201
192
202
193
-------------------------------------------------------------------------------
203
194
+17
-15
drivers/gpio/gpio-74xx-mmio.c
+17
-15
drivers/gpio/gpio-74xx-mmio.c
···
8
8
#include <linux/bits.h>
9
9
#include <linux/err.h>
10
10
#include <linux/gpio/driver.h>
11
+
#include <linux/gpio/generic.h>
11
12
#include <linux/mod_devicetable.h>
12
13
#include <linux/module.h>
13
14
#include <linux/platform_device.h>
···
19
18
#define MMIO_74XX_BIT_CNT(x) ((x) & GENMASK(7, 0))
20
19
21
20
struct mmio_74xx_gpio_priv {
22
-
struct gpio_chip gc;
23
-
unsigned flags;
21
+
struct gpio_generic_chip gen_gc;
22
+
unsigned int flags;
24
23
};
25
24
26
25
static const struct of_device_id mmio_74xx_gpio_ids[] = {
···
100
99
{
101
100
struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
102
101
103
-
if (priv->flags & MMIO_74XX_DIR_OUT) {
104
-
gc->set(gc, gpio, val);
105
-
return 0;
106
-
}
102
+
if (priv->flags & MMIO_74XX_DIR_OUT)
103
+
return gpio_generic_chip_set(&priv->gen_gc, gpio, val);
107
104
108
105
return -ENOTSUPP;
109
106
}
110
107
111
108
static int mmio_74xx_gpio_probe(struct platform_device *pdev)
112
109
{
110
+
struct gpio_generic_chip_config config = { };
113
111
struct mmio_74xx_gpio_priv *priv;
114
112
void __iomem *dat;
115
113
int err;
···
123
123
if (IS_ERR(dat))
124
124
return PTR_ERR(dat);
125
125
126
-
err = bgpio_init(&priv->gc, &pdev->dev,
127
-
DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8),
128
-
dat, NULL, NULL, NULL, NULL, 0);
126
+
config.dev = &pdev->dev;
127
+
config.sz = DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8);
128
+
config.dat = dat;
129
+
130
+
err = gpio_generic_chip_init(&priv->gen_gc, &config);
129
131
if (err)
130
132
return err;
131
133
132
-
priv->gc.direction_input = mmio_74xx_dir_in;
133
-
priv->gc.direction_output = mmio_74xx_dir_out;
134
-
priv->gc.get_direction = mmio_74xx_get_direction;
135
-
priv->gc.ngpio = MMIO_74XX_BIT_CNT(priv->flags);
136
-
priv->gc.owner = THIS_MODULE;
134
+
priv->gen_gc.gc.direction_input = mmio_74xx_dir_in;
135
+
priv->gen_gc.gc.direction_output = mmio_74xx_dir_out;
136
+
priv->gen_gc.gc.get_direction = mmio_74xx_get_direction;
137
+
priv->gen_gc.gc.ngpio = MMIO_74XX_BIT_CNT(priv->flags);
138
+
priv->gen_gc.gc.owner = THIS_MODULE;
137
139
138
-
return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
140
+
return devm_gpiochip_add_data(&pdev->dev, &priv->gen_gc.gc, priv);
139
141
}
140
142
141
143
static struct platform_driver mmio_74xx_gpio_driver = {
+330
-34
drivers/gpio/gpio-adp5585.c
+330
-34
drivers/gpio/gpio-adp5585.c
···
4
4
*
5
5
* Copyright 2022 NXP
6
6
* Copyright 2024 Ideas on Board Oy
7
+
* Copyright 2025 Analog Devices, Inc.
7
8
*/
8
9
10
+
#include <linux/bitmap.h>
11
+
#include <linux/bitops.h>
12
+
#include <linux/container_of.h>
9
13
#include <linux/device.h>
10
14
#include <linux/gpio/driver.h>
11
15
#include <linux/mfd/adp5585.h>
12
16
#include <linux/module.h>
17
+
#include <linux/mutex.h>
18
+
#include <linux/notifier.h>
13
19
#include <linux/platform_device.h>
14
20
#include <linux/regmap.h>
15
21
#include <linux/types.h>
16
22
17
-
#define ADP5585_GPIO_MAX 11
23
+
/*
24
+
* Bank 0 covers pins "GPIO 1/R0" to "GPIO 6/R5", numbered 0 to 5 by the
25
+
* driver, and bank 1 covers pins "GPIO 7/C0" to "GPIO 11/C4", numbered 6 to
26
+
* 10. Some variants of the ADP5585 don't support "GPIO 6/R5". As the driver
27
+
* uses identical GPIO numbering for all variants to avoid confusion, GPIO 5 is
28
+
* marked as reserved in the device tree for variants that don't support it.
29
+
*/
30
+
#define ADP5585_BANK(n) ((n) >= 6 ? 1 : 0)
31
+
#define ADP5585_BIT(n) ((n) >= 6 ? BIT((n) - 6) : BIT(n))
32
+
33
+
/*
34
+
* Bank 0 covers pins "GPIO 1/R0" to "GPIO 8/R7", numbered 0 to 7 by the
35
+
* driver, bank 1 covers pins "GPIO 9/C0" to "GPIO 16/C7", numbered 8 to
36
+
* 15 and bank 3 covers pins "GPIO 17/C8" to "GPIO 19/C10", numbered 16 to 18.
37
+
*/
38
+
#define ADP5589_BANK(n) ((n) >> 3)
39
+
#define ADP5589_BIT(n) BIT((n) & 0x7)
40
+
41
+
struct adp5585_gpio_chip {
42
+
int (*bank)(unsigned int off);
43
+
int (*bit)(unsigned int off);
44
+
unsigned int debounce_dis_a;
45
+
unsigned int rpull_cfg_a;
46
+
unsigned int gpo_data_a;
47
+
unsigned int gpo_out_a;
48
+
unsigned int gpio_dir_a;
49
+
unsigned int gpi_stat_a;
50
+
unsigned int gpi_int_lvl_a;
51
+
unsigned int gpi_ev_a;
52
+
unsigned int gpi_ev_min;
53
+
unsigned int gpi_ev_max;
54
+
bool has_bias_hole;
55
+
};
18
56
19
57
struct adp5585_gpio_dev {
20
58
struct gpio_chip gpio_chip;
59
+
struct notifier_block nb;
60
+
const struct adp5585_gpio_chip *info;
21
61
struct regmap *regmap;
62
+
unsigned long irq_mask;
63
+
unsigned long irq_en;
64
+
unsigned long irq_active_high;
65
+
/* used for irqchip bus locking */
66
+
struct mutex bus_lock;
22
67
};
68
+
69
+
static int adp5585_gpio_bank(unsigned int off)
70
+
{
71
+
return ADP5585_BANK(off);
72
+
}
73
+
74
+
static int adp5585_gpio_bit(unsigned int off)
75
+
{
76
+
return ADP5585_BIT(off);
77
+
}
78
+
79
+
static int adp5589_gpio_bank(unsigned int off)
80
+
{
81
+
return ADP5589_BANK(off);
82
+
}
83
+
84
+
static int adp5589_gpio_bit(unsigned int off)
85
+
{
86
+
return ADP5589_BIT(off);
87
+
}
23
88
24
89
static int adp5585_gpio_get_direction(struct gpio_chip *chip, unsigned int off)
25
90
{
26
91
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip);
27
-
unsigned int bank = ADP5585_BANK(off);
28
-
unsigned int bit = ADP5585_BIT(off);
92
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
29
93
unsigned int val;
30
94
31
-
regmap_read(adp5585_gpio->regmap, ADP5585_GPIO_DIRECTION_A + bank, &val);
95
+
regmap_read(adp5585_gpio->regmap, info->gpio_dir_a + info->bank(off), &val);
32
96
33
-
return val & bit ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
97
+
return val & info->bit(off) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
34
98
}
35
99
36
100
static int adp5585_gpio_direction_input(struct gpio_chip *chip, unsigned int off)
37
101
{
38
102
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip);
39
-
unsigned int bank = ADP5585_BANK(off);
40
-
unsigned int bit = ADP5585_BIT(off);
103
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
41
104
42
-
return regmap_clear_bits(adp5585_gpio->regmap,
43
-
ADP5585_GPIO_DIRECTION_A + bank, bit);
105
+
return regmap_clear_bits(adp5585_gpio->regmap, info->gpio_dir_a + info->bank(off),
106
+
info->bit(off));
44
107
}
45
108
46
109
static int adp5585_gpio_direction_output(struct gpio_chip *chip, unsigned int off, int val)
47
110
{
48
111
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip);
49
-
unsigned int bank = ADP5585_BANK(off);
50
-
unsigned int bit = ADP5585_BIT(off);
112
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
113
+
unsigned int bank = info->bank(off);
114
+
unsigned int bit = info->bit(off);
51
115
int ret;
52
116
53
-
ret = regmap_update_bits(adp5585_gpio->regmap,
54
-
ADP5585_GPO_DATA_OUT_A + bank, bit,
55
-
val ? bit : 0);
117
+
ret = regmap_update_bits(adp5585_gpio->regmap, info->gpo_data_a + bank,
118
+
bit, val ? bit : 0);
56
119
if (ret)
57
120
return ret;
58
121
59
-
return regmap_set_bits(adp5585_gpio->regmap,
60
-
ADP5585_GPIO_DIRECTION_A + bank, bit);
122
+
return regmap_set_bits(adp5585_gpio->regmap, info->gpio_dir_a + bank,
123
+
bit);
61
124
}
62
125
63
126
static int adp5585_gpio_get_value(struct gpio_chip *chip, unsigned int off)
64
127
{
65
128
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip);
66
-
unsigned int bank = ADP5585_BANK(off);
67
-
unsigned int bit = ADP5585_BIT(off);
129
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
130
+
unsigned int bank = info->bank(off);
131
+
unsigned int bit = info->bit(off);
68
132
unsigned int reg;
69
133
unsigned int val;
70
134
···
143
79
* .direction_input(), .direction_output() or .set() operations racing
144
80
* with this.
145
81
*/
146
-
regmap_read(adp5585_gpio->regmap, ADP5585_GPIO_DIRECTION_A + bank, &val);
147
-
reg = val & bit ? ADP5585_GPO_DATA_OUT_A : ADP5585_GPI_STATUS_A;
82
+
regmap_read(adp5585_gpio->regmap, info->gpio_dir_a + bank, &val);
83
+
reg = val & bit ? info->gpo_data_a : info->gpi_stat_a;
148
84
regmap_read(adp5585_gpio->regmap, reg + bank, &val);
149
85
150
86
return !!(val & bit);
···
154
90
int val)
155
91
{
156
92
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip);
157
-
unsigned int bank = ADP5585_BANK(off);
158
-
unsigned int bit = ADP5585_BIT(off);
93
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
94
+
unsigned int bit = adp5585_gpio->info->bit(off);
159
95
160
-
return regmap_update_bits(adp5585_gpio->regmap,
161
-
ADP5585_GPO_DATA_OUT_A + bank,
96
+
return regmap_update_bits(adp5585_gpio->regmap, info->gpo_data_a + info->bank(off),
162
97
bit, val ? bit : 0);
163
98
}
164
99
165
100
static int adp5585_gpio_set_bias(struct adp5585_gpio_dev *adp5585_gpio,
166
101
unsigned int off, unsigned int bias)
167
102
{
103
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
168
104
unsigned int bit, reg, mask, val;
169
105
170
106
/*
···
172
108
* consecutive registers ADP5585_RPULL_CONFIG_*, with a hole of 4 bits
173
109
* after R5.
174
110
*/
175
-
bit = off * 2 + (off > 5 ? 4 : 0);
176
-
reg = ADP5585_RPULL_CONFIG_A + bit / 8;
111
+
bit = off * 2;
112
+
if (info->has_bias_hole)
113
+
bit += (off > 5 ? 4 : 0);
114
+
reg = info->rpull_cfg_a + bit / 8;
177
115
mask = ADP5585_Rx_PULL_CFG_MASK << (bit % 8);
178
116
val = bias << (bit % 8);
179
117
···
185
119
static int adp5585_gpio_set_drive(struct adp5585_gpio_dev *adp5585_gpio,
186
120
unsigned int off, enum pin_config_param drive)
187
121
{
188
-
unsigned int bank = ADP5585_BANK(off);
189
-
unsigned int bit = ADP5585_BIT(off);
122
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
123
+
unsigned int bit = adp5585_gpio->info->bit(off);
190
124
191
125
return regmap_update_bits(adp5585_gpio->regmap,
192
-
ADP5585_GPO_OUT_MODE_A + bank, bit,
126
+
info->gpo_out_a + info->bank(off), bit,
193
127
drive == PIN_CONFIG_DRIVE_OPEN_DRAIN ? bit : 0);
194
128
}
195
129
196
130
static int adp5585_gpio_set_debounce(struct adp5585_gpio_dev *adp5585_gpio,
197
131
unsigned int off, unsigned int debounce)
198
132
{
199
-
unsigned int bank = ADP5585_BANK(off);
200
-
unsigned int bit = ADP5585_BIT(off);
133
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
134
+
unsigned int bit = adp5585_gpio->info->bit(off);
201
135
202
136
return regmap_update_bits(adp5585_gpio->regmap,
203
-
ADP5585_DEBOUNCE_DIS_A + bank, bit,
137
+
info->debounce_dis_a + info->bank(off), bit,
204
138
debounce ? 0 : bit);
205
139
}
206
140
···
238
172
};
239
173
}
240
174
175
+
static int adp5585_gpio_request(struct gpio_chip *chip, unsigned int off)
176
+
{
177
+
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip);
178
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
179
+
struct device *dev = chip->parent;
180
+
struct adp5585_dev *adp5585 = dev_get_drvdata(dev->parent);
181
+
const struct adp5585_regs *regs = adp5585->regs;
182
+
int ret;
183
+
184
+
ret = test_and_set_bit(off, adp5585->pin_usage);
185
+
if (ret)
186
+
return -EBUSY;
187
+
188
+
/* make sure it's configured for GPIO */
189
+
return regmap_clear_bits(adp5585_gpio->regmap,
190
+
regs->pin_cfg_a + info->bank(off),
191
+
info->bit(off));
192
+
}
193
+
194
+
static void adp5585_gpio_free(struct gpio_chip *chip, unsigned int off)
195
+
{
196
+
struct device *dev = chip->parent;
197
+
struct adp5585_dev *adp5585 = dev_get_drvdata(dev->parent);
198
+
199
+
clear_bit(off, adp5585->pin_usage);
200
+
}
201
+
202
+
static int adp5585_gpio_key_event(struct notifier_block *nb, unsigned long key,
203
+
void *data)
204
+
{
205
+
struct adp5585_gpio_dev *adp5585_gpio = container_of(nb, struct adp5585_gpio_dev, nb);
206
+
struct device *dev = adp5585_gpio->gpio_chip.parent;
207
+
unsigned long key_press = (unsigned long)data;
208
+
unsigned int irq, irq_type;
209
+
struct irq_data *irqd;
210
+
bool active_high;
211
+
unsigned int off;
212
+
213
+
/* make sure the event is for me */
214
+
if (key < adp5585_gpio->info->gpi_ev_min || key > adp5585_gpio->info->gpi_ev_max)
215
+
return NOTIFY_DONE;
216
+
217
+
off = key - adp5585_gpio->info->gpi_ev_min;
218
+
active_high = test_bit(off, &adp5585_gpio->irq_active_high);
219
+
220
+
irq = irq_find_mapping(adp5585_gpio->gpio_chip.irq.domain, off);
221
+
if (!irq)
222
+
return NOTIFY_BAD;
223
+
224
+
irqd = irq_get_irq_data(irq);
225
+
if (!irqd) {
226
+
dev_err(dev, "Could not get irq(%u) data\n", irq);
227
+
return NOTIFY_BAD;
228
+
}
229
+
230
+
dev_dbg_ratelimited(dev, "gpio-keys event(%u) press=%lu, a_high=%u\n",
231
+
off, key_press, active_high);
232
+
233
+
if (!active_high)
234
+
key_press = !key_press;
235
+
236
+
irq_type = irqd_get_trigger_type(irqd);
237
+
238
+
if ((irq_type & IRQ_TYPE_EDGE_RISING && key_press) ||
239
+
(irq_type & IRQ_TYPE_EDGE_FALLING && !key_press))
240
+
handle_nested_irq(irq);
241
+
242
+
return NOTIFY_STOP;
243
+
}
244
+
245
+
static void adp5585_irq_bus_lock(struct irq_data *d)
246
+
{
247
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
248
+
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(gc);
249
+
250
+
mutex_lock(&adp5585_gpio->bus_lock);
251
+
}
252
+
253
+
static void adp5585_irq_bus_sync_unlock(struct irq_data *d)
254
+
{
255
+
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
256
+
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(chip);
257
+
const struct adp5585_gpio_chip *info = adp5585_gpio->info;
258
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
259
+
bool active_high = test_bit(hwirq, &adp5585_gpio->irq_active_high);
260
+
bool enabled = test_bit(hwirq, &adp5585_gpio->irq_en);
261
+
bool masked = test_bit(hwirq, &adp5585_gpio->irq_mask);
262
+
unsigned int bank = adp5585_gpio->info->bank(hwirq);
263
+
unsigned int bit = adp5585_gpio->info->bit(hwirq);
264
+
265
+
if (masked && !enabled)
266
+
goto out_unlock;
267
+
if (!masked && enabled)
268
+
goto out_unlock;
269
+
270
+
regmap_update_bits(adp5585_gpio->regmap, info->gpi_int_lvl_a + bank, bit,
271
+
active_high ? bit : 0);
272
+
regmap_update_bits(adp5585_gpio->regmap, info->gpi_ev_a + bank, bit,
273
+
masked ? 0 : bit);
274
+
assign_bit(hwirq, &adp5585_gpio->irq_en, !masked);
275
+
276
+
out_unlock:
277
+
mutex_unlock(&adp5585_gpio->bus_lock);
278
+
}
279
+
280
+
static void adp5585_irq_mask(struct irq_data *d)
281
+
{
282
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
283
+
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(gc);
284
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
285
+
286
+
__set_bit(hwirq, &adp5585_gpio->irq_mask);
287
+
gpiochip_disable_irq(gc, hwirq);
288
+
}
289
+
290
+
static void adp5585_irq_unmask(struct irq_data *d)
291
+
{
292
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
293
+
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(gc);
294
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
295
+
296
+
gpiochip_enable_irq(gc, hwirq);
297
+
__clear_bit(hwirq, &adp5585_gpio->irq_mask);
298
+
}
299
+
300
+
static int adp5585_irq_set_type(struct irq_data *d, unsigned int type)
301
+
{
302
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
303
+
struct adp5585_gpio_dev *adp5585_gpio = gpiochip_get_data(gc);
304
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
305
+
306
+
if (!(type & IRQ_TYPE_EDGE_BOTH))
307
+
return -EINVAL;
308
+
309
+
assign_bit(hwirq, &adp5585_gpio->irq_active_high,
310
+
type == IRQ_TYPE_EDGE_RISING);
311
+
312
+
irq_set_handler_locked(d, handle_edge_irq);
313
+
return 0;
314
+
}
315
+
316
+
static const struct irq_chip adp5585_irq_chip = {
317
+
.name = "adp5585",
318
+
.irq_mask = adp5585_irq_mask,
319
+
.irq_unmask = adp5585_irq_unmask,
320
+
.irq_bus_lock = adp5585_irq_bus_lock,
321
+
.irq_bus_sync_unlock = adp5585_irq_bus_sync_unlock,
322
+
.irq_set_type = adp5585_irq_set_type,
323
+
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
324
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
325
+
};
326
+
327
+
static void adp5585_gpio_unreg_notifier(void *data)
328
+
{
329
+
struct adp5585_gpio_dev *adp5585_gpio = data;
330
+
struct device *dev = adp5585_gpio->gpio_chip.parent;
331
+
struct adp5585_dev *adp5585 = dev_get_drvdata(dev->parent);
332
+
333
+
blocking_notifier_chain_unregister(&adp5585->event_notifier,
334
+
&adp5585_gpio->nb);
335
+
}
336
+
241
337
static int adp5585_gpio_probe(struct platform_device *pdev)
242
338
{
243
339
struct adp5585_dev *adp5585 = dev_get_drvdata(pdev->dev.parent);
340
+
const struct platform_device_id *id = platform_get_device_id(pdev);
244
341
struct adp5585_gpio_dev *adp5585_gpio;
245
342
struct device *dev = &pdev->dev;
343
+
struct gpio_irq_chip *girq;
246
344
struct gpio_chip *gc;
247
345
int ret;
248
346
···
415
185
return -ENOMEM;
416
186
417
187
adp5585_gpio->regmap = adp5585->regmap;
188
+
189
+
adp5585_gpio->info = (const struct adp5585_gpio_chip *)id->driver_data;
190
+
if (!adp5585_gpio->info)
191
+
return -ENODEV;
418
192
419
193
device_set_of_node_from_dev(dev, dev->parent);
420
194
···
430
196
gc->get = adp5585_gpio_get_value;
431
197
gc->set_rv = adp5585_gpio_set_value;
432
198
gc->set_config = adp5585_gpio_set_config;
199
+
gc->request = adp5585_gpio_request;
200
+
gc->free = adp5585_gpio_free;
433
201
gc->can_sleep = true;
434
202
435
203
gc->base = -1;
436
-
gc->ngpio = ADP5585_GPIO_MAX;
204
+
gc->ngpio = adp5585->n_pins;
437
205
gc->label = pdev->name;
438
206
gc->owner = THIS_MODULE;
439
207
208
+
if (device_property_present(dev->parent, "interrupt-controller")) {
209
+
if (!adp5585->irq)
210
+
return dev_err_probe(dev, -EINVAL,
211
+
"Unable to serve as interrupt controller without IRQ\n");
212
+
213
+
girq = &adp5585_gpio->gpio_chip.irq;
214
+
gpio_irq_chip_set_chip(girq, &adp5585_irq_chip);
215
+
girq->handler = handle_bad_irq;
216
+
girq->threaded = true;
217
+
218
+
adp5585_gpio->nb.notifier_call = adp5585_gpio_key_event;
219
+
ret = blocking_notifier_chain_register(&adp5585->event_notifier,
220
+
&adp5585_gpio->nb);
221
+
if (ret)
222
+
return ret;
223
+
224
+
ret = devm_add_action_or_reset(dev, adp5585_gpio_unreg_notifier,
225
+
adp5585_gpio);
226
+
if (ret)
227
+
return ret;
228
+
}
229
+
230
+
/* everything masked by default */
231
+
adp5585_gpio->irq_mask = ~0UL;
232
+
233
+
ret = devm_mutex_init(dev, &adp5585_gpio->bus_lock);
234
+
if (ret)
235
+
return ret;
440
236
ret = devm_gpiochip_add_data(dev, &adp5585_gpio->gpio_chip,
441
237
adp5585_gpio);
442
238
if (ret)
···
475
211
return 0;
476
212
}
477
213
214
+
static const struct adp5585_gpio_chip adp5585_gpio_chip_info = {
215
+
.bank = adp5585_gpio_bank,
216
+
.bit = adp5585_gpio_bit,
217
+
.debounce_dis_a = ADP5585_DEBOUNCE_DIS_A,
218
+
.rpull_cfg_a = ADP5585_RPULL_CONFIG_A,
219
+
.gpo_data_a = ADP5585_GPO_DATA_OUT_A,
220
+
.gpo_out_a = ADP5585_GPO_OUT_MODE_A,
221
+
.gpio_dir_a = ADP5585_GPIO_DIRECTION_A,
222
+
.gpi_stat_a = ADP5585_GPI_STATUS_A,
223
+
.has_bias_hole = true,
224
+
.gpi_ev_min = ADP5585_GPI_EVENT_START,
225
+
.gpi_ev_max = ADP5585_GPI_EVENT_END,
226
+
.gpi_int_lvl_a = ADP5585_GPI_INT_LEVEL_A,
227
+
.gpi_ev_a = ADP5585_GPI_EVENT_EN_A,
228
+
};
229
+
230
+
static const struct adp5585_gpio_chip adp5589_gpio_chip_info = {
231
+
.bank = adp5589_gpio_bank,
232
+
.bit = adp5589_gpio_bit,
233
+
.debounce_dis_a = ADP5589_DEBOUNCE_DIS_A,
234
+
.rpull_cfg_a = ADP5589_RPULL_CONFIG_A,
235
+
.gpo_data_a = ADP5589_GPO_DATA_OUT_A,
236
+
.gpo_out_a = ADP5589_GPO_OUT_MODE_A,
237
+
.gpio_dir_a = ADP5589_GPIO_DIRECTION_A,
238
+
.gpi_stat_a = ADP5589_GPI_STATUS_A,
239
+
.gpi_ev_min = ADP5589_GPI_EVENT_START,
240
+
.gpi_ev_max = ADP5589_GPI_EVENT_END,
241
+
.gpi_int_lvl_a = ADP5589_GPI_INT_LEVEL_A,
242
+
.gpi_ev_a = ADP5589_GPI_EVENT_EN_A,
243
+
};
244
+
478
245
static const struct platform_device_id adp5585_gpio_id_table[] = {
479
-
{ "adp5585-gpio" },
246
+
{ "adp5585-gpio", (kernel_ulong_t)&adp5585_gpio_chip_info },
247
+
{ "adp5589-gpio", (kernel_ulong_t)&adp5589_gpio_chip_info },
480
248
{ /* Sentinel */ }
481
249
};
482
250
MODULE_DEVICE_TABLE(platform, adp5585_gpio_id_table);
-2
drivers/gpio/gpio-arizona.c
-2
drivers/gpio/gpio-arizona.c
···
39
39
return ret;
40
40
41
41
if (change && persistent) {
42
-
pm_runtime_mark_last_busy(chip->parent);
43
42
pm_runtime_put_autosuspend(chip->parent);
44
43
}
45
44
···
81
82
return ret;
82
83
}
83
84
84
-
pm_runtime_mark_last_busy(chip->parent);
85
85
pm_runtime_put_autosuspend(chip->parent);
86
86
}
87
87
+2
-4
drivers/gpio/gpio-brcmstb.c
+2
-4
drivers/gpio/gpio-brcmstb.c
···
436
436
struct device_node *np = dev->of_node;
437
437
int err;
438
438
439
-
priv->irq_domain =
440
-
irq_domain_create_linear(of_fwnode_handle(np), priv->num_gpios,
441
-
&brcmstb_gpio_irq_domain_ops,
442
-
priv);
439
+
priv->irq_domain = irq_domain_create_linear(dev_fwnode(dev), priv->num_gpios,
440
+
&brcmstb_gpio_irq_domain_ops, priv);
443
441
if (!priv->irq_domain) {
444
442
dev_err(dev, "Couldn't allocate IRQ domain\n");
445
443
return -ENXIO;
+27
-32
drivers/gpio/gpio-cadence.c
+27
-32
drivers/gpio/gpio-cadence.c
···
8
8
* Boris Brezillon <boris.brezillon@free-electrons.com>
9
9
*/
10
10
11
-
#include <linux/gpio/driver.h>
11
+
#include <linux/cleanup.h>
12
12
#include <linux/clk.h>
13
+
#include <linux/gpio/driver.h>
13
14
#include <linux/interrupt.h>
15
+
#include <linux/gpio/generic.h>
14
16
#include <linux/kernel.h>
15
17
#include <linux/module.h>
16
18
#include <linux/platform_device.h>
···
32
30
#define CDNS_GPIO_IRQ_ANY_EDGE 0x2c
33
31
34
32
struct cdns_gpio_chip {
35
-
struct gpio_chip gc;
33
+
struct gpio_generic_chip gen_gc;
36
34
void __iomem *regs;
37
35
u32 bypass_orig;
38
36
};
···
40
38
static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset)
41
39
{
42
40
struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
43
-
unsigned long flags;
44
41
45
-
raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
42
+
guard(gpio_generic_lock)(&cgpio->gen_gc);
46
43
47
44
iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),
48
45
cgpio->regs + CDNS_GPIO_BYPASS_MODE);
49
46
50
-
raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
51
47
return 0;
52
48
}
53
49
54
50
static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset)
55
51
{
56
52
struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
57
-
unsigned long flags;
58
53
59
-
raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
54
+
guard(gpio_generic_lock)(&cgpio->gen_gc);
60
55
61
56
iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |
62
57
(BIT(offset) & cgpio->bypass_orig),
63
58
cgpio->regs + CDNS_GPIO_BYPASS_MODE);
64
-
65
-
raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
66
59
}
67
60
68
61
static void cdns_gpio_irq_mask(struct irq_data *d)
···
82
85
{
83
86
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
84
87
struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
85
-
unsigned long flags;
86
88
u32 int_value;
87
89
u32 int_type;
88
90
u32 mask = BIT(d->hwirq);
89
91
int ret = 0;
90
92
91
-
raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
93
+
guard(gpio_generic_lock)(&cgpio->gen_gc);
92
94
93
95
int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
94
96
int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
···
104
108
} else if (type == IRQ_TYPE_LEVEL_LOW) {
105
109
int_type |= mask;
106
110
} else {
107
-
ret = -EINVAL;
108
-
goto err_irq_type;
111
+
return -EINVAL;
109
112
}
110
113
111
114
iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE);
112
115
iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
113
116
114
-
err_irq_type:
115
-
raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
116
117
return ret;
117
118
}
118
119
···
143
150
144
151
static int cdns_gpio_probe(struct platform_device *pdev)
145
152
{
153
+
struct gpio_generic_chip_config config = { };
146
154
struct cdns_gpio_chip *cgpio;
147
155
int ret, irq;
148
156
u32 dir_prev;
···
170
176
* gpiochip_lock_as_irq:
171
177
* tried to flag a GPIO set as output for IRQ
172
178
* Generic GPIO driver stores the direction value internally,
173
-
* so it needs to be changed before bgpio_init() is called.
179
+
* so it needs to be changed before gpio_generic_chip_init() is called.
174
180
*/
175
181
dir_prev = ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
176
182
iowrite32(GENMASK(num_gpios - 1, 0),
177
183
cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
178
184
179
-
ret = bgpio_init(&cgpio->gc, &pdev->dev, 4,
180
-
cgpio->regs + CDNS_GPIO_INPUT_VALUE,
181
-
cgpio->regs + CDNS_GPIO_OUTPUT_VALUE,
182
-
NULL,
183
-
NULL,
184
-
cgpio->regs + CDNS_GPIO_DIRECTION_MODE,
185
-
BGPIOF_READ_OUTPUT_REG_SET);
185
+
config.dev = &pdev->dev;
186
+
config.sz = 4;
187
+
config.dat = cgpio->regs + CDNS_GPIO_INPUT_VALUE;
188
+
config.set = cgpio->regs + CDNS_GPIO_OUTPUT_VALUE;
189
+
config.dirin = cgpio->regs + CDNS_GPIO_DIRECTION_MODE;
190
+
config.flags = BGPIOF_READ_OUTPUT_REG_SET;
191
+
192
+
ret = gpio_generic_chip_init(&cgpio->gen_gc, &config);
186
193
if (ret) {
187
194
dev_err(&pdev->dev, "Failed to register generic gpio, %d\n",
188
195
ret);
189
196
goto err_revert_dir;
190
197
}
191
198
192
-
cgpio->gc.label = dev_name(&pdev->dev);
193
-
cgpio->gc.ngpio = num_gpios;
194
-
cgpio->gc.parent = &pdev->dev;
195
-
cgpio->gc.base = -1;
196
-
cgpio->gc.owner = THIS_MODULE;
197
-
cgpio->gc.request = cdns_gpio_request;
198
-
cgpio->gc.free = cdns_gpio_free;
199
+
cgpio->gen_gc.gc.label = dev_name(&pdev->dev);
200
+
cgpio->gen_gc.gc.ngpio = num_gpios;
201
+
cgpio->gen_gc.gc.parent = &pdev->dev;
202
+
cgpio->gen_gc.gc.base = -1;
203
+
cgpio->gen_gc.gc.owner = THIS_MODULE;
204
+
cgpio->gen_gc.gc.request = cdns_gpio_request;
205
+
cgpio->gen_gc.gc.free = cdns_gpio_free;
199
206
200
207
clk = devm_clk_get_enabled(&pdev->dev, NULL);
201
208
if (IS_ERR(clk)) {
···
213
218
if (irq >= 0) {
214
219
struct gpio_irq_chip *girq;
215
220
216
-
girq = &cgpio->gc.irq;
221
+
girq = &cgpio->gen_gc.gc.irq;
217
222
gpio_irq_chip_set_chip(girq, &cdns_gpio_irqchip);
218
223
girq->parent_handler = cdns_gpio_irq_handler;
219
224
girq->num_parents = 1;
···
229
234
girq->handler = handle_level_irq;
230
235
}
231
236
232
-
ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
237
+
ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gen_gc.gc, cgpio);
233
238
if (ret < 0) {
234
239
dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
235
240
goto err_revert_dir;
+16
-12
drivers/gpio/gpio-clps711x.c
+16
-12
drivers/gpio/gpio-clps711x.c
···
8
8
#include <linux/err.h>
9
9
#include <linux/module.h>
10
10
#include <linux/gpio/driver.h>
11
+
#include <linux/gpio/generic.h>
11
12
#include <linux/platform_device.h>
12
13
13
14
static int clps711x_gpio_probe(struct platform_device *pdev)
14
15
{
16
+
struct gpio_generic_chip_config config = { };
15
17
struct device_node *np = pdev->dev.of_node;
18
+
struct gpio_generic_chip *gen_gc;
16
19
void __iomem *dat, *dir;
17
-
struct gpio_chip *gc;
18
20
int err, id;
19
21
20
22
if (!np)
···
26
24
if ((id < 0) || (id > 4))
27
25
return -ENODEV;
28
26
29
-
gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
30
-
if (!gc)
27
+
gen_gc = devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL);
28
+
if (!gen_gc)
31
29
return -ENOMEM;
32
30
33
31
dat = devm_platform_ioremap_resource(pdev, 0);
···
38
36
if (IS_ERR(dir))
39
37
return PTR_ERR(dir);
40
38
39
+
config.dev = &pdev->dev;
40
+
config.sz = 1;
41
+
config.dat = dat;
42
+
41
43
switch (id) {
42
44
case 3:
43
45
/* PORTD is inverted logic for direction register */
44
-
err = bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL,
45
-
NULL, dir, 0);
46
+
config.dirin = dir;
46
47
break;
47
48
default:
48
-
err = bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL,
49
-
dir, NULL, 0);
49
+
config.dirout = dir;
50
50
break;
51
51
}
52
52
53
+
err = gpio_generic_chip_init(gen_gc, &config);
53
54
if (err)
54
55
return err;
55
56
56
57
switch (id) {
57
58
case 4:
58
59
/* PORTE is 3 lines only */
59
-
gc->ngpio = 3;
60
+
gen_gc->gc.ngpio = 3;
60
61
break;
61
62
default:
62
63
break;
63
64
}
64
65
65
-
gc->base = -1;
66
-
gc->owner = THIS_MODULE;
67
-
platform_set_drvdata(pdev, gc);
66
+
gen_gc->gc.base = -1;
67
+
gen_gc->gc.owner = THIS_MODULE;
68
68
69
-
return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
69
+
return devm_gpiochip_add_data(&pdev->dev, &gen_gc->gc, NULL);
70
70
}
71
71
72
72
static const struct of_device_id clps711x_gpio_ids[] = {
+1
-1
drivers/gpio/gpio-davinci.c
+1
-1
drivers/gpio/gpio-davinci.c
···
478
478
return irq;
479
479
}
480
480
481
-
irq_domain = irq_domain_create_legacy(of_fwnode_handle(dev->of_node), ngpio, irq, 0,
481
+
irq_domain = irq_domain_create_legacy(dev_fwnode(dev), ngpio, irq, 0,
482
482
&davinci_gpio_irq_ops, chips);
483
483
if (!irq_domain) {
484
484
dev_err(dev, "Couldn't register an IRQ domain\n");
+1
-2
drivers/gpio/gpio-em.c
+1
-2
drivers/gpio/gpio-em.c
···
325
325
irq_chip->irq_release_resources = em_gio_irq_relres;
326
326
irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
327
327
328
-
p->irq_domain = irq_domain_create_simple(of_fwnode_handle(dev->of_node),
329
-
ngpios, 0,
328
+
p->irq_domain = irq_domain_create_simple(dev_fwnode(dev), ngpios, 0,
330
329
&em_gio_irq_domain_ops, p);
331
330
if (!p->irq_domain) {
332
331
dev_err(dev, "cannot initialize irq domain\n");
+18
-18
drivers/gpio/gpio-en7523.c
+18
-18
drivers/gpio/gpio-en7523.c
···
4
4
#include <linux/io.h>
5
5
#include <linux/bits.h>
6
6
#include <linux/gpio/driver.h>
7
+
#include <linux/gpio/generic.h>
7
8
#include <linux/mod_devicetable.h>
8
9
#include <linux/module.h>
9
10
#include <linux/platform_device.h>
···
14
13
15
14
/**
16
15
* struct airoha_gpio_ctrl - Airoha GPIO driver data
17
-
* @gc: Associated gpio_chip instance.
16
+
* @gen_gc: Associated gpio_generic_chip instance.
18
17
* @data: The data register.
19
18
* @dir: [0] The direction register for the lower 16 pins.
20
19
* [1]: The direction register for the higher 16 pins.
21
20
* @output: The output enable register.
22
21
*/
23
22
struct airoha_gpio_ctrl {
24
-
struct gpio_chip gc;
23
+
struct gpio_generic_chip gen_gc;
25
24
void __iomem *data;
26
25
void __iomem *dir[2];
27
26
void __iomem *output;
28
27
};
29
28
30
-
static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
31
-
{
32
-
return container_of(gc, struct airoha_gpio_ctrl, gc);
33
-
}
34
-
35
29
static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
36
30
int val, int out)
37
31
{
38
-
struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
32
+
struct airoha_gpio_ctrl *ctrl = gpiochip_get_data(gc);
39
33
u32 dir = ioread32(ctrl->dir[gpio / 16]);
40
34
u32 output = ioread32(ctrl->output);
41
35
u32 mask = BIT((gpio % 16) * 2);
···
46
50
iowrite32(dir, ctrl->dir[gpio / 16]);
47
51
48
52
if (out)
49
-
gc->set(gc, gpio, val);
53
+
gpio_generic_chip_set(&ctrl->gen_gc, gpio, val);
50
54
51
55
iowrite32(output, ctrl->output);
52
56
···
66
70
67
71
static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
68
72
{
69
-
struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
73
+
struct airoha_gpio_ctrl *ctrl = gpiochip_get_data(gc);
70
74
u32 dir = ioread32(ctrl->dir[gpio / 16]);
71
75
u32 mask = BIT((gpio % 16) * 2);
72
76
···
75
79
76
80
static int airoha_gpio_probe(struct platform_device *pdev)
77
81
{
82
+
struct gpio_generic_chip_config config = { };
78
83
struct device *dev = &pdev->dev;
79
84
struct airoha_gpio_ctrl *ctrl;
80
85
int err;
···
100
103
if (IS_ERR(ctrl->output))
101
104
return PTR_ERR(ctrl->output);
102
105
103
-
err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
104
-
NULL, NULL, NULL, 0);
106
+
config.dev = dev;
107
+
config.sz = 4;
108
+
config.dat = ctrl->data;
109
+
110
+
err = gpio_generic_chip_init(&ctrl->gen_gc, &config);
105
111
if (err)
106
112
return dev_err_probe(dev, err, "unable to init generic GPIO");
107
113
108
-
ctrl->gc.ngpio = AIROHA_GPIO_MAX;
109
-
ctrl->gc.owner = THIS_MODULE;
110
-
ctrl->gc.direction_output = airoha_dir_out;
111
-
ctrl->gc.direction_input = airoha_dir_in;
112
-
ctrl->gc.get_direction = airoha_get_dir;
114
+
ctrl->gen_gc.gc.ngpio = AIROHA_GPIO_MAX;
115
+
ctrl->gen_gc.gc.owner = THIS_MODULE;
116
+
ctrl->gen_gc.gc.direction_output = airoha_dir_out;
117
+
ctrl->gen_gc.gc.direction_input = airoha_dir_in;
118
+
ctrl->gen_gc.gc.get_direction = airoha_get_dir;
113
119
114
-
return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
120
+
return devm_gpiochip_add_data(dev, &ctrl->gen_gc.gc, ctrl);
115
121
}
116
122
117
123
static const struct of_device_id airoha_gpio_of_match[] = {
+2
-3
drivers/gpio/gpio-grgpio.c
+2
-3
drivers/gpio/gpio-grgpio.c
···
402
402
return -EINVAL;
403
403
}
404
404
405
-
priv->domain = irq_domain_create_linear(of_fwnode_handle(np), gc->ngpio,
406
-
&grgpio_irq_domain_ops,
407
-
priv);
405
+
priv->domain = irq_domain_create_linear(dev_fwnode(&ofdev->dev), gc->ngpio,
406
+
&grgpio_irq_domain_ops, priv);
408
407
if (!priv->domain) {
409
408
dev_err(dev, "Could not add irq domain\n");
410
409
return -EINVAL;
+6
drivers/gpio/gpio-loongson-64bit.c
+6
drivers/gpio/gpio-loongson-64bit.c
···
222
222
.conf_offset = 0x0,
223
223
.in_offset = 0xc,
224
224
.out_offset = 0x8,
225
+
.inten_offset = 0x14,
225
226
};
226
227
227
228
static const struct loongson_gpio_chip_data loongson_gpio_ls2k2000_data1 = {
···
231
230
.conf_offset = 0x0,
232
231
.in_offset = 0x20,
233
232
.out_offset = 0x10,
233
+
.inten_offset = 0x30,
234
234
};
235
235
236
236
static const struct loongson_gpio_chip_data loongson_gpio_ls2k2000_data2 = {
···
248
246
.conf_offset = 0x0,
249
247
.in_offset = 0xc,
250
248
.out_offset = 0x8,
249
+
.inten_offset = 0x14,
251
250
};
252
251
253
252
static const struct loongson_gpio_chip_data loongson_gpio_ls7a_data = {
···
257
254
.conf_offset = 0x800,
258
255
.in_offset = 0xa00,
259
256
.out_offset = 0x900,
257
+
.inten_offset = 0xb00,
260
258
};
261
259
262
260
/* LS7A2000 chipset GPIO */
···
267
263
.conf_offset = 0x800,
268
264
.in_offset = 0xa00,
269
265
.out_offset = 0x900,
266
+
.inten_offset = 0xb00,
270
267
};
271
268
272
269
/* LS7A2000 ACPI GPIO */
···
286
281
.conf_offset = 0x0,
287
282
.in_offset = 0xc,
288
283
.out_offset = 0x8,
284
+
.inten_offset = 0x14,
289
285
};
290
286
291
287
static const struct of_device_id loongson_gpio_of_match[] = {
+2
-2
drivers/gpio/gpio-lpc18xx.c
+2
-2
drivers/gpio/gpio-lpc18xx.c
···
249
249
raw_spin_lock_init(&ic->lock);
250
250
251
251
ic->domain = irq_domain_create_hierarchy(parent_domain, 0, NR_LPC18XX_GPIO_PIN_IC_IRQS,
252
-
of_fwnode_handle(dev->of_node),
253
-
&lpc18xx_gpio_pin_ic_domain_ops, ic);
252
+
dev_fwnode(dev), &lpc18xx_gpio_pin_ic_domain_ops,
253
+
ic);
254
254
if (!ic->domain) {
255
255
pr_err("unable to add irq domain\n");
256
256
ret = -ENODEV;
+292
drivers/gpio/gpio-macsmc.c
+292
drivers/gpio/gpio-macsmc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only OR MIT
2
+
/*
3
+
* Apple SMC GPIO driver
4
+
* Copyright The Asahi Linux Contributors
5
+
*
6
+
* This driver implements basic SMC PMU GPIO support that can read inputs
7
+
* and write outputs. Mode changes and IRQ config are not yet implemented.
8
+
*/
9
+
10
+
#include <linux/bitmap.h>
11
+
#include <linux/device.h>
12
+
#include <linux/gpio/driver.h>
13
+
#include <linux/mfd/core.h>
14
+
#include <linux/mfd/macsmc.h>
15
+
16
+
#define MAX_GPIO 64
17
+
18
+
/*
19
+
* Commands 0-6 are, presumably, the intended API.
20
+
* Command 0xff lets you get/set the pin configuration in detail directly,
21
+
* but the bit meanings seem not to be stable between devices/PMU hardware
22
+
* versions.
23
+
*
24
+
* We're going to try to make do with the low commands for now.
25
+
* We don't implement pin mode changes at this time.
26
+
*/
27
+
28
+
#define CMD_ACTION (0 << 24)
29
+
#define CMD_OUTPUT (1 << 24)
30
+
#define CMD_INPUT (2 << 24)
31
+
#define CMD_PINMODE (3 << 24)
32
+
#define CMD_IRQ_ENABLE (4 << 24)
33
+
#define CMD_IRQ_ACK (5 << 24)
34
+
#define CMD_IRQ_MODE (6 << 24)
35
+
#define CMD_CONFIG (0xff << 24)
36
+
37
+
#define MODE_INPUT 0
38
+
#define MODE_OUTPUT 1
39
+
#define MODE_VALUE_0 0
40
+
#define MODE_VALUE_1 2
41
+
42
+
#define IRQ_MODE_HIGH 0
43
+
#define IRQ_MODE_LOW 1
44
+
#define IRQ_MODE_RISING 2
45
+
#define IRQ_MODE_FALLING 3
46
+
#define IRQ_MODE_BOTH 4
47
+
48
+
#define CONFIG_MASK GENMASK(23, 16)
49
+
#define CONFIG_VAL GENMASK(7, 0)
50
+
51
+
#define CONFIG_OUTMODE GENMASK(7, 6)
52
+
#define CONFIG_IRQMODE GENMASK(5, 3)
53
+
#define CONFIG_PULLDOWN BIT(2)
54
+
#define CONFIG_PULLUP BIT(1)
55
+
#define CONFIG_OUTVAL BIT(0)
56
+
57
+
/*
58
+
* Output modes seem to differ depending on the PMU in use... ?
59
+
* j274 / M1 (Sera PMU):
60
+
* 0 = input
61
+
* 1 = output
62
+
* 2 = open drain
63
+
* 3 = disable
64
+
* j314 / M1Pro (Maverick PMU):
65
+
* 0 = input
66
+
* 1 = open drain
67
+
* 2 = output
68
+
* 3 = ?
69
+
*/
70
+
71
+
struct macsmc_gpio {
72
+
struct device *dev;
73
+
struct apple_smc *smc;
74
+
struct gpio_chip gc;
75
+
76
+
int first_index;
77
+
};
78
+
79
+
static int macsmc_gpio_nr(smc_key key)
80
+
{
81
+
int low = hex_to_bin(key & 0xff);
82
+
int high = hex_to_bin((key >> 8) & 0xff);
83
+
84
+
if (low < 0 || high < 0)
85
+
return -1;
86
+
87
+
return low | (high << 4);
88
+
}
89
+
90
+
static int macsmc_gpio_key(unsigned int offset)
91
+
{
92
+
return _SMC_KEY("gP\0\0") | hex_asc_hi(offset) << 8 | hex_asc_lo(offset);
93
+
}
94
+
95
+
static int macsmc_gpio_find_first_gpio_index(struct macsmc_gpio *smcgp)
96
+
{
97
+
struct apple_smc *smc = smcgp->smc;
98
+
smc_key key = macsmc_gpio_key(0);
99
+
smc_key first_key, last_key;
100
+
int start, count, ret;
101
+
102
+
/* Return early if the key is out of bounds */
103
+
ret = apple_smc_get_key_by_index(smc, 0, &first_key);
104
+
if (ret)
105
+
return ret;
106
+
if (key <= first_key)
107
+
return -ENODEV;
108
+
109
+
ret = apple_smc_get_key_by_index(smc, smc->key_count - 1, &last_key);
110
+
if (ret)
111
+
return ret;
112
+
if (key > last_key)
113
+
return -ENODEV;
114
+
115
+
/* Binary search to find index of first SMC key bigger or equal to key */
116
+
start = 0;
117
+
count = smc->key_count;
118
+
while (count > 1) {
119
+
smc_key pkey;
120
+
int pivot = start + ((count - 1) >> 1);
121
+
122
+
ret = apple_smc_get_key_by_index(smc, pivot, &pkey);
123
+
if (ret < 0)
124
+
return ret;
125
+
126
+
if (pkey == key)
127
+
return pivot;
128
+
129
+
pivot++;
130
+
131
+
if (pkey < key) {
132
+
count -= pivot - start;
133
+
start = pivot;
134
+
} else {
135
+
count = pivot - start;
136
+
}
137
+
}
138
+
139
+
return start;
140
+
}
141
+
142
+
static int macsmc_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
143
+
{
144
+
struct macsmc_gpio *smcgp = gpiochip_get_data(gc);
145
+
smc_key key = macsmc_gpio_key(offset);
146
+
u32 val;
147
+
int ret;
148
+
149
+
/* First try reading the explicit pin mode register */
150
+
ret = apple_smc_rw_u32(smcgp->smc, key, CMD_PINMODE, &val);
151
+
if (!ret)
152
+
return (val & MODE_OUTPUT) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
153
+
154
+
/*
155
+
* Less common IRQ configs cause CMD_PINMODE to fail, and so does open drain mode.
156
+
* Fall back to reading IRQ mode, which will only succeed for inputs.
157
+
*/
158
+
ret = apple_smc_rw_u32(smcgp->smc, key, CMD_IRQ_MODE, &val);
159
+
return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
160
+
}
161
+
162
+
static int macsmc_gpio_get(struct gpio_chip *gc, unsigned int offset)
163
+
{
164
+
struct macsmc_gpio *smcgp = gpiochip_get_data(gc);
165
+
smc_key key = macsmc_gpio_key(offset);
166
+
u32 cmd, val;
167
+
int ret;
168
+
169
+
ret = macsmc_gpio_get_direction(gc, offset);
170
+
if (ret < 0)
171
+
return ret;
172
+
173
+
if (ret == GPIO_LINE_DIRECTION_OUT)
174
+
cmd = CMD_OUTPUT;
175
+
else
176
+
cmd = CMD_INPUT;
177
+
178
+
ret = apple_smc_rw_u32(smcgp->smc, key, cmd, &val);
179
+
if (ret < 0)
180
+
return ret;
181
+
182
+
return val ? 1 : 0;
183
+
}
184
+
185
+
static int macsmc_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
186
+
{
187
+
struct macsmc_gpio *smcgp = gpiochip_get_data(gc);
188
+
smc_key key = macsmc_gpio_key(offset);
189
+
int ret;
190
+
191
+
value |= CMD_OUTPUT;
192
+
ret = apple_smc_write_u32(smcgp->smc, key, CMD_OUTPUT | value);
193
+
if (ret < 0)
194
+
dev_err(smcgp->dev, "GPIO set failed %p4ch = 0x%x\n",
195
+
&key, value);
196
+
197
+
return ret;
198
+
}
199
+
200
+
static int macsmc_gpio_init_valid_mask(struct gpio_chip *gc,
201
+
unsigned long *valid_mask, unsigned int ngpios)
202
+
{
203
+
struct macsmc_gpio *smcgp = gpiochip_get_data(gc);
204
+
int count;
205
+
int i;
206
+
207
+
count = min(smcgp->smc->key_count, MAX_GPIO);
208
+
209
+
bitmap_zero(valid_mask, ngpios);
210
+
211
+
for (i = 0; i < count; i++) {
212
+
int ret, gpio_nr;
213
+
smc_key key;
214
+
215
+
ret = apple_smc_get_key_by_index(smcgp->smc, smcgp->first_index + i, &key);
216
+
if (ret < 0)
217
+
return ret;
218
+
219
+
if (key > SMC_KEY(gPff))
220
+
break;
221
+
222
+
gpio_nr = macsmc_gpio_nr(key);
223
+
if (gpio_nr < 0 || gpio_nr > MAX_GPIO) {
224
+
dev_err(smcgp->dev, "Bad GPIO key %p4ch\n", &key);
225
+
continue;
226
+
}
227
+
228
+
set_bit(gpio_nr, valid_mask);
229
+
}
230
+
231
+
return 0;
232
+
}
233
+
234
+
static int macsmc_gpio_probe(struct platform_device *pdev)
235
+
{
236
+
struct macsmc_gpio *smcgp;
237
+
struct apple_smc *smc = dev_get_drvdata(pdev->dev.parent);
238
+
smc_key key;
239
+
int ret;
240
+
241
+
smcgp = devm_kzalloc(&pdev->dev, sizeof(*smcgp), GFP_KERNEL);
242
+
if (!smcgp)
243
+
return -ENOMEM;
244
+
245
+
smcgp->dev = &pdev->dev;
246
+
smcgp->smc = smc;
247
+
248
+
smcgp->first_index = macsmc_gpio_find_first_gpio_index(smcgp);
249
+
if (smcgp->first_index < 0)
250
+
return smcgp->first_index;
251
+
252
+
ret = apple_smc_get_key_by_index(smc, smcgp->first_index, &key);
253
+
if (ret < 0)
254
+
return ret;
255
+
256
+
if (key > macsmc_gpio_key(MAX_GPIO - 1))
257
+
return -ENODEV;
258
+
259
+
dev_info(smcgp->dev, "First GPIO key: %p4ch\n", &key);
260
+
261
+
smcgp->gc.label = "macsmc-pmu-gpio";
262
+
smcgp->gc.owner = THIS_MODULE;
263
+
smcgp->gc.get = macsmc_gpio_get;
264
+
smcgp->gc.set_rv = macsmc_gpio_set;
265
+
smcgp->gc.get_direction = macsmc_gpio_get_direction;
266
+
smcgp->gc.init_valid_mask = macsmc_gpio_init_valid_mask;
267
+
smcgp->gc.can_sleep = true;
268
+
smcgp->gc.ngpio = MAX_GPIO;
269
+
smcgp->gc.base = -1;
270
+
smcgp->gc.parent = &pdev->dev;
271
+
272
+
return devm_gpiochip_add_data(&pdev->dev, &smcgp->gc, smcgp);
273
+
}
274
+
275
+
static const struct of_device_id macsmc_gpio_of_table[] = {
276
+
{ .compatible = "apple,smc-gpio", },
277
+
{}
278
+
};
279
+
MODULE_DEVICE_TABLE(of, macsmc_gpio_of_table);
280
+
281
+
static struct platform_driver macsmc_gpio_driver = {
282
+
.driver = {
283
+
.name = "macsmc-gpio",
284
+
.of_match_table = macsmc_gpio_of_table,
285
+
},
286
+
.probe = macsmc_gpio_probe,
287
+
};
288
+
module_platform_driver(macsmc_gpio_driver);
289
+
290
+
MODULE_AUTHOR("Hector Martin <marcan@marcan.st>");
291
+
MODULE_LICENSE("Dual MIT/GPL");
292
+
MODULE_DESCRIPTION("Apple SMC GPIO driver");
+6
-6
drivers/gpio/gpio-mm-lantiq.c
+6
-6
drivers/gpio/gpio-mm-lantiq.c
···
55
55
* @gpio: GPIO signal number.
56
56
* @val: Value to be written to specified signal.
57
57
*
58
-
* Set the shadow value and call ltq_mm_apply.
58
+
* Set the shadow value and call ltq_mm_apply. Always returns 0.
59
59
*/
60
-
static void ltq_mm_set(struct gpio_chip *gc, unsigned offset, int value)
60
+
static int ltq_mm_set(struct gpio_chip *gc, unsigned int offset, int value)
61
61
{
62
62
struct ltq_mm *chip = gpiochip_get_data(gc);
63
63
···
66
66
else
67
67
chip->shadow &= ~(1 << offset);
68
68
ltq_mm_apply(chip);
69
+
70
+
return 0;
69
71
}
70
72
71
73
/**
···
80
78
*/
81
79
static int ltq_mm_dir_out(struct gpio_chip *gc, unsigned offset, int value)
82
80
{
83
-
ltq_mm_set(gc, offset, value);
84
-
85
-
return 0;
81
+
return ltq_mm_set(gc, offset, value);
86
82
}
87
83
88
84
/**
···
111
111
112
112
chip->mmchip.gc.ngpio = 16;
113
113
chip->mmchip.gc.direction_output = ltq_mm_dir_out;
114
-
chip->mmchip.gc.set = ltq_mm_set;
114
+
chip->mmchip.gc.set_rv = ltq_mm_set;
115
115
chip->mmchip.save_regs = ltq_mm_save_regs;
116
116
117
117
/* store the shadow value if one was passed by the devicetree */
+65
-66
drivers/gpio/gpio-mmio.c
+65
-66
drivers/gpio/gpio-mmio.c
···
211
211
return 0;
212
212
}
213
213
214
-
static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
214
+
static int bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
215
215
{
216
+
return 0;
216
217
}
217
218
218
-
static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
219
+
static int bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
219
220
{
220
221
unsigned long mask = bgpio_line2mask(gc, gpio);
221
222
unsigned long flags;
···
231
230
gc->write_reg(gc->reg_dat, gc->bgpio_data);
232
231
233
232
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
233
+
234
+
return 0;
234
235
}
235
236
236
-
static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
237
-
int val)
237
+
static int bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
238
+
int val)
238
239
{
239
240
unsigned long mask = bgpio_line2mask(gc, gpio);
240
241
···
244
241
gc->write_reg(gc->reg_set, mask);
245
242
else
246
243
gc->write_reg(gc->reg_clr, mask);
244
+
245
+
return 0;
247
246
}
248
247
249
-
static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
248
+
static int bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
250
249
{
251
250
unsigned long mask = bgpio_line2mask(gc, gpio);
252
251
unsigned long flags;
···
263
258
gc->write_reg(gc->reg_set, gc->bgpio_data);
264
259
265
260
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
261
+
262
+
return 0;
266
263
}
267
264
268
265
static void bgpio_multiple_get_masks(struct gpio_chip *gc,
···
305
298
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
306
299
}
307
300
308
-
static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
301
+
static int bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
309
302
unsigned long *bits)
310
303
{
311
304
bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
305
+
306
+
return 0;
312
307
}
313
308
314
-
static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
315
-
unsigned long *bits)
309
+
static int bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
310
+
unsigned long *bits)
316
311
{
317
312
bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
313
+
314
+
return 0;
318
315
}
319
316
320
-
static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
321
-
unsigned long *mask,
322
-
unsigned long *bits)
317
+
static int bgpio_set_multiple_with_clear(struct gpio_chip *gc,
318
+
unsigned long *mask,
319
+
unsigned long *bits)
323
320
{
324
321
unsigned long set_mask, clear_mask;
325
322
···
333
322
gc->write_reg(gc->reg_set, set_mask);
334
323
if (clear_mask)
335
324
gc->write_reg(gc->reg_clr, clear_mask);
325
+
326
+
return 0;
336
327
}
337
328
338
329
static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out)
···
346
333
return pinctrl_gpio_direction_output(gc, gpio);
347
334
else
348
335
return pinctrl_gpio_direction_input(gc, gpio);
336
+
}
337
+
338
+
static int bgpio_dir_in_err(struct gpio_chip *gc, unsigned int gpio)
339
+
{
340
+
return -EINVAL;
349
341
}
350
342
351
343
static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
···
367
349
static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
368
350
int val)
369
351
{
370
-
gc->set(gc, gpio, val);
352
+
gc->set_rv(gc, gpio, val);
371
353
372
354
return bgpio_dir_return(gc, gpio, true);
373
355
}
···
432
414
int val)
433
415
{
434
416
bgpio_dir_out(gc, gpio, val);
435
-
gc->set(gc, gpio, val);
417
+
gc->set_rv(gc, gpio, val);
436
418
return bgpio_dir_return(gc, gpio, true);
437
419
}
438
420
439
421
static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
440
422
int val)
441
423
{
442
-
gc->set(gc, gpio, val);
424
+
gc->set_rv(gc, gpio, val);
443
425
bgpio_dir_out(gc, gpio, val);
444
426
return bgpio_dir_return(gc, gpio, true);
445
427
}
···
528
510
if (set && clr) {
529
511
gc->reg_set = set;
530
512
gc->reg_clr = clr;
531
-
gc->set = bgpio_set_with_clear;
532
-
gc->set_multiple = bgpio_set_multiple_with_clear;
513
+
gc->set_rv = bgpio_set_with_clear;
514
+
gc->set_multiple_rv = bgpio_set_multiple_with_clear;
533
515
} else if (set && !clr) {
534
516
gc->reg_set = set;
535
-
gc->set = bgpio_set_set;
536
-
gc->set_multiple = bgpio_set_multiple_set;
517
+
gc->set_rv = bgpio_set_set;
518
+
gc->set_multiple_rv = bgpio_set_multiple_set;
537
519
} else if (flags & BGPIOF_NO_OUTPUT) {
538
-
gc->set = bgpio_set_none;
539
-
gc->set_multiple = NULL;
520
+
gc->set_rv = bgpio_set_none;
521
+
gc->set_multiple_rv = NULL;
540
522
} else {
541
-
gc->set = bgpio_set;
542
-
gc->set_multiple = bgpio_set_multiple;
523
+
gc->set_rv = bgpio_set;
524
+
gc->set_multiple_rv = bgpio_set_multiple;
543
525
}
544
526
545
527
if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
···
584
566
gc->direction_output = bgpio_dir_out_err;
585
567
else
586
568
gc->direction_output = bgpio_simple_dir_out;
587
-
gc->direction_input = bgpio_simple_dir_in;
569
+
570
+
if (flags & BGPIOF_NO_INPUT)
571
+
gc->direction_input = bgpio_dir_in_err;
572
+
else
573
+
gc->direction_input = bgpio_simple_dir_in;
588
574
}
589
575
590
576
return 0;
···
676
654
}
677
655
678
656
gc->bgpio_data = gc->read_reg(gc->reg_dat);
679
-
if (gc->set == bgpio_set_set &&
657
+
if (gc->set_rv == bgpio_set_set &&
680
658
!(flags & BGPIOF_UNREADABLE_REG_SET))
681
659
gc->bgpio_data = gc->read_reg(gc->reg_set);
682
660
···
734
712
};
735
713
MODULE_DEVICE_TABLE(of, bgpio_of_match);
736
714
737
-
static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *flags)
738
-
{
739
-
struct bgpio_pdata *pdata;
740
-
741
-
if (!dev_fwnode(dev))
742
-
return NULL;
743
-
744
-
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
745
-
if (!pdata)
746
-
return ERR_PTR(-ENOMEM);
747
-
748
-
pdata->base = -1;
749
-
750
-
if (device_is_big_endian(dev))
751
-
*flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
752
-
753
-
if (device_property_read_bool(dev, "no-output"))
754
-
*flags |= BGPIOF_NO_OUTPUT;
755
-
756
-
return pdata;
757
-
}
758
-
759
715
static int bgpio_pdev_probe(struct platform_device *pdev)
760
716
{
761
717
struct device *dev = &pdev->dev;
···
745
745
void __iomem *dirin;
746
746
unsigned long sz;
747
747
unsigned long flags = 0;
748
+
unsigned int base;
748
749
int err;
749
750
struct gpio_chip *gc;
750
-
struct bgpio_pdata *pdata;
751
-
752
-
pdata = bgpio_parse_fw(dev, &flags);
753
-
if (IS_ERR(pdata))
754
-
return PTR_ERR(pdata);
755
-
756
-
if (!pdata) {
757
-
pdata = dev_get_platdata(dev);
758
-
flags = pdev->id_entry->driver_data;
759
-
}
751
+
const char *label;
760
752
761
753
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
762
754
if (!r)
···
780
788
if (!gc)
781
789
return -ENOMEM;
782
790
791
+
if (device_is_big_endian(dev))
792
+
flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
793
+
794
+
if (device_property_read_bool(dev, "no-output"))
795
+
flags |= BGPIOF_NO_OUTPUT;
796
+
783
797
err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
784
798
if (err)
785
799
return err;
786
800
787
-
if (pdata) {
788
-
if (pdata->label)
789
-
gc->label = pdata->label;
790
-
gc->base = pdata->base;
791
-
if (pdata->ngpio > 0)
792
-
gc->ngpio = pdata->ngpio;
793
-
}
801
+
err = device_property_read_string(dev, "label", &label);
802
+
if (!err)
803
+
gc->label = label;
804
+
805
+
/*
806
+
* This property *must not* be used in device-tree sources, it's only
807
+
* meant to be passed to the driver from board files and MFD core.
808
+
*/
809
+
err = device_property_read_u32(dev, "gpio-mmio,base", &base);
810
+
if (!err && base <= INT_MAX)
811
+
gc->base = base;
794
812
795
813
platform_set_drvdata(pdev, gc);
796
814
···
811
809
{
812
810
.name = "basic-mmio-gpio",
813
811
.driver_data = 0,
814
-
}, {
815
-
.name = "basic-mmio-gpio-be",
816
-
.driver_data = BGPIOF_BIG_ENDIAN,
817
812
},
818
813
{ }
819
814
};
+7
-9
drivers/gpio/gpio-moxtet.c
+7
-9
drivers/gpio/gpio-moxtet.c
···
52
52
return !!(ret & BIT(offset));
53
53
}
54
54
55
-
static void moxtet_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
56
-
int val)
55
+
static int moxtet_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
56
+
int val)
57
57
{
58
58
struct moxtet_gpio_chip *chip = gpiochip_get_data(gc);
59
59
int state;
60
60
61
61
state = moxtet_device_written(chip->dev);
62
62
if (state < 0)
63
-
return;
63
+
return state;
64
64
65
65
offset -= MOXTET_GPIO_INPUTS;
66
66
···
69
69
else
70
70
state &= ~BIT(offset);
71
71
72
-
moxtet_device_write(chip->dev, state);
72
+
return moxtet_device_write(chip->dev, state);
73
73
}
74
74
75
75
static int moxtet_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
···
104
104
struct moxtet_gpio_chip *chip = gpiochip_get_data(gc);
105
105
106
106
if (chip->desc->out_mask & BIT(offset))
107
-
moxtet_gpio_set_value(gc, offset, val);
107
+
return moxtet_gpio_set_value(gc, offset, val);
108
108
else if (chip->desc->in_mask & BIT(offset))
109
109
return -ENOTSUPP;
110
-
else
111
-
return -EINVAL;
112
110
113
-
return 0;
111
+
return -EINVAL;
114
112
}
115
113
116
114
static int moxtet_gpio_probe(struct device *dev)
···
140
142
chip->gpio_chip.direction_input = moxtet_gpio_direction_input;
141
143
chip->gpio_chip.direction_output = moxtet_gpio_direction_output;
142
144
chip->gpio_chip.get = moxtet_gpio_get_value;
143
-
chip->gpio_chip.set = moxtet_gpio_set_value;
145
+
chip->gpio_chip.set_rv = moxtet_gpio_set_value;
144
146
chip->gpio_chip.base = -1;
145
147
146
148
chip->gpio_chip.ngpio = MOXTET_GPIO_NGPIOS;
+8
-4
drivers/gpio/gpio-mpc5200.c
+8
-4
drivers/gpio/gpio-mpc5200.c
···
69
69
out_8(®s->wkup_dvo, chip->shadow_dvo);
70
70
}
71
71
72
-
static void
72
+
static int
73
73
mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
74
74
{
75
75
unsigned long flags;
···
81
81
spin_unlock_irqrestore(&gpio_lock, flags);
82
82
83
83
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
84
+
85
+
return 0;
84
86
}
85
87
86
88
static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
···
153
151
gc->direction_input = mpc52xx_wkup_gpio_dir_in;
154
152
gc->direction_output = mpc52xx_wkup_gpio_dir_out;
155
153
gc->get = mpc52xx_wkup_gpio_get;
156
-
gc->set = mpc52xx_wkup_gpio_set;
154
+
gc->set_rv = mpc52xx_wkup_gpio_set;
157
155
158
156
ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
159
157
if (ret)
···
230
228
out_be32(®s->simple_dvo, chip->shadow_dvo);
231
229
}
232
230
233
-
static void
231
+
static int
234
232
mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
235
233
{
236
234
unsigned long flags;
···
242
240
spin_unlock_irqrestore(&gpio_lock, flags);
243
241
244
242
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
243
+
244
+
return 0;
245
245
}
246
246
247
247
static int mpc52xx_simple_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
···
315
311
gc->direction_input = mpc52xx_simple_gpio_dir_in;
316
312
gc->direction_output = mpc52xx_simple_gpio_dir_out;
317
313
gc->get = mpc52xx_simple_gpio_get;
318
-
gc->set = mpc52xx_simple_gpio_set;
314
+
gc->set_rv = mpc52xx_simple_gpio_set;
319
315
320
316
ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
321
317
if (ret)
+7
-4
drivers/gpio/gpio-mpfs.c
+7
-4
drivers/gpio/gpio-mpfs.c
···
99
99
return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->inp, BIT(gpio_index));
100
100
}
101
101
102
-
static void mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int value)
102
+
static int mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int value)
103
103
{
104
104
struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
105
+
int ret;
105
106
106
107
mpfs_gpio_get(gc, gpio_index);
107
108
108
-
regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index),
109
-
value << gpio_index);
109
+
ret = regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp,
110
+
BIT(gpio_index), value << gpio_index);
110
111
111
112
mpfs_gpio_get(gc, gpio_index);
113
+
114
+
return ret;
112
115
}
113
116
114
117
static int mpfs_gpio_probe(struct platform_device *pdev)
···
150
147
mpfs_gpio->gc.direction_output = mpfs_gpio_direction_output;
151
148
mpfs_gpio->gc.get_direction = mpfs_gpio_get_direction;
152
149
mpfs_gpio->gc.get = mpfs_gpio_get;
153
-
mpfs_gpio->gc.set = mpfs_gpio_set;
150
+
mpfs_gpio->gc.set_rv = mpfs_gpio_set;
154
151
mpfs_gpio->gc.base = -1;
155
152
mpfs_gpio->gc.ngpio = ngpios;
156
153
mpfs_gpio->gc.label = dev_name(dev);
+10
-12
drivers/gpio/gpio-mpsse.c
+10
-12
drivers/gpio/gpio-mpsse.c
···
160
160
return buf;
161
161
}
162
162
163
-
static void gpio_mpsse_set_multiple(struct gpio_chip *chip, unsigned long *mask,
164
-
unsigned long *bits)
163
+
static int gpio_mpsse_set_multiple(struct gpio_chip *chip, unsigned long *mask,
164
+
unsigned long *bits)
165
165
{
166
166
unsigned long i, bank, bank_mask, bank_bits;
167
167
int ret;
···
180
180
181
181
ret = gpio_mpsse_set_bank(priv, bank);
182
182
if (ret)
183
-
dev_err(&priv->intf->dev,
184
-
"Couldn't set values for bank %ld!",
185
-
bank);
183
+
return ret;
186
184
}
187
185
}
186
+
187
+
return 0;
188
188
}
189
189
190
190
static int gpio_mpsse_get_multiple(struct gpio_chip *chip, unsigned long *mask,
···
227
227
return 0;
228
228
}
229
229
230
-
static void gpio_mpsse_gpio_set(struct gpio_chip *chip, unsigned int offset,
230
+
static int gpio_mpsse_gpio_set(struct gpio_chip *chip, unsigned int offset,
231
231
int value)
232
232
{
233
233
unsigned long mask = 0, bits = 0;
···
236
236
if (value)
237
237
__set_bit(offset, &bits);
238
238
239
-
gpio_mpsse_set_multiple(chip, &mask, &bits);
239
+
return gpio_mpsse_set_multiple(chip, &mask, &bits);
240
240
}
241
241
242
242
static int gpio_mpsse_direction_output(struct gpio_chip *chip,
···
249
249
scoped_guard(mutex, &priv->io_mutex)
250
250
priv->gpio_dir[bank] |= BIT(bank_offset);
251
251
252
-
gpio_mpsse_gpio_set(chip, offset, value);
253
-
254
-
return 0;
252
+
return gpio_mpsse_gpio_set(chip, offset, value);
255
253
}
256
254
257
255
static int gpio_mpsse_direction_input(struct gpio_chip *chip,
···
448
450
priv->gpio.direction_input = gpio_mpsse_direction_input;
449
451
priv->gpio.direction_output = gpio_mpsse_direction_output;
450
452
priv->gpio.get = gpio_mpsse_gpio_get;
451
-
priv->gpio.set = gpio_mpsse_gpio_set;
453
+
priv->gpio.set_rv = gpio_mpsse_gpio_set;
452
454
priv->gpio.get_multiple = gpio_mpsse_get_multiple;
453
-
priv->gpio.set_multiple = gpio_mpsse_set_multiple;
455
+
priv->gpio.set_multiple_rv = gpio_mpsse_set_multiple;
454
456
priv->gpio.base = -1;
455
457
priv->gpio.ngpio = 16;
456
458
priv->gpio.offset = priv->intf_id * priv->gpio.ngpio;
+4
-2
drivers/gpio/gpio-msc313.c
+4
-2
drivers/gpio/gpio-msc313.c
···
486
486
u8 *saved;
487
487
};
488
488
489
-
static void msc313_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
489
+
static int msc313_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
490
490
{
491
491
struct msc313_gpio *gpio = gpiochip_get_data(chip);
492
492
u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
···
497
497
gpioreg &= ~MSC313_GPIO_OUT;
498
498
499
499
writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);
500
+
501
+
return 0;
500
502
}
501
503
502
504
static int msc313_gpio_get(struct gpio_chip *chip, unsigned int offset)
···
658
656
gpiochip->direction_input = msc313_gpio_direction_input;
659
657
gpiochip->direction_output = msc313_gpio_direction_output;
660
658
gpiochip->get = msc313_gpio_get;
661
-
gpiochip->set = msc313_gpio_set;
659
+
gpiochip->set_rv = msc313_gpio_set;
662
660
gpiochip->base = -1;
663
661
gpiochip->ngpio = gpio->gpio_data->num;
664
662
gpiochip->names = gpio->gpio_data->names;
+2
-2
drivers/gpio/gpio-mvebu.c
+2
-2
drivers/gpio/gpio-mvebu.c
···
1236
1236
if (!have_irqs)
1237
1237
return 0;
1238
1238
1239
-
mvchip->domain =
1240
-
irq_domain_create_linear(of_fwnode_handle(np), ngpios, &irq_generic_chip_ops, NULL);
1239
+
mvchip->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), ngpios,
1240
+
&irq_generic_chip_ops, NULL);
1241
1241
if (!mvchip->domain) {
1242
1242
dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1243
1243
mvchip->chip.label);
+46
-45
drivers/gpio/gpio-mxc.c
+46
-45
drivers/gpio/gpio-mxc.c
···
7
7
// Authors: Daniel Mack, Juergen Beisert.
8
8
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9
9
10
+
#include <linux/cleanup.h>
10
11
#include <linux/clk.h>
11
12
#include <linux/err.h>
12
13
#include <linux/init.h>
···
23
22
#include <linux/spinlock.h>
24
23
#include <linux/syscore_ops.h>
25
24
#include <linux/gpio/driver.h>
25
+
#include <linux/gpio/generic.h>
26
26
#include <linux/of.h>
27
27
#include <linux/bug.h>
28
28
···
66
64
int irq_high;
67
65
void (*mx_irq_handler)(struct irq_desc *desc);
68
66
struct irq_domain *domain;
69
-
struct gpio_chip gc;
67
+
struct gpio_generic_chip gen_gc;
70
68
struct device *dev;
71
69
u32 both_edges;
72
70
struct mxc_gpio_reg_saved gpio_saved_reg;
···
163
161
{
164
162
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
165
163
struct mxc_gpio_port *port = gc->private;
166
-
unsigned long flags;
167
164
u32 bit, val;
168
165
u32 gpio_idx = d->hwirq;
169
166
int edge;
···
180
179
if (GPIO_EDGE_SEL >= 0) {
181
180
edge = GPIO_INT_BOTH_EDGES;
182
181
} else {
183
-
val = port->gc.get(&port->gc, gpio_idx);
182
+
val = port->gen_gc.gc.get(&port->gen_gc.gc, gpio_idx);
184
183
if (val) {
185
184
edge = GPIO_INT_LOW_LEV;
186
185
pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
···
201
200
return -EINVAL;
202
201
}
203
202
204
-
raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
203
+
scoped_guard(gpio_generic_lock_irqsave, &port->gen_gc) {
204
+
if (GPIO_EDGE_SEL >= 0) {
205
+
val = readl(port->base + GPIO_EDGE_SEL);
206
+
if (edge == GPIO_INT_BOTH_EDGES)
207
+
writel(val | (1 << gpio_idx),
208
+
port->base + GPIO_EDGE_SEL);
209
+
else
210
+
writel(val & ~(1 << gpio_idx),
211
+
port->base + GPIO_EDGE_SEL);
212
+
}
205
213
206
-
if (GPIO_EDGE_SEL >= 0) {
207
-
val = readl(port->base + GPIO_EDGE_SEL);
208
-
if (edge == GPIO_INT_BOTH_EDGES)
209
-
writel(val | (1 << gpio_idx),
210
-
port->base + GPIO_EDGE_SEL);
211
-
else
212
-
writel(val & ~(1 << gpio_idx),
213
-
port->base + GPIO_EDGE_SEL);
214
+
if (edge != GPIO_INT_BOTH_EDGES) {
215
+
reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
216
+
bit = gpio_idx & 0xf;
217
+
val = readl(reg) & ~(0x3 << (bit << 1));
218
+
writel(val | (edge << (bit << 1)), reg);
219
+
}
220
+
221
+
writel(1 << gpio_idx, port->base + GPIO_ISR);
222
+
port->pad_type[gpio_idx] = type;
214
223
}
215
224
216
-
if (edge != GPIO_INT_BOTH_EDGES) {
217
-
reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
218
-
bit = gpio_idx & 0xf;
219
-
val = readl(reg) & ~(0x3 << (bit << 1));
220
-
writel(val | (edge << (bit << 1)), reg);
221
-
}
222
-
223
-
writel(1 << gpio_idx, port->base + GPIO_ISR);
224
-
port->pad_type[gpio_idx] = type;
225
-
226
-
raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
227
-
228
-
return port->gc.direction_input(&port->gc, gpio_idx);
225
+
return port->gen_gc.gc.direction_input(&port->gen_gc.gc, gpio_idx);
229
226
}
230
227
231
228
static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
232
229
{
233
230
void __iomem *reg = port->base;
234
-
unsigned long flags;
235
231
u32 bit, val;
236
232
int edge;
237
233
238
-
raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
234
+
guard(gpio_generic_lock_irqsave)(&port->gen_gc);
239
235
240
236
reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
241
237
bit = gpio & 0xf;
···
248
250
} else {
249
251
pr_err("mxc: invalid configuration for GPIO %d: %x\n",
250
252
gpio, edge);
251
-
goto unlock;
253
+
return;
252
254
}
253
255
writel(val | (edge << (bit << 1)), reg);
254
-
255
-
unlock:
256
-
raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
257
256
}
258
257
259
258
/* handle 32 interrupts in one status register */
···
415
420
416
421
static int mxc_gpio_probe(struct platform_device *pdev)
417
422
{
423
+
struct gpio_generic_chip_config config = { };
418
424
struct device_node *np = pdev->dev.of_node;
419
425
struct mxc_gpio_port *port;
420
426
int irq_count;
···
475
479
port->mx_irq_handler = mx3_gpio_irq_handler;
476
480
477
481
mxc_update_irq_chained_handler(port, true);
478
-
err = bgpio_init(&port->gc, &pdev->dev, 4,
479
-
port->base + GPIO_PSR,
480
-
port->base + GPIO_DR, NULL,
481
-
port->base + GPIO_GDIR, NULL,
482
-
BGPIOF_READ_OUTPUT_REG_SET);
482
+
483
+
config.dev = &pdev->dev;
484
+
config.sz = 4;
485
+
config.dat = port->base + GPIO_PSR;
486
+
config.set = port->base + GPIO_DR;
487
+
config.dirout = port->base + GPIO_GDIR;
488
+
config.flags = BGPIOF_READ_OUTPUT_REG_SET;
489
+
490
+
err = gpio_generic_chip_init(&port->gen_gc, &config);
483
491
if (err)
484
492
goto out_bgio;
485
493
486
-
port->gc.request = mxc_gpio_request;
487
-
port->gc.free = mxc_gpio_free;
488
-
port->gc.to_irq = mxc_gpio_to_irq;
494
+
port->gen_gc.gc.request = mxc_gpio_request;
495
+
port->gen_gc.gc.free = mxc_gpio_free;
496
+
port->gen_gc.gc.to_irq = mxc_gpio_to_irq;
489
497
/*
490
498
* Driver is DT-only, so a fixed base needs only be maintained for legacy
491
499
* userspace with sysfs interface.
492
500
*/
493
501
if (IS_ENABLED(CONFIG_GPIO_SYSFS))
494
-
port->gc.base = of_alias_get_id(np, "gpio") * 32;
502
+
port->gen_gc.gc.base = of_alias_get_id(np, "gpio") * 32;
495
503
else /* silence boot time warning */
496
-
port->gc.base = -1;
504
+
port->gen_gc.gc.base = -1;
497
505
498
-
err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
506
+
err = devm_gpiochip_add_data(&pdev->dev, &port->gen_gc.gc, port);
499
507
if (err)
500
508
goto out_bgio;
501
509
···
509
509
goto out_bgio;
510
510
}
511
511
512
-
port->domain = irq_domain_create_legacy(of_fwnode_handle(np), 32, irq_base, 0,
513
-
&irq_domain_simple_ops, NULL);
512
+
port->domain = irq_domain_create_legacy(dev_fwnode(&pdev->dev), 32, irq_base, 0,
513
+
&irq_domain_simple_ops, NULL);
514
514
if (!port->domain) {
515
515
err = -ENODEV;
516
516
goto out_bgio;
···
573
573
if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") ||
574
574
of_device_is_compatible(np, "fsl,imx8qxp-gpio") ||
575
575
of_device_is_compatible(np, "fsl,imx8qm-gpio"))
576
-
return (gpiochip_generic_config(&port->gc, offset, conf) == 0);
576
+
return (gpiochip_generic_config(&port->gen_gc.gc,
577
+
offset, conf) == 0);
577
578
578
579
return false;
579
580
}
+1
-1
drivers/gpio/gpio-mxs.c
+1
-1
drivers/gpio/gpio-mxs.c
···
303
303
goto out_iounmap;
304
304
}
305
305
306
-
port->domain = irq_domain_create_legacy(of_fwnode_handle(np), 32, irq_base, 0,
306
+
port->domain = irq_domain_create_legacy(dev_fwnode(&pdev->dev), 32, irq_base, 0,
307
307
&irq_domain_simple_ops, NULL);
308
308
if (!port->domain) {
309
309
err = -ENODEV;
+5
-3
drivers/gpio/gpio-nomadik.c
+5
-3
drivers/gpio/gpio-nomadik.c
···
347
347
return value;
348
348
}
349
349
350
-
static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned int offset,
351
-
int val)
350
+
static int nmk_gpio_set_output(struct gpio_chip *chip, unsigned int offset,
351
+
int val)
352
352
{
353
353
struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
354
354
···
357
357
__nmk_gpio_set_output(nmk_chip, offset, val);
358
358
359
359
clk_disable(nmk_chip->clk);
360
+
361
+
return 0;
360
362
}
361
363
362
364
static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned int offset,
···
674
672
chip->direction_input = nmk_gpio_make_input;
675
673
chip->get = nmk_gpio_get_input;
676
674
chip->direction_output = nmk_gpio_make_output;
677
-
chip->set = nmk_gpio_set_output;
675
+
chip->set_rv = nmk_gpio_set_output;
678
676
chip->dbg_show = nmk_gpio_dbg_show;
679
677
chip->can_sleep = false;
680
678
chip->owner = THIS_MODULE;
+5
-5
drivers/gpio/gpio-npcm-sgpio.c
+5
-5
drivers/gpio/gpio-npcm-sgpio.c
···
211
211
212
212
static int npcm_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
213
213
{
214
-
gc->set(gc, offset, val);
215
-
216
-
return 0;
214
+
return gc->set_rv(gc, offset, val);
217
215
}
218
216
219
217
static int npcm_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
···
224
226
return GPIO_LINE_DIRECTION_IN;
225
227
}
226
228
227
-
static void npcm_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
229
+
static int npcm_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
228
230
{
229
231
struct npcm_sgpio *gpio = gpiochip_get_data(gc);
230
232
const struct npcm_sgpio_bank *bank = offset_to_bank(offset);
···
240
242
reg &= ~BIT(GPIO_BIT(offset));
241
243
242
244
iowrite8(reg, addr);
245
+
246
+
return 0;
243
247
}
244
248
245
249
static int npcm_sgpio_get(struct gpio_chip *gc, unsigned int offset)
···
546
546
gpio->chip.direction_output = npcm_sgpio_dir_out;
547
547
gpio->chip.get_direction = npcm_sgpio_get_direction;
548
548
gpio->chip.get = npcm_sgpio_get;
549
-
gpio->chip.set = npcm_sgpio_set;
549
+
gpio->chip.set_rv = npcm_sgpio_set;
550
550
gpio->chip.label = dev_name(&pdev->dev);
551
551
gpio->chip.base = -1;
552
552
+5
-2
drivers/gpio/gpio-octeon.c
+5
-2
drivers/gpio/gpio-octeon.c
···
47
47
return 0;
48
48
}
49
49
50
-
static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
50
+
static int octeon_gpio_set(struct gpio_chip *chip, unsigned int offset,
51
+
int value)
51
52
{
52
53
struct octeon_gpio *gpio = gpiochip_get_data(chip);
53
54
u64 mask = 1ull << offset;
54
55
u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
55
56
cvmx_write_csr(reg, mask);
57
+
58
+
return 0;
56
59
}
57
60
58
61
static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
···
108
105
chip->direction_input = octeon_gpio_dir_in;
109
106
chip->get = octeon_gpio_get;
110
107
chip->direction_output = octeon_gpio_dir_out;
111
-
chip->set = octeon_gpio_set;
108
+
chip->set_rv = octeon_gpio_set;
112
109
err = devm_gpiochip_add_data(&pdev->dev, chip, gpio);
113
110
if (err)
114
111
return err;
+9
-5
drivers/gpio/gpio-omap.c
+9
-5
drivers/gpio/gpio-omap.c
···
953
953
return ret;
954
954
}
955
955
956
-
static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
956
+
static int omap_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
957
957
{
958
958
struct gpio_bank *bank;
959
959
unsigned long flags;
···
962
962
raw_spin_lock_irqsave(&bank->lock, flags);
963
963
bank->set_dataout(bank, offset, value);
964
964
raw_spin_unlock_irqrestore(&bank->lock, flags);
965
+
966
+
return 0;
965
967
}
966
968
967
-
static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
968
-
unsigned long *bits)
969
+
static int omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
970
+
unsigned long *bits)
969
971
{
970
972
struct gpio_bank *bank = gpiochip_get_data(chip);
971
973
void __iomem *reg = bank->base + bank->regs->dataout;
···
979
977
writel_relaxed(l, reg);
980
978
bank->context.dataout = l;
981
979
raw_spin_unlock_irqrestore(&bank->lock, flags);
980
+
981
+
return 0;
982
982
}
983
983
984
984
/*---------------------------------------------------------------------*/
···
1046
1042
bank->chip.get_multiple = omap_gpio_get_multiple;
1047
1043
bank->chip.direction_output = omap_gpio_output;
1048
1044
bank->chip.set_config = omap_gpio_set_config;
1049
-
bank->chip.set = omap_gpio_set;
1050
-
bank->chip.set_multiple = omap_gpio_set_multiple;
1045
+
bank->chip.set_rv = omap_gpio_set;
1046
+
bank->chip.set_multiple_rv = omap_gpio_set_multiple;
1051
1047
if (bank->is_mpuio) {
1052
1048
bank->chip.label = "mpuio";
1053
1049
if (bank->regs->wkup_en)
+18
-8
drivers/gpio/gpio-palmas.c
+18
-8
drivers/gpio/gpio-palmas.c
···
54
54
return !!(val & BIT(offset));
55
55
}
56
56
57
-
static void palmas_gpio_set(struct gpio_chip *gc, unsigned offset,
58
-
int value)
57
+
static int palmas_gpio_set(struct gpio_chip *gc, unsigned int offset,
58
+
int value)
59
59
{
60
60
struct palmas_gpio *pg = gpiochip_get_data(gc);
61
61
struct palmas *palmas = pg->palmas;
62
-
int ret;
63
62
unsigned int reg;
64
63
int gpio16 = (offset/8);
65
64
···
70
71
reg = (value) ?
71
72
PALMAS_GPIO_SET_DATA_OUT : PALMAS_GPIO_CLEAR_DATA_OUT;
72
73
73
-
ret = palmas_write(palmas, PALMAS_GPIO_BASE, reg, BIT(offset));
74
-
if (ret < 0)
75
-
dev_err(gc->parent, "Reg 0x%02x write failed, %d\n", reg, ret);
74
+
return palmas_write(palmas, PALMAS_GPIO_BASE, reg, BIT(offset));
76
75
}
77
76
78
77
static int palmas_gpio_output(struct gpio_chip *gc, unsigned offset,
···
86
89
reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR;
87
90
88
91
/* Set the initial value */
89
-
palmas_gpio_set(gc, offset, value);
92
+
ret = palmas_gpio_set(gc, offset, value);
93
+
if (ret)
94
+
return ret;
90
95
91
96
ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, reg,
92
97
BIT(offset), BIT(offset));
···
139
140
{ .compatible = "ti,tps80036-gpio", .data = &tps80036_dev_data,},
140
141
{ },
141
142
};
143
+
MODULE_DEVICE_TABLE(of, of_palmas_gpio_match);
142
144
143
145
static int palmas_gpio_probe(struct platform_device *pdev)
144
146
{
···
166
166
palmas_gpio->gpio_chip.direction_input = palmas_gpio_input;
167
167
palmas_gpio->gpio_chip.direction_output = palmas_gpio_output;
168
168
palmas_gpio->gpio_chip.to_irq = palmas_gpio_to_irq;
169
-
palmas_gpio->gpio_chip.set = palmas_gpio_set;
169
+
palmas_gpio->gpio_chip.set_rv = palmas_gpio_set;
170
170
palmas_gpio->gpio_chip.get = palmas_gpio_get;
171
171
palmas_gpio->gpio_chip.parent = &pdev->dev;
172
172
···
197
197
return platform_driver_register(&palmas_gpio_driver);
198
198
}
199
199
subsys_initcall(palmas_gpio_init);
200
+
201
+
static void __exit palmas_gpio_exit(void)
202
+
{
203
+
platform_driver_unregister(&palmas_gpio_driver);
204
+
}
205
+
module_exit(palmas_gpio_exit);
206
+
207
+
MODULE_DESCRIPTION("TI PALMAS series GPIO driver");
208
+
MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
209
+
MODULE_LICENSE("GPL");
+141
-28
drivers/gpio/gpio-pca953x.c
+141
-28
drivers/gpio/gpio-pca953x.c
···
38
38
#define PCA953X_INVERT 0x02
39
39
#define PCA953X_DIRECTION 0x03
40
40
41
+
#define TCA6418_INPUT 0x14
42
+
#define TCA6418_OUTPUT 0x17
43
+
#define TCA6418_DIRECTION 0x23
44
+
41
45
#define REG_ADDR_MASK GENMASK(5, 0)
42
46
#define REG_ADDR_EXT BIT(6)
43
47
#define REG_ADDR_AI BIT(7)
···
80
76
#define PCA953X_TYPE BIT(12)
81
77
#define PCA957X_TYPE BIT(13)
82
78
#define PCAL653X_TYPE BIT(14)
83
-
#define PCA_TYPE_MASK GENMASK(15, 12)
79
+
#define TCA6418_TYPE BIT(16)
80
+
#define PCA_TYPE_MASK GENMASK(16, 12)
84
81
85
82
#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
86
83
···
120
115
{ "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
121
116
{ "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
122
117
{ "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
118
+
{ "tca6418", 18 | TCA6418_TYPE | PCA_INT, },
123
119
{ "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
124
120
{ "tca9538", 8 | PCA953X_TYPE | PCA_INT, },
125
121
{ "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
···
210
204
.invert = PCA957X_INVRT,
211
205
};
212
206
207
+
static const struct pca953x_reg_config tca6418_regs = {
208
+
.direction = TCA6418_DIRECTION,
209
+
.output = TCA6418_OUTPUT,
210
+
.input = TCA6418_INPUT,
211
+
.invert = 0xFF, /* Does not apply */
212
+
};
213
+
213
214
struct pca953x_chip {
214
215
unsigned gpio_start;
215
216
struct mutex i2c_lock;
···
248
235
static int pca953x_bank_shift(struct pca953x_chip *chip)
249
236
{
250
237
return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
238
+
}
239
+
240
+
/*
241
+
* Helper function to get the correct bit mask for a given offset and chip type.
242
+
* The TCA6418's input, output, and direction banks have a peculiar bit order:
243
+
* the first byte uses reversed bit order, while the second byte uses standard order.
244
+
*/
245
+
static inline u8 pca953x_get_bit_mask(struct pca953x_chip *chip, unsigned int offset)
246
+
{
247
+
unsigned int bit_pos_in_bank = offset % BANK_SZ;
248
+
int msb = BANK_SZ - 1;
249
+
250
+
if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE && offset <= msb)
251
+
return BIT(msb - bit_pos_in_bank);
252
+
253
+
return BIT(bit_pos_in_bank);
251
254
}
252
255
253
256
#define PCA953x_BANK_INPUT BIT(0)
···
382
353
return true;
383
354
}
384
355
356
+
/* TCA6418 breaks the PCA953x register order rule */
357
+
static bool tca6418_check_register(struct pca953x_chip *chip, unsigned int reg,
358
+
u32 access_type_mask)
359
+
{
360
+
/* Valid Input Registers - BIT(0) for readable access */
361
+
if (reg >= TCA6418_INPUT && reg < (TCA6418_INPUT + NBANK(chip)))
362
+
return (access_type_mask & BIT(0));
363
+
364
+
/* Valid Output Registers - BIT(1) for writeable access */
365
+
if (reg >= TCA6418_OUTPUT && reg < (TCA6418_OUTPUT + NBANK(chip)))
366
+
return (access_type_mask & (BIT(0) | BIT(1)));
367
+
368
+
/* Valid Direction Registers - BIT(2) for volatile access */
369
+
if (reg >= TCA6418_DIRECTION && reg < (TCA6418_DIRECTION + NBANK(chip)))
370
+
return (access_type_mask & (BIT(0) | BIT(1)));
371
+
372
+
return false;
373
+
}
374
+
385
375
static bool pca953x_readable_register(struct device *dev, unsigned int reg)
386
376
{
387
377
struct pca953x_chip *chip = dev_get_drvdata(dev);
388
378
u32 bank;
389
379
390
-
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
380
+
switch (PCA_CHIP_TYPE(chip->driver_data)) {
381
+
case PCA957X_TYPE:
391
382
bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
392
383
PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
393
384
PCA957x_BANK_BUSHOLD;
394
-
} else {
385
+
break;
386
+
case TCA6418_TYPE:
387
+
/* BIT(0) to indicate read access */
388
+
return tca6418_check_register(chip, reg, BIT(0));
389
+
default:
395
390
bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
396
391
PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
392
+
break;
397
393
}
398
394
399
395
if (chip->driver_data & PCA_PCAL) {
···
435
381
struct pca953x_chip *chip = dev_get_drvdata(dev);
436
382
u32 bank;
437
383
438
-
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
384
+
switch (PCA_CHIP_TYPE(chip->driver_data)) {
385
+
case PCA957X_TYPE:
439
386
bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
440
387
PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
441
-
} else {
388
+
break;
389
+
case TCA6418_TYPE:
390
+
/* BIT(1) for write access */
391
+
return tca6418_check_register(chip, reg, BIT(1));
392
+
default:
442
393
bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
443
394
PCA953x_BANK_CONFIG;
395
+
break;
444
396
}
445
397
446
398
if (chip->driver_data & PCA_PCAL)
···
461
401
struct pca953x_chip *chip = dev_get_drvdata(dev);
462
402
u32 bank;
463
403
464
-
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
404
+
switch (PCA_CHIP_TYPE(chip->driver_data)) {
405
+
case PCA957X_TYPE:
465
406
bank = PCA957x_BANK_INPUT;
466
-
else
407
+
break;
408
+
case TCA6418_TYPE:
409
+
/* BIT(2) for volatile access */
410
+
return tca6418_check_register(chip, reg, BIT(2));
411
+
default:
467
412
bank = PCA953x_BANK_INPUT;
413
+
break;
414
+
}
468
415
469
416
if (chip->driver_data & PCA_PCAL)
470
417
bank |= PCAL9xxx_BANK_IRQ_STAT;
···
556
489
return pinctrl + addr + (off / BANK_SZ);
557
490
}
558
491
492
+
static u8 tca6418_recalc_addr(struct pca953x_chip *chip, int reg_base, int offset)
493
+
{
494
+
/*
495
+
* reg_base will be TCA6418_INPUT, TCA6418_OUTPUT, or TCA6418_DIRECTION
496
+
* offset is the global GPIO line offset (0-17)
497
+
* BANK_SZ is 8 for TCA6418 (8 bits per register bank)
498
+
*/
499
+
return reg_base + (offset / BANK_SZ);
500
+
}
501
+
559
502
static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
560
503
{
561
504
u8 regaddr = chip->recalc_addr(chip, reg, 0);
···
606
529
{
607
530
struct pca953x_chip *chip = gpiochip_get_data(gc);
608
531
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
609
-
u8 bit = BIT(off % BANK_SZ);
532
+
u8 bit = pca953x_get_bit_mask(chip, off);
610
533
611
534
guard(mutex)(&chip->i2c_lock);
612
535
613
-
return regmap_write_bits(chip->regmap, dirreg, bit, bit);
536
+
if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE)
537
+
return regmap_update_bits(chip->regmap, dirreg, bit, 0);
538
+
539
+
return regmap_update_bits(chip->regmap, dirreg, bit, bit);
614
540
}
615
541
616
542
static int pca953x_gpio_direction_output(struct gpio_chip *gc,
···
622
542
struct pca953x_chip *chip = gpiochip_get_data(gc);
623
543
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
624
544
u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
625
-
u8 bit = BIT(off % BANK_SZ);
545
+
u8 bit = pca953x_get_bit_mask(chip, off);
626
546
int ret;
627
547
628
548
guard(mutex)(&chip->i2c_lock);
629
549
630
550
/* set output level */
631
-
ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
551
+
ret = regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0);
632
552
if (ret)
633
553
return ret;
634
554
635
-
/* then direction */
636
-
return regmap_write_bits(chip->regmap, dirreg, bit, 0);
555
+
/*
556
+
* then direction
557
+
* (in/out logic is inverted on TCA6418)
558
+
*/
559
+
if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE)
560
+
return regmap_update_bits(chip->regmap, dirreg, bit, bit);
561
+
562
+
return regmap_update_bits(chip->regmap, dirreg, bit, 0);
637
563
}
638
564
639
565
static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
640
566
{
641
567
struct pca953x_chip *chip = gpiochip_get_data(gc);
642
568
u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
643
-
u8 bit = BIT(off % BANK_SZ);
569
+
u8 bit = pca953x_get_bit_mask(chip, off);
644
570
u32 reg_val;
645
571
int ret;
646
572
···
663
577
{
664
578
struct pca953x_chip *chip = gpiochip_get_data(gc);
665
579
u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
666
-
u8 bit = BIT(off % BANK_SZ);
580
+
u8 bit = pca953x_get_bit_mask(chip, off);
667
581
668
582
guard(mutex)(&chip->i2c_lock);
669
583
670
-
return regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
584
+
return regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0);
671
585
}
672
586
673
587
static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
674
588
{
675
589
struct pca953x_chip *chip = gpiochip_get_data(gc);
676
590
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
677
-
u8 bit = BIT(off % BANK_SZ);
591
+
u8 bit = pca953x_get_bit_mask(chip, off);
678
592
u32 reg_val;
679
593
int ret;
680
594
···
683
597
if (ret < 0)
684
598
return ret;
685
599
686
-
if (reg_val & bit)
600
+
/* (in/out logic is inverted on TCA6418) */
601
+
if (reg_val & bit) {
602
+
if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE)
603
+
return GPIO_LINE_DIRECTION_OUT;
604
+
605
+
return GPIO_LINE_DIRECTION_IN;
606
+
}
607
+
if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE)
687
608
return GPIO_LINE_DIRECTION_IN;
688
609
689
610
return GPIO_LINE_DIRECTION_OUT;
···
751
658
752
659
/* Configure pull-up/pull-down */
753
660
if (param == PIN_CONFIG_BIAS_PULL_UP)
754
-
ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
661
+
ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, bit);
755
662
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
756
-
ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
663
+
ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, 0);
757
664
else
758
665
ret = 0;
759
666
if (ret)
···
761
668
762
669
/* Disable/Enable pull-up/pull-down */
763
670
if (param == PIN_CONFIG_BIAS_DISABLE)
764
-
return regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
671
+
return regmap_update_bits(chip->regmap, pull_en_reg, bit, 0);
765
672
else
766
-
return regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
673
+
return regmap_update_bits(chip->regmap, pull_en_reg, bit, bit);
767
674
}
768
675
769
676
static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
···
1210
1117
regmap_config = &pca953x_i2c_regmap;
1211
1118
}
1212
1119
1213
-
if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
1120
+
switch (PCA_CHIP_TYPE(chip->driver_data)) {
1121
+
case PCAL653X_TYPE:
1214
1122
chip->recalc_addr = pcal6534_recalc_addr;
1215
1123
chip->check_reg = pcal6534_check_register;
1216
-
} else {
1124
+
break;
1125
+
case TCA6418_TYPE:
1126
+
chip->recalc_addr = tca6418_recalc_addr;
1127
+
/*
1128
+
* We don't assign chip->check_reg = tca6418_check_register directly here.
1129
+
* Instead, the wrappers handle the dispatch based on PCA_CHIP_TYPE.
1130
+
*/
1131
+
break;
1132
+
default:
1217
1133
chip->recalc_addr = pca953x_recalc_addr;
1218
1134
chip->check_reg = pca953x_check_register;
1135
+
break;
1219
1136
}
1220
1137
1221
1138
chip->regmap = devm_regmap_init_i2c(client, regmap_config);
···
1254
1151
lockdep_set_subclass(&chip->i2c_lock,
1255
1152
i2c_adapter_depth(client->adapter));
1256
1153
1257
-
/* initialize cached registers from their original values.
1154
+
/*
1155
+
* initialize cached registers from their original values.
1258
1156
* we can't share this chip with another i2c master.
1259
1157
*/
1260
-
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1158
+
switch (PCA_CHIP_TYPE(chip->driver_data)) {
1159
+
case PCA957X_TYPE:
1261
1160
chip->regs = &pca957x_regs;
1262
1161
ret = device_pca957x_init(chip);
1263
-
} else {
1162
+
break;
1163
+
case TCA6418_TYPE:
1164
+
chip->regs = &tca6418_regs;
1165
+
break;
1166
+
default:
1264
1167
chip->regs = &pca953x_regs;
1265
1168
ret = device_pca95xx_init(chip);
1169
+
break;
1266
1170
}
1267
1171
if (ret)
1268
1172
return ret;
···
1435
1325
{ .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1436
1326
{ .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1437
1327
{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1328
+
{ .compatible = "ti,tca6418", .data = (void *)(18 | TCA6418_TYPE | PCA_INT), },
1438
1329
{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1439
1330
{ .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), },
1440
1331
{ .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), },
···
1466
1355
{
1467
1356
return i2c_add_driver(&pca953x_driver);
1468
1357
}
1469
-
/* register after i2c postcore initcall and before
1358
+
1359
+
/*
1360
+
* register after i2c postcore initcall and before
1470
1361
* subsys initcalls that may rely on these GPIOs
1471
1362
*/
1472
1363
subsys_initcall(pca953x_init);
+3
-2
drivers/gpio/gpio-pca9570.c
+3
-2
drivers/gpio/gpio-pca9570.c
···
88
88
return !!(buffer & BIT(offset));
89
89
}
90
90
91
-
static void pca9570_set(struct gpio_chip *chip, unsigned offset, int value)
91
+
static int pca9570_set(struct gpio_chip *chip, unsigned int offset, int value)
92
92
{
93
93
struct pca9570 *gpio = gpiochip_get_data(chip);
94
94
u8 buffer;
···
110
110
111
111
out:
112
112
mutex_unlock(&gpio->lock);
113
+
return ret;
113
114
}
114
115
115
116
static int pca9570_probe(struct i2c_client *client)
···
126
125
gpio->chip.owner = THIS_MODULE;
127
126
gpio->chip.get_direction = pca9570_get_direction;
128
127
gpio->chip.get = pca9570_get;
129
-
gpio->chip.set = pca9570_set;
128
+
gpio->chip.set_rv = pca9570_set;
130
129
gpio->chip.base = -1;
131
130
gpio->chip_data = device_get_match_data(&client->dev);
132
131
gpio->chip.ngpio = gpio->chip_data->ngpio;
+10
-7
drivers/gpio/gpio-pcf857x.c
+10
-7
drivers/gpio/gpio-pcf857x.c
···
171
171
return status;
172
172
}
173
173
174
-
static void pcf857x_set(struct gpio_chip *chip, unsigned int offset, int value)
174
+
static int pcf857x_set(struct gpio_chip *chip, unsigned int offset, int value)
175
175
{
176
-
pcf857x_output(chip, offset, value);
176
+
return pcf857x_output(chip, offset, value);
177
177
}
178
178
179
-
static void pcf857x_set_multiple(struct gpio_chip *chip, unsigned long *mask,
180
-
unsigned long *bits)
179
+
static int pcf857x_set_multiple(struct gpio_chip *chip, unsigned long *mask,
180
+
unsigned long *bits)
181
181
{
182
182
struct pcf857x *gpio = gpiochip_get_data(chip);
183
+
int status;
183
184
184
185
mutex_lock(&gpio->lock);
185
186
gpio->out &= ~*mask;
186
187
gpio->out |= *bits & *mask;
187
-
gpio->write(gpio->client, gpio->out);
188
+
status = gpio->write(gpio->client, gpio->out);
188
189
mutex_unlock(&gpio->lock);
190
+
191
+
return status;
189
192
}
190
193
191
194
/*-------------------------------------------------------------------------*/
···
295
292
gpio->chip.owner = THIS_MODULE;
296
293
gpio->chip.get = pcf857x_get;
297
294
gpio->chip.get_multiple = pcf857x_get_multiple;
298
-
gpio->chip.set = pcf857x_set;
299
-
gpio->chip.set_multiple = pcf857x_set_multiple;
295
+
gpio->chip.set_rv = pcf857x_set;
296
+
gpio->chip.set_multiple_rv = pcf857x_set_multiple;
300
297
gpio->chip.direction_input = pcf857x_input;
301
298
gpio->chip.direction_output = pcf857x_output;
302
299
gpio->chip.ngpio = (uintptr_t)i2c_get_match_data(client);
+4
-2
drivers/gpio/gpio-pch.c
+4
-2
drivers/gpio/gpio-pch.c
···
99
99
spinlock_t spinlock;
100
100
};
101
101
102
-
static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
102
+
static int pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
103
103
{
104
104
u32 reg_val;
105
105
struct pch_gpio *chip = gpiochip_get_data(gpio);
···
114
114
115
115
iowrite32(reg_val, &chip->reg->po);
116
116
spin_unlock_irqrestore(&chip->spinlock, flags);
117
+
118
+
return 0;
117
119
}
118
120
119
121
static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
···
219
217
gpio->direction_input = pch_gpio_direction_input;
220
218
gpio->get = pch_gpio_get;
221
219
gpio->direction_output = pch_gpio_direction_output;
222
-
gpio->set = pch_gpio_set;
220
+
gpio->set_rv = pch_gpio_set;
223
221
gpio->base = -1;
224
222
gpio->ngpio = gpio_pins[chip->ioh];
225
223
gpio->can_sleep = false;
-8
drivers/gpio/gpio-pisosr.c
-8
drivers/gpio/gpio-pisosr.c
···
67
67
return 0;
68
68
}
69
69
70
-
static int pisosr_gpio_direction_output(struct gpio_chip *chip,
71
-
unsigned offset, int value)
72
-
{
73
-
/* This device is input only */
74
-
return -EINVAL;
75
-
}
76
-
77
70
static int pisosr_gpio_get(struct gpio_chip *chip, unsigned offset)
78
71
{
79
72
struct pisosr_gpio *gpio = gpiochip_get_data(chip);
···
101
108
.owner = THIS_MODULE,
102
109
.get_direction = pisosr_gpio_get_direction,
103
110
.direction_input = pisosr_gpio_direction_input,
104
-
.direction_output = pisosr_gpio_direction_output,
105
111
.get = pisosr_gpio_get,
106
112
.get_multiple = pisosr_gpio_get_multiple,
107
113
.base = -1,
+4
-2
drivers/gpio/gpio-pl061.c
+4
-2
drivers/gpio/gpio-pl061.c
···
115
115
return !!readb(pl061->base + (BIT(offset + 2)));
116
116
}
117
117
118
-
static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
118
+
static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int value)
119
119
{
120
120
struct pl061 *pl061 = gpiochip_get_data(gc);
121
121
122
122
writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
123
+
124
+
return 0;
123
125
}
124
126
125
127
static int pl061_irq_type(struct irq_data *d, unsigned trigger)
···
330
328
pl061->gc.direction_input = pl061_direction_input;
331
329
pl061->gc.direction_output = pl061_direction_output;
332
330
pl061->gc.get = pl061_get_value;
333
-
pl061->gc.set = pl061_set_value;
331
+
pl061->gc.set_rv = pl061_set_value;
334
332
pl061->gc.ngpio = PL061_GPIO_NR;
335
333
pl061->gc.label = dev_name(dev);
336
334
pl061->gc.parent = dev;
-7
drivers/gpio/gpio-pmic-eic-sprd.c
-7
drivers/gpio/gpio-pmic-eic-sprd.c
···
109
109
return 0;
110
110
}
111
111
112
-
static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
113
-
int value)
114
-
{
115
-
/* EICs are always input, nothing need to do here. */
116
-
}
117
-
118
112
static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
119
113
unsigned int offset,
120
114
unsigned int debounce)
···
345
351
pmic_eic->chip.request = sprd_pmic_eic_request;
346
352
pmic_eic->chip.free = sprd_pmic_eic_free;
347
353
pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
348
-
pmic_eic->chip.set = sprd_pmic_eic_set;
349
354
pmic_eic->chip.get = sprd_pmic_eic_get;
350
355
pmic_eic->chip.can_sleep = true;
351
356
+6
-5
drivers/gpio/gpio-pxa.c
+6
-5
drivers/gpio/gpio-pxa.c
···
315
315
return !!(gplr & GPIO_bit(offset));
316
316
}
317
317
318
-
static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
318
+
static int pxa_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
319
319
{
320
320
void __iomem *base = gpio_bank_base(chip, offset);
321
321
322
322
writel_relaxed(GPIO_bit(offset),
323
323
base + (value ? GPSR_OFFSET : GPCR_OFFSET));
324
+
325
+
return 0;
324
326
}
325
327
326
328
#ifdef CONFIG_OF_GPIO
···
355
353
pchip->chip.direction_input = pxa_gpio_direction_input;
356
354
pchip->chip.direction_output = pxa_gpio_direction_output;
357
355
pchip->chip.get = pxa_gpio_get;
358
-
pchip->chip.set = pxa_gpio_set;
356
+
pchip->chip.set_rv = pxa_gpio_set;
359
357
pchip->chip.to_irq = pxa_gpio_to_irq;
360
358
pchip->chip.ngpio = ngpio;
361
359
pchip->chip.request = gpiochip_generic_request;
···
644
642
if (!pxa_last_gpio)
645
643
return -EINVAL;
646
644
647
-
pchip->irqdomain = irq_domain_create_legacy(of_fwnode_handle(pdev->dev.of_node),
648
-
pxa_last_gpio + 1, irq_base, 0,
649
-
&pxa_irq_domain_ops, pchip);
645
+
pchip->irqdomain = irq_domain_create_legacy(dev_fwnode(&pdev->dev), pxa_last_gpio + 1,
646
+
irq_base, 0, &pxa_irq_domain_ops, pchip);
650
647
if (!pchip->irqdomain)
651
648
return -ENOMEM;
652
649
+7
-3
drivers/gpio/gpio-raspberrypi-exp.c
+7
-3
drivers/gpio/gpio-raspberrypi-exp.c
···
175
175
return !!get.state;
176
176
}
177
177
178
-
static void rpi_exp_gpio_set(struct gpio_chip *gc, unsigned int off, int val)
178
+
static int rpi_exp_gpio_set(struct gpio_chip *gc, unsigned int off, int val)
179
179
{
180
180
struct rpi_exp_gpio *gpio;
181
181
struct gpio_get_set_state set;
···
188
188
189
189
ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_SET_GPIO_STATE,
190
190
&set, sizeof(set));
191
-
if (ret || set.gpio != 0)
191
+
if (ret || set.gpio != 0) {
192
192
dev_err(gc->parent,
193
193
"Failed to set GPIO %u state (%d %x)\n", off, ret,
194
194
set.gpio);
195
+
return ret ? ret : -EIO;
196
+
}
197
+
198
+
return 0;
195
199
}
196
200
197
201
static int rpi_exp_gpio_probe(struct platform_device *pdev)
···
232
228
rpi_gpio->gc.direction_output = rpi_exp_gpio_dir_out;
233
229
rpi_gpio->gc.get_direction = rpi_exp_gpio_get_direction;
234
230
rpi_gpio->gc.get = rpi_exp_gpio_get;
235
-
rpi_gpio->gc.set = rpi_exp_gpio_set;
231
+
rpi_gpio->gc.set_rv = rpi_exp_gpio_set;
236
232
rpi_gpio->gc.can_sleep = true;
237
233
238
234
return devm_gpiochip_add_data(dev, &rpi_gpio->gc, rpi_gpio);
+14
-5
drivers/gpio/gpio-rc5t583.c
+14
-5
drivers/gpio/gpio-rc5t583.c
···
35
35
return !!(val & BIT(offset));
36
36
}
37
37
38
-
static void rc5t583_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
38
+
static int rc5t583_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
39
39
{
40
40
struct rc5t583_gpio *rc5t583_gpio = gpiochip_get_data(gc);
41
41
struct device *parent = rc5t583_gpio->rc5t583->dev;
42
+
int ret;
43
+
42
44
if (val)
43
-
rc5t583_set_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
45
+
ret = rc5t583_set_bits(parent, RC5T583_GPIO_IOOUT,
46
+
BIT(offset));
44
47
else
45
-
rc5t583_clear_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
48
+
ret = rc5t583_clear_bits(parent, RC5T583_GPIO_IOOUT,
49
+
BIT(offset));
50
+
51
+
return ret;
46
52
}
47
53
48
54
static int rc5t583_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
···
72
66
struct device *parent = rc5t583_gpio->rc5t583->dev;
73
67
int ret;
74
68
75
-
rc5t583_gpio_set(gc, offset, value);
69
+
ret = rc5t583_gpio_set(gc, offset, value);
70
+
if (ret)
71
+
return ret;
72
+
76
73
ret = rc5t583_set_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset));
77
74
if (ret < 0)
78
75
return ret;
···
118
109
rc5t583_gpio->gpio_chip.free = rc5t583_gpio_free,
119
110
rc5t583_gpio->gpio_chip.direction_input = rc5t583_gpio_dir_input,
120
111
rc5t583_gpio->gpio_chip.direction_output = rc5t583_gpio_dir_output,
121
-
rc5t583_gpio->gpio_chip.set = rc5t583_gpio_set,
112
+
rc5t583_gpio->gpio_chip.set_rv = rc5t583_gpio_set,
122
113
rc5t583_gpio->gpio_chip.get = rc5t583_gpio_get,
123
114
rc5t583_gpio->gpio_chip.to_irq = rc5t583_gpio_to_irq,
124
115
rc5t583_gpio->gpio_chip.ngpio = RC5T583_MAX_GPIO,
+16
-19
drivers/gpio/gpio-rcar.c
+16
-19
drivers/gpio/gpio-rcar.c
···
331
331
static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
332
332
unsigned long *bits)
333
333
{
334
+
u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
334
335
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
335
-
u32 bankmask, outputs, m, val = 0;
336
+
u32 outputs, m, val = 0;
336
337
unsigned long flags;
337
-
338
-
bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
339
-
if (!bankmask)
340
-
return 0;
341
338
342
339
if (p->info.has_always_in) {
343
340
bits[0] = gpio_rcar_read(p, INDT) & bankmask;
···
356
359
return 0;
357
360
}
358
361
359
-
static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
362
+
static int gpio_rcar_set(struct gpio_chip *chip, unsigned int offset, int value)
360
363
{
361
364
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
362
365
unsigned long flags;
···
364
367
raw_spin_lock_irqsave(&p->lock, flags);
365
368
gpio_rcar_modify_bit(p, OUTDT, offset, value);
366
369
raw_spin_unlock_irqrestore(&p->lock, flags);
370
+
371
+
return 0;
367
372
}
368
373
369
-
static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
370
-
unsigned long *bits)
374
+
static int gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
375
+
unsigned long *bits)
371
376
{
377
+
u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
372
378
struct gpio_rcar_priv *p = gpiochip_get_data(chip);
373
379
unsigned long flags;
374
-
u32 val, bankmask;
375
-
376
-
bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
377
-
if (!bankmask)
378
-
return;
380
+
u32 val;
379
381
380
382
raw_spin_lock_irqsave(&p->lock, flags);
381
383
val = gpio_rcar_read(p, OUTDT);
···
382
386
val |= (bankmask & bits[0]);
383
387
gpio_rcar_write(p, OUTDT, val);
384
388
raw_spin_unlock_irqrestore(&p->lock, flags);
389
+
390
+
return 0;
385
391
}
386
392
387
393
static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
···
535
537
gpio_chip->get = gpio_rcar_get;
536
538
gpio_chip->get_multiple = gpio_rcar_get_multiple;
537
539
gpio_chip->direction_output = gpio_rcar_direction_output;
538
-
gpio_chip->set = gpio_rcar_set;
539
-
gpio_chip->set_multiple = gpio_rcar_set_multiple;
540
+
gpio_chip->set_rv = gpio_rcar_set;
541
+
gpio_chip->set_multiple_rv = gpio_rcar_set_multiple;
540
542
gpio_chip->label = name;
541
543
gpio_chip->parent = dev;
542
544
gpio_chip->owner = THIS_MODULE;
···
592
594
pm_runtime_disable(&pdev->dev);
593
595
}
594
596
595
-
#ifdef CONFIG_PM_SLEEP
596
597
static int gpio_rcar_suspend(struct device *dev)
597
598
{
598
599
struct gpio_rcar_priv *p = dev_get_drvdata(dev);
···
650
653
651
654
return 0;
652
655
}
653
-
#endif /* CONFIG_PM_SLEEP*/
654
656
655
-
static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
657
+
static DEFINE_SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend,
658
+
gpio_rcar_resume);
656
659
657
660
static struct platform_driver gpio_rcar_device_driver = {
658
661
.probe = gpio_rcar_probe,
659
662
.remove = gpio_rcar_remove,
660
663
.driver = {
661
664
.name = "gpio_rcar",
662
-
.pm = &gpio_rcar_pm_ops,
665
+
.pm = pm_sleep_ptr(&gpio_rcar_pm_ops),
663
666
.of_match_table = gpio_rcar_of_table,
664
667
}
665
668
};
+5
-3
drivers/gpio/gpio-rdc321x.c
+5
-3
drivers/gpio/gpio-rdc321x.c
···
64
64
}
65
65
66
66
/* set GPIO pin to value */
67
-
static void rdc_gpio_set_value(struct gpio_chip *chip,
68
-
unsigned gpio, int value)
67
+
static int rdc_gpio_set_value(struct gpio_chip *chip, unsigned int gpio,
68
+
int value)
69
69
{
70
70
struct rdc321x_gpio *gpch;
71
71
···
73
73
spin_lock(&gpch->lock);
74
74
rdc_gpio_set_value_impl(chip, gpio, value);
75
75
spin_unlock(&gpch->lock);
76
+
77
+
return 0;
76
78
}
77
79
78
80
static int rdc_gpio_config(struct gpio_chip *chip,
···
159
157
rdc321x_gpio_dev->chip.direction_input = rdc_gpio_direction_input;
160
158
rdc321x_gpio_dev->chip.direction_output = rdc_gpio_config;
161
159
rdc321x_gpio_dev->chip.get = rdc_gpio_get_value;
162
-
rdc321x_gpio_dev->chip.set = rdc_gpio_set_value;
160
+
rdc321x_gpio_dev->chip.set_rv = rdc_gpio_set_value;
163
161
rdc321x_gpio_dev->chip.base = 0;
164
162
rdc321x_gpio_dev->chip.ngpio = pdata->max_gpios;
165
163
+10
-6
drivers/gpio/gpio-reg.c
+10
-6
drivers/gpio/gpio-reg.c
···
46
46
if (r->direction & BIT(offset))
47
47
return -ENOTSUPP;
48
48
49
-
gc->set(gc, offset, value);
49
+
gc->set_rv(gc, offset, value);
50
50
return 0;
51
51
}
52
52
···
57
57
return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
58
58
}
59
59
60
-
static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value)
60
+
static int gpio_reg_set(struct gpio_chip *gc, unsigned int offset, int value)
61
61
{
62
62
struct gpio_reg *r = to_gpio_reg(gc);
63
63
unsigned long flags;
···
72
72
r->out = val;
73
73
writel_relaxed(val, r->reg);
74
74
spin_unlock_irqrestore(&r->lock, flags);
75
+
76
+
return 0;
75
77
}
76
78
77
79
static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
···
94
92
return !!(val & mask);
95
93
}
96
94
97
-
static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
98
-
unsigned long *bits)
95
+
static int gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
96
+
unsigned long *bits)
99
97
{
100
98
struct gpio_reg *r = to_gpio_reg(gc);
101
99
unsigned long flags;
···
104
102
r->out = (r->out & ~*mask) | (*bits & *mask);
105
103
writel_relaxed(r->out, r->reg);
106
104
spin_unlock_irqrestore(&r->lock, flags);
105
+
106
+
return 0;
107
107
}
108
108
109
109
static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
···
161
157
r->gc.get_direction = gpio_reg_get_direction;
162
158
r->gc.direction_input = gpio_reg_direction_input;
163
159
r->gc.direction_output = gpio_reg_direction_output;
164
-
r->gc.set = gpio_reg_set;
160
+
r->gc.set_rv = gpio_reg_set;
165
161
r->gc.get = gpio_reg_get;
166
-
r->gc.set_multiple = gpio_reg_set_multiple;
162
+
r->gc.set_multiple_rv = gpio_reg_set_multiple;
167
163
if (irqs)
168
164
r->gc.to_irq = gpio_reg_to_irq;
169
165
r->gc.base = base;
+7
-5
drivers/gpio/gpio-rockchip.c
+7
-5
drivers/gpio/gpio-rockchip.c
···
177
177
return 0;
178
178
}
179
179
180
-
static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
181
-
int value)
180
+
static int rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
181
+
int value)
182
182
{
183
183
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
184
184
unsigned long flags;
···
186
186
raw_spin_lock_irqsave(&bank->slock, flags);
187
187
rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
188
188
raw_spin_unlock_irqrestore(&bank->slock, flags);
189
+
190
+
return 0;
189
191
}
190
192
191
193
static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
···
327
325
static const struct gpio_chip rockchip_gpiolib_chip = {
328
326
.request = gpiochip_generic_request,
329
327
.free = gpiochip_generic_free,
330
-
.set = rockchip_gpio_set,
328
+
.set_rv = rockchip_gpio_set,
331
329
.get = rockchip_gpio_get,
332
330
.get_direction = rockchip_gpio_get_direction,
333
331
.direction_input = rockchip_gpio_direction_input,
···
523
521
struct irq_chip_generic *gc;
524
522
int ret;
525
523
526
-
bank->domain = irq_domain_create_linear(of_fwnode_handle(bank->of_node), 32,
527
-
&irq_generic_chip_ops, NULL);
524
+
bank->domain = irq_domain_create_linear(dev_fwnode(bank->dev), 32, &irq_generic_chip_ops,
525
+
NULL);
528
526
if (!bank->domain) {
529
527
dev_warn(bank->dev, "could not init irq domain for bank %s\n",
530
528
bank->name);
+4
-2
drivers/gpio/gpio-rtd.c
+4
-2
drivers/gpio/gpio-rtd.c
···
275
275
}
276
276
}
277
277
278
-
static void rtd_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
278
+
static int rtd_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
279
279
{
280
280
struct rtd_gpio *data = gpiochip_get_data(chip);
281
281
u32 mask = BIT(offset % 32);
···
292
292
else
293
293
val &= ~mask;
294
294
writel_relaxed(val, data->base + dato_reg_offset);
295
+
296
+
return 0;
295
297
}
296
298
297
299
static int rtd_gpio_get(struct gpio_chip *chip, unsigned int offset)
···
565
563
data->gpio_chip.get_direction = rtd_gpio_get_direction;
566
564
data->gpio_chip.direction_input = rtd_gpio_direction_input;
567
565
data->gpio_chip.direction_output = rtd_gpio_direction_output;
568
-
data->gpio_chip.set = rtd_gpio_set;
566
+
data->gpio_chip.set_rv = rtd_gpio_set;
569
567
data->gpio_chip.get = rtd_gpio_get;
570
568
data->gpio_chip.set_config = rtd_gpio_set_config;
571
569
data->gpio_chip.parent = dev;
+5
-2
drivers/gpio/gpio-sa1100.c
+5
-2
drivers/gpio/gpio-sa1100.c
···
43
43
BIT(offset);
44
44
}
45
45
46
-
static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
46
+
static int sa1100_gpio_set(struct gpio_chip *chip, unsigned int offset,
47
+
int value)
47
48
{
48
49
int reg = value ? R_GPSR : R_GPCR;
49
50
50
51
writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
52
+
53
+
return 0;
51
54
}
52
55
53
56
static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset)
···
99
96
.get_direction = sa1100_get_direction,
100
97
.direction_input = sa1100_direction_input,
101
98
.direction_output = sa1100_direction_output,
102
-
.set = sa1100_gpio_set,
99
+
.set_rv = sa1100_gpio_set,
103
100
.get = sa1100_gpio_get,
104
101
.to_irq = sa1100_to_irq,
105
102
.base = 0,
+4
-4
drivers/gpio/gpio-sama5d2-piobu.c
+4
-4
drivers/gpio/gpio-sama5d2-piobu.c
···
169
169
/*
170
170
* sama5d2_piobu_set() - gpiochip set
171
171
*/
172
-
static void sama5d2_piobu_set(struct gpio_chip *chip, unsigned int pin,
173
-
int value)
172
+
static int sama5d2_piobu_set(struct gpio_chip *chip, unsigned int pin,
173
+
int value)
174
174
{
175
175
if (!value)
176
176
value = PIOBU_LOW;
177
177
else
178
178
value = PIOBU_HIGH;
179
179
180
-
sama5d2_piobu_write_value(chip, pin, PIOBU_SOD, value);
180
+
return sama5d2_piobu_write_value(chip, pin, PIOBU_SOD, value);
181
181
}
182
182
183
183
static int sama5d2_piobu_probe(struct platform_device *pdev)
···
196
196
piobu->chip.direction_input = sama5d2_piobu_direction_input;
197
197
piobu->chip.direction_output = sama5d2_piobu_direction_output;
198
198
piobu->chip.get = sama5d2_piobu_get;
199
-
piobu->chip.set = sama5d2_piobu_set;
199
+
piobu->chip.set_rv = sama5d2_piobu_set;
200
200
piobu->chip.base = -1;
201
201
piobu->chip.ngpio = PIOBU_NUM;
202
202
piobu->chip.can_sleep = 0;
+5
-4
drivers/gpio/gpio-sch.c
+5
-4
drivers/gpio/gpio-sch.c
···
117
117
return sch_gpio_reg_get(sch, gpio_num, GLV);
118
118
}
119
119
120
-
static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
120
+
static int sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
121
121
{
122
122
struct sch_gpio *sch = gpiochip_get_data(gc);
123
123
unsigned long flags;
···
125
125
spin_lock_irqsave(&sch->lock, flags);
126
126
sch_gpio_reg_set(sch, gpio_num, GLV, val);
127
127
spin_unlock_irqrestore(&sch->lock, flags);
128
+
129
+
return 0;
128
130
}
129
131
130
132
static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
···
148
146
* But we cannot prevent a short low pulse if direction is set to high
149
147
* and an external pull-up is connected.
150
148
*/
151
-
sch_gpio_set(gc, gpio_num, val);
152
-
return 0;
149
+
return sch_gpio_set(gc, gpio_num, val);
153
150
}
154
151
155
152
static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
···
167
166
.direction_input = sch_gpio_direction_in,
168
167
.get = sch_gpio_get,
169
168
.direction_output = sch_gpio_direction_out,
170
-
.set = sch_gpio_set,
169
+
.set_rv = sch_gpio_set,
171
170
.get_direction = sch_gpio_get_direction,
172
171
};
173
172
+5
-3
drivers/gpio/gpio-sch311x.c
+5
-3
drivers/gpio/gpio-sch311x.c
···
178
178
outb(data, block->runtime_reg + block->data_reg);
179
179
}
180
180
181
-
static void sch311x_gpio_set(struct gpio_chip *chip, unsigned offset,
182
-
int value)
181
+
static int sch311x_gpio_set(struct gpio_chip *chip, unsigned int offset,
182
+
int value)
183
183
{
184
184
struct sch311x_gpio_block *block = gpiochip_get_data(chip);
185
185
186
186
spin_lock(&block->lock);
187
187
__sch311x_gpio_set(block, offset, value);
188
188
spin_unlock(&block->lock);
189
+
190
+
return 0;
189
191
}
190
192
191
193
static int sch311x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
···
297
295
block->chip.get_direction = sch311x_gpio_get_direction;
298
296
block->chip.set_config = sch311x_gpio_set_config;
299
297
block->chip.get = sch311x_gpio_get;
300
-
block->chip.set = sch311x_gpio_set;
298
+
block->chip.set_rv = sch311x_gpio_set;
301
299
block->chip.ngpio = 8;
302
300
block->chip.parent = &pdev->dev;
303
301
block->chip.base = sch311x_gpio_blocks[i].base;
+81
-2
drivers/gpio/gpio-sim.c
+81
-2
drivers/gpio/gpio-sim.c
···
39
39
#include "dev-sync-probe.h"
40
40
41
41
#define GPIO_SIM_NGPIO_MAX 1024
42
-
#define GPIO_SIM_PROP_MAX 4 /* Max 3 properties + sentinel. */
42
+
#define GPIO_SIM_PROP_MAX 5 /* Max 4 properties + sentinel. */
43
43
#define GPIO_SIM_NUM_ATTRS 3 /* value, pull and sentinel */
44
44
45
45
static DEFINE_IDA(gpio_sim_ida);
···
629
629
630
630
unsigned int offset;
631
631
char *name;
632
+
bool valid;
632
633
633
634
/* There can only be one hog per line. */
634
635
struct gpio_sim_hog *hog;
···
745
744
}
746
745
}
747
746
747
+
static unsigned int gpio_sim_get_reserved_ranges_size(struct gpio_sim_bank *bank)
748
+
{
749
+
struct gpio_sim_line *line;
750
+
unsigned int size = 0;
751
+
752
+
list_for_each_entry(line, &bank->line_list, siblings) {
753
+
if (line->valid)
754
+
continue;
755
+
756
+
size += 2;
757
+
}
758
+
759
+
return size;
760
+
}
761
+
762
+
static void gpio_sim_set_reserved_ranges(struct gpio_sim_bank *bank,
763
+
u32 *ranges)
764
+
{
765
+
struct gpio_sim_line *line;
766
+
int i = 0;
767
+
768
+
list_for_each_entry(line, &bank->line_list, siblings) {
769
+
if (line->valid)
770
+
continue;
771
+
772
+
ranges[i++] = line->offset;
773
+
ranges[i++] = 1;
774
+
}
775
+
}
776
+
748
777
static void gpio_sim_remove_hogs(struct gpio_sim_device *dev)
749
778
{
750
779
struct gpiod_hog *hog;
···
875
844
gpio_sim_make_bank_swnode(struct gpio_sim_bank *bank,
876
845
struct fwnode_handle *parent)
877
846
{
847
+
unsigned int prop_idx = 0, line_names_size, ranges_size;
878
848
struct property_entry properties[GPIO_SIM_PROP_MAX];
879
-
unsigned int prop_idx = 0, line_names_size;
880
849
char **line_names __free(kfree) = NULL;
850
+
u32 *ranges __free(kfree) = NULL;
881
851
882
852
memset(properties, 0, sizeof(properties));
883
853
···
900
868
properties[prop_idx++] = PROPERTY_ENTRY_STRING_ARRAY_LEN(
901
869
"gpio-line-names",
902
870
line_names, line_names_size);
871
+
}
872
+
873
+
ranges_size = gpio_sim_get_reserved_ranges_size(bank);
874
+
if (ranges_size) {
875
+
ranges = kcalloc(ranges_size, sizeof(u32), GFP_KERNEL);
876
+
if (!ranges)
877
+
return ERR_PTR(-ENOMEM);
878
+
879
+
gpio_sim_set_reserved_ranges(bank, ranges);
880
+
881
+
properties[prop_idx++] = PROPERTY_ENTRY_U32_ARRAY_LEN(
882
+
"gpio-reserved-ranges",
883
+
ranges, ranges_size);
903
884
}
904
885
905
886
return fwnode_create_software_node(properties, parent);
···
1234
1189
1235
1190
CONFIGFS_ATTR(gpio_sim_line_config_, name);
1236
1191
1192
+
static ssize_t
1193
+
gpio_sim_line_config_valid_show(struct config_item *item, char *page)
1194
+
{
1195
+
struct gpio_sim_line *line = to_gpio_sim_line(item);
1196
+
struct gpio_sim_device *dev = gpio_sim_line_get_device(line);
1197
+
1198
+
guard(mutex)(&dev->lock);
1199
+
1200
+
return sprintf(page, "%c\n", line->valid ? '1' : '0');
1201
+
}
1202
+
1203
+
static ssize_t gpio_sim_line_config_valid_store(struct config_item *item,
1204
+
const char *page, size_t count)
1205
+
{
1206
+
struct gpio_sim_line *line = to_gpio_sim_line(item);
1207
+
struct gpio_sim_device *dev = gpio_sim_line_get_device(line);
1208
+
bool valid;
1209
+
int ret;
1210
+
1211
+
ret = kstrtobool(page, &valid);
1212
+
if (ret)
1213
+
return ret;
1214
+
1215
+
guard(mutex)(&dev->lock);
1216
+
1217
+
line->valid = valid;
1218
+
1219
+
return count;
1220
+
}
1221
+
1222
+
CONFIGFS_ATTR(gpio_sim_line_config_, valid);
1223
+
1237
1224
static struct configfs_attribute *gpio_sim_line_config_attrs[] = {
1238
1225
&gpio_sim_line_config_attr_name,
1226
+
&gpio_sim_line_config_attr_valid,
1239
1227
NULL
1240
1228
};
1241
1229
···
1477
1399
1478
1400
line->parent = bank;
1479
1401
line->offset = offset;
1402
+
line->valid = true;
1480
1403
list_add_tail(&line->siblings, &bank->line_list);
1481
1404
1482
1405
return &line->group;
+6
-5
drivers/gpio/gpio-siox.c
+6
-5
drivers/gpio/gpio-siox.c
···
160
160
return ret;
161
161
}
162
162
163
-
static void gpio_siox_set(struct gpio_chip *chip,
164
-
unsigned int offset, int value)
163
+
static int gpio_siox_set(struct gpio_chip *chip,
164
+
unsigned int offset, int value)
165
165
{
166
166
struct gpio_siox_ddata *ddata = gpiochip_get_data(chip);
167
167
u8 mask = 1 << (19 - offset);
···
174
174
ddata->setdata[0] &= ~mask;
175
175
176
176
mutex_unlock(&ddata->lock);
177
+
178
+
return 0;
177
179
}
178
180
179
181
static int gpio_siox_direction_input(struct gpio_chip *chip,
···
193
191
if (offset < 12)
194
192
return -EINVAL;
195
193
196
-
gpio_siox_set(chip, offset, value);
197
-
return 0;
194
+
return gpio_siox_set(chip, offset, value);
198
195
}
199
196
200
197
static int gpio_siox_get_direction(struct gpio_chip *chip, unsigned int offset)
···
237
236
gc->parent = dev;
238
237
gc->owner = THIS_MODULE;
239
238
gc->get = gpio_siox_get;
240
-
gc->set = gpio_siox_set;
239
+
gc->set_rv = gpio_siox_set;
241
240
gc->direction_input = gpio_siox_direction_input;
242
241
gc->direction_output = gpio_siox_direction_output;
243
242
gc->get_direction = gpio_siox_get_direction;
+1
-1
drivers/gpio/gpio-sloppy-logic-analyzer.c
+1
-1
drivers/gpio/gpio-sloppy-logic-analyzer.c
+2
-2
drivers/gpio/gpio-sodaville.c
+2
-2
drivers/gpio/gpio-sodaville.c
···
169
169
IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
170
170
IRQ_LEVEL | IRQ_NOPROBE);
171
171
172
-
sd->id = irq_domain_create_legacy(of_fwnode_handle(pdev->dev.of_node), SDV_NUM_PUB_GPIOS,
173
-
sd->irq_base, 0, &irq_domain_sdv_ops, sd);
172
+
sd->id = irq_domain_create_legacy(dev_fwnode(&pdev->dev), SDV_NUM_PUB_GPIOS, sd->irq_base,
173
+
0, &irq_domain_sdv_ops, sd);
174
174
if (!sd->id)
175
175
return -ENODEV;
176
176
+5
-16
drivers/gpio/gpio-spear-spics.c
+5
-16
drivers/gpio/gpio-spear-spics.c
···
51
51
struct gpio_chip chip;
52
52
};
53
53
54
-
/* gpio framework specific routines */
55
-
static int spics_get_value(struct gpio_chip *chip, unsigned offset)
56
-
{
57
-
return -ENXIO;
58
-
}
59
-
60
-
static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
54
+
static int spics_set_value(struct gpio_chip *chip, unsigned int offset,
55
+
int value)
61
56
{
62
57
struct spear_spics *spics = gpiochip_get_data(chip);
63
58
u32 tmp;
···
69
74
tmp &= ~(0x1 << spics->cs_value_bit);
70
75
tmp |= value << spics->cs_value_bit;
71
76
writel_relaxed(tmp, spics->base + spics->perip_cfg);
72
-
}
73
77
74
-
static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
75
-
{
76
-
return -ENXIO;
78
+
return 0;
77
79
}
78
80
79
81
static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
80
82
int value)
81
83
{
82
-
spics_set_value(chip, offset, value);
83
-
return 0;
84
+
return spics_set_value(chip, offset, value);
84
85
}
85
86
86
87
static int spics_request(struct gpio_chip *chip, unsigned offset)
···
139
148
spics->chip.base = -1;
140
149
spics->chip.request = spics_request;
141
150
spics->chip.free = spics_free;
142
-
spics->chip.direction_input = spics_direction_input;
143
151
spics->chip.direction_output = spics_direction_output;
144
-
spics->chip.get = spics_get_value;
145
-
spics->chip.set = spics_set_value;
152
+
spics->chip.set_rv = spics_set_value;
146
153
spics->chip.label = dev_name(&pdev->dev);
147
154
spics->chip.parent = &pdev->dev;
148
155
spics->chip.owner = THIS_MODULE;
+5
-3
drivers/gpio/gpio-sprd.c
+5
-3
drivers/gpio/gpio-sprd.c
···
108
108
return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA);
109
109
}
110
110
111
-
static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
112
-
int value)
111
+
static int sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
112
+
int value)
113
113
{
114
114
sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
115
+
116
+
return 0;
115
117
}
116
118
117
119
static void sprd_gpio_irq_mask(struct irq_data *data)
···
245
243
sprd_gpio->chip.request = sprd_gpio_request;
246
244
sprd_gpio->chip.free = sprd_gpio_free;
247
245
sprd_gpio->chip.get = sprd_gpio_get;
248
-
sprd_gpio->chip.set = sprd_gpio_set;
246
+
sprd_gpio->chip.set_rv = sprd_gpio_set;
249
247
sprd_gpio->chip.direction_input = sprd_gpio_direction_input;
250
248
sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
251
249
+9
-6
drivers/gpio/gpio-stmpe.c
+9
-6
drivers/gpio/gpio-stmpe.c
···
54
54
return !!(ret & mask);
55
55
}
56
56
57
-
static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57
+
static int stmpe_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
58
58
{
59
59
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
60
60
struct stmpe *stmpe = stmpe_gpio->stmpe;
···
67
67
* For them we need to write 0 to clear and 1 to set.
68
68
*/
69
69
if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
70
-
stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
71
-
else
72
-
stmpe_reg_write(stmpe, reg, mask);
70
+
return stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
71
+
72
+
return stmpe_reg_write(stmpe, reg, mask);
73
73
}
74
74
75
75
static int stmpe_gpio_get_direction(struct gpio_chip *chip,
···
98
98
struct stmpe *stmpe = stmpe_gpio->stmpe;
99
99
u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
100
100
u8 mask = BIT(offset % 8);
101
+
int ret;
101
102
102
-
stmpe_gpio_set(chip, offset, val);
103
+
ret = stmpe_gpio_set(chip, offset, val);
104
+
if (ret)
105
+
return ret;
103
106
104
107
return stmpe_set_bits(stmpe, reg, mask, mask);
105
108
}
···
136
133
.direction_input = stmpe_gpio_direction_input,
137
134
.get = stmpe_gpio_get,
138
135
.direction_output = stmpe_gpio_direction_output,
139
-
.set = stmpe_gpio_set,
136
+
.set_rv = stmpe_gpio_set,
140
137
.request = stmpe_gpio_request,
141
138
.can_sleep = true,
142
139
};
+5
-5
drivers/gpio/gpio-stp-xway.c
+5
-5
drivers/gpio/gpio-stp-xway.c
···
113
113
*
114
114
* Set the shadow value and call ltq_ebu_apply.
115
115
*/
116
-
static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
116
+
static int xway_stp_set(struct gpio_chip *gc, unsigned int gpio, int val)
117
117
{
118
118
struct xway_stp *chip = gpiochip_get_data(gc);
119
119
···
124
124
xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
125
125
if (!chip->reserved)
126
126
xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
127
+
128
+
return 0;
127
129
}
128
130
129
131
/**
···
138
136
*/
139
137
static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
140
138
{
141
-
xway_stp_set(gc, gpio, val);
142
-
143
-
return 0;
139
+
return xway_stp_set(gc, gpio, val);
144
140
}
145
141
146
142
/**
···
249
249
chip->gc.label = "stp-xway";
250
250
chip->gc.direction_output = xway_stp_dir_out;
251
251
chip->gc.get = xway_stp_get;
252
-
chip->gc.set = xway_stp_set;
252
+
chip->gc.set_rv = xway_stp_set;
253
253
chip->gc.request = xway_stp_request;
254
254
chip->gc.base = -1;
255
255
chip->gc.owner = THIS_MODULE;
+18
-15
drivers/gpio/gpio-syscon.c
+18
-15
drivers/gpio/gpio-syscon.c
···
40
40
unsigned int bit_count;
41
41
unsigned int dat_bit_offset;
42
42
unsigned int dir_bit_offset;
43
-
void (*set)(struct gpio_chip *chip,
44
-
unsigned offset, int value);
43
+
int (*set)(struct gpio_chip *chip, unsigned int offset,
44
+
int value);
45
45
};
46
46
47
47
struct syscon_gpio_priv {
···
68
68
return !!(val & BIT(offs % SYSCON_REG_BITS));
69
69
}
70
70
71
-
static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
71
+
static int syscon_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
72
72
{
73
73
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
74
74
unsigned int offs;
75
75
76
76
offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
77
77
78
-
regmap_update_bits(priv->syscon,
79
-
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
80
-
BIT(offs % SYSCON_REG_BITS),
81
-
val ? BIT(offs % SYSCON_REG_BITS) : 0);
78
+
return regmap_update_bits(priv->syscon,
79
+
(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
80
+
BIT(offs % SYSCON_REG_BITS),
81
+
val ? BIT(offs % SYSCON_REG_BITS) : 0);
82
82
}
83
83
84
84
static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
···
115
115
BIT(offs % SYSCON_REG_BITS));
116
116
}
117
117
118
-
chip->set(chip, offset, val);
119
-
120
-
return 0;
118
+
return chip->set_rv(chip, offset, val);
121
119
}
122
120
123
121
static const struct syscon_gpio_data clps711x_mctrl_gpio = {
···
125
127
.dat_bit_offset = 0x40 * 8 + 8,
126
128
};
127
129
128
-
static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
129
-
int val)
130
+
static int rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
131
+
int val)
130
132
{
131
133
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
132
134
unsigned int offs;
···
142
144
data);
143
145
if (ret < 0)
144
146
dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
147
+
148
+
return ret;
145
149
}
146
150
147
151
static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
···
156
156
157
157
#define KEYSTONE_LOCK_BIT BIT(0)
158
158
159
-
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
159
+
static int keystone_gpio_set(struct gpio_chip *chip, unsigned int offset,
160
+
int val)
160
161
{
161
162
struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
162
163
unsigned int offs;
···
166
165
offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
167
166
168
167
if (!val)
169
-
return;
168
+
return 0;
170
169
171
170
ret = regmap_update_bits(
172
171
priv->syscon,
···
175
174
BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
176
175
if (ret < 0)
177
176
dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
177
+
178
+
return ret;
178
179
}
179
180
180
181
static const struct syscon_gpio_data keystone_dsp_gpio = {
···
251
248
if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
252
249
priv->chip.direction_input = syscon_gpio_dir_in;
253
250
if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
254
-
priv->chip.set = priv->data->set ? : syscon_gpio_set;
251
+
priv->chip.set_rv = priv->data->set ? : syscon_gpio_set;
255
252
priv->chip.direction_output = syscon_gpio_dir_out;
256
253
}
257
254
+4
-2
drivers/gpio/gpio-tangier.c
+4
-2
drivers/gpio/gpio-tangier.c
···
90
90
return !!(readl(gplr) & BIT(shift));
91
91
}
92
92
93
-
static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
93
+
static int tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
94
94
{
95
95
struct tng_gpio *priv = gpiochip_get_data(chip);
96
96
void __iomem *reg;
···
101
101
guard(raw_spinlock_irqsave)(&priv->lock);
102
102
103
103
writel(BIT(shift), reg);
104
+
105
+
return 0;
104
106
}
105
107
106
108
static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
···
430
428
gpio->chip.direction_input = tng_gpio_direction_input;
431
429
gpio->chip.direction_output = tng_gpio_direction_output;
432
430
gpio->chip.get = tng_gpio_get;
433
-
gpio->chip.set = tng_gpio_set;
431
+
gpio->chip.set_rv = tng_gpio_set;
434
432
gpio->chip.get_direction = tng_gpio_get_direction;
435
433
gpio->chip.set_config = tng_gpio_set_config;
436
434
gpio->chip.base = info->base;
+2
-3
drivers/gpio/gpio-tb10x.c
+2
-3
drivers/gpio/gpio-tb10x.c
···
183
183
if (ret != 0)
184
184
return ret;
185
185
186
-
tb10x_gpio->domain = irq_domain_create_linear(of_fwnode_handle(np),
187
-
tb10x_gpio->gc.ngpio,
188
-
&irq_generic_chip_ops, NULL);
186
+
tb10x_gpio->domain = irq_domain_create_linear(dev_fwnode(dev), tb10x_gpio->gc.ngpio,
187
+
&irq_generic_chip_ops, NULL);
189
188
if (!tb10x_gpio->domain) {
190
189
return -ENOMEM;
191
190
}
+7
-4
drivers/gpio/gpio-tc3589x.c
+7
-4
drivers/gpio/gpio-tc3589x.c
···
49
49
return !!(ret & mask);
50
50
}
51
51
52
-
static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
52
+
static int tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
53
53
{
54
54
struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
55
55
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
···
57
57
unsigned int pos = offset % 8;
58
58
u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
59
59
60
-
tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
60
+
return tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
61
61
}
62
62
63
63
static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
···
67
67
struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
68
68
u8 reg = TC3589x_GPIODIR0 + offset / 8;
69
69
unsigned int pos = offset % 8;
70
+
int ret;
70
71
71
-
tc3589x_gpio_set(chip, offset, val);
72
+
ret = tc3589x_gpio_set(chip, offset, val);
73
+
if (ret)
74
+
return ret;
72
75
73
76
return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
74
77
}
···
149
146
.label = "tc3589x",
150
147
.owner = THIS_MODULE,
151
148
.get = tc3589x_gpio_get,
152
-
.set = tc3589x_gpio_set,
149
+
.set_rv = tc3589x_gpio_set,
153
150
.direction_output = tc3589x_gpio_direction_output,
154
151
.direction_input = tc3589x_gpio_direction_input,
155
152
.get_direction = tc3589x_gpio_get_direction,
+5
-3
drivers/gpio/gpio-tegra.c
+5
-3
drivers/gpio/gpio-tegra.c
···
146
146
tegra_gpio_disable(tgi, offset);
147
147
}
148
148
149
-
static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
150
-
int value)
149
+
static int tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
150
+
int value)
151
151
{
152
152
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
153
153
154
154
tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
155
+
156
+
return 0;
155
157
}
156
158
157
159
static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
···
720
718
tgi->gc.direction_input = tegra_gpio_direction_input;
721
719
tgi->gc.get = tegra_gpio_get;
722
720
tgi->gc.direction_output = tegra_gpio_direction_output;
723
-
tgi->gc.set = tegra_gpio_set;
721
+
tgi->gc.set_rv = tegra_gpio_set;
724
722
tgi->gc.get_direction = tegra_gpio_get_direction;
725
723
tgi->gc.base = 0;
726
724
tgi->gc.ngpio = tgi->bank_count * 32;
+27
-22
drivers/gpio/gpio-tegra186.c
+27
-22
drivers/gpio/gpio-tegra186.c
···
202
202
return 0;
203
203
}
204
204
205
+
static int tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
206
+
int level)
207
+
{
208
+
struct tegra_gpio *gpio = gpiochip_get_data(chip);
209
+
void __iomem *base;
210
+
u32 value;
211
+
212
+
base = tegra186_gpio_get_base(gpio, offset);
213
+
if (WARN_ON(base == NULL))
214
+
return -ENODEV;
215
+
216
+
value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
217
+
if (level == 0)
218
+
value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
219
+
else
220
+
value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
221
+
222
+
writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
223
+
224
+
return 0;
225
+
}
226
+
205
227
static int tegra186_gpio_get_direction(struct gpio_chip *chip,
206
228
unsigned int offset)
207
229
{
···
271
249
struct tegra_gpio *gpio = gpiochip_get_data(chip);
272
250
void __iomem *base;
273
251
u32 value;
252
+
int ret;
274
253
275
254
/* configure output level first */
276
-
chip->set(chip, offset, level);
255
+
ret = tegra186_gpio_set(chip, offset, level);
256
+
if (ret)
257
+
return ret;
277
258
278
259
base = tegra186_gpio_get_base(gpio, offset);
279
260
if (WARN_ON(base == NULL))
···
382
357
value = readl(base + TEGRA186_GPIO_INPUT);
383
358
384
359
return value & BIT(0);
385
-
}
386
-
387
-
static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
388
-
int level)
389
-
{
390
-
struct tegra_gpio *gpio = gpiochip_get_data(chip);
391
-
void __iomem *base;
392
-
u32 value;
393
-
394
-
base = tegra186_gpio_get_base(gpio, offset);
395
-
if (WARN_ON(base == NULL))
396
-
return;
397
-
398
-
value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
399
-
if (level == 0)
400
-
value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
401
-
else
402
-
value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
403
-
404
-
writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
405
360
}
406
361
407
362
static int tegra186_gpio_set_config(struct gpio_chip *chip,
···
891
886
gpio->gpio.direction_input = tegra186_gpio_direction_input;
892
887
gpio->gpio.direction_output = tegra186_gpio_direction_output;
893
888
gpio->gpio.get = tegra186_gpio_get;
894
-
gpio->gpio.set = tegra186_gpio_set;
889
+
gpio->gpio.set_rv = tegra186_gpio_set;
895
890
gpio->gpio.set_config = tegra186_gpio_set_config;
896
891
gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
897
892
gpio->gpio.init_valid_mask = tegra186_init_valid_mask;
+11
-7
drivers/gpio/gpio-thunderx.c
+11
-7
drivers/gpio/gpio-thunderx.c
···
116
116
return 0;
117
117
}
118
118
119
-
static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
120
-
int value)
119
+
static int thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
120
+
int value)
121
121
{
122
122
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
123
123
int bank = line / 64;
···
127
127
(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
128
128
129
129
writeq(BIT_ULL(bank_bit), reg);
130
+
131
+
return 0;
130
132
}
131
133
132
134
static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
···
271
269
return masked_bits != 0;
272
270
}
273
271
274
-
static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
275
-
unsigned long *mask,
276
-
unsigned long *bits)
272
+
static int thunderx_gpio_set_multiple(struct gpio_chip *chip,
273
+
unsigned long *mask,
274
+
unsigned long *bits)
277
275
{
278
276
int bank;
279
277
u64 set_bits, clear_bits;
···
285
283
writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
286
284
writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
287
285
}
286
+
287
+
return 0;
288
288
}
289
289
290
290
static void thunderx_gpio_irq_ack(struct irq_data *d)
···
533
529
chip->direction_input = thunderx_gpio_dir_in;
534
530
chip->get = thunderx_gpio_get;
535
531
chip->direction_output = thunderx_gpio_dir_out;
536
-
chip->set = thunderx_gpio_set;
537
-
chip->set_multiple = thunderx_gpio_set_multiple;
532
+
chip->set_rv = thunderx_gpio_set;
533
+
chip->set_multiple_rv = thunderx_gpio_set_multiple;
538
534
chip->set_config = thunderx_gpio_set_config;
539
535
girq = &chip->irq;
540
536
gpio_irq_chip_set_chip(girq, &thunderx_gpio_irq_chip);
+3
-4
drivers/gpio/gpio-timberdale.c
+3
-4
drivers/gpio/gpio-timberdale.c
···
80
80
return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
81
81
}
82
82
83
-
static void timbgpio_gpio_set(struct gpio_chip *gpio,
84
-
unsigned nr, int val)
83
+
static int timbgpio_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
85
84
{
86
-
timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
85
+
return timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
87
86
}
88
87
89
88
static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
···
253
254
gc->direction_input = timbgpio_gpio_direction_input;
254
255
gc->get = timbgpio_gpio_get;
255
256
gc->direction_output = timbgpio_gpio_direction_output;
256
-
gc->set = timbgpio_gpio_set;
257
+
gc->set_rv = timbgpio_gpio_set;
257
258
gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
258
259
gc->dbg_show = NULL;
259
260
gc->base = pdata->gpio_base;
+11
-16
drivers/gpio/gpio-tpic2810.c
+11
-16
drivers/gpio/gpio-tpic2810.c
···
25
25
struct mutex lock;
26
26
};
27
27
28
-
static void tpic2810_set(struct gpio_chip *chip, unsigned offset, int value);
28
+
static int tpic2810_set(struct gpio_chip *chip, unsigned int offset, int value);
29
29
30
30
static int tpic2810_get_direction(struct gpio_chip *chip,
31
31
unsigned offset)
···
34
34
return GPIO_LINE_DIRECTION_OUT;
35
35
}
36
36
37
-
static int tpic2810_direction_input(struct gpio_chip *chip,
38
-
unsigned offset)
39
-
{
40
-
/* This device is output only */
41
-
return -EINVAL;
42
-
}
43
-
44
37
static int tpic2810_direction_output(struct gpio_chip *chip,
45
38
unsigned offset, int value)
46
39
{
47
40
/* This device always output */
48
-
tpic2810_set(chip, offset, value);
49
-
return 0;
41
+
return tpic2810_set(chip, offset, value);
50
42
}
51
43
52
44
static void tpic2810_set_mask_bits(struct gpio_chip *chip, u8 mask, u8 bits)
···
60
68
mutex_unlock(&gpio->lock);
61
69
}
62
70
63
-
static void tpic2810_set(struct gpio_chip *chip, unsigned offset, int value)
71
+
static int tpic2810_set(struct gpio_chip *chip, unsigned int offset, int value)
64
72
{
65
73
tpic2810_set_mask_bits(chip, BIT(offset), value ? BIT(offset) : 0);
74
+
75
+
return 0;
66
76
}
67
77
68
-
static void tpic2810_set_multiple(struct gpio_chip *chip, unsigned long *mask,
69
-
unsigned long *bits)
78
+
static int tpic2810_set_multiple(struct gpio_chip *chip, unsigned long *mask,
79
+
unsigned long *bits)
70
80
{
71
81
tpic2810_set_mask_bits(chip, *mask, *bits);
82
+
83
+
return 0;
72
84
}
73
85
74
86
static const struct gpio_chip template_chip = {
75
87
.label = "tpic2810",
76
88
.owner = THIS_MODULE,
77
89
.get_direction = tpic2810_get_direction,
78
-
.direction_input = tpic2810_direction_input,
79
90
.direction_output = tpic2810_direction_output,
80
-
.set = tpic2810_set,
81
-
.set_multiple = tpic2810_set_multiple,
91
+
.set_rv = tpic2810_set,
92
+
.set_multiple_rv = tpic2810_set_multiple,
82
93
.base = -1,
83
94
.ngpio = 8,
84
95
.can_sleep = true,
+7
-9
drivers/gpio/gpio-tps65086.c
+7
-9
drivers/gpio/gpio-tps65086.c
···
37
37
struct tps65086_gpio *gpio = gpiochip_get_data(chip);
38
38
39
39
/* Set the initial value */
40
-
regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL,
41
-
BIT(4 + offset), value ? BIT(4 + offset) : 0);
42
-
43
-
return 0;
40
+
return regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL,
41
+
BIT(4 + offset), value ? BIT(4 + offset) : 0);
44
42
}
45
43
46
44
static int tps65086_gpio_get(struct gpio_chip *chip, unsigned offset)
···
53
55
return val & BIT(4 + offset);
54
56
}
55
57
56
-
static void tps65086_gpio_set(struct gpio_chip *chip, unsigned offset,
57
-
int value)
58
+
static int tps65086_gpio_set(struct gpio_chip *chip, unsigned int offset,
59
+
int value)
58
60
{
59
61
struct tps65086_gpio *gpio = gpiochip_get_data(chip);
60
62
61
-
regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL,
62
-
BIT(4 + offset), value ? BIT(4 + offset) : 0);
63
+
return regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL,
64
+
BIT(4 + offset), value ? BIT(4 + offset) : 0);
63
65
}
64
66
65
67
static const struct gpio_chip template_chip = {
···
69
71
.direction_input = tps65086_gpio_direction_input,
70
72
.direction_output = tps65086_gpio_direction_output,
71
73
.get = tps65086_gpio_get,
72
-
.set = tps65086_gpio_set,
74
+
.set_rv = tps65086_gpio_set,
73
75
.base = -1,
74
76
.ngpio = 4,
75
77
.can_sleep = true,
+12
-19
drivers/gpio/gpio-tps65218.c
+12
-19
drivers/gpio/gpio-tps65218.c
···
34
34
return !!(val & (TPS65218_ENABLE2_GPIO1 << offset));
35
35
}
36
36
37
-
static void tps65218_gpio_set(struct gpio_chip *gc, unsigned offset,
38
-
int value)
37
+
static int tps65218_gpio_set(struct gpio_chip *gc, unsigned int offset,
38
+
int value)
39
39
{
40
40
struct tps65218_gpio *tps65218_gpio = gpiochip_get_data(gc);
41
41
struct tps65218 *tps65218 = tps65218_gpio->tps65218;
42
42
43
43
if (value)
44
-
tps65218_set_bits(tps65218, TPS65218_REG_ENABLE2,
45
-
TPS65218_ENABLE2_GPIO1 << offset,
46
-
TPS65218_ENABLE2_GPIO1 << offset,
47
-
TPS65218_PROTECT_L1);
48
-
else
49
-
tps65218_clear_bits(tps65218, TPS65218_REG_ENABLE2,
50
-
TPS65218_ENABLE2_GPIO1 << offset,
51
-
TPS65218_PROTECT_L1);
44
+
return tps65218_set_bits(tps65218, TPS65218_REG_ENABLE2,
45
+
TPS65218_ENABLE2_GPIO1 << offset,
46
+
TPS65218_ENABLE2_GPIO1 << offset,
47
+
TPS65218_PROTECT_L1);
48
+
49
+
return tps65218_clear_bits(tps65218, TPS65218_REG_ENABLE2,
50
+
TPS65218_ENABLE2_GPIO1 << offset,
51
+
TPS65218_PROTECT_L1);
52
52
}
53
53
54
54
static int tps65218_gpio_output(struct gpio_chip *gc, unsigned offset,
55
55
int value)
56
56
{
57
57
/* Only drives GPOs */
58
-
tps65218_gpio_set(gc, offset, value);
59
-
return 0;
60
-
}
61
-
62
-
static int tps65218_gpio_input(struct gpio_chip *gc, unsigned offset)
63
-
{
64
-
return -EPERM;
58
+
return tps65218_gpio_set(gc, offset, value);
65
59
}
66
60
67
61
static int tps65218_gpio_request(struct gpio_chip *gc, unsigned offset)
···
168
174
.owner = THIS_MODULE,
169
175
.request = tps65218_gpio_request,
170
176
.direction_output = tps65218_gpio_output,
171
-
.direction_input = tps65218_gpio_input,
172
177
.get = tps65218_gpio_get,
173
-
.set = tps65218_gpio_set,
178
+
.set_rv = tps65218_gpio_set,
174
179
.set_config = tps65218_gpio_set_config,
175
180
.can_sleep = true,
176
181
.ngpio = 3,
+105
-19
drivers/gpio/gpio-tps65219.c
+105
-19
drivers/gpio/gpio-tps65219.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
-
* GPIO driver for TI TPS65219 PMICs
3
+
* GPIO driver for TI TPS65214/TPS65215/TPS65219 PMICs
4
4
*
5
-
* Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
5
+
* Copyright (C) 2022, 2025 Texas Instruments Incorporated - http://www.ti.com/
6
6
*/
7
7
8
8
#include <linux/bits.h>
···
13
13
#include <linux/regmap.h>
14
14
15
15
#define TPS65219_GPIO0_DIR_MASK BIT(3)
16
-
#define TPS65219_GPIO0_OFFSET 2
17
-
#define TPS65219_GPIO0_IDX 0
16
+
#define TPS65214_GPIO0_DIR_MASK BIT(1)
17
+
#define TPS6521X_GPIO0_OFFSET 2
18
+
#define TPS6521X_GPIO0_IDX 0
19
+
20
+
/*
21
+
* TPS65214 GPIO mapping
22
+
* Linux gpio offset 0 -> GPIO (pin16) -> bit_offset 2
23
+
* Linux gpio offset 1 -> GPO1 (pin9 ) -> bit_offset 0
24
+
*
25
+
* TPS65215 & TPS65219 GPIO mapping
26
+
* Linux gpio offset 0 -> GPIO (pin16) -> bit_offset 2
27
+
* Linux gpio offset 1 -> GPO1 (pin8 ) -> bit_offset 0
28
+
* Linux gpio offset 2 -> GPO2 (pin17) -> bit_offset 1
29
+
*/
18
30
19
31
struct tps65219_gpio {
32
+
int (*change_dir)(struct gpio_chip *gc, unsigned int offset, unsigned int dir);
20
33
struct gpio_chip gpio_chip;
21
34
struct tps65219 *tps;
22
35
};
36
+
37
+
static int tps65214_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
38
+
{
39
+
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
40
+
int ret, val;
41
+
42
+
if (offset != TPS6521X_GPIO0_IDX)
43
+
return GPIO_LINE_DIRECTION_OUT;
44
+
45
+
ret = regmap_read(gpio->tps->regmap, TPS65219_REG_GENERAL_CONFIG, &val);
46
+
if (ret)
47
+
return ret;
48
+
49
+
return !(val & TPS65214_GPIO0_DIR_MASK);
50
+
}
23
51
24
52
static int tps65219_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
25
53
{
26
54
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
27
55
int ret, val;
28
56
29
-
if (offset != TPS65219_GPIO0_IDX)
57
+
if (offset != TPS6521X_GPIO0_IDX)
30
58
return GPIO_LINE_DIRECTION_OUT;
31
59
32
60
ret = regmap_read(gpio->tps->regmap, TPS65219_REG_MFP_1_CONFIG, &val);
···
70
42
struct device *dev = gpio->tps->dev;
71
43
int ret, val;
72
44
73
-
if (offset != TPS65219_GPIO0_IDX) {
45
+
if (offset != TPS6521X_GPIO0_IDX) {
74
46
dev_err(dev, "GPIO%d is output only, cannot get\n", offset);
75
47
return -ENOTSUPP;
76
48
}
···
93
65
return ret;
94
66
}
95
67
96
-
static void tps65219_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
68
+
static int tps65219_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
97
69
{
98
70
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
99
-
struct device *dev = gpio->tps->dev;
100
71
int v, mask, bit;
101
72
102
-
bit = (offset == TPS65219_GPIO0_IDX) ? TPS65219_GPIO0_OFFSET : offset - 1;
73
+
bit = (offset == TPS6521X_GPIO0_IDX) ? TPS6521X_GPIO0_OFFSET : offset - 1;
103
74
104
75
mask = BIT(bit);
105
76
v = value ? mask : 0;
106
77
107
-
if (regmap_update_bits(gpio->tps->regmap, TPS65219_REG_GENERAL_CONFIG, mask, v))
108
-
dev_err(dev, "GPIO%d, set to value %d failed.\n", offset, value);
78
+
return regmap_update_bits(gpio->tps->regmap,
79
+
TPS65219_REG_GENERAL_CONFIG, mask, v);
109
80
}
110
81
111
82
static int tps65219_gpio_change_direction(struct gpio_chip *gc, unsigned int offset,
···
139
112
return -ENOTSUPP;
140
113
}
141
114
115
+
static int tps65214_gpio_change_direction(struct gpio_chip *gc, unsigned int offset,
116
+
unsigned int direction)
117
+
{
118
+
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
119
+
struct device *dev = gpio->tps->dev;
120
+
int val, ret;
121
+
122
+
/**
123
+
* Verified if GPIO or GPO in parent function
124
+
* Masked value: 0 = GPIO, 1 = VSEL
125
+
*/
126
+
ret = regmap_read(gpio->tps->regmap, TPS65219_REG_MFP_1_CONFIG, &val);
127
+
if (ret)
128
+
return ret;
129
+
130
+
ret = !!(val & BIT(TPS65219_GPIO0_DIR_MASK));
131
+
if (ret)
132
+
dev_err(dev, "GPIO%d configured as VSEL, not GPIO\n", offset);
133
+
134
+
ret = regmap_update_bits(gpio->tps->regmap, TPS65219_REG_GENERAL_CONFIG,
135
+
TPS65214_GPIO0_DIR_MASK, direction);
136
+
if (ret)
137
+
dev_err(dev, "Fail to change direction to %u for GPIO%d.\n", direction, offset);
138
+
139
+
return ret;
140
+
}
141
+
142
142
static int tps65219_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
143
143
{
144
144
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
145
145
struct device *dev = gpio->tps->dev;
146
146
147
-
if (offset != TPS65219_GPIO0_IDX) {
147
+
if (offset != TPS6521X_GPIO0_IDX) {
148
148
dev_err(dev, "GPIO%d is output only, cannot change to input\n", offset);
149
149
return -ENOTSUPP;
150
150
}
···
179
125
if (tps65219_gpio_get_direction(gc, offset) == GPIO_LINE_DIRECTION_IN)
180
126
return 0;
181
127
182
-
return tps65219_gpio_change_direction(gc, offset, GPIO_LINE_DIRECTION_IN);
128
+
return gpio->change_dir(gc, offset, GPIO_LINE_DIRECTION_IN);
183
129
}
184
130
185
131
static int tps65219_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
186
132
{
133
+
struct tps65219_gpio *gpio = gpiochip_get_data(gc);
134
+
187
135
tps65219_gpio_set(gc, offset, value);
188
-
if (offset != TPS65219_GPIO0_IDX)
136
+
if (offset != TPS6521X_GPIO0_IDX)
189
137
return 0;
190
138
191
139
if (tps65219_gpio_get_direction(gc, offset) == GPIO_LINE_DIRECTION_OUT)
192
140
return 0;
193
141
194
-
return tps65219_gpio_change_direction(gc, offset, GPIO_LINE_DIRECTION_OUT);
142
+
return gpio->change_dir(gc, offset, GPIO_LINE_DIRECTION_OUT);
195
143
}
144
+
145
+
static const struct gpio_chip tps65214_template_chip = {
146
+
.label = "tps65214-gpio",
147
+
.owner = THIS_MODULE,
148
+
.get_direction = tps65214_gpio_get_direction,
149
+
.direction_input = tps65219_gpio_direction_input,
150
+
.direction_output = tps65219_gpio_direction_output,
151
+
.get = tps65219_gpio_get,
152
+
.set_rv = tps65219_gpio_set,
153
+
.base = -1,
154
+
.ngpio = 2,
155
+
.can_sleep = true,
156
+
};
196
157
197
158
static const struct gpio_chip tps65219_template_chip = {
198
159
.label = "tps65219-gpio",
···
216
147
.direction_input = tps65219_gpio_direction_input,
217
148
.direction_output = tps65219_gpio_direction_output,
218
149
.get = tps65219_gpio_get,
219
-
.set = tps65219_gpio_set,
150
+
.set_rv = tps65219_gpio_set,
220
151
.base = -1,
221
152
.ngpio = 3,
222
153
.can_sleep = true,
···
224
155
225
156
static int tps65219_gpio_probe(struct platform_device *pdev)
226
157
{
158
+
enum pmic_id chip = platform_get_device_id(pdev)->driver_data;
227
159
struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent);
228
160
struct tps65219_gpio *gpio;
229
161
···
232
162
if (!gpio)
233
163
return -ENOMEM;
234
164
165
+
if (chip == TPS65214) {
166
+
gpio->gpio_chip = tps65214_template_chip;
167
+
gpio->change_dir = tps65214_gpio_change_direction;
168
+
} else if (chip == TPS65219) {
169
+
gpio->gpio_chip = tps65219_template_chip;
170
+
gpio->change_dir = tps65219_gpio_change_direction;
171
+
} else {
172
+
return -ENODATA;
173
+
}
174
+
235
175
gpio->tps = tps;
236
-
gpio->gpio_chip = tps65219_template_chip;
237
176
gpio->gpio_chip.parent = tps->dev;
238
177
239
178
return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio_chip, gpio);
240
179
}
180
+
181
+
static const struct platform_device_id tps6521x_gpio_id_table[] = {
182
+
{ "tps65214-gpio", TPS65214 },
183
+
{ "tps65219-gpio", TPS65219 },
184
+
{ /* sentinel */ }
185
+
};
186
+
MODULE_DEVICE_TABLE(platform, tps6521x_gpio_id_table);
241
187
242
188
static struct platform_driver tps65219_gpio_driver = {
243
189
.driver = {
244
190
.name = "tps65219-gpio",
245
191
},
246
192
.probe = tps65219_gpio_probe,
193
+
.id_table = tps6521x_gpio_id_table,
247
194
};
248
195
module_platform_driver(tps65219_gpio_driver);
249
196
250
-
MODULE_ALIAS("platform:tps65219-gpio");
251
197
MODULE_AUTHOR("Jonathan Cormier <jcormier@criticallink.com>");
252
-
MODULE_DESCRIPTION("TPS65219 GPIO driver");
198
+
MODULE_DESCRIPTION("TPS65214/TPS65215/TPS65219 GPIO driver");
253
199
MODULE_LICENSE("GPL");
+9
-6
drivers/gpio/gpio-tps6586x.c
+9
-6
drivers/gpio/gpio-tps6586x.c
···
40
40
return !!(val & (1 << offset));
41
41
}
42
42
43
-
static void tps6586x_gpio_set(struct gpio_chip *gc, unsigned offset,
44
-
int value)
43
+
static int tps6586x_gpio_set(struct gpio_chip *gc, unsigned int offset,
44
+
int value)
45
45
{
46
46
struct tps6586x_gpio *tps6586x_gpio = gpiochip_get_data(gc);
47
47
48
-
tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET2,
49
-
value << offset, 1 << offset);
48
+
return tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET2,
49
+
value << offset, 1 << offset);
50
50
}
51
51
52
52
static int tps6586x_gpio_output(struct gpio_chip *gc, unsigned offset,
···
54
54
{
55
55
struct tps6586x_gpio *tps6586x_gpio = gpiochip_get_data(gc);
56
56
uint8_t val, mask;
57
+
int ret;
57
58
58
-
tps6586x_gpio_set(gc, offset, value);
59
+
ret = tps6586x_gpio_set(gc, offset, value);
60
+
if (ret)
61
+
return ret;
59
62
60
63
val = 0x1 << (offset * 2);
61
64
mask = 0x3 << (offset * 2);
···
98
95
99
96
/* FIXME: add handling of GPIOs as dedicated inputs */
100
97
tps6586x_gpio->gpio_chip.direction_output = tps6586x_gpio_output;
101
-
tps6586x_gpio->gpio_chip.set = tps6586x_gpio_set;
98
+
tps6586x_gpio->gpio_chip.set_rv = tps6586x_gpio_set;
102
99
tps6586x_gpio->gpio_chip.get = tps6586x_gpio_get;
103
100
tps6586x_gpio->gpio_chip.to_irq = tps6586x_gpio_to_irq;
104
101
+12
-9
drivers/gpio/gpio-tps65910.c
+12
-9
drivers/gpio/gpio-tps65910.c
···
36
36
return 0;
37
37
}
38
38
39
-
static void tps65910_gpio_set(struct gpio_chip *gc, unsigned offset,
40
-
int value)
39
+
static int tps65910_gpio_set(struct gpio_chip *gc, unsigned int offset,
40
+
int value)
41
41
{
42
42
struct tps65910_gpio *tps65910_gpio = gpiochip_get_data(gc);
43
43
struct tps65910 *tps65910 = tps65910_gpio->tps65910;
44
44
45
45
if (value)
46
-
regmap_set_bits(tps65910->regmap, TPS65910_GPIO0 + offset,
47
-
GPIO_SET_MASK);
48
-
else
49
-
regmap_clear_bits(tps65910->regmap, TPS65910_GPIO0 + offset,
50
-
GPIO_SET_MASK);
46
+
return regmap_set_bits(tps65910->regmap,
47
+
TPS65910_GPIO0 + offset, GPIO_SET_MASK);
48
+
49
+
return regmap_clear_bits(tps65910->regmap, TPS65910_GPIO0 + offset,
50
+
GPIO_SET_MASK);
51
51
}
52
52
53
53
static int tps65910_gpio_output(struct gpio_chip *gc, unsigned offset,
···
55
55
{
56
56
struct tps65910_gpio *tps65910_gpio = gpiochip_get_data(gc);
57
57
struct tps65910 *tps65910 = tps65910_gpio->tps65910;
58
+
int ret;
58
59
59
60
/* Set the initial value */
60
-
tps65910_gpio_set(gc, offset, value);
61
+
ret = tps65910_gpio_set(gc, offset, value);
62
+
if (ret)
63
+
return ret;
61
64
62
65
return regmap_set_bits(tps65910->regmap, TPS65910_GPIO0 + offset,
63
66
GPIO_CFG_MASK);
···
139
136
tps65910_gpio->gpio_chip.can_sleep = true;
140
137
tps65910_gpio->gpio_chip.direction_input = tps65910_gpio_input;
141
138
tps65910_gpio->gpio_chip.direction_output = tps65910_gpio_output;
142
-
tps65910_gpio->gpio_chip.set = tps65910_gpio_set;
139
+
tps65910_gpio->gpio_chip.set_rv = tps65910_gpio_set;
143
140
tps65910_gpio->gpio_chip.get = tps65910_gpio_get;
144
141
tps65910_gpio->gpio_chip.parent = &pdev->dev;
145
142
+10
-7
drivers/gpio/gpio-tps65912.c
+10
-7
drivers/gpio/gpio-tps65912.c
···
49
49
unsigned offset, int value)
50
50
{
51
51
struct tps65912_gpio *gpio = gpiochip_get_data(gc);
52
+
int ret;
52
53
53
54
/* Set the initial value */
54
-
regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
55
-
GPIO_SET_MASK, value ? GPIO_SET_MASK : 0);
55
+
ret = regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
56
+
GPIO_SET_MASK, value ? GPIO_SET_MASK : 0);
57
+
if (ret)
58
+
return ret;
56
59
57
60
return regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
58
61
GPIO_CFG_MASK, GPIO_CFG_MASK);
···
76
73
return 0;
77
74
}
78
75
79
-
static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset,
80
-
int value)
76
+
static int tps65912_gpio_set(struct gpio_chip *gc, unsigned int offset,
77
+
int value)
81
78
{
82
79
struct tps65912_gpio *gpio = gpiochip_get_data(gc);
83
80
84
-
regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
85
-
GPIO_SET_MASK, value ? GPIO_SET_MASK : 0);
81
+
return regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset,
82
+
GPIO_SET_MASK, value ? GPIO_SET_MASK : 0);
86
83
}
87
84
88
85
static const struct gpio_chip template_chip = {
···
92
89
.direction_input = tps65912_gpio_direction_input,
93
90
.direction_output = tps65912_gpio_direction_output,
94
91
.get = tps65912_gpio_get,
95
-
.set = tps65912_gpio_set,
92
+
.set_rv = tps65912_gpio_set,
96
93
.base = -1,
97
94
.ngpio = 5,
98
95
.can_sleep = true,
+9
-5
drivers/gpio/gpio-tps68470.c
+9
-5
drivers/gpio/gpio-tps68470.c
···
70
70
GPIO_LINE_DIRECTION_IN;
71
71
}
72
72
73
-
static void tps68470_gpio_set(struct gpio_chip *gc, unsigned int offset,
74
-
int value)
73
+
static int tps68470_gpio_set(struct gpio_chip *gc, unsigned int offset,
74
+
int value)
75
75
{
76
76
struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc);
77
77
struct regmap *regmap = tps68470_gpio->tps68470_regmap;
···
82
82
offset -= TPS68470_N_REGULAR_GPIO;
83
83
}
84
84
85
-
regmap_update_bits(regmap, reg, BIT(offset), value ? BIT(offset) : 0);
85
+
return regmap_update_bits(regmap, reg, BIT(offset),
86
+
value ? BIT(offset) : 0);
86
87
}
87
88
88
89
static int tps68470_gpio_output(struct gpio_chip *gc, unsigned int offset,
···
91
90
{
92
91
struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc);
93
92
struct regmap *regmap = tps68470_gpio->tps68470_regmap;
93
+
int ret;
94
94
95
95
/* Set the initial value */
96
-
tps68470_gpio_set(gc, offset, value);
96
+
ret = tps68470_gpio_set(gc, offset, value);
97
+
if (ret)
98
+
return ret;
97
99
98
100
/* rest are always outputs */
99
101
if (offset >= TPS68470_N_REGULAR_GPIO)
···
142
138
tps68470_gpio->gc.direction_output = tps68470_gpio_output;
143
139
tps68470_gpio->gc.get = tps68470_gpio_get;
144
140
tps68470_gpio->gc.get_direction = tps68470_gpio_get_direction;
145
-
tps68470_gpio->gc.set = tps68470_gpio_set;
141
+
tps68470_gpio->gc.set_rv = tps68470_gpio_set;
146
142
tps68470_gpio->gc.can_sleep = true;
147
143
tps68470_gpio->gc.names = tps68470_names;
148
144
tps68470_gpio->gc.ngpio = TPS68470_N_GPIO;
+5
-3
drivers/gpio/gpio-tqmx86.c
+5
-3
drivers/gpio/gpio-tqmx86.c
···
93
93
tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD);
94
94
}
95
95
96
-
static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
97
-
int value)
96
+
static int tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
97
+
int value)
98
98
{
99
99
struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
100
100
101
101
guard(raw_spinlock_irqsave)(&gpio->spinlock);
102
102
103
103
_tqmx86_gpio_set(gpio, offset, value);
104
+
105
+
return 0;
104
106
}
105
107
106
108
static int tqmx86_gpio_direction_input(struct gpio_chip *chip,
···
370
368
chip->direction_output = tqmx86_gpio_direction_output;
371
369
chip->get_direction = tqmx86_gpio_get_direction;
372
370
chip->get = tqmx86_gpio_get;
373
-
chip->set = tqmx86_gpio_set;
371
+
chip->set_rv = tqmx86_gpio_set;
374
372
chip->ngpio = TQMX86_NGPIO;
375
373
chip->parent = pdev->dev.parent;
376
374
+7
-7
drivers/gpio/gpio-ts4900.c
+7
-7
drivers/gpio/gpio-ts4900.c
···
95
95
return !!(reg & priv->input_bit);
96
96
}
97
97
98
-
static void ts4900_gpio_set(struct gpio_chip *chip, unsigned int offset,
99
-
int value)
98
+
static int ts4900_gpio_set(struct gpio_chip *chip, unsigned int offset,
99
+
int value)
100
100
{
101
101
struct ts4900_gpio_priv *priv = gpiochip_get_data(chip);
102
102
103
103
if (value)
104
-
regmap_update_bits(priv->regmap, offset, TS4900_GPIO_OUT,
105
-
TS4900_GPIO_OUT);
106
-
else
107
-
regmap_update_bits(priv->regmap, offset, TS4900_GPIO_OUT, 0);
104
+
return regmap_update_bits(priv->regmap, offset,
105
+
TS4900_GPIO_OUT, TS4900_GPIO_OUT);
106
+
107
+
return regmap_update_bits(priv->regmap, offset, TS4900_GPIO_OUT, 0);
108
108
}
109
109
110
110
static const struct regmap_config ts4900_regmap_config = {
···
119
119
.direction_input = ts4900_gpio_direction_input,
120
120
.direction_output = ts4900_gpio_direction_output,
121
121
.get = ts4900_gpio_get,
122
-
.set = ts4900_gpio_set,
122
+
.set_rv = ts4900_gpio_set,
123
123
.base = -1,
124
124
.can_sleep = true,
125
125
};
+4
-2
drivers/gpio/gpio-ts5500.c
+4
-2
drivers/gpio/gpio-ts5500.c
···
244
244
return 0;
245
245
}
246
246
247
-
static void ts5500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
247
+
static int ts5500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
248
248
{
249
249
struct ts5500_priv *priv = gpiochip_get_data(chip);
250
250
const struct ts5500_dio line = priv->pinout[offset];
···
256
256
else
257
257
ts5500_clear_mask(line.value_mask, line.value_addr);
258
258
spin_unlock_irqrestore(&priv->lock, flags);
259
+
260
+
return 0;
259
261
}
260
262
261
263
static int ts5500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
···
340
338
priv->gpio_chip.direction_input = ts5500_gpio_input;
341
339
priv->gpio_chip.direction_output = ts5500_gpio_output;
342
340
priv->gpio_chip.get = ts5500_gpio_get;
343
-
priv->gpio_chip.set = ts5500_gpio_set;
341
+
priv->gpio_chip.set_rv = ts5500_gpio_set;
344
342
priv->gpio_chip.to_irq = ts5500_gpio_to_irq;
345
343
priv->gpio_chip.base = -1;
346
344
+13
-12
drivers/gpio/gpio-twl4030.c
+13
-12
drivers/gpio/gpio-twl4030.c
···
120
120
* external pullup is needed. We could also expose the integrated PWM
121
121
* as a LED brightness control; we initialize it as "always on".
122
122
*/
123
-
static void twl4030_led_set_value(int led, int value)
123
+
static int twl4030_led_set_value(int led, int value)
124
124
{
125
125
u8 mask = LEDEN_LEDAON | LEDEN_LEDAPWM;
126
126
···
132
132
else
133
133
cached_leden |= mask;
134
134
135
-
WARN_ON_ONCE(twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden,
136
-
TWL4030_LED_LEDEN_REG));
135
+
return twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden,
136
+
TWL4030_LED_LEDEN_REG);
137
137
}
138
138
139
139
static int twl4030_set_gpio_direction(int gpio, int is_input)
···
278
278
279
279
mutex_lock(&priv->mutex);
280
280
if (offset >= TWL4030_GPIO_MAX) {
281
-
twl4030_led_set_value(offset - TWL4030_GPIO_MAX, 1);
281
+
WARN_ON_ONCE(twl4030_led_set_value(offset - TWL4030_GPIO_MAX, 1));
282
282
goto out;
283
283
}
284
284
···
334
334
return ret;
335
335
}
336
336
337
-
static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
337
+
static int twl_set(struct gpio_chip *chip, unsigned int offset, int value)
338
338
{
339
339
struct gpio_twl4030_priv *priv = gpiochip_get_data(chip);
340
+
int ret;
340
341
341
342
mutex_lock(&priv->mutex);
342
343
if (offset < TWL4030_GPIO_MAX)
343
-
twl4030_set_gpio_dataout(offset, value);
344
+
ret = twl4030_set_gpio_dataout(offset, value);
344
345
else
345
-
twl4030_led_set_value(offset - TWL4030_GPIO_MAX, value);
346
+
ret = twl4030_led_set_value(offset - TWL4030_GPIO_MAX, value);
346
347
347
348
if (value)
348
349
priv->out_state |= BIT(offset);
···
351
350
priv->out_state &= ~BIT(offset);
352
351
353
352
mutex_unlock(&priv->mutex);
353
+
354
+
return ret;
354
355
}
355
356
356
357
static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
···
376
373
priv->direction |= BIT(offset);
377
374
mutex_unlock(&priv->mutex);
378
375
379
-
twl_set(chip, offset, value);
380
-
381
-
return ret;
376
+
return twl_set(chip, offset, value);
382
377
}
383
378
384
379
static int twl_get_direction(struct gpio_chip *chip, unsigned offset)
···
419
418
.direction_output = twl_direction_out,
420
419
.get_direction = twl_get_direction,
421
420
.get = twl_get,
422
-
.set = twl_set,
421
+
.set_rv = twl_set,
423
422
.to_irq = twl_to_irq,
424
423
.can_sleep = true,
425
424
};
···
524
523
return irq_base;
525
524
}
526
525
527
-
irq_domain_create_legacy(of_fwnode_handle(pdev->dev.of_node), TWL4030_GPIO_MAX, irq_base, 0,
526
+
irq_domain_create_legacy(dev_fwnode(&pdev->dev), TWL4030_GPIO_MAX, irq_base, 0,
528
527
&irq_domain_simple_ops, NULL);
529
528
530
529
ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
+12
-11
drivers/gpio/gpio-twl6040.c
+12
-11
drivers/gpio/gpio-twl6040.c
···
37
37
return GPIO_LINE_DIRECTION_OUT;
38
38
}
39
39
40
-
static int twl6040gpo_direction_out(struct gpio_chip *chip, unsigned offset,
41
-
int value)
42
-
{
43
-
/* This only drives GPOs, and can't change direction */
44
-
return 0;
45
-
}
46
-
47
-
static void twl6040gpo_set(struct gpio_chip *chip, unsigned offset, int value)
40
+
static int twl6040gpo_set(struct gpio_chip *chip, unsigned int offset,
41
+
int value)
48
42
{
49
43
struct twl6040 *twl6040 = gpiochip_get_data(chip);
50
44
int ret;
···
46
52
47
53
ret = twl6040_reg_read(twl6040, TWL6040_REG_GPOCTL);
48
54
if (ret < 0)
49
-
return;
55
+
return ret;
50
56
51
57
if (value)
52
58
gpoctl = ret | BIT(offset);
53
59
else
54
60
gpoctl = ret & ~BIT(offset);
55
61
56
-
twl6040_reg_write(twl6040, TWL6040_REG_GPOCTL, gpoctl);
62
+
return twl6040_reg_write(twl6040, TWL6040_REG_GPOCTL, gpoctl);
63
+
}
64
+
65
+
static int twl6040gpo_direction_out(struct gpio_chip *chip, unsigned int offset,
66
+
int value)
67
+
{
68
+
/* This only drives GPOs, and can't change direction */
69
+
return twl6040gpo_set(chip, offset, value);
57
70
}
58
71
59
72
static struct gpio_chip twl6040gpo_chip = {
···
69
68
.get = twl6040gpo_get,
70
69
.direction_output = twl6040gpo_direction_out,
71
70
.get_direction = twl6040gpo_get_direction,
72
-
.set = twl6040gpo_set,
71
+
.set_rv = twl6040gpo_set,
73
72
.can_sleep = true,
74
73
};
75
74
+10
-6
drivers/gpio/gpio-uniphier.c
+10
-6
drivers/gpio/gpio-uniphier.c
···
138
138
return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
139
139
}
140
140
141
-
static void uniphier_gpio_set(struct gpio_chip *chip,
142
-
unsigned int offset, int val)
141
+
static int uniphier_gpio_set(struct gpio_chip *chip,
142
+
unsigned int offset, int val)
143
143
{
144
144
uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
145
+
146
+
return 0;
145
147
}
146
148
147
-
static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
148
-
unsigned long *mask, unsigned long *bits)
149
+
static int uniphier_gpio_set_multiple(struct gpio_chip *chip,
150
+
unsigned long *mask, unsigned long *bits)
149
151
{
150
152
unsigned long i, bank, bank_mask, bank_bits;
151
153
···
158
156
uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
159
157
bank_mask, bank_bits);
160
158
}
159
+
160
+
return 0;
161
161
}
162
162
163
163
static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
···
386
382
chip->direction_input = uniphier_gpio_direction_input;
387
383
chip->direction_output = uniphier_gpio_direction_output;
388
384
chip->get = uniphier_gpio_get;
389
-
chip->set = uniphier_gpio_set;
390
-
chip->set_multiple = uniphier_gpio_set_multiple;
385
+
chip->set_rv = uniphier_gpio_set;
386
+
chip->set_multiple_rv = uniphier_gpio_set_multiple;
391
387
chip->to_irq = uniphier_gpio_to_irq;
392
388
chip->base = -1;
393
389
chip->ngpio = ngpios;
+64
-56
drivers/gpio/gpio-viperboard.c
+64
-56
drivers/gpio/gpio-viperboard.c
···
128
128
return answer;
129
129
}
130
130
131
-
static void vprbrd_gpioa_set(struct gpio_chip *chip,
132
-
unsigned int offset, int value)
131
+
static int vprbrd_gpioa_set(struct gpio_chip *chip, unsigned int offset,
132
+
int value)
133
133
{
134
-
int ret;
134
+
int ret = 0;
135
135
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
136
136
struct vprbrd *vb = gpio->vb;
137
137
struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
138
138
139
-
if (gpio->gpioa_out & (1 << offset)) {
140
-
if (value)
141
-
gpio->gpioa_val |= (1 << offset);
142
-
else
143
-
gpio->gpioa_val &= ~(1 << offset);
139
+
if (!(gpio->gpioa_out & (1 << offset)))
140
+
return 0;
144
141
145
-
mutex_lock(&vb->lock);
142
+
if (value)
143
+
gpio->gpioa_val |= (1 << offset);
144
+
else
145
+
gpio->gpioa_val &= ~(1 << offset);
146
146
147
-
gamsg->cmd = VPRBRD_GPIOA_CMD_SETOUT;
148
-
gamsg->clk = 0x00;
149
-
gamsg->offset = offset;
150
-
gamsg->t1 = 0x00;
151
-
gamsg->t2 = 0x00;
152
-
gamsg->invert = 0x00;
153
-
gamsg->pwmlevel = 0x00;
154
-
gamsg->outval = value;
155
-
gamsg->risefall = 0x00;
156
-
gamsg->answer = 0x00;
157
-
gamsg->__fill = 0x00;
147
+
mutex_lock(&vb->lock);
158
148
159
-
ret = usb_control_msg(vb->usb_dev,
160
-
usb_sndctrlpipe(vb->usb_dev, 0),
161
-
VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT,
162
-
0x0000, 0x0000, gamsg,
163
-
sizeof(struct vprbrd_gpioa_msg), VPRBRD_USB_TIMEOUT_MS);
149
+
gamsg->cmd = VPRBRD_GPIOA_CMD_SETOUT;
150
+
gamsg->clk = 0x00;
151
+
gamsg->offset = offset;
152
+
gamsg->t1 = 0x00;
153
+
gamsg->t2 = 0x00;
154
+
gamsg->invert = 0x00;
155
+
gamsg->pwmlevel = 0x00;
156
+
gamsg->outval = value;
157
+
gamsg->risefall = 0x00;
158
+
gamsg->answer = 0x00;
159
+
gamsg->__fill = 0x00;
164
160
165
-
mutex_unlock(&vb->lock);
161
+
ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
162
+
VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT,
163
+
0x0000, 0x0000, gamsg,
164
+
sizeof(struct vprbrd_gpioa_msg),
165
+
VPRBRD_USB_TIMEOUT_MS);
166
166
167
-
if (ret != sizeof(struct vprbrd_gpioa_msg))
168
-
dev_err(chip->parent, "usb error setting pin value\n");
167
+
mutex_unlock(&vb->lock);
168
+
169
+
if (ret != sizeof(struct vprbrd_gpioa_msg)) {
170
+
dev_err(chip->parent, "usb error setting pin value\n");
171
+
return -EREMOTEIO;
169
172
}
173
+
174
+
return 0;
170
175
}
171
176
172
177
static int vprbrd_gpioa_direction_input(struct gpio_chip *chip,
···
309
304
return (gpio->gpiob_val >> offset) & 0x1;
310
305
}
311
306
312
-
static void vprbrd_gpiob_set(struct gpio_chip *chip,
313
-
unsigned int offset, int value)
307
+
static int vprbrd_gpiob_set(struct gpio_chip *chip, unsigned int offset,
308
+
int value)
314
309
{
315
310
int ret;
316
311
struct vprbrd_gpio *gpio = gpiochip_get_data(chip);
317
312
struct vprbrd *vb = gpio->vb;
318
313
struct vprbrd_gpiob_msg *gbmsg = (struct vprbrd_gpiob_msg *)vb->buf;
319
314
320
-
if (gpio->gpiob_out & (1 << offset)) {
321
-
if (value)
322
-
gpio->gpiob_val |= (1 << offset);
323
-
else
324
-
gpio->gpiob_val &= ~(1 << offset);
315
+
if (!(gpio->gpiob_out & (1 << offset)))
316
+
return 0;
325
317
326
-
mutex_lock(&vb->lock);
318
+
if (value)
319
+
gpio->gpiob_val |= (1 << offset);
320
+
else
321
+
gpio->gpiob_val &= ~(1 << offset);
327
322
328
-
gbmsg->cmd = VPRBRD_GPIOB_CMD_SETVAL;
329
-
gbmsg->val = cpu_to_be16(value << offset);
330
-
gbmsg->mask = cpu_to_be16(0x0001 << offset);
323
+
mutex_lock(&vb->lock);
331
324
332
-
ret = usb_control_msg(vb->usb_dev,
333
-
usb_sndctrlpipe(vb->usb_dev, 0),
334
-
VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_OUT,
335
-
0x0000, 0x0000, gbmsg,
336
-
sizeof(struct vprbrd_gpiob_msg), VPRBRD_USB_TIMEOUT_MS);
325
+
gbmsg->cmd = VPRBRD_GPIOB_CMD_SETVAL;
326
+
gbmsg->val = cpu_to_be16(value << offset);
327
+
gbmsg->mask = cpu_to_be16(0x0001 << offset);
337
328
338
-
mutex_unlock(&vb->lock);
329
+
ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
330
+
VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_OUT,
331
+
0x0000, 0x0000, gbmsg,
332
+
sizeof(struct vprbrd_gpiob_msg),
333
+
VPRBRD_USB_TIMEOUT_MS);
339
334
340
-
if (ret != sizeof(struct vprbrd_gpiob_msg))
341
-
dev_err(chip->parent, "usb error setting pin value\n");
335
+
mutex_unlock(&vb->lock);
336
+
337
+
if (ret != sizeof(struct vprbrd_gpiob_msg)) {
338
+
dev_err(chip->parent, "usb error setting pin value\n");
339
+
return -EREMOTEIO;
342
340
}
341
+
342
+
return 0;
343
343
}
344
344
345
345
static int vprbrd_gpiob_direction_input(struct gpio_chip *chip,
···
378
368
gpio->gpiob_out |= (1 << offset);
379
369
380
370
mutex_lock(&vb->lock);
381
-
382
371
ret = vprbrd_gpiob_setdir(vb, offset, 1);
383
-
if (ret)
384
-
dev_err(chip->parent, "usb error setting pin to output\n");
385
-
386
372
mutex_unlock(&vb->lock);
373
+
if (ret) {
374
+
dev_err(chip->parent, "usb error setting pin to output\n");
375
+
return ret;
376
+
}
387
377
388
-
vprbrd_gpiob_set(chip, offset, value);
389
-
390
-
return ret;
378
+
return vprbrd_gpiob_set(chip, offset, value);
391
379
}
392
380
393
381
/* ----- end of gpio b chip ---------------------------------------------- */
···
408
400
vb_gpio->gpioa.base = -1;
409
401
vb_gpio->gpioa.ngpio = 16;
410
402
vb_gpio->gpioa.can_sleep = true;
411
-
vb_gpio->gpioa.set = vprbrd_gpioa_set;
403
+
vb_gpio->gpioa.set_rv = vprbrd_gpioa_set;
412
404
vb_gpio->gpioa.get = vprbrd_gpioa_get;
413
405
vb_gpio->gpioa.direction_input = vprbrd_gpioa_direction_input;
414
406
vb_gpio->gpioa.direction_output = vprbrd_gpioa_direction_output;
···
424
416
vb_gpio->gpiob.base = -1;
425
417
vb_gpio->gpiob.ngpio = 16;
426
418
vb_gpio->gpiob.can_sleep = true;
427
-
vb_gpio->gpiob.set = vprbrd_gpiob_set;
419
+
vb_gpio->gpiob.set_rv = vprbrd_gpiob_set;
428
420
vb_gpio->gpiob.get = vprbrd_gpiob_get;
429
421
vb_gpio->gpiob.direction_input = vprbrd_gpiob_direction_input;
430
422
vb_gpio->gpiob.direction_output = vprbrd_gpiob_direction_output;
+9
-7
drivers/gpio/gpio-virtio.c
+9
-7
drivers/gpio/gpio-virtio.c
···
194
194
return ret ? ret : value;
195
195
}
196
196
197
-
static void virtio_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
197
+
static int virtio_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
198
198
{
199
199
struct virtio_gpio *vgpio = gpiochip_get_data(gc);
200
200
201
-
virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_SET_VALUE, gpio, value, NULL);
201
+
return virtio_gpio_req(vgpio, VIRTIO_GPIO_MSG_SET_VALUE, gpio, value,
202
+
NULL);
202
203
}
203
204
204
205
/* Interrupt handling */
···
527
526
528
527
static int virtio_gpio_probe(struct virtio_device *vdev)
529
528
{
530
-
struct virtio_gpio_config config;
531
529
struct device *dev = &vdev->dev;
532
530
struct virtio_gpio *vgpio;
533
531
struct irq_chip *gpio_irq_chip;
···
539
539
return -ENOMEM;
540
540
541
541
/* Read configuration */
542
-
virtio_cread_bytes(vdev, 0, &config, sizeof(config));
543
-
gpio_names_size = le32_to_cpu(config.gpio_names_size);
544
-
ngpio = le16_to_cpu(config.ngpio);
542
+
gpio_names_size =
543
+
virtio_cread32(vdev, offsetof(struct virtio_gpio_config,
544
+
gpio_names_size));
545
+
ngpio = virtio_cread16(vdev, offsetof(struct virtio_gpio_config,
546
+
ngpio));
545
547
if (!ngpio) {
546
548
dev_err(dev, "Number of GPIOs can't be zero\n");
547
549
return -EINVAL;
···
567
565
vgpio->gc.direction_input = virtio_gpio_direction_input;
568
566
vgpio->gc.direction_output = virtio_gpio_direction_output;
569
567
vgpio->gc.get = virtio_gpio_get;
570
-
vgpio->gc.set = virtio_gpio_set;
568
+
vgpio->gc.set_rv = virtio_gpio_set;
571
569
vgpio->gc.ngpio = ngpio;
572
570
vgpio->gc.base = -1; /* Allocate base dynamically */
573
571
vgpio->gc.label = dev_name(dev);
+1
-3
drivers/gpio/gpio-virtuser.c
+1
-3
drivers/gpio/gpio-virtuser.c
···
215
215
struct gpio_virtuser_irq_work_context ctx;
216
216
217
217
if (!atomic)
218
-
return gpiod_set_array_value_cansleep(descs->ndescs,
219
-
descs->desc,
220
-
descs->info, values);
218
+
return gpiod_multi_set_value_cansleep(descs, values);
221
219
222
220
gpio_virtuser_init_irq_work_context(&ctx);
223
221
ctx.work = IRQ_WORK_INIT_HARD(gpio_virtuser_set_value_array_atomic);
+5
-4
drivers/gpio/gpio-vx855.c
+5
-4
drivers/gpio/gpio-vx855.c
···
127
127
return ret;
128
128
}
129
129
130
-
static void vx855gpio_set(struct gpio_chip *gpio, unsigned int nr,
131
-
int val)
130
+
static int vx855gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
132
131
{
133
132
struct vx855_gpio *vg = gpiochip_get_data(gpio);
134
133
unsigned long flags;
···
135
136
136
137
/* True GPI cannot be switched to output mode */
137
138
if (nr < NR_VX855_GPI)
138
-
return;
139
+
return -EPERM;
139
140
140
141
spin_lock_irqsave(&vg->lock, flags);
141
142
reg_out = inl(vg->io_gpo);
···
152
153
}
153
154
outl(reg_out, vg->io_gpo);
154
155
spin_unlock_irqrestore(&vg->lock, flags);
156
+
157
+
return 0;
155
158
}
156
159
157
160
static int vx855gpio_direction_output(struct gpio_chip *gpio,
···
216
215
c->direction_input = vx855gpio_direction_input;
217
216
c->direction_output = vx855gpio_direction_output;
218
217
c->get = vx855gpio_get;
219
-
c->set = vx855gpio_set;
218
+
c->set_rv = vx855gpio_set;
220
219
c->set_config = vx855gpio_set_config;
221
220
c->dbg_show = NULL;
222
221
c->base = 0;
+10
-6
drivers/gpio/gpio-wcd934x.c
+10
-6
drivers/gpio/gpio-wcd934x.c
···
46
46
int val)
47
47
{
48
48
struct wcd_gpio_data *data = gpiochip_get_data(chip);
49
+
int ret;
49
50
50
-
regmap_update_bits(data->map, WCD_REG_DIR_CTL_OFFSET,
51
-
WCD_PIN_MASK(pin), WCD_PIN_MASK(pin));
51
+
ret = regmap_update_bits(data->map, WCD_REG_DIR_CTL_OFFSET,
52
+
WCD_PIN_MASK(pin), WCD_PIN_MASK(pin));
53
+
if (ret)
54
+
return ret;
52
55
53
56
return regmap_update_bits(data->map, WCD_REG_VAL_CTL_OFFSET,
54
57
WCD_PIN_MASK(pin),
···
68
65
return !!(value & WCD_PIN_MASK(pin));
69
66
}
70
67
71
-
static void wcd_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
68
+
static int wcd_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
72
69
{
73
70
struct wcd_gpio_data *data = gpiochip_get_data(chip);
74
71
75
-
regmap_update_bits(data->map, WCD_REG_VAL_CTL_OFFSET,
76
-
WCD_PIN_MASK(pin), val ? WCD_PIN_MASK(pin) : 0);
72
+
return regmap_update_bits(data->map, WCD_REG_VAL_CTL_OFFSET,
73
+
WCD_PIN_MASK(pin),
74
+
val ? WCD_PIN_MASK(pin) : 0);
77
75
}
78
76
79
77
static int wcd_gpio_probe(struct platform_device *pdev)
···
98
94
chip->direction_output = wcd_gpio_direction_output;
99
95
chip->get_direction = wcd_gpio_get_direction;
100
96
chip->get = wcd_gpio_get;
101
-
chip->set = wcd_gpio_set;
97
+
chip->set_rv = wcd_gpio_set;
102
98
chip->parent = dev;
103
99
chip->base = -1;
104
100
chip->ngpio = WCD934X_NPINS;
+4
-7
drivers/gpio/gpio-wcove.c
+4
-7
drivers/gpio/gpio-wcove.c
···
200
200
return val & 0x1;
201
201
}
202
202
203
-
static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
203
+
static int wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
204
204
{
205
205
struct wcove_gpio *wg = gpiochip_get_data(chip);
206
206
int reg = to_reg(gpio, CTRL_OUT);
207
207
208
208
if (reg < 0)
209
-
return;
209
+
return 0;
210
210
211
-
if (value)
212
-
regmap_set_bits(wg->regmap, reg, 1);
213
-
else
214
-
regmap_clear_bits(wg->regmap, reg, 1);
211
+
return regmap_assign_bits(wg->regmap, reg, 1, value);
215
212
}
216
213
217
214
static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
···
439
442
wg->chip.direction_output = wcove_gpio_dir_out;
440
443
wg->chip.get_direction = wcove_gpio_get_direction;
441
444
wg->chip.get = wcove_gpio_get;
442
-
wg->chip.set = wcove_gpio_set;
445
+
wg->chip.set_rv = wcove_gpio_set;
443
446
wg->chip.set_config = wcove_gpio_set_config;
444
447
wg->chip.base = -1;
445
448
wg->chip.ngpio = WCOVE_VGPIO_NUM;
+10
-6
drivers/gpio/gpio-winbond.c
+10
-6
drivers/gpio/gpio-winbond.c
···
458
458
return 0;
459
459
}
460
460
461
-
static void winbond_gpio_set(struct gpio_chip *gc, unsigned int offset,
462
-
int val)
461
+
static int winbond_gpio_set(struct gpio_chip *gc, unsigned int offset,
462
+
int val)
463
463
{
464
464
unsigned long *base = gpiochip_get_data(gc);
465
465
const struct winbond_gpio_info *info;
466
+
int ret;
466
467
467
468
if (!winbond_gpio_get_info(&offset, &info))
468
-
return;
469
+
return -EACCES;
469
470
470
-
if (winbond_sio_enter(*base) != 0)
471
-
return;
471
+
ret = winbond_sio_enter(*base);
472
+
if (ret)
473
+
return ret;
472
474
473
475
winbond_sio_select_logical(*base, info->dev);
474
476
···
483
481
winbond_sio_reg_bclear(*base, info->datareg, offset);
484
482
485
483
winbond_sio_leave(*base);
484
+
485
+
return 0;
486
486
}
487
487
488
488
static struct gpio_chip winbond_gpio_chip = {
···
494
490
.can_sleep = true,
495
491
.get = winbond_gpio_get,
496
492
.direction_input = winbond_gpio_direction_in,
497
-
.set = winbond_gpio_set,
493
+
.set_rv = winbond_gpio_set,
498
494
.direction_output = winbond_gpio_direction_out,
499
495
};
500
496
+6
-7
drivers/gpio/gpio-wm831x.c
+6
-7
drivers/gpio/gpio-wm831x.c
···
58
58
return 0;
59
59
}
60
60
61
-
static void wm831x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
61
+
static int wm831x_gpio_set(struct gpio_chip *chip, unsigned int offset,
62
+
int value)
62
63
{
63
64
struct wm831x_gpio *wm831x_gpio = gpiochip_get_data(chip);
64
65
struct wm831x *wm831x = wm831x_gpio->wm831x;
65
66
66
-
wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << offset,
67
-
value << offset);
67
+
return wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << offset,
68
+
value << offset);
68
69
}
69
70
70
71
static int wm831x_gpio_direction_out(struct gpio_chip *chip,
···
86
85
return ret;
87
86
88
87
/* Can only set GPIO state once it's in output mode */
89
-
wm831x_gpio_set(chip, offset, value);
90
-
91
-
return 0;
88
+
return wm831x_gpio_set(chip, offset, value);
92
89
}
93
90
94
91
static int wm831x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
···
253
254
.direction_input = wm831x_gpio_direction_in,
254
255
.get = wm831x_gpio_get,
255
256
.direction_output = wm831x_gpio_direction_out,
256
-
.set = wm831x_gpio_set,
257
+
.set_rv = wm831x_gpio_set,
257
258
.to_irq = wm831x_gpio_to_irq,
258
259
.set_config = wm831x_set_config,
259
260
.dbg_show = wm831x_gpio_dbg_show,
+7
-8
drivers/gpio/gpio-wm8350.c
+7
-8
drivers/gpio/gpio-wm8350.c
···
48
48
return 0;
49
49
}
50
50
51
-
static void wm8350_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
51
+
static int wm8350_gpio_set(struct gpio_chip *chip, unsigned int offset,
52
+
int value)
52
53
{
53
54
struct wm8350_gpio_data *wm8350_gpio = gpiochip_get_data(chip);
54
55
struct wm8350 *wm8350 = wm8350_gpio->wm8350;
55
56
56
57
if (value)
57
-
wm8350_set_bits(wm8350, WM8350_GPIO_LEVEL, 1 << offset);
58
-
else
59
-
wm8350_clear_bits(wm8350, WM8350_GPIO_LEVEL, 1 << offset);
58
+
return wm8350_set_bits(wm8350, WM8350_GPIO_LEVEL, 1 << offset);
59
+
60
+
return wm8350_clear_bits(wm8350, WM8350_GPIO_LEVEL, 1 << offset);
60
61
}
61
62
62
63
static int wm8350_gpio_direction_out(struct gpio_chip *chip,
···
73
72
return ret;
74
73
75
74
/* Don't have an atomic direction/value setup */
76
-
wm8350_gpio_set(chip, offset, value);
77
-
78
-
return 0;
75
+
return wm8350_gpio_set(chip, offset, value);
79
76
}
80
77
81
78
static int wm8350_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
···
93
94
.direction_input = wm8350_gpio_direction_in,
94
95
.get = wm8350_gpio_get,
95
96
.direction_output = wm8350_gpio_direction_out,
96
-
.set = wm8350_gpio_set,
97
+
.set_rv = wm8350_gpio_set,
97
98
.to_irq = wm8350_gpio_to_irq,
98
99
.can_sleep = true,
99
100
};
+5
-3
drivers/gpio/gpio-wm8994.c
+5
-3
drivers/gpio/gpio-wm8994.c
···
89
89
WM8994_GPN_DIR | WM8994_GPN_LVL, value);
90
90
}
91
91
92
-
static void wm8994_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
92
+
static int wm8994_gpio_set(struct gpio_chip *chip, unsigned int offset,
93
+
int value)
93
94
{
94
95
struct wm8994_gpio *wm8994_gpio = gpiochip_get_data(chip);
95
96
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
···
98
97
if (value)
99
98
value = WM8994_GPN_LVL;
100
99
101
-
wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset, WM8994_GPN_LVL, value);
100
+
return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset, WM8994_GPN_LVL,
101
+
value);
102
102
}
103
103
104
104
static int wm8994_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
···
256
254
.direction_input = wm8994_gpio_direction_in,
257
255
.get = wm8994_gpio_get,
258
256
.direction_output = wm8994_gpio_direction_out,
259
-
.set = wm8994_gpio_set,
257
+
.set_rv = wm8994_gpio_set,
260
258
.set_config = wm8994_gpio_set_config,
261
259
.to_irq = wm8994_gpio_to_irq,
262
260
.dbg_show = wm8994_gpio_dbg_show,
+4
-2
drivers/gpio/gpio-xgene.c
+4
-2
drivers/gpio/gpio-xgene.c
···
62
62
iowrite32(setval, chip->base + bank_offset);
63
63
}
64
64
65
-
static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
65
+
static int xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
66
66
{
67
67
struct xgene_gpio *chip = gpiochip_get_data(gc);
68
68
unsigned long flags;
···
70
70
spin_lock_irqsave(&chip->lock, flags);
71
71
__xgene_gpio_set(gc, offset, val);
72
72
spin_unlock_irqrestore(&chip->lock, flags);
73
+
74
+
return 0;
73
75
}
74
76
75
77
static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
···
178
176
gpio->chip.direction_input = xgene_gpio_dir_in;
179
177
gpio->chip.direction_output = xgene_gpio_dir_out;
180
178
gpio->chip.get = xgene_gpio_get;
181
-
gpio->chip.set = xgene_gpio_set;
179
+
gpio->chip.set_rv = xgene_gpio_set;
182
180
gpio->chip.label = dev_name(&pdev->dev);
183
181
gpio->chip.base = -1;
184
182
+9
-5
drivers/gpio/gpio-xilinx.c
+9
-5
drivers/gpio/gpio-xilinx.c
···
148
148
* This function writes the specified value in to the specified signal of the
149
149
* GPIO device.
150
150
*/
151
-
static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
151
+
static int xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
152
152
{
153
153
unsigned long flags;
154
154
struct xgpio_instance *chip = gpiochip_get_data(gc);
···
162
162
xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
163
163
164
164
raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
165
+
166
+
return 0;
165
167
}
166
168
167
169
/**
···
175
173
* This function writes the specified values into the specified signals of the
176
174
* GPIO devices.
177
175
*/
178
-
static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
179
-
unsigned long *bits)
176
+
static int xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
177
+
unsigned long *bits)
180
178
{
181
179
DECLARE_BITMAP(hw_mask, 64);
182
180
DECLARE_BITMAP(hw_bits, 64);
···
196
194
bitmap_copy(chip->state, state, 64);
197
195
198
196
raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
197
+
198
+
return 0;
199
199
}
200
200
201
201
/**
···
604
600
chip->gc.direction_input = xgpio_dir_in;
605
601
chip->gc.direction_output = xgpio_dir_out;
606
602
chip->gc.get = xgpio_get;
607
-
chip->gc.set = xgpio_set;
603
+
chip->gc.set_rv = xgpio_set;
608
604
chip->gc.request = xgpio_request;
609
605
chip->gc.free = xgpio_free;
610
-
chip->gc.set_multiple = xgpio_set_multiple;
606
+
chip->gc.set_multiple_rv = xgpio_set_multiple;
611
607
612
608
chip->gc.label = dev_name(dev);
613
609
+4
-6
drivers/gpio/gpio-xlp.c
+4
-6
drivers/gpio/gpio-xlp.c
···
206
206
{
207
207
struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
208
208
209
-
BUG_ON(gpio >= gc->ngpio);
210
209
xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
211
210
212
211
return 0;
···
215
216
{
216
217
struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
217
218
218
-
BUG_ON(gpio >= gc->ngpio);
219
219
xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
220
220
221
221
return 0;
···
224
226
{
225
227
struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
226
228
227
-
BUG_ON(gpio >= gc->ngpio);
228
229
return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
229
230
}
230
231
231
-
static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
232
+
static int xlp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int state)
232
233
{
233
234
struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
234
235
235
-
BUG_ON(gpio >= gc->ngpio);
236
236
xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
237
+
238
+
return 0;
237
239
}
238
240
239
241
static int xlp_gpio_probe(struct platform_device *pdev)
···
274
276
gc->ngpio = 70;
275
277
gc->direction_output = xlp_gpio_dir_output;
276
278
gc->direction_input = xlp_gpio_dir_input;
277
-
gc->set = xlp_gpio_set;
279
+
gc->set_rv = xlp_gpio_set;
278
280
gc->get = xlp_gpio_get;
279
281
280
282
spin_lock_init(&priv->lock);
+5
-8
drivers/gpio/gpio-xra1403.c
+5
-8
drivers/gpio/gpio-xra1403.c
···
102
102
return !!(val & BIT(offset % 8));
103
103
}
104
104
105
-
static void xra1403_set(struct gpio_chip *chip, unsigned int offset, int value)
105
+
static int xra1403_set(struct gpio_chip *chip, unsigned int offset, int value)
106
106
{
107
-
int ret;
108
107
struct xra1403 *xra = gpiochip_get_data(chip);
109
108
110
-
ret = regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
111
-
BIT(offset % 8), value ? BIT(offset % 8) : 0);
112
-
if (ret)
113
-
dev_err(chip->parent, "Failed to set pin: %d, ret: %d\n",
114
-
offset, ret);
109
+
return regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
110
+
BIT(offset % 8),
111
+
value ? BIT(offset % 8) : 0);
115
112
}
116
113
117
114
#ifdef CONFIG_DEBUG_FS
···
164
167
xra->chip.direction_output = xra1403_direction_output;
165
168
xra->chip.get_direction = xra1403_get_direction;
166
169
xra->chip.get = xra1403_get;
167
-
xra->chip.set = xra1403_set;
170
+
xra->chip.set_rv = xra1403_set;
168
171
169
172
xra->chip.dbg_show = xra1403_dbg_show;
170
173
+4
-9
drivers/gpio/gpio-xtensa.c
+4
-9
drivers/gpio/gpio-xtensa.c
···
86
86
return !!(impwire & BIT(offset));
87
87
}
88
88
89
-
static void xtensa_impwire_set_value(struct gpio_chip *gc, unsigned offset,
90
-
int value)
91
-
{
92
-
BUG(); /* output only; should never be called */
93
-
}
94
-
95
89
static int xtensa_expstate_get_direction(struct gpio_chip *gc, unsigned offset)
96
90
{
97
91
return GPIO_LINE_DIRECTION_OUT; /* output only */
···
103
109
return !!(expstate & BIT(offset));
104
110
}
105
111
106
-
static void xtensa_expstate_set_value(struct gpio_chip *gc, unsigned offset,
112
+
static int xtensa_expstate_set_value(struct gpio_chip *gc, unsigned int offset,
107
113
int value)
108
114
{
109
115
unsigned long flags, saved_cpenable;
···
114
120
__asm__ __volatile__("wrmsk_expstate %0, %1"
115
121
:: "a" (val), "a" (mask));
116
122
disable_cp(flags, saved_cpenable);
123
+
124
+
return 0;
117
125
}
118
126
119
127
static struct gpio_chip impwire_chip = {
···
124
128
.ngpio = 32,
125
129
.get_direction = xtensa_impwire_get_direction,
126
130
.get = xtensa_impwire_get_value,
127
-
.set = xtensa_impwire_set_value,
128
131
};
129
132
130
133
static struct gpio_chip expstate_chip = {
···
132
137
.ngpio = 32,
133
138
.get_direction = xtensa_expstate_get_direction,
134
139
.get = xtensa_expstate_get_value,
135
-
.set = xtensa_expstate_set_value,
140
+
.set_rv = xtensa_expstate_set_value,
136
141
};
137
142
138
143
static int xtensa_gpio_probe(struct platform_device *pdev)
+4
-2
drivers/gpio/gpio-zevio.c
+4
-2
drivers/gpio/gpio-zevio.c
···
91
91
return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
92
92
}
93
93
94
-
static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
94
+
static int zevio_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
95
95
{
96
96
struct zevio_gpio *controller = gpiochip_get_data(chip);
97
97
u32 val;
···
105
105
106
106
zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
107
107
spin_unlock(&controller->lock);
108
+
109
+
return 0;
108
110
}
109
111
110
112
static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
···
161
159
static const struct gpio_chip zevio_gpio_chip = {
162
160
.direction_input = zevio_gpio_direction_input,
163
161
.direction_output = zevio_gpio_direction_output,
164
-
.set = zevio_gpio_set,
162
+
.set_rv = zevio_gpio_set,
165
163
.get = zevio_gpio_get,
166
164
.to_irq = zevio_gpio_to_irq,
167
165
.base = 0,
+5
-3
drivers/gpio/gpio-zynq.c
+5
-3
drivers/gpio/gpio-zynq.c
···
265
265
* upper 16 bits) based on the given pin number and sets the state of a
266
266
* gpio pin to the specified value. The state is either 0 or non-zero.
267
267
*/
268
-
static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
269
-
int state)
268
+
static int zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
269
+
int state)
270
270
{
271
271
unsigned int reg_offset, bank_num, bank_pin_num;
272
272
struct zynq_gpio *gpio = gpiochip_get_data(chip);
···
290
290
((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
291
291
292
292
writel_relaxed(state, gpio->base_addr + reg_offset);
293
+
294
+
return 0;
293
295
}
294
296
295
297
/**
···
932
930
chip->owner = THIS_MODULE;
933
931
chip->parent = &pdev->dev;
934
932
chip->get = zynq_gpio_get_value;
935
-
chip->set = zynq_gpio_set_value;
933
+
chip->set_rv = zynq_gpio_set_value;
936
934
chip->request = zynq_gpio_request;
937
935
chip->free = zynq_gpio_free;
938
936
chip->direction_input = zynq_gpio_dir_in;
+6
-4
drivers/gpio/gpio-zynqmp-modepin.c
+6
-4
drivers/gpio/gpio-zynqmp-modepin.c
···
57
57
*
58
58
* Return: None.
59
59
*/
60
-
static void modepin_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
61
-
int state)
60
+
static int modepin_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
61
+
int state)
62
62
{
63
63
u32 bootpin_val = 0;
64
64
int ret;
···
77
77
ret = zynqmp_pm_bootmode_write(bootpin_val);
78
78
if (ret)
79
79
pr_err("modepin: set value error %d for pin %d\n", ret, pin);
80
+
81
+
return ret;
80
82
}
81
83
82
84
/**
···
104
102
static int modepin_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
105
103
int state)
106
104
{
107
-
return 0;
105
+
return modepin_gpio_set_value(chip, pin, state);
108
106
}
109
107
110
108
/**
···
130
128
chip->owner = THIS_MODULE;
131
129
chip->parent = &pdev->dev;
132
130
chip->get = modepin_gpio_get_value;
133
-
chip->set = modepin_gpio_set_value;
131
+
chip->set_rv = modepin_gpio_set_value;
134
132
chip->direction_input = modepin_gpio_dir_in;
135
133
chip->direction_output = modepin_gpio_dir_out;
136
134
chip->label = dev_name(&pdev->dev);
-38
drivers/gpio/gpiolib-legacy.c
-38
drivers/gpio/gpiolib-legacy.c
···
86
86
}
87
87
88
88
/**
89
-
* devm_gpio_request - request a GPIO for a managed device
90
-
* @dev: device to request the GPIO for
91
-
* @gpio: GPIO to allocate
92
-
* @label: the name of the requested GPIO
93
-
*
94
-
* Except for the extra @dev argument, this function takes the
95
-
* same arguments and performs the same function as gpio_request().
96
-
* GPIOs requested with this function will be automatically freed
97
-
* on driver detach.
98
-
*
99
-
* **DEPRECATED** This function is deprecated and must not be used in new code.
100
-
*
101
-
* Returns:
102
-
* 0 on success, or negative errno on failure.
103
-
*/
104
-
int devm_gpio_request(struct device *dev, unsigned gpio, const char *label)
105
-
{
106
-
unsigned *dr;
107
-
int rc;
108
-
109
-
dr = devres_alloc(devm_gpio_release, sizeof(unsigned), GFP_KERNEL);
110
-
if (!dr)
111
-
return -ENOMEM;
112
-
113
-
rc = gpio_request(gpio, label);
114
-
if (rc) {
115
-
devres_free(dr);
116
-
return rc;
117
-
}
118
-
119
-
*dr = gpio;
120
-
devres_add(dev, dr);
121
-
122
-
return 0;
123
-
}
124
-
EXPORT_SYMBOL_GPL(devm_gpio_request);
125
-
126
-
/**
127
89
* devm_gpio_request_one - request a single GPIO with initial setup
128
90
* @dev: device to request for
129
91
* @gpio: the GPIO number
+1
-1
drivers/gpio/gpiolib-of.h
+1
-1
drivers/gpio/gpiolib-of.h
+482
-194
drivers/gpio/gpiolib-sysfs.c
+482
-194
drivers/gpio/gpiolib-sysfs.c
···
3
3
#include <linux/bitops.h>
4
4
#include <linux/cleanup.h>
5
5
#include <linux/device.h>
6
-
#include <linux/idr.h>
7
6
#include <linux/init.h>
8
7
#include <linux/interrupt.h>
9
8
#include <linux/kdev_t.h>
···
11
12
#include <linux/mutex.h>
12
13
#include <linux/printk.h>
13
14
#include <linux/slab.h>
14
-
#include <linux/spinlock.h>
15
15
#include <linux/string.h>
16
16
#include <linux/srcu.h>
17
17
#include <linux/sysfs.h>
···
24
26
#include "gpiolib.h"
25
27
#include "gpiolib-sysfs.h"
26
28
29
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
30
+
27
31
struct kernfs_node;
28
32
29
33
#define GPIO_IRQF_TRIGGER_NONE 0
···
34
34
#define GPIO_IRQF_TRIGGER_BOTH (GPIO_IRQF_TRIGGER_FALLING | \
35
35
GPIO_IRQF_TRIGGER_RISING)
36
36
37
+
enum {
38
+
GPIO_SYSFS_LINE_CLASS_ATTR_DIRECTION = 0,
39
+
GPIO_SYSFS_LINE_CLASS_ATTR_VALUE,
40
+
GPIO_SYSFS_LINE_CLASS_ATTR_EDGE,
41
+
GPIO_SYSFS_LINE_CLASS_ATTR_ACTIVE_LOW,
42
+
GPIO_SYSFS_LINE_CLASS_ATTR_SENTINEL,
43
+
GPIO_SYSFS_LINE_CLASS_ATTR_SIZE,
44
+
};
45
+
46
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
47
+
48
+
enum {
49
+
GPIO_SYSFS_LINE_CHIP_ATTR_DIRECTION = 0,
50
+
GPIO_SYSFS_LINE_CHIP_ATTR_VALUE,
51
+
GPIO_SYSFS_LINE_CHIP_ATTR_SENTINEL,
52
+
GPIO_SYSFS_LINE_CHIP_ATTR_SIZE,
53
+
};
54
+
37
55
struct gpiod_data {
56
+
struct list_head list;
57
+
38
58
struct gpio_desc *desc;
59
+
struct device *dev;
39
60
40
61
struct mutex mutex;
62
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
41
63
struct kernfs_node *value_kn;
42
64
int irq;
43
65
unsigned char irq_flags;
66
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
44
67
45
68
bool direction_can_change;
69
+
70
+
struct kobject *parent;
71
+
struct device_attribute dir_attr;
72
+
struct device_attribute val_attr;
73
+
74
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
75
+
struct device_attribute edge_attr;
76
+
struct device_attribute active_low_attr;
77
+
78
+
struct attribute *class_attrs[GPIO_SYSFS_LINE_CLASS_ATTR_SIZE];
79
+
struct attribute_group class_attr_group;
80
+
const struct attribute_group *class_attr_groups[2];
81
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
82
+
83
+
struct attribute *chip_attrs[GPIO_SYSFS_LINE_CHIP_ATTR_SIZE];
84
+
struct attribute_group chip_attr_group;
85
+
const struct attribute_group *chip_attr_groups[2];
86
+
};
87
+
88
+
struct gpiodev_data {
89
+
struct list_head exported_lines;
90
+
struct gpio_device *gdev;
91
+
struct device *cdev_id; /* Class device by GPIO device ID */
92
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
93
+
struct device *cdev_base; /* Class device by GPIO base */
94
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
46
95
};
47
96
48
97
/*
···
122
73
*/
123
74
124
75
static ssize_t direction_show(struct device *dev,
125
-
struct device_attribute *attr, char *buf)
76
+
struct device_attribute *attr, char *buf)
126
77
{
127
-
struct gpiod_data *data = dev_get_drvdata(dev);
78
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
79
+
dir_attr);
128
80
struct gpio_desc *desc = data->desc;
129
81
int value;
130
82
···
138
88
}
139
89
140
90
static ssize_t direction_store(struct device *dev,
141
-
struct device_attribute *attr, const char *buf, size_t size)
91
+
struct device_attribute *attr, const char *buf,
92
+
size_t size)
142
93
{
143
-
struct gpiod_data *data = dev_get_drvdata(dev);
94
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
95
+
dir_attr);
144
96
struct gpio_desc *desc = data->desc;
145
-
ssize_t status;
97
+
ssize_t status;
146
98
147
99
guard(mutex)(&data->mutex);
148
100
···
159
107
160
108
return status ? : size;
161
109
}
162
-
static DEVICE_ATTR_RW(direction);
163
110
164
-
static ssize_t value_show(struct device *dev,
165
-
struct device_attribute *attr, char *buf)
111
+
static ssize_t value_show(struct device *dev, struct device_attribute *attr,
112
+
char *buf)
166
113
{
167
-
struct gpiod_data *data = dev_get_drvdata(dev);
114
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
115
+
val_attr);
168
116
struct gpio_desc *desc = data->desc;
169
-
ssize_t status;
117
+
ssize_t status;
170
118
171
119
scoped_guard(mutex, &data->mutex)
172
120
status = gpiod_get_value_cansleep(desc);
···
177
125
return sysfs_emit(buf, "%zd\n", status);
178
126
}
179
127
180
-
static ssize_t value_store(struct device *dev,
181
-
struct device_attribute *attr, const char *buf, size_t size)
128
+
static ssize_t value_store(struct device *dev, struct device_attribute *attr,
129
+
const char *buf, size_t size)
182
130
{
183
-
struct gpiod_data *data = dev_get_drvdata(dev);
131
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
132
+
val_attr);
184
133
struct gpio_desc *desc = data->desc;
185
134
ssize_t status;
186
135
long value;
···
198
145
199
146
return size;
200
147
}
201
-
static DEVICE_ATTR_PREALLOC(value, S_IWUSR | S_IRUGO, value_show, value_store);
202
148
149
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
203
150
static irqreturn_t gpio_sysfs_irq(int irq, void *priv)
204
151
{
205
152
struct gpiod_data *data = priv;
···
210
157
}
211
158
212
159
/* Caller holds gpiod-data mutex. */
213
-
static int gpio_sysfs_request_irq(struct device *dev, unsigned char flags)
160
+
static int gpio_sysfs_request_irq(struct gpiod_data *data, unsigned char flags)
214
161
{
215
-
struct gpiod_data *data = dev_get_drvdata(dev);
216
162
struct gpio_desc *desc = data->desc;
217
163
unsigned long irq_flags;
218
164
int ret;
···
224
172
if (data->irq < 0)
225
173
return -EIO;
226
174
227
-
data->value_kn = sysfs_get_dirent(dev->kobj.sd, "value");
228
-
if (!data->value_kn)
229
-
return -ENODEV;
230
-
231
175
irq_flags = IRQF_SHARED;
232
176
if (flags & GPIO_IRQF_TRIGGER_FALLING) {
233
177
irq_flags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ?
234
-
IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING;
178
+
IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING;
235
179
set_bit(FLAG_EDGE_FALLING, &desc->flags);
236
180
}
237
181
if (flags & GPIO_IRQF_TRIGGER_RISING) {
238
182
irq_flags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ?
239
-
IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING;
183
+
IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING;
240
184
set_bit(FLAG_EDGE_RISING, &desc->flags);
241
185
}
242
186
243
187
/*
244
188
* FIXME: This should be done in the irq_request_resources callback
245
-
* when the irq is requested, but a few drivers currently fail
246
-
* to do so.
189
+
* when the irq is requested, but a few drivers currently fail to do
190
+
* so.
247
191
*
248
-
* Remove this redundant call (along with the corresponding
249
-
* unlock) when those drivers have been fixed.
192
+
* Remove this redundant call (along with the corresponding unlock)
193
+
* when those drivers have been fixed.
250
194
*/
251
195
ret = gpiochip_lock_as_irq(guard.gc, gpio_chip_hwgpio(desc));
252
196
if (ret < 0)
253
-
goto err_put_kn;
197
+
goto err_clr_bits;
254
198
255
199
ret = request_any_context_irq(data->irq, gpio_sysfs_irq, irq_flags,
256
200
"gpiolib", data);
···
259
211
260
212
err_unlock:
261
213
gpiochip_unlock_as_irq(guard.gc, gpio_chip_hwgpio(desc));
262
-
err_put_kn:
214
+
err_clr_bits:
263
215
clear_bit(FLAG_EDGE_RISING, &desc->flags);
264
216
clear_bit(FLAG_EDGE_FALLING, &desc->flags);
265
-
sysfs_put(data->value_kn);
266
217
267
218
return ret;
268
219
}
···
270
223
* Caller holds gpiod-data mutex (unless called after class-device
271
224
* deregistration).
272
225
*/
273
-
static void gpio_sysfs_free_irq(struct device *dev)
226
+
static void gpio_sysfs_free_irq(struct gpiod_data *data)
274
227
{
275
-
struct gpiod_data *data = dev_get_drvdata(dev);
276
228
struct gpio_desc *desc = data->desc;
277
229
278
230
CLASS(gpio_chip_guard, guard)(desc);
···
283
237
gpiochip_unlock_as_irq(guard.gc, gpio_chip_hwgpio(desc));
284
238
clear_bit(FLAG_EDGE_RISING, &desc->flags);
285
239
clear_bit(FLAG_EDGE_FALLING, &desc->flags);
286
-
sysfs_put(data->value_kn);
287
240
}
288
241
289
-
static const char * const trigger_names[] = {
242
+
static const char *const trigger_names[] = {
290
243
[GPIO_IRQF_TRIGGER_NONE] = "none",
291
244
[GPIO_IRQF_TRIGGER_FALLING] = "falling",
292
245
[GPIO_IRQF_TRIGGER_RISING] = "rising",
293
246
[GPIO_IRQF_TRIGGER_BOTH] = "both",
294
247
};
295
248
296
-
static ssize_t edge_show(struct device *dev,
297
-
struct device_attribute *attr, char *buf)
249
+
static ssize_t edge_show(struct device *dev, struct device_attribute *attr,
250
+
char *buf)
298
251
{
299
-
struct gpiod_data *data = dev_get_drvdata(dev);
252
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
253
+
edge_attr);
300
254
int flags;
301
255
302
256
scoped_guard(mutex, &data->mutex)
···
308
262
return sysfs_emit(buf, "%s\n", trigger_names[flags]);
309
263
}
310
264
311
-
static ssize_t edge_store(struct device *dev,
312
-
struct device_attribute *attr, const char *buf, size_t size)
265
+
static ssize_t edge_store(struct device *dev, struct device_attribute *attr,
266
+
const char *buf, size_t size)
313
267
{
314
-
struct gpiod_data *data = dev_get_drvdata(dev);
268
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
269
+
edge_attr);
315
270
ssize_t status = size;
316
271
int flags;
317
272
···
326
279
return size;
327
280
328
281
if (data->irq_flags)
329
-
gpio_sysfs_free_irq(dev);
282
+
gpio_sysfs_free_irq(data);
330
283
331
284
if (!flags)
332
285
return size;
333
286
334
-
status = gpio_sysfs_request_irq(dev, flags);
287
+
status = gpio_sysfs_request_irq(data, flags);
335
288
if (status)
336
289
return status;
337
290
···
339
292
340
293
return size;
341
294
}
342
-
static DEVICE_ATTR_RW(edge);
343
295
344
296
/* Caller holds gpiod-data mutex. */
345
-
static int gpio_sysfs_set_active_low(struct device *dev, int value)
297
+
static int gpio_sysfs_set_active_low(struct gpiod_data *data, int value)
346
298
{
347
-
struct gpiod_data *data = dev_get_drvdata(dev);
348
299
unsigned int flags = data->irq_flags;
349
300
struct gpio_desc *desc = data->desc;
350
301
int status = 0;
351
-
352
302
353
303
if (!!test_bit(FLAG_ACTIVE_LOW, &desc->flags) == !!value)
354
304
return 0;
···
354
310
355
311
/* reconfigure poll(2) support if enabled on one edge only */
356
312
if (flags == GPIO_IRQF_TRIGGER_FALLING ||
357
-
flags == GPIO_IRQF_TRIGGER_RISING) {
358
-
gpio_sysfs_free_irq(dev);
359
-
status = gpio_sysfs_request_irq(dev, flags);
313
+
flags == GPIO_IRQF_TRIGGER_RISING) {
314
+
gpio_sysfs_free_irq(data);
315
+
status = gpio_sysfs_request_irq(data, flags);
360
316
}
361
317
362
318
gpiod_line_state_notify(desc, GPIO_V2_LINE_CHANGED_CONFIG);
···
365
321
}
366
322
367
323
static ssize_t active_low_show(struct device *dev,
368
-
struct device_attribute *attr, char *buf)
324
+
struct device_attribute *attr, char *buf)
369
325
{
370
-
struct gpiod_data *data = dev_get_drvdata(dev);
326
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
327
+
active_low_attr);
371
328
struct gpio_desc *desc = data->desc;
372
329
int value;
373
330
···
379
334
}
380
335
381
336
static ssize_t active_low_store(struct device *dev,
382
-
struct device_attribute *attr, const char *buf, size_t size)
337
+
struct device_attribute *attr,
338
+
const char *buf, size_t size)
383
339
{
384
-
struct gpiod_data *data = dev_get_drvdata(dev);
340
+
struct gpiod_data *data = container_of(attr, struct gpiod_data,
341
+
active_low_attr);
385
342
ssize_t status;
386
343
long value;
387
344
···
393
346
394
347
guard(mutex)(&data->mutex);
395
348
396
-
return gpio_sysfs_set_active_low(dev, value) ?: size;
349
+
return gpio_sysfs_set_active_low(data, value) ?: size;
397
350
}
398
-
static DEVICE_ATTR_RW(active_low);
351
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
399
352
400
353
static umode_t gpio_is_visible(struct kobject *kobj, struct attribute *attr,
401
354
int n)
402
355
{
403
-
struct device *dev = kobj_to_dev(kobj);
404
-
struct gpiod_data *data = dev_get_drvdata(dev);
405
-
struct gpio_desc *desc = data->desc;
356
+
struct device_attribute *dev_attr = container_of(attr,
357
+
struct device_attribute, attr);
406
358
umode_t mode = attr->mode;
407
-
bool show_direction = data->direction_can_change;
359
+
struct gpiod_data *data;
408
360
409
-
if (attr == &dev_attr_direction.attr) {
410
-
if (!show_direction)
361
+
if (strcmp(attr->name, "direction") == 0) {
362
+
data = container_of(dev_attr, struct gpiod_data, dir_attr);
363
+
364
+
if (!data->direction_can_change)
411
365
mode = 0;
412
-
} else if (attr == &dev_attr_edge.attr) {
413
-
if (gpiod_to_irq(desc) < 0)
366
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
367
+
} else if (strcmp(attr->name, "edge") == 0) {
368
+
data = container_of(dev_attr, struct gpiod_data, edge_attr);
369
+
370
+
if (gpiod_to_irq(data->desc) < 0)
414
371
mode = 0;
415
-
if (!show_direction && test_bit(FLAG_IS_OUT, &desc->flags))
372
+
373
+
if (!data->direction_can_change &&
374
+
test_bit(FLAG_IS_OUT, &data->desc->flags))
416
375
mode = 0;
376
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
417
377
}
418
378
419
379
return mode;
420
380
}
421
-
422
-
static struct attribute *gpio_attrs[] = {
423
-
&dev_attr_direction.attr,
424
-
&dev_attr_edge.attr,
425
-
&dev_attr_value.attr,
426
-
&dev_attr_active_low.attr,
427
-
NULL,
428
-
};
429
-
430
-
static const struct attribute_group gpio_group = {
431
-
.attrs = gpio_attrs,
432
-
.is_visible = gpio_is_visible,
433
-
};
434
-
435
-
static const struct attribute_group *gpio_groups[] = {
436
-
&gpio_group,
437
-
NULL
438
-
};
439
381
440
382
/*
441
383
* /sys/class/gpio/gpiochipN/
442
384
* /base ... matching gpio_chip.base (N)
443
385
* /label ... matching gpio_chip.label
444
386
* /ngpio ... matching gpio_chip.ngpio
387
+
*
388
+
* AND
389
+
*
390
+
* /sys/class/gpio/chipX/
391
+
* /export ... export GPIO at given offset
392
+
* /unexport ... unexport GPIO at given offset
393
+
* /label ... matching gpio_chip.label
394
+
* /ngpio ... matching gpio_chip.ngpio
445
395
*/
446
396
447
-
static ssize_t base_show(struct device *dev,
448
-
struct device_attribute *attr, char *buf)
397
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
398
+
static ssize_t base_show(struct device *dev, struct device_attribute *attr,
399
+
char *buf)
449
400
{
450
-
const struct gpio_device *gdev = dev_get_drvdata(dev);
401
+
const struct gpiodev_data *data = dev_get_drvdata(dev);
451
402
452
-
return sysfs_emit(buf, "%u\n", gdev->base);
403
+
return sysfs_emit(buf, "%u\n", data->gdev->base);
453
404
}
454
405
static DEVICE_ATTR_RO(base);
406
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
455
407
456
-
static ssize_t label_show(struct device *dev,
457
-
struct device_attribute *attr, char *buf)
408
+
static ssize_t label_show(struct device *dev, struct device_attribute *attr,
409
+
char *buf)
458
410
{
459
-
const struct gpio_device *gdev = dev_get_drvdata(dev);
411
+
const struct gpiodev_data *data = dev_get_drvdata(dev);
460
412
461
-
return sysfs_emit(buf, "%s\n", gdev->label);
413
+
return sysfs_emit(buf, "%s\n", data->gdev->label);
462
414
}
463
415
static DEVICE_ATTR_RO(label);
464
416
465
-
static ssize_t ngpio_show(struct device *dev,
466
-
struct device_attribute *attr, char *buf)
417
+
static ssize_t ngpio_show(struct device *dev, struct device_attribute *attr,
418
+
char *buf)
467
419
{
468
-
const struct gpio_device *gdev = dev_get_drvdata(dev);
420
+
const struct gpiodev_data *data = dev_get_drvdata(dev);
469
421
470
-
return sysfs_emit(buf, "%u\n", gdev->ngpio);
422
+
return sysfs_emit(buf, "%u\n", data->gdev->ngpio);
471
423
}
472
424
static DEVICE_ATTR_RO(ngpio);
473
425
426
+
static int export_gpio_desc(struct gpio_desc *desc)
427
+
{
428
+
int offset, ret;
429
+
430
+
CLASS(gpio_chip_guard, guard)(desc);
431
+
if (!guard.gc)
432
+
return -ENODEV;
433
+
434
+
offset = gpio_chip_hwgpio(desc);
435
+
if (!gpiochip_line_is_valid(guard.gc, offset)) {
436
+
pr_debug_ratelimited("%s: GPIO %d masked\n", __func__,
437
+
gpio_chip_hwgpio(desc));
438
+
return -EINVAL;
439
+
}
440
+
441
+
/*
442
+
* No extra locking here; FLAG_SYSFS just signifies that the
443
+
* request and export were done by on behalf of userspace, so
444
+
* they may be undone on its behalf too.
445
+
*/
446
+
447
+
ret = gpiod_request_user(desc, "sysfs");
448
+
if (ret)
449
+
return ret;
450
+
451
+
ret = gpiod_set_transitory(desc, false);
452
+
if (ret) {
453
+
gpiod_free(desc);
454
+
return ret;
455
+
}
456
+
457
+
ret = gpiod_export(desc, true);
458
+
if (ret < 0) {
459
+
gpiod_free(desc);
460
+
} else {
461
+
set_bit(FLAG_SYSFS, &desc->flags);
462
+
gpiod_line_state_notify(desc, GPIO_V2_LINE_CHANGED_REQUESTED);
463
+
}
464
+
465
+
return ret;
466
+
}
467
+
468
+
static int unexport_gpio_desc(struct gpio_desc *desc)
469
+
{
470
+
/*
471
+
* No extra locking here; FLAG_SYSFS just signifies that the
472
+
* request and export were done by on behalf of userspace, so
473
+
* they may be undone on its behalf too.
474
+
*/
475
+
if (!test_and_clear_bit(FLAG_SYSFS, &desc->flags))
476
+
return -EINVAL;
477
+
478
+
gpiod_unexport(desc);
479
+
gpiod_free(desc);
480
+
481
+
return 0;
482
+
}
483
+
484
+
static ssize_t do_chip_export_store(struct device *dev,
485
+
struct device_attribute *attr,
486
+
const char *buf, ssize_t size,
487
+
int (*handler)(struct gpio_desc *desc))
488
+
{
489
+
struct gpiodev_data *data = dev_get_drvdata(dev);
490
+
struct gpio_device *gdev = data->gdev;
491
+
struct gpio_desc *desc;
492
+
unsigned int gpio;
493
+
int ret;
494
+
495
+
ret = kstrtouint(buf, 0, &gpio);
496
+
if (ret)
497
+
return ret;
498
+
499
+
desc = gpio_device_get_desc(gdev, gpio);
500
+
if (IS_ERR(desc))
501
+
return PTR_ERR(desc);
502
+
503
+
ret = handler(desc);
504
+
if (ret)
505
+
return ret;
506
+
507
+
return size;
508
+
}
509
+
510
+
static ssize_t chip_export_store(struct device *dev,
511
+
struct device_attribute *attr,
512
+
const char *buf, size_t size)
513
+
{
514
+
return do_chip_export_store(dev, attr, buf, size, export_gpio_desc);
515
+
}
516
+
517
+
static struct device_attribute dev_attr_export = __ATTR(export, 0200, NULL,
518
+
chip_export_store);
519
+
520
+
static ssize_t chip_unexport_store(struct device *dev,
521
+
struct device_attribute *attr,
522
+
const char *buf, size_t size)
523
+
{
524
+
return do_chip_export_store(dev, attr, buf, size, unexport_gpio_desc);
525
+
}
526
+
527
+
static struct device_attribute dev_attr_unexport = __ATTR(unexport, 0200,
528
+
NULL,
529
+
chip_unexport_store);
530
+
531
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
474
532
static struct attribute *gpiochip_attrs[] = {
475
533
&dev_attr_base.attr,
476
534
&dev_attr_label.attr,
···
583
431
NULL,
584
432
};
585
433
ATTRIBUTE_GROUPS(gpiochip);
434
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
586
435
436
+
static struct attribute *gpiochip_ext_attrs[] = {
437
+
&dev_attr_label.attr,
438
+
&dev_attr_ngpio.attr,
439
+
&dev_attr_export.attr,
440
+
&dev_attr_unexport.attr,
441
+
NULL
442
+
};
443
+
ATTRIBUTE_GROUPS(gpiochip_ext);
444
+
445
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
587
446
/*
588
447
* /sys/class/gpio/export ... write-only
589
448
* integer N ... number of GPIO to export (full access)
···
602
439
* integer N ... number of GPIO to unexport
603
440
*/
604
441
static ssize_t export_store(const struct class *class,
605
-
const struct class_attribute *attr,
606
-
const char *buf, size_t len)
442
+
const struct class_attribute *attr,
443
+
const char *buf, size_t len)
607
444
{
608
445
struct gpio_desc *desc;
609
-
int status, offset;
446
+
int status;
610
447
long gpio;
611
448
612
449
status = kstrtol(buf, 0, &gpio);
···
620
457
return -EINVAL;
621
458
}
622
459
623
-
CLASS(gpio_chip_guard, guard)(desc);
624
-
if (!guard.gc)
625
-
return -ENODEV;
626
-
627
-
offset = gpio_chip_hwgpio(desc);
628
-
if (!gpiochip_line_is_valid(guard.gc, offset)) {
629
-
pr_debug_ratelimited("%s: GPIO %ld masked\n", __func__, gpio);
630
-
return -EINVAL;
631
-
}
632
-
633
-
/* No extra locking here; FLAG_SYSFS just signifies that the
634
-
* request and export were done by on behalf of userspace, so
635
-
* they may be undone on its behalf too.
636
-
*/
637
-
638
-
status = gpiod_request_user(desc, "sysfs");
639
-
if (status)
640
-
goto done;
641
-
642
-
status = gpiod_set_transitory(desc, false);
643
-
if (status) {
644
-
gpiod_free(desc);
645
-
goto done;
646
-
}
647
-
648
-
status = gpiod_export(desc, true);
649
-
if (status < 0) {
650
-
gpiod_free(desc);
651
-
} else {
652
-
set_bit(FLAG_SYSFS, &desc->flags);
653
-
gpiod_line_state_notify(desc, GPIO_V2_LINE_CHANGED_REQUESTED);
654
-
}
655
-
656
-
done:
460
+
status = export_gpio_desc(desc);
657
461
if (status)
658
462
pr_debug("%s: status %d\n", __func__, status);
659
463
return status ? : len;
···
628
498
static CLASS_ATTR_WO(export);
629
499
630
500
static ssize_t unexport_store(const struct class *class,
631
-
const struct class_attribute *attr,
632
-
const char *buf, size_t len)
501
+
const struct class_attribute *attr,
502
+
const char *buf, size_t len)
633
503
{
634
504
struct gpio_desc *desc;
635
505
int status;
···
637
507
638
508
status = kstrtol(buf, 0, &gpio);
639
509
if (status < 0)
640
-
goto done;
510
+
return status;
641
511
642
512
desc = gpio_to_desc(gpio);
643
513
/* reject bogus commands (gpiod_unexport() ignores them) */
···
646
516
return -EINVAL;
647
517
}
648
518
649
-
status = -EINVAL;
650
-
651
-
/* No extra locking here; FLAG_SYSFS just signifies that the
652
-
* request and export were done by on behalf of userspace, so
653
-
* they may be undone on its behalf too.
654
-
*/
655
-
if (test_and_clear_bit(FLAG_SYSFS, &desc->flags)) {
656
-
gpiod_unexport(desc);
657
-
gpiod_free(desc);
658
-
status = 0;
659
-
}
660
-
done:
519
+
status = unexport_gpio_desc(desc);
661
520
if (status)
662
521
pr_debug("%s: status %d\n", __func__, status);
663
522
return status ? : len;
···
659
540
NULL,
660
541
};
661
542
ATTRIBUTE_GROUPS(gpio_class);
543
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
662
544
663
545
static const struct class gpio_class = {
664
546
.name = "gpio",
547
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
665
548
.class_groups = gpio_class_groups,
549
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
666
550
};
551
+
552
+
static int match_gdev(struct device *dev, const void *desc)
553
+
{
554
+
struct gpiodev_data *data = dev_get_drvdata(dev);
555
+
const struct gpio_device *gdev = desc;
556
+
557
+
return data && data->gdev == gdev;
558
+
}
559
+
560
+
static struct gpiodev_data *
561
+
gdev_get_data(struct gpio_device *gdev) __must_hold(&sysfs_lock)
562
+
{
563
+
/*
564
+
* Find the first device in GPIO class that matches. Whether that's
565
+
* the one indexed by GPIO base or device ID doesn't matter, it has
566
+
* the same address set as driver data.
567
+
*/
568
+
struct device *cdev __free(put_device) = class_find_device(&gpio_class,
569
+
NULL, gdev,
570
+
match_gdev);
571
+
if (!cdev)
572
+
return NULL;
573
+
574
+
return dev_get_drvdata(cdev);
575
+
};
576
+
577
+
static void gpiod_attr_init(struct device_attribute *dev_attr, const char *name,
578
+
ssize_t (*show)(struct device *dev,
579
+
struct device_attribute *attr,
580
+
char *buf),
581
+
ssize_t (*store)(struct device *dev,
582
+
struct device_attribute *attr,
583
+
const char *buf, size_t count))
584
+
{
585
+
sysfs_attr_init(&dev_attr->attr);
586
+
dev_attr->attr.name = name;
587
+
dev_attr->attr.mode = 0644;
588
+
dev_attr->show = show;
589
+
dev_attr->store = store;
590
+
}
667
591
668
592
/**
669
593
* gpiod_export - export a GPIO through sysfs
···
726
564
*/
727
565
int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
728
566
{
567
+
char *path __free(kfree) = NULL;
568
+
struct gpiodev_data *gdev_data;
569
+
struct gpiod_data *desc_data;
729
570
struct gpio_device *gdev;
730
-
struct gpiod_data *data;
731
-
struct device *dev;
571
+
struct attribute **attrs;
732
572
int status;
733
573
734
574
/* can't export until sysfs is available ... */
···
755
591
756
592
guard(mutex)(&sysfs_lock);
757
593
758
-
/* check if chip is being removed */
759
-
if (!gdev->mockdev) {
760
-
status = -ENODEV;
761
-
goto err_clear_bit;
762
-
}
763
-
764
594
if (!test_bit(FLAG_REQUESTED, &desc->flags)) {
765
595
gpiod_dbg(desc, "%s: unavailable (not requested)\n", __func__);
766
596
status = -EPERM;
767
597
goto err_clear_bit;
768
598
}
769
599
770
-
data = kzalloc(sizeof(*data), GFP_KERNEL);
771
-
if (!data) {
600
+
desc_data = kzalloc(sizeof(*desc_data), GFP_KERNEL);
601
+
if (!desc_data) {
772
602
status = -ENOMEM;
773
603
goto err_clear_bit;
774
604
}
775
605
776
-
data->desc = desc;
777
-
mutex_init(&data->mutex);
606
+
desc_data->desc = desc;
607
+
mutex_init(&desc_data->mutex);
778
608
if (guard.gc->direction_input && guard.gc->direction_output)
779
-
data->direction_can_change = direction_may_change;
609
+
desc_data->direction_can_change = direction_may_change;
780
610
else
781
-
data->direction_can_change = false;
611
+
desc_data->direction_can_change = false;
782
612
783
-
dev = device_create_with_groups(&gpio_class, &gdev->dev,
784
-
MKDEV(0, 0), data, gpio_groups,
785
-
"gpio%u", desc_to_gpio(desc));
786
-
if (IS_ERR(dev)) {
787
-
status = PTR_ERR(dev);
613
+
gpiod_attr_init(&desc_data->dir_attr, "direction",
614
+
direction_show, direction_store);
615
+
gpiod_attr_init(&desc_data->val_attr, "value", value_show, value_store);
616
+
617
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
618
+
gpiod_attr_init(&desc_data->edge_attr, "edge", edge_show, edge_store);
619
+
gpiod_attr_init(&desc_data->active_low_attr, "active_low",
620
+
active_low_show, active_low_store);
621
+
622
+
attrs = desc_data->class_attrs;
623
+
desc_data->class_attr_group.is_visible = gpio_is_visible;
624
+
attrs[GPIO_SYSFS_LINE_CLASS_ATTR_DIRECTION] = &desc_data->dir_attr.attr;
625
+
attrs[GPIO_SYSFS_LINE_CLASS_ATTR_VALUE] = &desc_data->val_attr.attr;
626
+
attrs[GPIO_SYSFS_LINE_CLASS_ATTR_EDGE] = &desc_data->edge_attr.attr;
627
+
attrs[GPIO_SYSFS_LINE_CLASS_ATTR_ACTIVE_LOW] = &desc_data->active_low_attr.attr;
628
+
629
+
desc_data->class_attr_group.attrs = desc_data->class_attrs;
630
+
desc_data->class_attr_groups[0] = &desc_data->class_attr_group;
631
+
632
+
/*
633
+
* Note: we need to continue passing desc_data here as there's still
634
+
* at least one known user of gpiod_export_link() in the tree. This
635
+
* function still uses class_find_device() internally.
636
+
*/
637
+
desc_data->dev = device_create_with_groups(&gpio_class, &gdev->dev,
638
+
MKDEV(0, 0), desc_data,
639
+
desc_data->class_attr_groups,
640
+
"gpio%u",
641
+
desc_to_gpio(desc));
642
+
if (IS_ERR(desc_data->dev)) {
643
+
status = PTR_ERR(desc_data->dev);
788
644
goto err_free_data;
789
645
}
790
646
647
+
desc_data->value_kn = sysfs_get_dirent(desc_data->dev->kobj.sd,
648
+
"value");
649
+
if (!desc_data->value_kn) {
650
+
status = -ENODEV;
651
+
goto err_unregister_device;
652
+
}
653
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
654
+
655
+
gdev_data = gdev_get_data(gdev);
656
+
if (!gdev_data) {
657
+
status = -ENODEV;
658
+
goto err_put_dirent;
659
+
}
660
+
661
+
desc_data->chip_attr_group.name = kasprintf(GFP_KERNEL, "gpio%u",
662
+
gpio_chip_hwgpio(desc));
663
+
if (!desc_data->chip_attr_group.name) {
664
+
status = -ENOMEM;
665
+
goto err_put_dirent;
666
+
}
667
+
668
+
attrs = desc_data->chip_attrs;
669
+
desc_data->chip_attr_group.is_visible = gpio_is_visible;
670
+
attrs[GPIO_SYSFS_LINE_CHIP_ATTR_DIRECTION] = &desc_data->dir_attr.attr;
671
+
attrs[GPIO_SYSFS_LINE_CHIP_ATTR_VALUE] = &desc_data->val_attr.attr;
672
+
673
+
desc_data->chip_attr_group.attrs = attrs;
674
+
desc_data->chip_attr_groups[0] = &desc_data->chip_attr_group;
675
+
676
+
desc_data->parent = &gdev_data->cdev_id->kobj;
677
+
status = sysfs_create_groups(desc_data->parent,
678
+
desc_data->chip_attr_groups);
679
+
if (status)
680
+
goto err_free_name;
681
+
682
+
path = kasprintf(GFP_KERNEL, "gpio%u/value", gpio_chip_hwgpio(desc));
683
+
if (!path) {
684
+
status = -ENOMEM;
685
+
goto err_remove_groups;
686
+
}
687
+
688
+
list_add(&desc_data->list, &gdev_data->exported_lines);
689
+
791
690
return 0;
792
691
692
+
err_remove_groups:
693
+
sysfs_remove_groups(desc_data->parent, desc_data->chip_attr_groups);
694
+
err_free_name:
695
+
kfree(desc_data->chip_attr_group.name);
696
+
err_put_dirent:
697
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
698
+
sysfs_put(desc_data->value_kn);
699
+
err_unregister_device:
700
+
device_unregister(desc_data->dev);
793
701
err_free_data:
794
-
kfree(data);
702
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
703
+
kfree(desc_data);
795
704
err_clear_bit:
796
705
clear_bit(FLAG_EXPORT, &desc->flags);
797
706
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
···
872
635
}
873
636
EXPORT_SYMBOL_GPL(gpiod_export);
874
637
638
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
875
639
static int match_export(struct device *dev, const void *desc)
876
640
{
877
641
struct gpiod_data *data = dev_get_drvdata(dev);
878
642
879
-
return data->desc == desc;
643
+
return gpiod_is_equal(data->desc, desc);
880
644
}
645
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
881
646
882
647
/**
883
648
* gpiod_export_link - create a sysfs link to an exported GPIO node
···
896
657
int gpiod_export_link(struct device *dev, const char *name,
897
658
struct gpio_desc *desc)
898
659
{
660
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
899
661
struct device *cdev;
900
662
int ret;
901
663
···
913
673
put_device(cdev);
914
674
915
675
return ret;
676
+
#else
677
+
return -EOPNOTSUPP;
678
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
916
679
}
917
680
EXPORT_SYMBOL_GPL(gpiod_export_link);
918
681
···
927
684
*/
928
685
void gpiod_unexport(struct gpio_desc *desc)
929
686
{
930
-
struct gpiod_data *data;
931
-
struct device *dev;
687
+
struct gpiod_data *tmp, *desc_data = NULL;
688
+
struct gpiodev_data *gdev_data;
689
+
struct gpio_device *gdev;
932
690
933
691
if (!desc) {
934
692
pr_warn("%s: invalid GPIO\n", __func__);
···
940
696
if (!test_bit(FLAG_EXPORT, &desc->flags))
941
697
return;
942
698
943
-
dev = class_find_device(&gpio_class, NULL, desc, match_export);
944
-
if (!dev)
699
+
gdev = gpiod_to_gpio_device(desc);
700
+
gdev_data = gdev_get_data(gdev);
701
+
if (!gdev_data)
945
702
return;
946
703
947
-
data = dev_get_drvdata(dev);
704
+
list_for_each_entry(tmp, &gdev_data->exported_lines, list) {
705
+
if (gpiod_is_equal(desc, tmp->desc)) {
706
+
desc_data = tmp;
707
+
break;
708
+
}
709
+
}
710
+
711
+
if (!desc_data)
712
+
return;
713
+
714
+
list_del(&desc_data->list);
948
715
clear_bit(FLAG_EXPORT, &desc->flags);
949
-
device_unregister(dev);
716
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
717
+
sysfs_put(desc_data->value_kn);
718
+
device_unregister(desc_data->dev);
950
719
951
720
/*
952
721
* Release irq after deregistration to prevent race with
953
722
* edge_store.
954
723
*/
955
-
if (data->irq_flags)
956
-
gpio_sysfs_free_irq(dev);
724
+
if (desc_data->irq_flags)
725
+
gpio_sysfs_free_irq(desc_data);
726
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
727
+
728
+
sysfs_remove_groups(desc_data->parent,
729
+
desc_data->chip_attr_groups);
957
730
}
958
731
959
-
put_device(dev);
960
-
kfree(data);
732
+
mutex_destroy(&desc_data->mutex);
733
+
kfree(desc_data);
961
734
}
962
735
EXPORT_SYMBOL_GPL(gpiod_unexport);
963
736
964
737
int gpiochip_sysfs_register(struct gpio_device *gdev)
965
738
{
739
+
struct gpiodev_data *data;
966
740
struct gpio_chip *chip;
967
741
struct device *parent;
968
-
struct device *dev;
742
+
int err;
969
743
970
744
/*
971
745
* Many systems add gpio chips for SOC support very early,
···
1009
747
else
1010
748
parent = &gdev->dev;
1011
749
1012
-
/* use chip->base for the ID; it's already known to be unique */
1013
-
dev = device_create_with_groups(&gpio_class, parent, MKDEV(0, 0), gdev,
1014
-
gpiochip_groups, GPIOCHIP_NAME "%d",
1015
-
chip->base);
1016
-
if (IS_ERR(dev))
1017
-
return PTR_ERR(dev);
750
+
data = kmalloc(sizeof(*data), GFP_KERNEL);
751
+
if (!data)
752
+
return -ENOMEM;
753
+
754
+
data->gdev = gdev;
755
+
INIT_LIST_HEAD(&data->exported_lines);
1018
756
1019
757
guard(mutex)(&sysfs_lock);
1020
-
gdev->mockdev = dev;
758
+
759
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
760
+
/* use chip->base for the ID; it's already known to be unique */
761
+
data->cdev_base = device_create_with_groups(&gpio_class, parent,
762
+
MKDEV(0, 0), data,
763
+
gpiochip_groups,
764
+
GPIOCHIP_NAME "%d",
765
+
chip->base);
766
+
if (IS_ERR(data->cdev_base)) {
767
+
err = PTR_ERR(data->cdev_base);
768
+
kfree(data);
769
+
return err;
770
+
}
771
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
772
+
773
+
data->cdev_id = device_create_with_groups(&gpio_class, parent,
774
+
MKDEV(0, 0), data,
775
+
gpiochip_ext_groups,
776
+
"chip%d", gdev->id);
777
+
if (IS_ERR(data->cdev_id)) {
778
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
779
+
device_unregister(data->cdev_base);
780
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
781
+
err = PTR_ERR(data->cdev_id);
782
+
kfree(data);
783
+
return err;
784
+
}
1021
785
1022
786
return 0;
1023
787
}
1024
788
1025
789
void gpiochip_sysfs_unregister(struct gpio_device *gdev)
1026
790
{
791
+
struct gpiodev_data *data;
1027
792
struct gpio_desc *desc;
1028
793
struct gpio_chip *chip;
1029
794
1030
795
scoped_guard(mutex, &sysfs_lock) {
1031
-
if (!gdev->mockdev)
796
+
data = gdev_get_data(gdev);
797
+
if (!data)
1032
798
return;
1033
799
1034
-
device_unregister(gdev->mockdev);
1035
-
1036
-
/* prevent further gpiod exports */
1037
-
gdev->mockdev = NULL;
800
+
#if IS_ENABLED(CONFIG_GPIO_SYSFS_LEGACY)
801
+
device_unregister(data->cdev_base);
802
+
#endif /* CONFIG_GPIO_SYSFS_LEGACY */
803
+
device_unregister(data->cdev_id);
804
+
kfree(data);
1038
805
}
1039
806
1040
807
guard(srcu)(&gdev->srcu);
···
1088
797
{
1089
798
struct gpio_device *gdev = gc->gpiodev;
1090
799
int ret;
1091
-
1092
-
if (gdev->mockdev)
1093
-
return 0;
1094
800
1095
801
ret = gpiochip_sysfs_register(gdev);
1096
802
if (ret)
+30
-17
drivers/gpio/gpiolib.c
+30
-17
drivers/gpio/gpiolib.c
···
75
75
};
76
76
77
77
/*
78
+
* At the end we want all GPIOs to be dynamically allocated from 0.
79
+
* However, some legacy drivers still perform fixed allocation.
80
+
* Until they are all fixed, leave 0-512 space for them.
81
+
*/
82
+
#define GPIO_DYNAMIC_BASE 512
83
+
/*
84
+
* Define the maximum of the possible GPIO in the global numberspace.
85
+
* While the GPIO base and numbers are positive, we limit it with signed
86
+
* maximum as a lot of code is using negative values for special cases.
87
+
*/
88
+
#define GPIO_DYNAMIC_MAX INT_MAX
89
+
90
+
/*
78
91
* Number of GPIOs to use for the fast path in set array
79
92
*/
80
93
#define FASTPATH_NGPIO CONFIG_GPIOLIB_FASTPATH_LIMIT
···
279
266
EXPORT_SYMBOL_GPL(gpiod_to_gpio_device);
280
267
281
268
/**
282
-
* gpiod_is_equal() - Check if two GPIO descriptors refer to the same pin.
283
-
* @desc: Descriptor to compare.
284
-
* @other: The second descriptor to compare against.
285
-
*
286
-
* Returns:
287
-
* True if the descriptors refer to the same physical pin. False otherwise.
288
-
*/
289
-
bool gpiod_is_equal(struct gpio_desc *desc, struct gpio_desc *other)
290
-
{
291
-
return desc == other;
292
-
}
293
-
EXPORT_SYMBOL_GPL(gpiod_is_equal);
294
-
295
-
/**
296
269
* gpio_device_get_base() - Get the base GPIO number allocated by this device
297
270
* @gdev: GPIO device
298
271
*
···
385
386
if (__valid <= 0) \
386
387
return; \
387
388
} while (0)
389
+
390
+
/**
391
+
* gpiod_is_equal() - Check if two GPIO descriptors refer to the same pin.
392
+
* @desc: Descriptor to compare.
393
+
* @other: The second descriptor to compare against.
394
+
*
395
+
* Returns:
396
+
* True if the descriptors refer to the same physical pin. False otherwise.
397
+
*/
398
+
bool gpiod_is_equal(const struct gpio_desc *desc, const struct gpio_desc *other)
399
+
{
400
+
return validate_desc(desc, __func__) > 0 &&
401
+
!IS_ERR_OR_NULL(other) && desc == other;
402
+
}
403
+
EXPORT_SYMBOL_GPL(gpiod_is_equal);
388
404
389
405
static int gpiochip_get_direction(struct gpio_chip *gc, unsigned int offset)
390
406
{
···
5235
5221
static void gpiolib_dbg_show(struct seq_file *s, struct gpio_device *gdev)
5236
5222
{
5237
5223
bool active_low, is_irq, is_out;
5238
-
unsigned int gpio = gdev->base;
5239
5224
struct gpio_desc *desc;
5225
+
unsigned int gpio = 0;
5240
5226
struct gpio_chip *gc;
5241
5227
unsigned long flags;
5242
5228
int value;
···
5340
5326
return 0;
5341
5327
}
5342
5328
5343
-
seq_printf(s, "%s: GPIOs %u-%u", dev_name(&gdev->dev), gdev->base,
5344
-
gdev->base + gdev->ngpio - 1);
5329
+
seq_printf(s, "%s: %u GPIOs", dev_name(&gdev->dev), gdev->ngpio);
5345
5330
parent = gc->parent;
5346
5331
if (parent)
5347
5332
seq_printf(s, ", parent: %s/%s",
-3
drivers/gpio/gpiolib.h
-3
drivers/gpio/gpiolib.h
···
27
27
* @dev: the GPIO device struct
28
28
* @chrdev: character device for the GPIO device
29
29
* @id: numerical ID number for the GPIO chip
30
-
* @mockdev: class device used by the deprecated sysfs interface (may be
31
-
* NULL)
32
30
* @owner: helps prevent removal of modules exporting active GPIOs
33
31
* @chip: pointer to the corresponding gpiochip, holding static
34
32
* data for this device
···
63
65
struct device dev;
64
66
struct cdev chrdev;
65
67
int id;
66
-
struct device *mockdev;
67
68
struct module *owner;
68
69
struct gpio_chip __rcu *chip;
69
70
struct gpio_desc *descs;
+11
-10
drivers/input/keyboard/Kconfig
+11
-10
drivers/input/keyboard/Kconfig
···
37
37
To compile this driver as a module, choose M here: the module will
38
38
be called adp5520-keys.
39
39
40
+
config KEYBOARD_ADP5585
41
+
tristate "ADP558x keypad support"
42
+
depends on MFD_ADP5585
43
+
select INPUT_MATRIXKMAP
44
+
help
45
+
This option enables support for the KEYPAD function found in the Analog
46
+
Devices ADP5585 and similar devices.
47
+
48
+
To compile this driver as a module, choose M here: the
49
+
module will be called adp5585-keys.
50
+
40
51
config KEYBOARD_ADP5588
41
52
tristate "ADP5588/87 I2C QWERTY Keypad and IO Expander"
42
53
depends on I2C
···
60
49
61
50
To compile this driver as a module, choose M here: the
62
51
module will be called adp5588-keys.
63
-
64
-
config KEYBOARD_ADP5589
65
-
tristate "ADP5585/ADP5589 I2C QWERTY Keypad and IO Expander"
66
-
depends on I2C
67
-
help
68
-
Say Y here if you want to use a ADP5585/ADP5589 attached to your
69
-
system I2C bus.
70
-
71
-
To compile this driver as a module, choose M here: the
72
-
module will be called adp5589-keys.
73
52
74
53
config KEYBOARD_AMIGA
75
54
tristate "Amiga keyboard"
+1
-1
drivers/input/keyboard/Makefile
+1
-1
drivers/input/keyboard/Makefile
···
7
7
8
8
obj-$(CONFIG_KEYBOARD_ADC) += adc-keys.o
9
9
obj-$(CONFIG_KEYBOARD_ADP5520) += adp5520-keys.o
10
+
obj-$(CONFIG_KEYBOARD_ADP5585) += adp5585-keys.o
10
11
obj-$(CONFIG_KEYBOARD_ADP5588) += adp5588-keys.o
11
-
obj-$(CONFIG_KEYBOARD_ADP5589) += adp5589-keys.o
12
12
obj-$(CONFIG_KEYBOARD_AMIGA) += amikbd.o
13
13
obj-$(CONFIG_KEYBOARD_APPLESPI) += applespi.o
14
14
obj-$(CONFIG_KEYBOARD_ATARI) += atakbd.o
+371
drivers/input/keyboard/adp5585-keys.c
+371
drivers/input/keyboard/adp5585-keys.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Analog Devices ADP5585 Keys driver
4
+
*
5
+
* Copyright (C) 2025 Analog Devices, Inc.
6
+
*/
7
+
8
+
#include <linux/bitmap.h>
9
+
#include <linux/container_of.h>
10
+
#include <linux/device.h>
11
+
#include <linux/find.h>
12
+
#include <linux/input.h>
13
+
#include <linux/input/matrix_keypad.h>
14
+
#include <linux/mfd/adp5585.h>
15
+
#include <linux/module.h>
16
+
#include <linux/mod_devicetable.h>
17
+
#include <linux/notifier.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/property.h>
20
+
#include <linux/regmap.h>
21
+
#include <linux/types.h>
22
+
23
+
/* As needed for the matrix parsing code */
24
+
#define ADP5589_MAX_KEYMAPSIZE 123
25
+
26
+
struct adp5585_kpad_chip {
27
+
u8 key_ev_min;
28
+
u8 key_ev_max;
29
+
u8 max_rows;
30
+
u8 max_cols;
31
+
};
32
+
33
+
struct adp5585_kpad {
34
+
const struct adp5585_kpad_chip *info;
35
+
struct notifier_block nb;
36
+
struct input_dev *input;
37
+
unsigned short keycode[ADP5589_MAX_KEYMAPSIZE];
38
+
struct device *dev;
39
+
unsigned long keypad;
40
+
int row_shift;
41
+
};
42
+
43
+
static int adp5585_keys_validate_events(const struct adp5585_kpad *kpad,
44
+
const u32 *events, u32 n_events)
45
+
{
46
+
unsigned int ev;
47
+
u32 row, col;
48
+
49
+
for (ev = 0; ev < n_events; ev++) {
50
+
if (events[ev] < kpad->info->key_ev_min ||
51
+
events[ev] > kpad->info->key_ev_max)
52
+
continue;
53
+
54
+
/*
55
+
* if the event is to be generated by the keymap, we need to make
56
+
* sure that the pins are part of it!
57
+
*/
58
+
row = (events[ev] - 1) / kpad->info->max_cols;
59
+
col = (events[ev] - 1) % kpad->info->max_cols;
60
+
61
+
if (test_bit(row, &kpad->keypad) &&
62
+
test_bit(col + kpad->info->max_rows, &kpad->keypad))
63
+
continue;
64
+
65
+
return dev_err_probe(kpad->dev, -EINVAL,
66
+
"Invalid unlock/reset event(%u) not used in the keypad\n",
67
+
events[ev]);
68
+
}
69
+
70
+
return 0;
71
+
}
72
+
73
+
static int adp5585_keys_check_special_events(const struct adp5585_dev *adp5585,
74
+
const struct adp5585_kpad *kpad)
75
+
{
76
+
int error;
77
+
78
+
error = adp5585_keys_validate_events(kpad, adp5585->unlock_keys,
79
+
adp5585->nkeys_unlock);
80
+
if (error)
81
+
return error;
82
+
83
+
error = adp5585_keys_validate_events(kpad, adp5585->reset1_keys,
84
+
adp5585->nkeys_reset1);
85
+
if (error)
86
+
return error;
87
+
88
+
return adp5585_keys_validate_events(kpad, adp5585->reset2_keys,
89
+
adp5585->nkeys_reset2);
90
+
}
91
+
92
+
static void adp5585_keys_pins_free(void *data)
93
+
{
94
+
struct adp5585_kpad *kpad = data;
95
+
struct adp5585_dev *adp5585 = dev_get_drvdata(kpad->dev->parent);
96
+
unsigned int pin;
97
+
98
+
for_each_set_bit(pin, &kpad->keypad, adp5585->n_pins)
99
+
clear_bit(pin, adp5585->pin_usage);
100
+
}
101
+
102
+
static int adp5585_keys_parse_fw(const struct adp5585_dev *adp5585,
103
+
struct adp5585_kpad *kpad)
104
+
{
105
+
struct device *dev = kpad->dev;
106
+
u32 cols = 0, rows = 0, pin;
107
+
int error, n_pins;
108
+
109
+
/*
110
+
* We do not check for errors (or no value) since the input device is
111
+
* only added if this property is present in the first place.
112
+
*/
113
+
n_pins = device_property_count_u32(dev, "adi,keypad-pins");
114
+
if (n_pins > adp5585->n_pins)
115
+
return dev_err_probe(dev, -EINVAL,
116
+
"Too many keypad pins (%d) defined (max=%d)\n",
117
+
n_pins, adp5585->n_pins);
118
+
119
+
unsigned int *keypad_pins __free(kfree) = kcalloc(n_pins, sizeof(*keypad_pins),
120
+
GFP_KERNEL);
121
+
if (!keypad_pins)
122
+
return -ENOMEM;
123
+
124
+
error = device_property_read_u32_array(dev, "adi,keypad-pins",
125
+
keypad_pins, n_pins);
126
+
if (error)
127
+
return error;
128
+
129
+
/*
130
+
* We can add the action here since it makes the code easier and nothing
131
+
* "bad" will happen out of it. Worst case, it will be a no-op and no
132
+
* bit will set.
133
+
*/
134
+
error = devm_add_action_or_reset(dev, adp5585_keys_pins_free, kpad);
135
+
if (error)
136
+
return error;
137
+
138
+
for (pin = 0; pin < n_pins; pin++) {
139
+
if (keypad_pins[pin] >= adp5585->n_pins)
140
+
return dev_err_probe(dev, -EINVAL,
141
+
"Invalid keypad pin(%u) defined\n",
142
+
keypad_pins[pin]);
143
+
144
+
if (test_and_set_bit(keypad_pins[pin], adp5585->pin_usage))
145
+
return dev_err_probe(dev, -EBUSY,
146
+
"Keypad pin(%u) already used\n",
147
+
keypad_pins[pin]);
148
+
149
+
__set_bit(keypad_pins[pin], &kpad->keypad);
150
+
}
151
+
152
+
/*
153
+
* Note that given that we get a mask (and the HW allows it), we
154
+
* can have holes in our keypad (eg: row0, row1 and row7 enabled).
155
+
* However, for the matrix parsing functions we need to pass the
156
+
* number of rows/cols as the maximum row/col used plus 1. This
157
+
* pretty much means we will also have holes in our SW keypad.
158
+
*/
159
+
160
+
rows = find_last_bit(&kpad->keypad, kpad->info->max_rows) + 1;
161
+
if (rows == kpad->info->max_rows + 1)
162
+
return dev_err_probe(dev, -EINVAL,
163
+
"Now rows defined in the keypad!\n");
164
+
165
+
cols = find_last_bit(&kpad->keypad, kpad->info->max_cols + kpad->info->max_rows);
166
+
if (cols < kpad->info->max_rows)
167
+
return dev_err_probe(dev, -EINVAL,
168
+
"No columns defined in the keypad!\n");
169
+
170
+
cols = cols + 1 - kpad->info->max_rows;
171
+
172
+
error = matrix_keypad_build_keymap(NULL, NULL, rows, cols,
173
+
kpad->keycode, kpad->input);
174
+
if (error)
175
+
return error;
176
+
177
+
kpad->row_shift = get_count_order(cols);
178
+
179
+
if (device_property_read_bool(kpad->dev, "autorepeat"))
180
+
__set_bit(EV_REP, kpad->input->evbit);
181
+
182
+
error = adp5585_keys_check_special_events(adp5585, kpad);
183
+
if (error)
184
+
return error;
185
+
186
+
return 0;
187
+
}
188
+
189
+
static int adp5585_keys_setup(const struct adp5585_dev *adp5585,
190
+
struct adp5585_kpad *kpad)
191
+
{
192
+
unsigned long keys_bits, start = 0, nbits = kpad->info->max_rows;
193
+
const struct adp5585_regs *regs = adp5585->regs;
194
+
unsigned int i = 0, max_cols = kpad->info->max_cols;
195
+
int error;
196
+
197
+
/*
198
+
* Take care as the below assumes max_rows is always less or equal than
199
+
* 8 which is true for the supported devices. If we happen to add
200
+
* another device we need to make sure this still holds true. Although
201
+
* adding a new device is very unlikely.
202
+
*/
203
+
do {
204
+
keys_bits = bitmap_read(&kpad->keypad, start, nbits);
205
+
if (keys_bits) {
206
+
error = regmap_write(adp5585->regmap, regs->pin_cfg_a + i,
207
+
keys_bits);
208
+
if (error)
209
+
return error;
210
+
}
211
+
212
+
start += nbits;
213
+
if (max_cols > 8) {
214
+
nbits = 8;
215
+
max_cols -= nbits;
216
+
} else {
217
+
nbits = max_cols;
218
+
}
219
+
220
+
i++;
221
+
} while (start < kpad->info->max_rows + kpad->info->max_cols);
222
+
223
+
return 0;
224
+
}
225
+
226
+
static int adp5585_keys_ev_handle(struct notifier_block *nb, unsigned long key,
227
+
void *data)
228
+
{
229
+
struct adp5585_kpad *kpad = container_of(nb, struct adp5585_kpad, nb);
230
+
unsigned long key_press = (unsigned long)data;
231
+
unsigned int row, col, code;
232
+
233
+
/* make sure the event is for us */
234
+
if (key < kpad->info->key_ev_min || key > kpad->info->key_ev_max)
235
+
return NOTIFY_DONE;
236
+
237
+
/*
238
+
* Unlikely but lets be on the safe side! We do not return any error
239
+
* because the event was indeed for us but with some weird value. So,
240
+
* we still want the caller know that the right handler was called.
241
+
*/
242
+
if (!key)
243
+
return NOTIFY_BAD;
244
+
245
+
row = (key - 1) / (kpad->info->max_cols);
246
+
col = (key - 1) % (kpad->info->max_cols);
247
+
code = MATRIX_SCAN_CODE(row, col, kpad->row_shift);
248
+
249
+
dev_dbg_ratelimited(kpad->dev, "report key(%lu) r(%d) c(%d) code(%d)\n",
250
+
key, row, col, kpad->keycode[code]);
251
+
252
+
input_report_key(kpad->input, kpad->keycode[code], key_press);
253
+
input_sync(kpad->input);
254
+
255
+
return NOTIFY_STOP;
256
+
}
257
+
258
+
static void adp5585_keys_unreg_notifier(void *data)
259
+
{
260
+
struct adp5585_kpad *kpad = data;
261
+
struct adp5585_dev *adp5585 = dev_get_drvdata(kpad->dev->parent);
262
+
263
+
blocking_notifier_chain_unregister(&adp5585->event_notifier,
264
+
&kpad->nb);
265
+
}
266
+
267
+
static int adp5585_keys_probe(struct platform_device *pdev)
268
+
{
269
+
const struct platform_device_id *id = platform_get_device_id(pdev);
270
+
struct adp5585_dev *adp5585 = dev_get_drvdata(pdev->dev.parent);
271
+
struct device *dev = &pdev->dev;
272
+
struct adp5585_kpad *kpad;
273
+
unsigned int revid;
274
+
const char *phys;
275
+
int error;
276
+
277
+
kpad = devm_kzalloc(dev, sizeof(*kpad), GFP_KERNEL);
278
+
if (!kpad)
279
+
return -ENOMEM;
280
+
281
+
if (!adp5585->irq)
282
+
return dev_err_probe(dev, -EINVAL,
283
+
"IRQ is mandatory for the keypad\n");
284
+
285
+
kpad->dev = dev;
286
+
287
+
kpad->input = devm_input_allocate_device(dev);
288
+
if (!kpad->input)
289
+
return -ENOMEM;
290
+
291
+
kpad->info = (const struct adp5585_kpad_chip *)id->driver_data;
292
+
if (!kpad->info)
293
+
return -ENODEV;
294
+
295
+
error = regmap_read(adp5585->regmap, ADP5585_ID, &revid);
296
+
if (error)
297
+
return dev_err_probe(dev, error, "Failed to read device ID\n");
298
+
299
+
phys = devm_kasprintf(dev, GFP_KERNEL, "%s/input0", pdev->name);
300
+
if (!phys)
301
+
return -ENOMEM;
302
+
303
+
kpad->input->name = pdev->name;
304
+
kpad->input->phys = phys;
305
+
306
+
kpad->input->id.bustype = BUS_I2C;
307
+
kpad->input->id.vendor = 0x0001;
308
+
kpad->input->id.product = 0x0001;
309
+
kpad->input->id.version = revid & ADP5585_REV_ID_MASK;
310
+
311
+
device_set_of_node_from_dev(dev, dev->parent);
312
+
313
+
error = adp5585_keys_parse_fw(adp5585, kpad);
314
+
if (error)
315
+
return error;
316
+
317
+
error = adp5585_keys_setup(adp5585, kpad);
318
+
if (error)
319
+
return error;
320
+
321
+
kpad->nb.notifier_call = adp5585_keys_ev_handle;
322
+
error = blocking_notifier_chain_register(&adp5585->event_notifier,
323
+
&kpad->nb);
324
+
if (error)
325
+
return error;
326
+
327
+
error = devm_add_action_or_reset(dev, adp5585_keys_unreg_notifier, kpad);
328
+
if (error)
329
+
return error;
330
+
331
+
error = input_register_device(kpad->input);
332
+
if (error)
333
+
return dev_err_probe(dev, error,
334
+
"Failed to register input device\n");
335
+
336
+
return 0;
337
+
}
338
+
339
+
static const struct adp5585_kpad_chip adp5585_kpad_chip_info = {
340
+
.max_rows = 6,
341
+
.max_cols = 5,
342
+
.key_ev_min = ADP5585_ROW5_KEY_EVENT_START,
343
+
.key_ev_max = ADP5585_ROW5_KEY_EVENT_END,
344
+
};
345
+
346
+
static const struct adp5585_kpad_chip adp5589_kpad_chip_info = {
347
+
.max_rows = 8,
348
+
.max_cols = 11,
349
+
.key_ev_min = ADP5589_KEY_EVENT_START,
350
+
.key_ev_max = ADP5589_KEY_EVENT_END,
351
+
};
352
+
353
+
static const struct platform_device_id adp5585_keys_id_table[] = {
354
+
{ "adp5585-keys", (kernel_ulong_t)&adp5585_kpad_chip_info },
355
+
{ "adp5589-keys", (kernel_ulong_t)&adp5589_kpad_chip_info },
356
+
{ }
357
+
};
358
+
MODULE_DEVICE_TABLE(platform, adp5585_keys_id_table);
359
+
360
+
static struct platform_driver adp5585_keys_driver = {
361
+
.driver = {
362
+
.name = "adp5585-keys",
363
+
},
364
+
.probe = adp5585_keys_probe,
365
+
.id_table = adp5585_keys_id_table,
366
+
};
367
+
module_platform_driver(adp5585_keys_driver);
368
+
369
+
MODULE_AUTHOR("Nuno Sá <nuno.sa@analog.com>");
370
+
MODULE_DESCRIPTION("ADP5585 Keys Driver");
371
+
MODULE_LICENSE("GPL");
-1066
drivers/input/keyboard/adp5589-keys.c
-1066
drivers/input/keyboard/adp5589-keys.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* Description: keypad driver for ADP5589, ADP5585
4
-
* I2C QWERTY Keypad and IO Expander
5
-
* Bugs: Enter bugs at http://blackfin.uclinux.org/
6
-
*
7
-
* Copyright (C) 2010-2011 Analog Devices Inc.
8
-
*/
9
-
10
-
#include <linux/bitops.h>
11
-
#include <linux/module.h>
12
-
#include <linux/interrupt.h>
13
-
#include <linux/irq.h>
14
-
#include <linux/workqueue.h>
15
-
#include <linux/errno.h>
16
-
#include <linux/pm.h>
17
-
#include <linux/pm_wakeirq.h>
18
-
#include <linux/platform_device.h>
19
-
#include <linux/input.h>
20
-
#include <linux/i2c.h>
21
-
#include <linux/gpio/driver.h>
22
-
#include <linux/slab.h>
23
-
24
-
#include <linux/input/adp5589.h>
25
-
26
-
/* ADP5589/ADP5585 Common Registers */
27
-
#define ADP5589_5_ID 0x00
28
-
#define ADP5589_5_INT_STATUS 0x01
29
-
#define ADP5589_5_STATUS 0x02
30
-
#define ADP5589_5_FIFO_1 0x03
31
-
#define ADP5589_5_FIFO_2 0x04
32
-
#define ADP5589_5_FIFO_3 0x05
33
-
#define ADP5589_5_FIFO_4 0x06
34
-
#define ADP5589_5_FIFO_5 0x07
35
-
#define ADP5589_5_FIFO_6 0x08
36
-
#define ADP5589_5_FIFO_7 0x09
37
-
#define ADP5589_5_FIFO_8 0x0A
38
-
#define ADP5589_5_FIFO_9 0x0B
39
-
#define ADP5589_5_FIFO_10 0x0C
40
-
#define ADP5589_5_FIFO_11 0x0D
41
-
#define ADP5589_5_FIFO_12 0x0E
42
-
#define ADP5589_5_FIFO_13 0x0F
43
-
#define ADP5589_5_FIFO_14 0x10
44
-
#define ADP5589_5_FIFO_15 0x11
45
-
#define ADP5589_5_FIFO_16 0x12
46
-
#define ADP5589_5_GPI_INT_STAT_A 0x13
47
-
#define ADP5589_5_GPI_INT_STAT_B 0x14
48
-
49
-
/* ADP5589 Registers */
50
-
#define ADP5589_GPI_INT_STAT_C 0x15
51
-
#define ADP5589_GPI_STATUS_A 0x16
52
-
#define ADP5589_GPI_STATUS_B 0x17
53
-
#define ADP5589_GPI_STATUS_C 0x18
54
-
#define ADP5589_RPULL_CONFIG_A 0x19
55
-
#define ADP5589_RPULL_CONFIG_B 0x1A
56
-
#define ADP5589_RPULL_CONFIG_C 0x1B
57
-
#define ADP5589_RPULL_CONFIG_D 0x1C
58
-
#define ADP5589_RPULL_CONFIG_E 0x1D
59
-
#define ADP5589_GPI_INT_LEVEL_A 0x1E
60
-
#define ADP5589_GPI_INT_LEVEL_B 0x1F
61
-
#define ADP5589_GPI_INT_LEVEL_C 0x20
62
-
#define ADP5589_GPI_EVENT_EN_A 0x21
63
-
#define ADP5589_GPI_EVENT_EN_B 0x22
64
-
#define ADP5589_GPI_EVENT_EN_C 0x23
65
-
#define ADP5589_GPI_INTERRUPT_EN_A 0x24
66
-
#define ADP5589_GPI_INTERRUPT_EN_B 0x25
67
-
#define ADP5589_GPI_INTERRUPT_EN_C 0x26
68
-
#define ADP5589_DEBOUNCE_DIS_A 0x27
69
-
#define ADP5589_DEBOUNCE_DIS_B 0x28
70
-
#define ADP5589_DEBOUNCE_DIS_C 0x29
71
-
#define ADP5589_GPO_DATA_OUT_A 0x2A
72
-
#define ADP5589_GPO_DATA_OUT_B 0x2B
73
-
#define ADP5589_GPO_DATA_OUT_C 0x2C
74
-
#define ADP5589_GPO_OUT_MODE_A 0x2D
75
-
#define ADP5589_GPO_OUT_MODE_B 0x2E
76
-
#define ADP5589_GPO_OUT_MODE_C 0x2F
77
-
#define ADP5589_GPIO_DIRECTION_A 0x30
78
-
#define ADP5589_GPIO_DIRECTION_B 0x31
79
-
#define ADP5589_GPIO_DIRECTION_C 0x32
80
-
#define ADP5589_UNLOCK1 0x33
81
-
#define ADP5589_UNLOCK2 0x34
82
-
#define ADP5589_EXT_LOCK_EVENT 0x35
83
-
#define ADP5589_UNLOCK_TIMERS 0x36
84
-
#define ADP5589_LOCK_CFG 0x37
85
-
#define ADP5589_RESET1_EVENT_A 0x38
86
-
#define ADP5589_RESET1_EVENT_B 0x39
87
-
#define ADP5589_RESET1_EVENT_C 0x3A
88
-
#define ADP5589_RESET2_EVENT_A 0x3B
89
-
#define ADP5589_RESET2_EVENT_B 0x3C
90
-
#define ADP5589_RESET_CFG 0x3D
91
-
#define ADP5589_PWM_OFFT_LOW 0x3E
92
-
#define ADP5589_PWM_OFFT_HIGH 0x3F
93
-
#define ADP5589_PWM_ONT_LOW 0x40
94
-
#define ADP5589_PWM_ONT_HIGH 0x41
95
-
#define ADP5589_PWM_CFG 0x42
96
-
#define ADP5589_CLOCK_DIV_CFG 0x43
97
-
#define ADP5589_LOGIC_1_CFG 0x44
98
-
#define ADP5589_LOGIC_2_CFG 0x45
99
-
#define ADP5589_LOGIC_FF_CFG 0x46
100
-
#define ADP5589_LOGIC_INT_EVENT_EN 0x47
101
-
#define ADP5589_POLL_PTIME_CFG 0x48
102
-
#define ADP5589_PIN_CONFIG_A 0x49
103
-
#define ADP5589_PIN_CONFIG_B 0x4A
104
-
#define ADP5589_PIN_CONFIG_C 0x4B
105
-
#define ADP5589_PIN_CONFIG_D 0x4C
106
-
#define ADP5589_GENERAL_CFG 0x4D
107
-
#define ADP5589_INT_EN 0x4E
108
-
109
-
/* ADP5585 Registers */
110
-
#define ADP5585_GPI_STATUS_A 0x15
111
-
#define ADP5585_GPI_STATUS_B 0x16
112
-
#define ADP5585_RPULL_CONFIG_A 0x17
113
-
#define ADP5585_RPULL_CONFIG_B 0x18
114
-
#define ADP5585_RPULL_CONFIG_C 0x19
115
-
#define ADP5585_RPULL_CONFIG_D 0x1A
116
-
#define ADP5585_GPI_INT_LEVEL_A 0x1B
117
-
#define ADP5585_GPI_INT_LEVEL_B 0x1C
118
-
#define ADP5585_GPI_EVENT_EN_A 0x1D
119
-
#define ADP5585_GPI_EVENT_EN_B 0x1E
120
-
#define ADP5585_GPI_INTERRUPT_EN_A 0x1F
121
-
#define ADP5585_GPI_INTERRUPT_EN_B 0x20
122
-
#define ADP5585_DEBOUNCE_DIS_A 0x21
123
-
#define ADP5585_DEBOUNCE_DIS_B 0x22
124
-
#define ADP5585_GPO_DATA_OUT_A 0x23
125
-
#define ADP5585_GPO_DATA_OUT_B 0x24
126
-
#define ADP5585_GPO_OUT_MODE_A 0x25
127
-
#define ADP5585_GPO_OUT_MODE_B 0x26
128
-
#define ADP5585_GPIO_DIRECTION_A 0x27
129
-
#define ADP5585_GPIO_DIRECTION_B 0x28
130
-
#define ADP5585_RESET1_EVENT_A 0x29
131
-
#define ADP5585_RESET1_EVENT_B 0x2A
132
-
#define ADP5585_RESET1_EVENT_C 0x2B
133
-
#define ADP5585_RESET2_EVENT_A 0x2C
134
-
#define ADP5585_RESET2_EVENT_B 0x2D
135
-
#define ADP5585_RESET_CFG 0x2E
136
-
#define ADP5585_PWM_OFFT_LOW 0x2F
137
-
#define ADP5585_PWM_OFFT_HIGH 0x30
138
-
#define ADP5585_PWM_ONT_LOW 0x31
139
-
#define ADP5585_PWM_ONT_HIGH 0x32
140
-
#define ADP5585_PWM_CFG 0x33
141
-
#define ADP5585_LOGIC_CFG 0x34
142
-
#define ADP5585_LOGIC_FF_CFG 0x35
143
-
#define ADP5585_LOGIC_INT_EVENT_EN 0x36
144
-
#define ADP5585_POLL_PTIME_CFG 0x37
145
-
#define ADP5585_PIN_CONFIG_A 0x38
146
-
#define ADP5585_PIN_CONFIG_B 0x39
147
-
#define ADP5585_PIN_CONFIG_D 0x3A
148
-
#define ADP5585_GENERAL_CFG 0x3B
149
-
#define ADP5585_INT_EN 0x3C
150
-
151
-
/* ID Register */
152
-
#define ADP5589_5_DEVICE_ID_MASK 0xF
153
-
#define ADP5589_5_MAN_ID_MASK 0xF
154
-
#define ADP5589_5_MAN_ID_SHIFT 4
155
-
#define ADP5589_5_MAN_ID 0x02
156
-
157
-
/* GENERAL_CFG Register */
158
-
#define OSC_EN BIT(7)
159
-
#define CORE_CLK(x) (((x) & 0x3) << 5)
160
-
#define LCK_TRK_LOGIC BIT(4) /* ADP5589 only */
161
-
#define LCK_TRK_GPI BIT(3) /* ADP5589 only */
162
-
#define INT_CFG BIT(1)
163
-
#define RST_CFG BIT(0)
164
-
165
-
/* INT_EN Register */
166
-
#define LOGIC2_IEN BIT(5) /* ADP5589 only */
167
-
#define LOGIC1_IEN BIT(4)
168
-
#define LOCK_IEN BIT(3) /* ADP5589 only */
169
-
#define OVRFLOW_IEN BIT(2)
170
-
#define GPI_IEN BIT(1)
171
-
#define EVENT_IEN BIT(0)
172
-
173
-
/* Interrupt Status Register */
174
-
#define LOGIC2_INT BIT(5) /* ADP5589 only */
175
-
#define LOGIC1_INT BIT(4)
176
-
#define LOCK_INT BIT(3) /* ADP5589 only */
177
-
#define OVRFLOW_INT BIT(2)
178
-
#define GPI_INT BIT(1)
179
-
#define EVENT_INT BIT(0)
180
-
181
-
/* STATUS Register */
182
-
#define LOGIC2_STAT BIT(7) /* ADP5589 only */
183
-
#define LOGIC1_STAT BIT(6)
184
-
#define LOCK_STAT BIT(5) /* ADP5589 only */
185
-
#define KEC 0x1F
186
-
187
-
/* PIN_CONFIG_D Register */
188
-
#define C4_EXTEND_CFG BIT(6) /* RESET2 */
189
-
#define R4_EXTEND_CFG BIT(5) /* RESET1 */
190
-
191
-
/* LOCK_CFG */
192
-
#define LOCK_EN BIT(0)
193
-
194
-
#define PTIME_MASK 0x3
195
-
#define LTIME_MASK 0x3 /* ADP5589 only */
196
-
197
-
/* Key Event Register xy */
198
-
#define KEY_EV_PRESSED BIT(7)
199
-
#define KEY_EV_MASK 0x7F
200
-
201
-
#define KEYP_MAX_EVENT 16
202
-
#define ADP5589_MAXGPIO 19
203
-
#define ADP5585_MAXGPIO 11 /* 10 on the ADP5585-01, 11 on ADP5585-02 */
204
-
205
-
enum {
206
-
ADP5589,
207
-
ADP5585_01,
208
-
ADP5585_02
209
-
};
210
-
211
-
struct adp_constants {
212
-
u8 maxgpio;
213
-
u8 keymapsize;
214
-
u8 gpi_pin_row_base;
215
-
u8 gpi_pin_row_end;
216
-
u8 gpi_pin_col_base;
217
-
u8 gpi_pin_base;
218
-
u8 gpi_pin_end;
219
-
u8 gpimapsize_max;
220
-
u8 max_row_num;
221
-
u8 max_col_num;
222
-
u8 row_mask;
223
-
u8 col_mask;
224
-
u8 col_shift;
225
-
u8 c4_extend_cfg;
226
-
u8 (*bank) (u8 offset);
227
-
u8 (*bit) (u8 offset);
228
-
u8 (*reg) (u8 reg);
229
-
};
230
-
231
-
struct adp5589_kpad {
232
-
struct i2c_client *client;
233
-
struct input_dev *input;
234
-
const struct adp_constants *var;
235
-
unsigned short keycode[ADP5589_KEYMAPSIZE];
236
-
const struct adp5589_gpi_map *gpimap;
237
-
unsigned short gpimapsize;
238
-
unsigned extend_cfg;
239
-
bool is_adp5585;
240
-
bool support_row5;
241
-
#ifdef CONFIG_GPIOLIB
242
-
unsigned char gpiomap[ADP5589_MAXGPIO];
243
-
struct gpio_chip gc;
244
-
struct mutex gpio_lock; /* Protect cached dir, dat_out */
245
-
u8 dat_out[3];
246
-
u8 dir[3];
247
-
#endif
248
-
};
249
-
250
-
/*
251
-
* ADP5589 / ADP5585 derivative / variant handling
252
-
*/
253
-
254
-
255
-
/* ADP5589 */
256
-
257
-
static unsigned char adp5589_bank(unsigned char offset)
258
-
{
259
-
return offset >> 3;
260
-
}
261
-
262
-
static unsigned char adp5589_bit(unsigned char offset)
263
-
{
264
-
return 1u << (offset & 0x7);
265
-
}
266
-
267
-
static unsigned char adp5589_reg(unsigned char reg)
268
-
{
269
-
return reg;
270
-
}
271
-
272
-
static const struct adp_constants const_adp5589 = {
273
-
.maxgpio = ADP5589_MAXGPIO,
274
-
.keymapsize = ADP5589_KEYMAPSIZE,
275
-
.gpi_pin_row_base = ADP5589_GPI_PIN_ROW_BASE,
276
-
.gpi_pin_row_end = ADP5589_GPI_PIN_ROW_END,
277
-
.gpi_pin_col_base = ADP5589_GPI_PIN_COL_BASE,
278
-
.gpi_pin_base = ADP5589_GPI_PIN_BASE,
279
-
.gpi_pin_end = ADP5589_GPI_PIN_END,
280
-
.gpimapsize_max = ADP5589_GPIMAPSIZE_MAX,
281
-
.c4_extend_cfg = 12,
282
-
.max_row_num = ADP5589_MAX_ROW_NUM,
283
-
.max_col_num = ADP5589_MAX_COL_NUM,
284
-
.row_mask = ADP5589_ROW_MASK,
285
-
.col_mask = ADP5589_COL_MASK,
286
-
.col_shift = ADP5589_COL_SHIFT,
287
-
.bank = adp5589_bank,
288
-
.bit = adp5589_bit,
289
-
.reg = adp5589_reg,
290
-
};
291
-
292
-
/* ADP5585 */
293
-
294
-
static unsigned char adp5585_bank(unsigned char offset)
295
-
{
296
-
return offset > ADP5585_MAX_ROW_NUM;
297
-
}
298
-
299
-
static unsigned char adp5585_bit(unsigned char offset)
300
-
{
301
-
return (offset > ADP5585_MAX_ROW_NUM) ?
302
-
1u << (offset - ADP5585_COL_SHIFT) : 1u << offset;
303
-
}
304
-
305
-
static const unsigned char adp5585_reg_lut[] = {
306
-
[ADP5589_GPI_STATUS_A] = ADP5585_GPI_STATUS_A,
307
-
[ADP5589_GPI_STATUS_B] = ADP5585_GPI_STATUS_B,
308
-
[ADP5589_RPULL_CONFIG_A] = ADP5585_RPULL_CONFIG_A,
309
-
[ADP5589_RPULL_CONFIG_B] = ADP5585_RPULL_CONFIG_B,
310
-
[ADP5589_RPULL_CONFIG_C] = ADP5585_RPULL_CONFIG_C,
311
-
[ADP5589_RPULL_CONFIG_D] = ADP5585_RPULL_CONFIG_D,
312
-
[ADP5589_GPI_INT_LEVEL_A] = ADP5585_GPI_INT_LEVEL_A,
313
-
[ADP5589_GPI_INT_LEVEL_B] = ADP5585_GPI_INT_LEVEL_B,
314
-
[ADP5589_GPI_EVENT_EN_A] = ADP5585_GPI_EVENT_EN_A,
315
-
[ADP5589_GPI_EVENT_EN_B] = ADP5585_GPI_EVENT_EN_B,
316
-
[ADP5589_GPI_INTERRUPT_EN_A] = ADP5585_GPI_INTERRUPT_EN_A,
317
-
[ADP5589_GPI_INTERRUPT_EN_B] = ADP5585_GPI_INTERRUPT_EN_B,
318
-
[ADP5589_DEBOUNCE_DIS_A] = ADP5585_DEBOUNCE_DIS_A,
319
-
[ADP5589_DEBOUNCE_DIS_B] = ADP5585_DEBOUNCE_DIS_B,
320
-
[ADP5589_GPO_DATA_OUT_A] = ADP5585_GPO_DATA_OUT_A,
321
-
[ADP5589_GPO_DATA_OUT_B] = ADP5585_GPO_DATA_OUT_B,
322
-
[ADP5589_GPO_OUT_MODE_A] = ADP5585_GPO_OUT_MODE_A,
323
-
[ADP5589_GPO_OUT_MODE_B] = ADP5585_GPO_OUT_MODE_B,
324
-
[ADP5589_GPIO_DIRECTION_A] = ADP5585_GPIO_DIRECTION_A,
325
-
[ADP5589_GPIO_DIRECTION_B] = ADP5585_GPIO_DIRECTION_B,
326
-
[ADP5589_RESET1_EVENT_A] = ADP5585_RESET1_EVENT_A,
327
-
[ADP5589_RESET1_EVENT_B] = ADP5585_RESET1_EVENT_B,
328
-
[ADP5589_RESET1_EVENT_C] = ADP5585_RESET1_EVENT_C,
329
-
[ADP5589_RESET2_EVENT_A] = ADP5585_RESET2_EVENT_A,
330
-
[ADP5589_RESET2_EVENT_B] = ADP5585_RESET2_EVENT_B,
331
-
[ADP5589_RESET_CFG] = ADP5585_RESET_CFG,
332
-
[ADP5589_PWM_OFFT_LOW] = ADP5585_PWM_OFFT_LOW,
333
-
[ADP5589_PWM_OFFT_HIGH] = ADP5585_PWM_OFFT_HIGH,
334
-
[ADP5589_PWM_ONT_LOW] = ADP5585_PWM_ONT_LOW,
335
-
[ADP5589_PWM_ONT_HIGH] = ADP5585_PWM_ONT_HIGH,
336
-
[ADP5589_PWM_CFG] = ADP5585_PWM_CFG,
337
-
[ADP5589_LOGIC_1_CFG] = ADP5585_LOGIC_CFG,
338
-
[ADP5589_LOGIC_FF_CFG] = ADP5585_LOGIC_FF_CFG,
339
-
[ADP5589_LOGIC_INT_EVENT_EN] = ADP5585_LOGIC_INT_EVENT_EN,
340
-
[ADP5589_POLL_PTIME_CFG] = ADP5585_POLL_PTIME_CFG,
341
-
[ADP5589_PIN_CONFIG_A] = ADP5585_PIN_CONFIG_A,
342
-
[ADP5589_PIN_CONFIG_B] = ADP5585_PIN_CONFIG_B,
343
-
[ADP5589_PIN_CONFIG_D] = ADP5585_PIN_CONFIG_D,
344
-
[ADP5589_GENERAL_CFG] = ADP5585_GENERAL_CFG,
345
-
[ADP5589_INT_EN] = ADP5585_INT_EN,
346
-
};
347
-
348
-
static unsigned char adp5585_reg(unsigned char reg)
349
-
{
350
-
return adp5585_reg_lut[reg];
351
-
}
352
-
353
-
static const struct adp_constants const_adp5585 = {
354
-
.maxgpio = ADP5585_MAXGPIO,
355
-
.keymapsize = ADP5585_KEYMAPSIZE,
356
-
.gpi_pin_row_base = ADP5585_GPI_PIN_ROW_BASE,
357
-
.gpi_pin_row_end = ADP5585_GPI_PIN_ROW_END,
358
-
.gpi_pin_col_base = ADP5585_GPI_PIN_COL_BASE,
359
-
.gpi_pin_base = ADP5585_GPI_PIN_BASE,
360
-
.gpi_pin_end = ADP5585_GPI_PIN_END,
361
-
.gpimapsize_max = ADP5585_GPIMAPSIZE_MAX,
362
-
.c4_extend_cfg = 10,
363
-
.max_row_num = ADP5585_MAX_ROW_NUM,
364
-
.max_col_num = ADP5585_MAX_COL_NUM,
365
-
.row_mask = ADP5585_ROW_MASK,
366
-
.col_mask = ADP5585_COL_MASK,
367
-
.col_shift = ADP5585_COL_SHIFT,
368
-
.bank = adp5585_bank,
369
-
.bit = adp5585_bit,
370
-
.reg = adp5585_reg,
371
-
};
372
-
373
-
static int adp5589_read(struct i2c_client *client, u8 reg)
374
-
{
375
-
int ret = i2c_smbus_read_byte_data(client, reg);
376
-
377
-
if (ret < 0)
378
-
dev_err(&client->dev, "Read Error\n");
379
-
380
-
return ret;
381
-
}
382
-
383
-
static int adp5589_write(struct i2c_client *client, u8 reg, u8 val)
384
-
{
385
-
return i2c_smbus_write_byte_data(client, reg, val);
386
-
}
387
-
388
-
#ifdef CONFIG_GPIOLIB
389
-
static int adp5589_gpio_get_value(struct gpio_chip *chip, unsigned off)
390
-
{
391
-
struct adp5589_kpad *kpad = gpiochip_get_data(chip);
392
-
unsigned int bank = kpad->var->bank(kpad->gpiomap[off]);
393
-
unsigned int bit = kpad->var->bit(kpad->gpiomap[off]);
394
-
int val;
395
-
396
-
mutex_lock(&kpad->gpio_lock);
397
-
if (kpad->dir[bank] & bit)
398
-
val = kpad->dat_out[bank];
399
-
else
400
-
val = adp5589_read(kpad->client,
401
-
kpad->var->reg(ADP5589_GPI_STATUS_A) + bank);
402
-
mutex_unlock(&kpad->gpio_lock);
403
-
404
-
return !!(val & bit);
405
-
}
406
-
407
-
static void adp5589_gpio_set_value(struct gpio_chip *chip,
408
-
unsigned off, int val)
409
-
{
410
-
struct adp5589_kpad *kpad = gpiochip_get_data(chip);
411
-
unsigned int bank = kpad->var->bank(kpad->gpiomap[off]);
412
-
unsigned int bit = kpad->var->bit(kpad->gpiomap[off]);
413
-
414
-
guard(mutex)(&kpad->gpio_lock);
415
-
416
-
if (val)
417
-
kpad->dat_out[bank] |= bit;
418
-
else
419
-
kpad->dat_out[bank] &= ~bit;
420
-
421
-
adp5589_write(kpad->client, kpad->var->reg(ADP5589_GPO_DATA_OUT_A) +
422
-
bank, kpad->dat_out[bank]);
423
-
}
424
-
425
-
static int adp5589_gpio_direction_input(struct gpio_chip *chip, unsigned off)
426
-
{
427
-
struct adp5589_kpad *kpad = gpiochip_get_data(chip);
428
-
unsigned int bank = kpad->var->bank(kpad->gpiomap[off]);
429
-
unsigned int bit = kpad->var->bit(kpad->gpiomap[off]);
430
-
431
-
guard(mutex)(&kpad->gpio_lock);
432
-
433
-
kpad->dir[bank] &= ~bit;
434
-
return adp5589_write(kpad->client,
435
-
kpad->var->reg(ADP5589_GPIO_DIRECTION_A) + bank,
436
-
kpad->dir[bank]);
437
-
}
438
-
439
-
static int adp5589_gpio_direction_output(struct gpio_chip *chip,
440
-
unsigned off, int val)
441
-
{
442
-
struct adp5589_kpad *kpad = gpiochip_get_data(chip);
443
-
unsigned int bank = kpad->var->bank(kpad->gpiomap[off]);
444
-
unsigned int bit = kpad->var->bit(kpad->gpiomap[off]);
445
-
int error;
446
-
447
-
guard(mutex)(&kpad->gpio_lock);
448
-
449
-
kpad->dir[bank] |= bit;
450
-
451
-
if (val)
452
-
kpad->dat_out[bank] |= bit;
453
-
else
454
-
kpad->dat_out[bank] &= ~bit;
455
-
456
-
error = adp5589_write(kpad->client,
457
-
kpad->var->reg(ADP5589_GPO_DATA_OUT_A) + bank,
458
-
kpad->dat_out[bank]);
459
-
if (error)
460
-
return error;
461
-
462
-
error = adp5589_write(kpad->client,
463
-
kpad->var->reg(ADP5589_GPIO_DIRECTION_A) + bank,
464
-
kpad->dir[bank]);
465
-
if (error)
466
-
return error;
467
-
468
-
return 0;
469
-
}
470
-
471
-
static int adp5589_build_gpiomap(struct adp5589_kpad *kpad,
472
-
const struct adp5589_kpad_platform_data *pdata)
473
-
{
474
-
bool pin_used[ADP5589_MAXGPIO];
475
-
int n_unused = 0;
476
-
int i;
477
-
478
-
memset(pin_used, false, sizeof(pin_used));
479
-
480
-
for (i = 0; i < kpad->var->maxgpio; i++)
481
-
if (pdata->keypad_en_mask & BIT(i))
482
-
pin_used[i] = true;
483
-
484
-
for (i = 0; i < kpad->gpimapsize; i++)
485
-
pin_used[kpad->gpimap[i].pin - kpad->var->gpi_pin_base] = true;
486
-
487
-
if (kpad->extend_cfg & R4_EXTEND_CFG)
488
-
pin_used[4] = true;
489
-
490
-
if (kpad->extend_cfg & C4_EXTEND_CFG)
491
-
pin_used[kpad->var->c4_extend_cfg] = true;
492
-
493
-
if (!kpad->support_row5)
494
-
pin_used[5] = true;
495
-
496
-
for (i = 0; i < kpad->var->maxgpio; i++)
497
-
if (!pin_used[i])
498
-
kpad->gpiomap[n_unused++] = i;
499
-
500
-
return n_unused;
501
-
}
502
-
503
-
static int adp5589_gpio_add(struct adp5589_kpad *kpad)
504
-
{
505
-
struct device *dev = &kpad->client->dev;
506
-
const struct adp5589_kpad_platform_data *pdata = dev_get_platdata(dev);
507
-
const struct adp5589_gpio_platform_data *gpio_data = pdata->gpio_data;
508
-
int i, error;
509
-
510
-
if (!gpio_data)
511
-
return 0;
512
-
513
-
kpad->gc.parent = dev;
514
-
kpad->gc.ngpio = adp5589_build_gpiomap(kpad, pdata);
515
-
if (kpad->gc.ngpio == 0) {
516
-
dev_info(dev, "No unused gpios left to export\n");
517
-
return 0;
518
-
}
519
-
520
-
kpad->gc.direction_input = adp5589_gpio_direction_input;
521
-
kpad->gc.direction_output = adp5589_gpio_direction_output;
522
-
kpad->gc.get = adp5589_gpio_get_value;
523
-
kpad->gc.set = adp5589_gpio_set_value;
524
-
kpad->gc.can_sleep = 1;
525
-
526
-
kpad->gc.base = gpio_data->gpio_start;
527
-
kpad->gc.label = kpad->client->name;
528
-
kpad->gc.owner = THIS_MODULE;
529
-
530
-
mutex_init(&kpad->gpio_lock);
531
-
532
-
error = devm_gpiochip_add_data(dev, &kpad->gc, kpad);
533
-
if (error)
534
-
return error;
535
-
536
-
for (i = 0; i <= kpad->var->bank(kpad->var->maxgpio); i++) {
537
-
kpad->dat_out[i] = adp5589_read(kpad->client, kpad->var->reg(
538
-
ADP5589_GPO_DATA_OUT_A) + i);
539
-
kpad->dir[i] = adp5589_read(kpad->client, kpad->var->reg(
540
-
ADP5589_GPIO_DIRECTION_A) + i);
541
-
}
542
-
543
-
return 0;
544
-
}
545
-
#else
546
-
static inline int adp5589_gpio_add(struct adp5589_kpad *kpad)
547
-
{
548
-
return 0;
549
-
}
550
-
#endif
551
-
552
-
static void adp5589_report_switches(struct adp5589_kpad *kpad,
553
-
int key, int key_val)
554
-
{
555
-
int i;
556
-
557
-
for (i = 0; i < kpad->gpimapsize; i++) {
558
-
if (key_val == kpad->gpimap[i].pin) {
559
-
input_report_switch(kpad->input,
560
-
kpad->gpimap[i].sw_evt,
561
-
key & KEY_EV_PRESSED);
562
-
break;
563
-
}
564
-
}
565
-
}
566
-
567
-
static void adp5589_report_events(struct adp5589_kpad *kpad, int ev_cnt)
568
-
{
569
-
int i;
570
-
571
-
for (i = 0; i < ev_cnt; i++) {
572
-
int key = adp5589_read(kpad->client, ADP5589_5_FIFO_1 + i);
573
-
int key_val = key & KEY_EV_MASK;
574
-
575
-
if (key_val >= kpad->var->gpi_pin_base &&
576
-
key_val <= kpad->var->gpi_pin_end) {
577
-
adp5589_report_switches(kpad, key, key_val);
578
-
} else {
579
-
input_report_key(kpad->input,
580
-
kpad->keycode[key_val - 1],
581
-
key & KEY_EV_PRESSED);
582
-
}
583
-
}
584
-
}
585
-
586
-
static irqreturn_t adp5589_irq(int irq, void *handle)
587
-
{
588
-
struct adp5589_kpad *kpad = handle;
589
-
struct i2c_client *client = kpad->client;
590
-
int status, ev_cnt;
591
-
592
-
status = adp5589_read(client, ADP5589_5_INT_STATUS);
593
-
594
-
if (status & OVRFLOW_INT) /* Unlikely and should never happen */
595
-
dev_err(&client->dev, "Event Overflow Error\n");
596
-
597
-
if (status & EVENT_INT) {
598
-
ev_cnt = adp5589_read(client, ADP5589_5_STATUS) & KEC;
599
-
if (ev_cnt) {
600
-
adp5589_report_events(kpad, ev_cnt);
601
-
input_sync(kpad->input);
602
-
}
603
-
}
604
-
605
-
adp5589_write(client, ADP5589_5_INT_STATUS, status); /* Status is W1C */
606
-
607
-
return IRQ_HANDLED;
608
-
}
609
-
610
-
static int adp5589_get_evcode(struct adp5589_kpad *kpad, unsigned short key)
611
-
{
612
-
int i;
613
-
614
-
for (i = 0; i < kpad->var->keymapsize; i++)
615
-
if (key == kpad->keycode[i])
616
-
return (i + 1) | KEY_EV_PRESSED;
617
-
618
-
dev_err(&kpad->client->dev, "RESET/UNLOCK key not in keycode map\n");
619
-
620
-
return -EINVAL;
621
-
}
622
-
623
-
static int adp5589_setup(struct adp5589_kpad *kpad)
624
-
{
625
-
struct i2c_client *client = kpad->client;
626
-
const struct adp5589_kpad_platform_data *pdata =
627
-
dev_get_platdata(&client->dev);
628
-
u8 (*reg) (u8) = kpad->var->reg;
629
-
unsigned char evt_mode1 = 0, evt_mode2 = 0, evt_mode3 = 0;
630
-
unsigned char pull_mask = 0;
631
-
int i, ret;
632
-
633
-
ret = adp5589_write(client, reg(ADP5589_PIN_CONFIG_A),
634
-
pdata->keypad_en_mask & kpad->var->row_mask);
635
-
ret |= adp5589_write(client, reg(ADP5589_PIN_CONFIG_B),
636
-
(pdata->keypad_en_mask >> kpad->var->col_shift) &
637
-
kpad->var->col_mask);
638
-
639
-
if (!kpad->is_adp5585)
640
-
ret |= adp5589_write(client, ADP5589_PIN_CONFIG_C,
641
-
(pdata->keypad_en_mask >> 16) & 0xFF);
642
-
643
-
if (!kpad->is_adp5585 && pdata->en_keylock) {
644
-
ret |= adp5589_write(client, ADP5589_UNLOCK1,
645
-
pdata->unlock_key1);
646
-
ret |= adp5589_write(client, ADP5589_UNLOCK2,
647
-
pdata->unlock_key2);
648
-
ret |= adp5589_write(client, ADP5589_UNLOCK_TIMERS,
649
-
pdata->unlock_timer & LTIME_MASK);
650
-
ret |= adp5589_write(client, ADP5589_LOCK_CFG, LOCK_EN);
651
-
}
652
-
653
-
for (i = 0; i < KEYP_MAX_EVENT; i++)
654
-
ret |= adp5589_read(client, ADP5589_5_FIFO_1 + i);
655
-
656
-
for (i = 0; i < pdata->gpimapsize; i++) {
657
-
unsigned short pin = pdata->gpimap[i].pin;
658
-
659
-
if (pin <= kpad->var->gpi_pin_row_end) {
660
-
evt_mode1 |= BIT(pin - kpad->var->gpi_pin_row_base);
661
-
} else {
662
-
evt_mode2 |=
663
-
BIT(pin - kpad->var->gpi_pin_col_base) & 0xFF;
664
-
if (!kpad->is_adp5585)
665
-
evt_mode3 |=
666
-
BIT(pin - kpad->var->gpi_pin_col_base) >> 8;
667
-
}
668
-
}
669
-
670
-
if (pdata->gpimapsize) {
671
-
ret |= adp5589_write(client, reg(ADP5589_GPI_EVENT_EN_A),
672
-
evt_mode1);
673
-
ret |= adp5589_write(client, reg(ADP5589_GPI_EVENT_EN_B),
674
-
evt_mode2);
675
-
if (!kpad->is_adp5585)
676
-
ret |= adp5589_write(client,
677
-
reg(ADP5589_GPI_EVENT_EN_C),
678
-
evt_mode3);
679
-
}
680
-
681
-
if (pdata->pull_dis_mask & pdata->pullup_en_100k &
682
-
pdata->pullup_en_300k & pdata->pulldown_en_300k)
683
-
dev_warn(&client->dev, "Conflicting pull resistor config\n");
684
-
685
-
for (i = 0; i <= kpad->var->max_row_num; i++) {
686
-
unsigned int val = 0, bit = BIT(i);
687
-
if (pdata->pullup_en_300k & bit)
688
-
val = 0;
689
-
else if (pdata->pulldown_en_300k & bit)
690
-
val = 1;
691
-
else if (pdata->pullup_en_100k & bit)
692
-
val = 2;
693
-
else if (pdata->pull_dis_mask & bit)
694
-
val = 3;
695
-
696
-
pull_mask |= val << (2 * (i & 0x3));
697
-
698
-
if (i % 4 == 3 || i == kpad->var->max_row_num) {
699
-
ret |= adp5589_write(client, reg(ADP5585_RPULL_CONFIG_A)
700
-
+ (i >> 2), pull_mask);
701
-
pull_mask = 0;
702
-
}
703
-
}
704
-
705
-
for (i = 0; i <= kpad->var->max_col_num; i++) {
706
-
unsigned int val = 0, bit = BIT(i + kpad->var->col_shift);
707
-
if (pdata->pullup_en_300k & bit)
708
-
val = 0;
709
-
else if (pdata->pulldown_en_300k & bit)
710
-
val = 1;
711
-
else if (pdata->pullup_en_100k & bit)
712
-
val = 2;
713
-
else if (pdata->pull_dis_mask & bit)
714
-
val = 3;
715
-
716
-
pull_mask |= val << (2 * (i & 0x3));
717
-
718
-
if (i % 4 == 3 || i == kpad->var->max_col_num) {
719
-
ret |= adp5589_write(client,
720
-
reg(ADP5585_RPULL_CONFIG_C) +
721
-
(i >> 2), pull_mask);
722
-
pull_mask = 0;
723
-
}
724
-
}
725
-
726
-
if (pdata->reset1_key_1 && pdata->reset1_key_2 && pdata->reset1_key_3) {
727
-
ret |= adp5589_write(client, reg(ADP5589_RESET1_EVENT_A),
728
-
adp5589_get_evcode(kpad,
729
-
pdata->reset1_key_1));
730
-
ret |= adp5589_write(client, reg(ADP5589_RESET1_EVENT_B),
731
-
adp5589_get_evcode(kpad,
732
-
pdata->reset1_key_2));
733
-
ret |= adp5589_write(client, reg(ADP5589_RESET1_EVENT_C),
734
-
adp5589_get_evcode(kpad,
735
-
pdata->reset1_key_3));
736
-
kpad->extend_cfg |= R4_EXTEND_CFG;
737
-
}
738
-
739
-
if (pdata->reset2_key_1 && pdata->reset2_key_2) {
740
-
ret |= adp5589_write(client, reg(ADP5589_RESET2_EVENT_A),
741
-
adp5589_get_evcode(kpad,
742
-
pdata->reset2_key_1));
743
-
ret |= adp5589_write(client, reg(ADP5589_RESET2_EVENT_B),
744
-
adp5589_get_evcode(kpad,
745
-
pdata->reset2_key_2));
746
-
kpad->extend_cfg |= C4_EXTEND_CFG;
747
-
}
748
-
749
-
if (kpad->extend_cfg) {
750
-
ret |= adp5589_write(client, reg(ADP5589_RESET_CFG),
751
-
pdata->reset_cfg);
752
-
ret |= adp5589_write(client, reg(ADP5589_PIN_CONFIG_D),
753
-
kpad->extend_cfg);
754
-
}
755
-
756
-
ret |= adp5589_write(client, reg(ADP5589_DEBOUNCE_DIS_A),
757
-
pdata->debounce_dis_mask & kpad->var->row_mask);
758
-
759
-
ret |= adp5589_write(client, reg(ADP5589_DEBOUNCE_DIS_B),
760
-
(pdata->debounce_dis_mask >> kpad->var->col_shift)
761
-
& kpad->var->col_mask);
762
-
763
-
if (!kpad->is_adp5585)
764
-
ret |= adp5589_write(client, reg(ADP5589_DEBOUNCE_DIS_C),
765
-
(pdata->debounce_dis_mask >> 16) & 0xFF);
766
-
767
-
ret |= adp5589_write(client, reg(ADP5589_POLL_PTIME_CFG),
768
-
pdata->scan_cycle_time & PTIME_MASK);
769
-
ret |= adp5589_write(client, ADP5589_5_INT_STATUS,
770
-
(kpad->is_adp5585 ? 0 : LOGIC2_INT) |
771
-
LOGIC1_INT | OVRFLOW_INT |
772
-
(kpad->is_adp5585 ? 0 : LOCK_INT) |
773
-
GPI_INT | EVENT_INT); /* Status is W1C */
774
-
775
-
ret |= adp5589_write(client, reg(ADP5589_GENERAL_CFG),
776
-
INT_CFG | OSC_EN | CORE_CLK(3));
777
-
ret |= adp5589_write(client, reg(ADP5589_INT_EN),
778
-
OVRFLOW_IEN | GPI_IEN | EVENT_IEN);
779
-
780
-
if (ret < 0) {
781
-
dev_err(&client->dev, "Write Error\n");
782
-
return ret;
783
-
}
784
-
785
-
return 0;
786
-
}
787
-
788
-
static void adp5589_report_switch_state(struct adp5589_kpad *kpad)
789
-
{
790
-
int gpi_stat_tmp, pin_loc;
791
-
int i;
792
-
int gpi_stat1 = adp5589_read(kpad->client,
793
-
kpad->var->reg(ADP5589_GPI_STATUS_A));
794
-
int gpi_stat2 = adp5589_read(kpad->client,
795
-
kpad->var->reg(ADP5589_GPI_STATUS_B));
796
-
int gpi_stat3 = !kpad->is_adp5585 ?
797
-
adp5589_read(kpad->client, ADP5589_GPI_STATUS_C) : 0;
798
-
799
-
for (i = 0; i < kpad->gpimapsize; i++) {
800
-
unsigned short pin = kpad->gpimap[i].pin;
801
-
802
-
if (pin <= kpad->var->gpi_pin_row_end) {
803
-
gpi_stat_tmp = gpi_stat1;
804
-
pin_loc = pin - kpad->var->gpi_pin_row_base;
805
-
} else if ((pin - kpad->var->gpi_pin_col_base) < 8) {
806
-
gpi_stat_tmp = gpi_stat2;
807
-
pin_loc = pin - kpad->var->gpi_pin_col_base;
808
-
} else {
809
-
gpi_stat_tmp = gpi_stat3;
810
-
pin_loc = pin - kpad->var->gpi_pin_col_base - 8;
811
-
}
812
-
813
-
if (gpi_stat_tmp < 0) {
814
-
dev_err(&kpad->client->dev,
815
-
"Can't read GPIO_DAT_STAT switch %d, default to OFF\n",
816
-
pin);
817
-
gpi_stat_tmp = 0;
818
-
}
819
-
820
-
input_report_switch(kpad->input,
821
-
kpad->gpimap[i].sw_evt,
822
-
!(gpi_stat_tmp & BIT(pin_loc)));
823
-
}
824
-
825
-
input_sync(kpad->input);
826
-
}
827
-
828
-
static int adp5589_keypad_add(struct adp5589_kpad *kpad, unsigned int revid)
829
-
{
830
-
struct i2c_client *client = kpad->client;
831
-
const struct adp5589_kpad_platform_data *pdata =
832
-
dev_get_platdata(&client->dev);
833
-
struct input_dev *input;
834
-
unsigned int i;
835
-
int error;
836
-
837
-
if (!((pdata->keypad_en_mask & kpad->var->row_mask) &&
838
-
(pdata->keypad_en_mask >> kpad->var->col_shift)) ||
839
-
!pdata->keymap) {
840
-
dev_err(&client->dev, "no rows, cols or keymap from pdata\n");
841
-
return -EINVAL;
842
-
}
843
-
844
-
if (pdata->keymapsize != kpad->var->keymapsize) {
845
-
dev_err(&client->dev, "invalid keymapsize\n");
846
-
return -EINVAL;
847
-
}
848
-
849
-
if (!pdata->gpimap && pdata->gpimapsize) {
850
-
dev_err(&client->dev, "invalid gpimap from pdata\n");
851
-
return -EINVAL;
852
-
}
853
-
854
-
if (pdata->gpimapsize > kpad->var->gpimapsize_max) {
855
-
dev_err(&client->dev, "invalid gpimapsize\n");
856
-
return -EINVAL;
857
-
}
858
-
859
-
for (i = 0; i < pdata->gpimapsize; i++) {
860
-
unsigned short pin = pdata->gpimap[i].pin;
861
-
862
-
if (pin < kpad->var->gpi_pin_base ||
863
-
pin > kpad->var->gpi_pin_end) {
864
-
dev_err(&client->dev, "invalid gpi pin data\n");
865
-
return -EINVAL;
866
-
}
867
-
868
-
if (BIT(pin - kpad->var->gpi_pin_row_base) &
869
-
pdata->keypad_en_mask) {
870
-
dev_err(&client->dev, "invalid gpi row/col data\n");
871
-
return -EINVAL;
872
-
}
873
-
}
874
-
875
-
if (!client->irq) {
876
-
dev_err(&client->dev, "no IRQ?\n");
877
-
return -EINVAL;
878
-
}
879
-
880
-
input = devm_input_allocate_device(&client->dev);
881
-
if (!input)
882
-
return -ENOMEM;
883
-
884
-
kpad->input = input;
885
-
886
-
input->name = client->name;
887
-
input->phys = "adp5589-keys/input0";
888
-
input->dev.parent = &client->dev;
889
-
890
-
input_set_drvdata(input, kpad);
891
-
892
-
input->id.bustype = BUS_I2C;
893
-
input->id.vendor = 0x0001;
894
-
input->id.product = 0x0001;
895
-
input->id.version = revid;
896
-
897
-
input->keycodesize = sizeof(kpad->keycode[0]);
898
-
input->keycodemax = pdata->keymapsize;
899
-
input->keycode = kpad->keycode;
900
-
901
-
memcpy(kpad->keycode, pdata->keymap,
902
-
pdata->keymapsize * input->keycodesize);
903
-
904
-
kpad->gpimap = pdata->gpimap;
905
-
kpad->gpimapsize = pdata->gpimapsize;
906
-
907
-
/* setup input device */
908
-
__set_bit(EV_KEY, input->evbit);
909
-
910
-
if (pdata->repeat)
911
-
__set_bit(EV_REP, input->evbit);
912
-
913
-
for (i = 0; i < input->keycodemax; i++)
914
-
if (kpad->keycode[i] <= KEY_MAX)
915
-
__set_bit(kpad->keycode[i], input->keybit);
916
-
__clear_bit(KEY_RESERVED, input->keybit);
917
-
918
-
if (kpad->gpimapsize)
919
-
__set_bit(EV_SW, input->evbit);
920
-
for (i = 0; i < kpad->gpimapsize; i++)
921
-
__set_bit(kpad->gpimap[i].sw_evt, input->swbit);
922
-
923
-
error = input_register_device(input);
924
-
if (error) {
925
-
dev_err(&client->dev, "unable to register input device\n");
926
-
return error;
927
-
}
928
-
929
-
error = devm_request_threaded_irq(&client->dev, client->irq,
930
-
NULL, adp5589_irq,
931
-
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
932
-
client->dev.driver->name, kpad);
933
-
if (error) {
934
-
dev_err(&client->dev, "unable to request irq %d\n", client->irq);
935
-
return error;
936
-
}
937
-
938
-
return 0;
939
-
}
940
-
941
-
static void adp5589_clear_config(void *data)
942
-
{
943
-
struct adp5589_kpad *kpad = data;
944
-
945
-
adp5589_write(kpad->client, kpad->var->reg(ADP5589_GENERAL_CFG), 0);
946
-
}
947
-
948
-
static int adp5589_probe(struct i2c_client *client)
949
-
{
950
-
const struct i2c_device_id *id = i2c_client_get_device_id(client);
951
-
struct adp5589_kpad *kpad;
952
-
const struct adp5589_kpad_platform_data *pdata =
953
-
dev_get_platdata(&client->dev);
954
-
unsigned int revid;
955
-
int error, ret;
956
-
957
-
if (!i2c_check_functionality(client->adapter,
958
-
I2C_FUNC_SMBUS_BYTE_DATA)) {
959
-
dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
960
-
return -EIO;
961
-
}
962
-
963
-
if (!pdata) {
964
-
dev_err(&client->dev, "no platform data?\n");
965
-
return -EINVAL;
966
-
}
967
-
968
-
kpad = devm_kzalloc(&client->dev, sizeof(*kpad), GFP_KERNEL);
969
-
if (!kpad)
970
-
return -ENOMEM;
971
-
972
-
kpad->client = client;
973
-
974
-
switch (id->driver_data) {
975
-
case ADP5585_02:
976
-
kpad->support_row5 = true;
977
-
fallthrough;
978
-
case ADP5585_01:
979
-
kpad->is_adp5585 = true;
980
-
kpad->var = &const_adp5585;
981
-
break;
982
-
case ADP5589:
983
-
kpad->support_row5 = true;
984
-
kpad->var = &const_adp5589;
985
-
break;
986
-
}
987
-
988
-
error = devm_add_action_or_reset(&client->dev, adp5589_clear_config,
989
-
kpad);
990
-
if (error)
991
-
return error;
992
-
993
-
ret = adp5589_read(client, ADP5589_5_ID);
994
-
if (ret < 0)
995
-
return ret;
996
-
997
-
revid = (u8) ret & ADP5589_5_DEVICE_ID_MASK;
998
-
999
-
if (pdata->keymapsize) {
1000
-
error = adp5589_keypad_add(kpad, revid);
1001
-
if (error)
1002
-
return error;
1003
-
}
1004
-
1005
-
error = adp5589_setup(kpad);
1006
-
if (error)
1007
-
return error;
1008
-
1009
-
if (kpad->gpimapsize)
1010
-
adp5589_report_switch_state(kpad);
1011
-
1012
-
error = adp5589_gpio_add(kpad);
1013
-
if (error)
1014
-
return error;
1015
-
1016
-
dev_info(&client->dev, "Rev.%d keypad, irq %d\n", revid, client->irq);
1017
-
return 0;
1018
-
}
1019
-
1020
-
static int adp5589_suspend(struct device *dev)
1021
-
{
1022
-
struct i2c_client *client = to_i2c_client(dev);
1023
-
struct adp5589_kpad *kpad = i2c_get_clientdata(client);
1024
-
1025
-
if (kpad->input)
1026
-
disable_irq(client->irq);
1027
-
1028
-
return 0;
1029
-
}
1030
-
1031
-
static int adp5589_resume(struct device *dev)
1032
-
{
1033
-
struct i2c_client *client = to_i2c_client(dev);
1034
-
struct adp5589_kpad *kpad = i2c_get_clientdata(client);
1035
-
1036
-
if (kpad->input)
1037
-
enable_irq(client->irq);
1038
-
1039
-
return 0;
1040
-
}
1041
-
1042
-
static DEFINE_SIMPLE_DEV_PM_OPS(adp5589_dev_pm_ops, adp5589_suspend, adp5589_resume);
1043
-
1044
-
static const struct i2c_device_id adp5589_id[] = {
1045
-
{"adp5589-keys", ADP5589},
1046
-
{"adp5585-keys", ADP5585_01},
1047
-
{"adp5585-02-keys", ADP5585_02}, /* Adds ROW5 to ADP5585 */
1048
-
{}
1049
-
};
1050
-
1051
-
MODULE_DEVICE_TABLE(i2c, adp5589_id);
1052
-
1053
-
static struct i2c_driver adp5589_driver = {
1054
-
.driver = {
1055
-
.name = KBUILD_MODNAME,
1056
-
.pm = pm_sleep_ptr(&adp5589_dev_pm_ops),
1057
-
},
1058
-
.probe = adp5589_probe,
1059
-
.id_table = adp5589_id,
1060
-
};
1061
-
1062
-
module_i2c_driver(adp5589_driver);
1063
-
1064
-
MODULE_LICENSE("GPL");
1065
-
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1066
-
MODULE_DESCRIPTION("ADP5589/ADP5585 Keypad driver");
+18
drivers/mfd/Kconfig
+18
drivers/mfd/Kconfig
···
285
285
Select this to support the Cirrus Logic CS42L43 PC CODEC with
286
286
headphone and class D speaker drivers over SoundWire.
287
287
288
+
config MFD_MACSMC
289
+
tristate "Apple Silicon System Management Controller (SMC)"
290
+
depends on ARCH_APPLE || COMPILE_TEST
291
+
depends on OF
292
+
depends on APPLE_RTKIT
293
+
select MFD_CORE
294
+
help
295
+
The System Management Controller (SMC) on Apple Silicon machines is a
296
+
piece of hardware that exposes various functionalities such as
297
+
temperature sensors, voltage/power meters, shutdown/reboot handling,
298
+
GPIOs and more.
299
+
300
+
Communication happens via a shared mailbox using the RTKit protocol
301
+
which is also used for other co-processors. The SMC protocol then
302
+
allows reading and writing many different keys which implement the
303
+
various features. The MFD core device handles this protocol and
304
+
exposes it to the sub-devices.
305
+
288
306
config MFD_MADERA
289
307
tristate "Cirrus Logic Madera codecs"
290
308
select MFD_CORE
+1
drivers/mfd/Makefile
+1
drivers/mfd/Makefile
···
21
21
obj-$(CONFIG_MFD_ENE_KB3930) += ene-kb3930.o
22
22
obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o
23
23
obj-$(CONFIG_MFD_GATEWORKS_GSC) += gateworks-gsc.o
24
+
obj-$(CONFIG_MFD_MACSMC) += macsmc.o
24
25
25
26
obj-$(CONFIG_MFD_TI_LP873X) += lp873x.o
26
27
obj-$(CONFIG_MFD_TI_LP87565) += lp87565.o
+690
-51
drivers/mfd/adp5585.c
+690
-51
drivers/mfd/adp5585.c
···
4
4
*
5
5
* Copyright 2022 NXP
6
6
* Copyright 2024 Ideas on Board Oy
7
+
* Copyright 2025 Analog Devices Inc.
7
8
*/
8
9
9
10
#include <linux/array_size.h>
11
+
#include <linux/bitfield.h>
10
12
#include <linux/device.h>
11
13
#include <linux/err.h>
12
14
#include <linux/i2c.h>
15
+
#include <linux/gpio/consumer.h>
13
16
#include <linux/mfd/adp5585.h>
14
17
#include <linux/mfd/core.h>
15
18
#include <linux/mod_devicetable.h>
16
19
#include <linux/module.h>
17
20
#include <linux/regmap.h>
21
+
#include <linux/regulator/consumer.h>
18
22
#include <linux/types.h>
19
23
20
-
static const struct mfd_cell adp5585_devs[] = {
21
-
{ .name = "adp5585-gpio", },
22
-
{ .name = "adp5585-pwm", },
24
+
enum {
25
+
ADP5585_DEV_GPIO,
26
+
ADP5585_DEV_PWM,
27
+
ADP5585_DEV_INPUT,
28
+
ADP5585_DEV_MAX
29
+
};
30
+
31
+
static const struct mfd_cell adp5585_devs[ADP5585_DEV_MAX] = {
32
+
MFD_CELL_NAME("adp5585-gpio"),
33
+
MFD_CELL_NAME("adp5585-pwm"),
34
+
MFD_CELL_NAME("adp5585-keys"),
35
+
};
36
+
37
+
static const struct mfd_cell adp5589_devs[] = {
38
+
MFD_CELL_NAME("adp5589-gpio"),
39
+
MFD_CELL_NAME("adp5589-pwm"),
40
+
MFD_CELL_NAME("adp5589-keys"),
23
41
};
24
42
25
43
static const struct regmap_range adp5585_volatile_ranges[] = {
···
47
29
static const struct regmap_access_table adp5585_volatile_regs = {
48
30
.yes_ranges = adp5585_volatile_ranges,
49
31
.n_yes_ranges = ARRAY_SIZE(adp5585_volatile_ranges),
32
+
};
33
+
34
+
static const struct regmap_range adp5589_volatile_ranges[] = {
35
+
regmap_reg_range(ADP5585_ID, ADP5589_GPI_STATUS_C),
36
+
};
37
+
38
+
static const struct regmap_access_table adp5589_volatile_regs = {
39
+
.yes_ranges = adp5589_volatile_ranges,
40
+
.n_yes_ranges = ARRAY_SIZE(adp5589_volatile_ranges),
50
41
};
51
42
52
43
/*
···
101
74
/* 0x38 */ 0x00, 0x00, 0x00, 0x00, 0x00,
102
75
};
103
76
104
-
enum adp5585_regmap_type {
105
-
ADP5585_REGMAP_00,
106
-
ADP5585_REGMAP_02,
107
-
ADP5585_REGMAP_04,
77
+
static const u8 adp5589_regmap_defaults_00[ADP5589_MAX_REG + 1] = {
78
+
/* 0x00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79
+
/* 0x08 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
80
+
/* 0x10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
81
+
/* 0x18 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
82
+
/* 0x20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
83
+
/* 0x28 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
84
+
/* 0x30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
85
+
/* 0x38 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
86
+
/* 0x40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
87
+
/* 0x48 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
108
88
};
109
89
110
-
static const struct regmap_config adp5585_regmap_configs[] = {
111
-
[ADP5585_REGMAP_00] = {
112
-
.reg_bits = 8,
113
-
.val_bits = 8,
114
-
.max_register = ADP5585_MAX_REG,
115
-
.volatile_table = &adp5585_volatile_regs,
116
-
.cache_type = REGCACHE_MAPLE,
117
-
.reg_defaults_raw = adp5585_regmap_defaults_00,
118
-
.num_reg_defaults_raw = sizeof(adp5585_regmap_defaults_00),
119
-
},
120
-
[ADP5585_REGMAP_02] = {
121
-
.reg_bits = 8,
122
-
.val_bits = 8,
123
-
.max_register = ADP5585_MAX_REG,
124
-
.volatile_table = &adp5585_volatile_regs,
125
-
.cache_type = REGCACHE_MAPLE,
126
-
.reg_defaults_raw = adp5585_regmap_defaults_02,
127
-
.num_reg_defaults_raw = sizeof(adp5585_regmap_defaults_02),
128
-
},
129
-
[ADP5585_REGMAP_04] = {
130
-
.reg_bits = 8,
131
-
.val_bits = 8,
132
-
.max_register = ADP5585_MAX_REG,
133
-
.volatile_table = &adp5585_volatile_regs,
134
-
.cache_type = REGCACHE_MAPLE,
135
-
.reg_defaults_raw = adp5585_regmap_defaults_04,
136
-
.num_reg_defaults_raw = sizeof(adp5585_regmap_defaults_04),
137
-
},
90
+
static const u8 adp5589_regmap_defaults_01[ADP5589_MAX_REG + 1] = {
91
+
/* 0x00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92
+
/* 0x08 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93
+
/* 0x10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
94
+
/* 0x18 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
95
+
/* 0x20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
96
+
/* 0x28 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
97
+
/* 0x30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
98
+
/* 0x38 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
99
+
/* 0x40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
100
+
/* 0x48 */ 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
138
101
};
102
+
103
+
static const u8 adp5589_regmap_defaults_02[ADP5589_MAX_REG + 1] = {
104
+
/* 0x00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
105
+
/* 0x08 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
106
+
/* 0x10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
107
+
/* 0x18 */ 0x00, 0x41, 0x01, 0x00, 0x11, 0x04, 0x00, 0x00,
108
+
/* 0x20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
109
+
/* 0x28 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
110
+
/* 0x30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
111
+
/* 0x38 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
112
+
/* 0x40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
113
+
/* 0x48 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
114
+
};
115
+
116
+
static const u8 *adp5585_regmap_defaults[ADP5585_MAX] = {
117
+
[ADP5585_00] = adp5585_regmap_defaults_00,
118
+
[ADP5585_01] = adp5585_regmap_defaults_00,
119
+
[ADP5585_02] = adp5585_regmap_defaults_02,
120
+
[ADP5585_03] = adp5585_regmap_defaults_00,
121
+
[ADP5585_04] = adp5585_regmap_defaults_04,
122
+
[ADP5589_00] = adp5589_regmap_defaults_00,
123
+
[ADP5589_01] = adp5589_regmap_defaults_01,
124
+
[ADP5589_02] = adp5589_regmap_defaults_02,
125
+
};
126
+
127
+
static const struct regmap_config adp5585_regmap_config_template = {
128
+
.reg_bits = 8,
129
+
.val_bits = 8,
130
+
.max_register = ADP5585_MAX_REG,
131
+
.volatile_table = &adp5585_volatile_regs,
132
+
.cache_type = REGCACHE_MAPLE,
133
+
.num_reg_defaults_raw = ADP5585_MAX_REG + 1,
134
+
};
135
+
136
+
static const struct regmap_config adp5589_regmap_config_template = {
137
+
.reg_bits = 8,
138
+
.val_bits = 8,
139
+
.max_register = ADP5589_MAX_REG,
140
+
.volatile_table = &adp5589_volatile_regs,
141
+
.cache_type = REGCACHE_MAPLE,
142
+
.num_reg_defaults_raw = ADP5589_MAX_REG + 1,
143
+
};
144
+
145
+
static const struct adp5585_regs adp5585_regs = {
146
+
.ext_cfg = ADP5585_PIN_CONFIG_C,
147
+
.int_en = ADP5585_INT_EN,
148
+
.gen_cfg = ADP5585_GENERAL_CFG,
149
+
.poll_ptime_cfg = ADP5585_POLL_PTIME_CFG,
150
+
.reset_cfg = ADP5585_RESET_CFG,
151
+
.reset1_event_a = ADP5585_RESET1_EVENT_A,
152
+
.reset2_event_a = ADP5585_RESET2_EVENT_A,
153
+
.pin_cfg_a = ADP5585_PIN_CONFIG_A,
154
+
};
155
+
156
+
static const struct adp5585_regs adp5589_regs = {
157
+
.ext_cfg = ADP5589_PIN_CONFIG_D,
158
+
.int_en = ADP5589_INT_EN,
159
+
.gen_cfg = ADP5589_GENERAL_CFG,
160
+
.poll_ptime_cfg = ADP5589_POLL_PTIME_CFG,
161
+
.reset_cfg = ADP5589_RESET_CFG,
162
+
.reset1_event_a = ADP5589_RESET1_EVENT_A,
163
+
.reset2_event_a = ADP5589_RESET2_EVENT_A,
164
+
.pin_cfg_a = ADP5589_PIN_CONFIG_A,
165
+
};
166
+
167
+
static int adp5585_validate_event(const struct adp5585_dev *adp5585, unsigned int ev)
168
+
{
169
+
if (adp5585->has_pin6) {
170
+
if (ev >= ADP5585_ROW5_KEY_EVENT_START && ev <= ADP5585_ROW5_KEY_EVENT_END)
171
+
return 0;
172
+
if (ev >= ADP5585_GPI_EVENT_START && ev <= ADP5585_GPI_EVENT_END)
173
+
return 0;
174
+
175
+
return dev_err_probe(adp5585->dev, -EINVAL,
176
+
"Invalid unlock/reset event(%u) for this device\n", ev);
177
+
}
178
+
179
+
if (ev >= ADP5585_KEY_EVENT_START && ev <= ADP5585_KEY_EVENT_END)
180
+
return 0;
181
+
if (ev >= ADP5585_GPI_EVENT_START && ev <= ADP5585_GPI_EVENT_END) {
182
+
/*
183
+
* Some variants of the adp5585 do not have the Row 5
184
+
* (meaning pin 6 or GPIO 6) available. Instead that pin serves
185
+
* as a reset pin. So, we need to make sure no event is
186
+
* configured for it.
187
+
*/
188
+
if (ev == (ADP5585_GPI_EVENT_START + 5))
189
+
return dev_err_probe(adp5585->dev, -EINVAL,
190
+
"Invalid unlock/reset event(%u). R5 not available\n",
191
+
ev);
192
+
return 0;
193
+
}
194
+
195
+
return dev_err_probe(adp5585->dev, -EINVAL,
196
+
"Invalid unlock/reset event(%u) for this device\n", ev);
197
+
}
198
+
199
+
static int adp5589_validate_event(const struct adp5585_dev *adp5585, unsigned int ev)
200
+
{
201
+
if (ev >= ADP5589_KEY_EVENT_START && ev <= ADP5589_KEY_EVENT_END)
202
+
return 0;
203
+
if (ev >= ADP5589_GPI_EVENT_START && ev <= ADP5589_GPI_EVENT_END)
204
+
return 0;
205
+
206
+
return dev_err_probe(adp5585->dev, -EINVAL,
207
+
"Invalid unlock/reset event(%u) for this device\n", ev);
208
+
}
209
+
210
+
static struct regmap_config *adp5585_fill_variant_config(struct adp5585_dev *adp5585)
211
+
{
212
+
struct regmap_config *regmap_config;
213
+
214
+
switch (adp5585->variant) {
215
+
case ADP5585_00:
216
+
case ADP5585_01:
217
+
case ADP5585_02:
218
+
case ADP5585_03:
219
+
case ADP5585_04:
220
+
adp5585->id = ADP5585_MAN_ID_VALUE;
221
+
adp5585->regs = &adp5585_regs;
222
+
adp5585->n_pins = ADP5585_PIN_MAX;
223
+
adp5585->reset2_out = ADP5585_RESET2_OUT;
224
+
if (adp5585->variant == ADP5585_01)
225
+
adp5585->has_pin6 = true;
226
+
regmap_config = devm_kmemdup(adp5585->dev, &adp5585_regmap_config_template,
227
+
sizeof(*regmap_config), GFP_KERNEL);
228
+
break;
229
+
case ADP5589_00:
230
+
case ADP5589_01:
231
+
case ADP5589_02:
232
+
adp5585->id = ADP5589_MAN_ID_VALUE;
233
+
adp5585->regs = &adp5589_regs;
234
+
adp5585->has_unlock = true;
235
+
adp5585->has_pin6 = true;
236
+
adp5585->n_pins = ADP5589_PIN_MAX;
237
+
adp5585->reset2_out = ADP5589_RESET2_OUT;
238
+
regmap_config = devm_kmemdup(adp5585->dev, &adp5589_regmap_config_template,
239
+
sizeof(*regmap_config), GFP_KERNEL);
240
+
break;
241
+
default:
242
+
return ERR_PTR(-ENODEV);
243
+
}
244
+
245
+
if (!regmap_config)
246
+
return ERR_PTR(-ENOMEM);
247
+
248
+
regmap_config->reg_defaults_raw = adp5585_regmap_defaults[adp5585->variant];
249
+
250
+
return regmap_config;
251
+
}
252
+
253
+
static int adp5585_parse_ev_array(const struct adp5585_dev *adp5585, const char *prop, u32 *events,
254
+
u32 *n_events, u32 max_evs, bool reset_ev)
255
+
{
256
+
struct device *dev = adp5585->dev;
257
+
unsigned int ev;
258
+
int ret;
259
+
260
+
/*
261
+
* The device has the capability of handling special events through GPIs or a Keypad:
262
+
* unlock events: Unlock the keymap until one of the configured events is detected.
263
+
* reset events: Generate a reset pulse when one of the configured events is detected.
264
+
*/
265
+
ret = device_property_count_u32(dev, prop);
266
+
if (ret < 0)
267
+
return 0;
268
+
269
+
*n_events = ret;
270
+
271
+
if (!adp5585->has_unlock && !reset_ev)
272
+
return dev_err_probe(dev, -EOPNOTSUPP, "Unlock keys not supported\n");
273
+
274
+
if (*n_events > max_evs)
275
+
return dev_err_probe(dev, -EINVAL,
276
+
"Invalid number of keys(%u > %u) for %s\n",
277
+
*n_events, max_evs, prop);
278
+
279
+
ret = device_property_read_u32_array(dev, prop, events, *n_events);
280
+
if (ret)
281
+
return ret;
282
+
283
+
for (ev = 0; ev < *n_events; ev++) {
284
+
if (!reset_ev && events[ev] == ADP5589_UNLOCK_WILDCARD)
285
+
continue;
286
+
287
+
if (adp5585->id == ADP5585_MAN_ID_VALUE)
288
+
ret = adp5585_validate_event(adp5585, events[ev]);
289
+
else
290
+
ret = adp5589_validate_event(adp5585, events[ev]);
291
+
if (ret)
292
+
return ret;
293
+
}
294
+
295
+
return 0;
296
+
}
297
+
298
+
static int adp5585_unlock_ev_parse(struct adp5585_dev *adp5585)
299
+
{
300
+
struct device *dev = adp5585->dev;
301
+
int ret;
302
+
303
+
ret = adp5585_parse_ev_array(adp5585, "adi,unlock-events", adp5585->unlock_keys,
304
+
&adp5585->nkeys_unlock, ARRAY_SIZE(adp5585->unlock_keys),
305
+
false);
306
+
if (ret)
307
+
return ret;
308
+
if (!adp5585->nkeys_unlock)
309
+
return 0;
310
+
311
+
ret = device_property_read_u32(dev, "adi,unlock-trigger-sec", &adp5585->unlock_time);
312
+
if (!ret) {
313
+
if (adp5585->unlock_time > ADP5585_MAX_UNLOCK_TIME_SEC)
314
+
return dev_err_probe(dev, -EINVAL,
315
+
"Invalid unlock time(%u > %d)\n",
316
+
adp5585->unlock_time,
317
+
ADP5585_MAX_UNLOCK_TIME_SEC);
318
+
}
319
+
320
+
return 0;
321
+
}
322
+
323
+
static int adp5585_reset_ev_parse(struct adp5585_dev *adp5585)
324
+
{
325
+
struct device *dev = adp5585->dev;
326
+
u32 prop_val;
327
+
int ret;
328
+
329
+
ret = adp5585_parse_ev_array(adp5585, "adi,reset1-events", adp5585->reset1_keys,
330
+
&adp5585->nkeys_reset1,
331
+
ARRAY_SIZE(adp5585->reset1_keys), true);
332
+
if (ret)
333
+
return ret;
334
+
335
+
ret = adp5585_parse_ev_array(adp5585, "adi,reset2-events",
336
+
adp5585->reset2_keys,
337
+
&adp5585->nkeys_reset2,
338
+
ARRAY_SIZE(adp5585->reset2_keys), true);
339
+
if (ret)
340
+
return ret;
341
+
342
+
if (!adp5585->nkeys_reset1 && !adp5585->nkeys_reset2)
343
+
return 0;
344
+
345
+
if (adp5585->nkeys_reset1 && device_property_read_bool(dev, "adi,reset1-active-high"))
346
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET1_POL, 1);
347
+
348
+
if (adp5585->nkeys_reset2 && device_property_read_bool(dev, "adi,reset2-active-high"))
349
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET2_POL, 1);
350
+
351
+
if (device_property_read_bool(dev, "adi,rst-passthrough-enable"))
352
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RST_PASSTHRU_EN, 1);
353
+
354
+
ret = device_property_read_u32(dev, "adi,reset-trigger-ms", &prop_val);
355
+
if (!ret) {
356
+
switch (prop_val) {
357
+
case 0:
358
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 0);
359
+
break;
360
+
case 1000:
361
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 1);
362
+
break;
363
+
case 1500:
364
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 2);
365
+
break;
366
+
case 2000:
367
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 3);
368
+
break;
369
+
case 2500:
370
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 4);
371
+
break;
372
+
case 3000:
373
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 5);
374
+
break;
375
+
case 3500:
376
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 6);
377
+
break;
378
+
case 4000:
379
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_RESET_TRIG_TIME, 7);
380
+
break;
381
+
default:
382
+
return dev_err_probe(dev, -EINVAL,
383
+
"Invalid value(%u) for adi,reset-trigger-ms\n",
384
+
prop_val);
385
+
}
386
+
}
387
+
388
+
ret = device_property_read_u32(dev, "adi,reset-pulse-width-us", &prop_val);
389
+
if (!ret) {
390
+
switch (prop_val) {
391
+
case 500:
392
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_PULSE_WIDTH, 0);
393
+
break;
394
+
case 1000:
395
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_PULSE_WIDTH, 1);
396
+
break;
397
+
case 2000:
398
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_PULSE_WIDTH, 2);
399
+
break;
400
+
case 10000:
401
+
adp5585->reset_cfg |= FIELD_PREP(ADP5585_PULSE_WIDTH, 3);
402
+
break;
403
+
default:
404
+
return dev_err_probe(dev, -EINVAL,
405
+
"Invalid value(%u) for adi,reset-pulse-width-us\n",
406
+
prop_val);
407
+
}
408
+
return ret;
409
+
}
410
+
411
+
return 0;
412
+
}
413
+
414
+
static int adp5585_add_devices(const struct adp5585_dev *adp5585)
415
+
{
416
+
struct device *dev = adp5585->dev;
417
+
const struct mfd_cell *cells;
418
+
int ret;
419
+
420
+
if (adp5585->id == ADP5585_MAN_ID_VALUE)
421
+
cells = adp5585_devs;
422
+
else
423
+
cells = adp5589_devs;
424
+
425
+
if (device_property_present(dev, "#pwm-cells")) {
426
+
/* Make sure the PWM output pin is not used by the GPIO or INPUT devices */
427
+
__set_bit(ADP5585_PWM_OUT, adp5585->pin_usage);
428
+
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
429
+
&cells[ADP5585_DEV_PWM], 1, NULL, 0, NULL);
430
+
if (ret)
431
+
return dev_err_probe(dev, ret, "Failed to add PWM device\n");
432
+
}
433
+
434
+
if (device_property_present(dev, "#gpio-cells")) {
435
+
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
436
+
&cells[ADP5585_DEV_GPIO], 1, NULL, 0, NULL);
437
+
if (ret)
438
+
return dev_err_probe(dev, ret, "Failed to add GPIO device\n");
439
+
}
440
+
441
+
if (device_property_present(adp5585->dev, "adi,keypad-pins")) {
442
+
ret = devm_mfd_add_devices(adp5585->dev, PLATFORM_DEVID_AUTO,
443
+
&cells[ADP5585_DEV_INPUT], 1, NULL, 0, NULL);
444
+
if (ret)
445
+
return dev_err_probe(dev, ret, "Failed to add input device\n");
446
+
}
447
+
448
+
return 0;
449
+
}
450
+
451
+
static void adp5585_osc_disable(void *data)
452
+
{
453
+
const struct adp5585_dev *adp5585 = data;
454
+
455
+
regmap_write(adp5585->regmap, ADP5585_GENERAL_CFG, 0);
456
+
}
457
+
458
+
static void adp5585_report_events(struct adp5585_dev *adp5585, int ev_cnt)
459
+
{
460
+
unsigned int i;
461
+
462
+
for (i = 0; i < ev_cnt; i++) {
463
+
unsigned long key_val, key_press;
464
+
unsigned int key;
465
+
int ret;
466
+
467
+
ret = regmap_read(adp5585->regmap, ADP5585_FIFO_1 + i, &key);
468
+
if (ret)
469
+
return;
470
+
471
+
key_val = FIELD_GET(ADP5585_KEY_EVENT_MASK, key);
472
+
key_press = FIELD_GET(ADP5585_KEV_EV_PRESS_MASK, key);
473
+
474
+
blocking_notifier_call_chain(&adp5585->event_notifier, key_val, (void *)key_press);
475
+
}
476
+
}
477
+
478
+
static irqreturn_t adp5585_irq(int irq, void *data)
479
+
{
480
+
struct adp5585_dev *adp5585 = data;
481
+
unsigned int status, ev_cnt;
482
+
int ret;
483
+
484
+
ret = regmap_read(adp5585->regmap, ADP5585_INT_STATUS, &status);
485
+
if (ret)
486
+
return IRQ_HANDLED;
487
+
488
+
if (status & ADP5585_OVRFLOW_INT)
489
+
dev_err_ratelimited(adp5585->dev, "Event overflow error\n");
490
+
491
+
if (!(status & ADP5585_EVENT_INT))
492
+
goto out_irq;
493
+
494
+
ret = regmap_read(adp5585->regmap, ADP5585_STATUS, &ev_cnt);
495
+
if (ret)
496
+
goto out_irq;
497
+
498
+
ev_cnt = FIELD_GET(ADP5585_EC_MASK, ev_cnt);
499
+
if (!ev_cnt)
500
+
goto out_irq;
501
+
502
+
adp5585_report_events(adp5585, ev_cnt);
503
+
out_irq:
504
+
regmap_write(adp5585->regmap, ADP5585_INT_STATUS, status);
505
+
return IRQ_HANDLED;
506
+
}
507
+
508
+
static int adp5585_setup(struct adp5585_dev *adp5585)
509
+
{
510
+
const struct adp5585_regs *regs = adp5585->regs;
511
+
unsigned int reg_val = 0, i;
512
+
int ret;
513
+
514
+
/* If pin_6 (ROW5/GPI6) is not available, make sure to mark it as "busy" */
515
+
if (!adp5585->has_pin6)
516
+
__set_bit(ADP5585_ROW5, adp5585->pin_usage);
517
+
518
+
/* Configure the device with reset and unlock events */
519
+
for (i = 0; i < adp5585->nkeys_unlock; i++) {
520
+
ret = regmap_write(adp5585->regmap, ADP5589_UNLOCK1 + i,
521
+
adp5585->unlock_keys[i] | ADP5589_UNLOCK_EV_PRESS);
522
+
if (ret)
523
+
return ret;
524
+
}
525
+
526
+
if (adp5585->nkeys_unlock) {
527
+
ret = regmap_update_bits(adp5585->regmap, ADP5589_UNLOCK_TIMERS,
528
+
ADP5589_UNLOCK_TIMER, adp5585->unlock_time);
529
+
if (ret)
530
+
return ret;
531
+
532
+
ret = regmap_set_bits(adp5585->regmap, ADP5589_LOCK_CFG, ADP5589_LOCK_EN);
533
+
if (ret)
534
+
return ret;
535
+
}
536
+
537
+
for (i = 0; i < adp5585->nkeys_reset1; i++) {
538
+
ret = regmap_write(adp5585->regmap, regs->reset1_event_a + i,
539
+
adp5585->reset1_keys[i] | ADP5585_RESET_EV_PRESS);
540
+
if (ret)
541
+
return ret;
542
+
543
+
/* Mark that pin as not usable for the INPUT and GPIO devices. */
544
+
__set_bit(ADP5585_RESET1_OUT, adp5585->pin_usage);
545
+
}
546
+
547
+
for (i = 0; i < adp5585->nkeys_reset2; i++) {
548
+
ret = regmap_write(adp5585->regmap, regs->reset2_event_a + i,
549
+
adp5585->reset2_keys[i] | ADP5585_RESET_EV_PRESS);
550
+
if (ret)
551
+
return ret;
552
+
553
+
__set_bit(adp5585->reset2_out, adp5585->pin_usage);
554
+
}
555
+
556
+
if (adp5585->nkeys_reset1 || adp5585->nkeys_reset2) {
557
+
ret = regmap_write(adp5585->regmap, regs->reset_cfg, adp5585->reset_cfg);
558
+
if (ret)
559
+
return ret;
560
+
561
+
/* If there's a reset1 event, then R4 is used as an output for the reset signal */
562
+
if (adp5585->nkeys_reset1)
563
+
reg_val = ADP5585_R4_EXTEND_CFG_RESET1;
564
+
/* If there's a reset2 event, then C4 is used as an output for the reset signal */
565
+
if (adp5585->nkeys_reset2)
566
+
reg_val |= ADP5585_C4_EXTEND_CFG_RESET2;
567
+
568
+
ret = regmap_update_bits(adp5585->regmap, regs->ext_cfg,
569
+
ADP5585_C4_EXTEND_CFG_MASK | ADP5585_R4_EXTEND_CFG_MASK,
570
+
reg_val);
571
+
if (ret)
572
+
return ret;
573
+
}
574
+
575
+
/* Clear any possible event by reading all the FIFO entries */
576
+
for (i = 0; i < ADP5585_EV_MAX; i++) {
577
+
ret = regmap_read(adp5585->regmap, ADP5585_FIFO_1 + i, ®_val);
578
+
if (ret)
579
+
return ret;
580
+
}
581
+
582
+
ret = regmap_write(adp5585->regmap, regs->poll_ptime_cfg, adp5585->ev_poll_time);
583
+
if (ret)
584
+
return ret;
585
+
586
+
/*
587
+
* Enable the internal oscillator, as it's shared between multiple
588
+
* functions.
589
+
*/
590
+
ret = regmap_write(adp5585->regmap, regs->gen_cfg,
591
+
ADP5585_OSC_FREQ_500KHZ | ADP5585_INT_CFG | ADP5585_OSC_EN);
592
+
if (ret)
593
+
return ret;
594
+
595
+
return devm_add_action_or_reset(adp5585->dev, adp5585_osc_disable, adp5585);
596
+
}
597
+
598
+
static int adp5585_parse_fw(struct adp5585_dev *adp5585)
599
+
{
600
+
unsigned int prop_val;
601
+
int ret;
602
+
603
+
ret = device_property_read_u32(adp5585->dev, "poll-interval", &prop_val);
604
+
if (!ret) {
605
+
adp5585->ev_poll_time = prop_val / 10 - 1;
606
+
/*
607
+
* ev_poll_time is the raw value to be written on the register and 0 to 3 are the
608
+
* valid values.
609
+
*/
610
+
if (adp5585->ev_poll_time > 3)
611
+
return dev_err_probe(adp5585->dev, -EINVAL,
612
+
"Invalid value(%u) for poll-interval\n", prop_val);
613
+
}
614
+
615
+
ret = adp5585_unlock_ev_parse(adp5585);
616
+
if (ret)
617
+
return ret;
618
+
619
+
return adp5585_reset_ev_parse(adp5585);
620
+
}
621
+
622
+
static void adp5585_irq_disable(void *data)
623
+
{
624
+
struct adp5585_dev *adp5585 = data;
625
+
626
+
regmap_write(adp5585->regmap, adp5585->regs->int_en, 0);
627
+
}
628
+
629
+
static int adp5585_irq_enable(struct i2c_client *i2c,
630
+
struct adp5585_dev *adp5585)
631
+
{
632
+
const struct adp5585_regs *regs = adp5585->regs;
633
+
unsigned int stat;
634
+
int ret;
635
+
636
+
if (i2c->irq <= 0)
637
+
return 0;
638
+
639
+
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, adp5585_irq,
640
+
IRQF_ONESHOT, i2c->name, adp5585);
641
+
if (ret)
642
+
return ret;
643
+
644
+
/*
645
+
* Clear any possible outstanding interrupt before enabling them. We do that by reading
646
+
* the status register and writing back the same value.
647
+
*/
648
+
ret = regmap_read(adp5585->regmap, ADP5585_INT_STATUS, &stat);
649
+
if (ret)
650
+
return ret;
651
+
652
+
ret = regmap_write(adp5585->regmap, ADP5585_INT_STATUS, stat);
653
+
if (ret)
654
+
return ret;
655
+
656
+
ret = regmap_write(adp5585->regmap, regs->int_en, ADP5585_OVRFLOW_IEN | ADP5585_EVENT_IEN);
657
+
if (ret)
658
+
return ret;
659
+
660
+
return devm_add_action_or_reset(&i2c->dev, adp5585_irq_disable, adp5585);
661
+
}
139
662
140
663
static int adp5585_i2c_probe(struct i2c_client *i2c)
141
664
{
142
-
const struct regmap_config *regmap_config;
665
+
struct regmap_config *regmap_config;
143
666
struct adp5585_dev *adp5585;
667
+
struct gpio_desc *gpio;
144
668
unsigned int id;
145
669
int ret;
146
670
···
700
122
return -ENOMEM;
701
123
702
124
i2c_set_clientdata(i2c, adp5585);
125
+
adp5585->dev = &i2c->dev;
126
+
adp5585->irq = i2c->irq;
127
+
BLOCKING_INIT_NOTIFIER_HEAD(&adp5585->event_notifier);
703
128
704
-
regmap_config = i2c_get_match_data(i2c);
129
+
adp5585->variant = (enum adp5585_variant)(uintptr_t)i2c_get_match_data(i2c);
130
+
if (!adp5585->variant)
131
+
return -ENODEV;
132
+
133
+
regmap_config = adp5585_fill_variant_config(adp5585);
134
+
if (IS_ERR(regmap_config))
135
+
return PTR_ERR(regmap_config);
136
+
137
+
ret = devm_regulator_get_enable(&i2c->dev, "vdd");
138
+
if (ret)
139
+
return ret;
140
+
141
+
gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_HIGH);
142
+
if (IS_ERR(gpio))
143
+
return PTR_ERR(gpio);
144
+
145
+
/*
146
+
* Note the timings are not documented anywhere in the datasheet. They are just
147
+
* reasonable values that work.
148
+
*/
149
+
if (gpio) {
150
+
fsleep(30);
151
+
gpiod_set_value_cansleep(gpio, 0);
152
+
fsleep(60);
153
+
}
154
+
705
155
adp5585->regmap = devm_regmap_init_i2c(i2c, regmap_config);
706
156
if (IS_ERR(adp5585->regmap))
707
157
return dev_err_probe(&i2c->dev, PTR_ERR(adp5585->regmap),
···
740
134
return dev_err_probe(&i2c->dev, ret,
741
135
"Failed to read device ID\n");
742
136
743
-
if ((id & ADP5585_MAN_ID_MASK) != ADP5585_MAN_ID_VALUE)
137
+
id &= ADP5585_MAN_ID_MASK;
138
+
if (id != adp5585->id)
744
139
return dev_err_probe(&i2c->dev, -ENODEV,
745
140
"Invalid device ID 0x%02x\n", id);
746
141
747
-
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
748
-
adp5585_devs, ARRAY_SIZE(adp5585_devs),
749
-
NULL, 0, NULL);
750
-
if (ret)
751
-
return dev_err_probe(&i2c->dev, ret,
752
-
"Failed to add child devices\n");
142
+
adp5585->pin_usage = devm_bitmap_zalloc(&i2c->dev, adp5585->n_pins, GFP_KERNEL);
143
+
if (!adp5585->pin_usage)
144
+
return -ENOMEM;
753
145
754
-
return 0;
146
+
ret = adp5585_parse_fw(adp5585);
147
+
if (ret)
148
+
return ret;
149
+
150
+
ret = adp5585_setup(adp5585);
151
+
if (ret)
152
+
return ret;
153
+
154
+
ret = adp5585_add_devices(adp5585);
155
+
if (ret)
156
+
return ret;
157
+
158
+
return adp5585_irq_enable(i2c, adp5585);
755
159
}
756
160
757
161
static int adp5585_suspend(struct device *dev)
758
162
{
759
163
struct adp5585_dev *adp5585 = dev_get_drvdata(dev);
164
+
165
+
if (adp5585->irq)
166
+
disable_irq(adp5585->irq);
760
167
761
168
regcache_cache_only(adp5585->regmap, true);
762
169
···
779
160
static int adp5585_resume(struct device *dev)
780
161
{
781
162
struct adp5585_dev *adp5585 = dev_get_drvdata(dev);
163
+
int ret;
782
164
783
165
regcache_cache_only(adp5585->regmap, false);
784
166
regcache_mark_dirty(adp5585->regmap);
785
167
786
-
return regcache_sync(adp5585->regmap);
168
+
ret = regcache_sync(adp5585->regmap);
169
+
if (ret)
170
+
return ret;
171
+
172
+
if (adp5585->irq)
173
+
enable_irq(adp5585->irq);
174
+
175
+
return 0;
787
176
}
788
177
789
178
static DEFINE_SIMPLE_DEV_PM_OPS(adp5585_pm, adp5585_suspend, adp5585_resume);
···
799
172
static const struct of_device_id adp5585_of_match[] = {
800
173
{
801
174
.compatible = "adi,adp5585-00",
802
-
.data = &adp5585_regmap_configs[ADP5585_REGMAP_00],
175
+
.data = (void *)ADP5585_00,
803
176
}, {
804
177
.compatible = "adi,adp5585-01",
805
-
.data = &adp5585_regmap_configs[ADP5585_REGMAP_00],
178
+
.data = (void *)ADP5585_01,
806
179
}, {
807
180
.compatible = "adi,adp5585-02",
808
-
.data = &adp5585_regmap_configs[ADP5585_REGMAP_02],
181
+
.data = (void *)ADP5585_02,
809
182
}, {
810
183
.compatible = "adi,adp5585-03",
811
-
.data = &adp5585_regmap_configs[ADP5585_REGMAP_00],
184
+
.data = (void *)ADP5585_03,
812
185
}, {
813
186
.compatible = "adi,adp5585-04",
814
-
.data = &adp5585_regmap_configs[ADP5585_REGMAP_04],
187
+
.data = (void *)ADP5585_04,
188
+
}, {
189
+
.compatible = "adi,adp5589-00",
190
+
.data = (void *)ADP5589_00,
191
+
}, {
192
+
.compatible = "adi,adp5589-01",
193
+
.data = (void *)ADP5589_01,
194
+
}, {
195
+
.compatible = "adi,adp5589-02",
196
+
.data = (void *)ADP5589_02,
197
+
}, {
198
+
.compatible = "adi,adp5589",
199
+
.data = (void *)ADP5589_00,
815
200
},
816
201
{ /* sentinel */ }
817
202
};
+498
drivers/mfd/macsmc.c
+498
drivers/mfd/macsmc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only OR MIT
2
+
/*
3
+
* Apple SMC (System Management Controller) MFD driver
4
+
*
5
+
* Copyright The Asahi Linux Contributors
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/delay.h>
10
+
#include <linux/device.h>
11
+
#include <linux/io.h>
12
+
#include <linux/ioport.h>
13
+
#include <linux/math.h>
14
+
#include <linux/mfd/core.h>
15
+
#include <linux/mfd/macsmc.h>
16
+
#include <linux/notifier.h>
17
+
#include <linux/of.h>
18
+
#include <linux/of_platform.h>
19
+
#include <linux/overflow.h>
20
+
#include <linux/platform_device.h>
21
+
#include <linux/soc/apple/rtkit.h>
22
+
#include <linux/unaligned.h>
23
+
24
+
#define SMC_ENDPOINT 0x20
25
+
26
+
/* We don't actually know the true size here but this seem reasonable */
27
+
#define SMC_SHMEM_SIZE 0x1000
28
+
#define SMC_MAX_SIZE 255
29
+
30
+
#define SMC_MSG_READ_KEY 0x10
31
+
#define SMC_MSG_WRITE_KEY 0x11
32
+
#define SMC_MSG_GET_KEY_BY_INDEX 0x12
33
+
#define SMC_MSG_GET_KEY_INFO 0x13
34
+
#define SMC_MSG_INITIALIZE 0x17
35
+
#define SMC_MSG_NOTIFICATION 0x18
36
+
#define SMC_MSG_RW_KEY 0x20
37
+
38
+
#define SMC_DATA GENMASK_ULL(63, 32)
39
+
#define SMC_WSIZE GENMASK_ULL(31, 24)
40
+
#define SMC_SIZE GENMASK_ULL(23, 16)
41
+
#define SMC_ID GENMASK_ULL(15, 12)
42
+
#define SMC_MSG GENMASK_ULL(7, 0)
43
+
#define SMC_RESULT SMC_MSG
44
+
45
+
#define SMC_TIMEOUT_MS 500
46
+
47
+
static const struct mfd_cell apple_smc_devs[] = {
48
+
MFD_CELL_OF("macsmc-gpio", NULL, NULL, 0, 0, "apple,smc-gpio"),
49
+
MFD_CELL_OF("macsmc-reboot", NULL, NULL, 0, 0, "apple,smc-reboot"),
50
+
};
51
+
52
+
static int apple_smc_cmd_locked(struct apple_smc *smc, u64 cmd, u64 arg,
53
+
u64 size, u64 wsize, u32 *ret_data)
54
+
{
55
+
u8 result;
56
+
int ret;
57
+
u64 msg;
58
+
59
+
lockdep_assert_held(&smc->mutex);
60
+
61
+
if (smc->boot_stage != APPLE_SMC_INITIALIZED)
62
+
return -EIO;
63
+
if (smc->atomic_mode)
64
+
return -EIO;
65
+
66
+
reinit_completion(&smc->cmd_done);
67
+
68
+
smc->msg_id = (smc->msg_id + 1) & 0xf;
69
+
msg = (FIELD_PREP(SMC_MSG, cmd) |
70
+
FIELD_PREP(SMC_SIZE, size) |
71
+
FIELD_PREP(SMC_WSIZE, wsize) |
72
+
FIELD_PREP(SMC_ID, smc->msg_id) |
73
+
FIELD_PREP(SMC_DATA, arg));
74
+
75
+
ret = apple_rtkit_send_message(smc->rtk, SMC_ENDPOINT, msg, NULL, false);
76
+
if (ret) {
77
+
dev_err(smc->dev, "Failed to send command\n");
78
+
return ret;
79
+
}
80
+
81
+
if (wait_for_completion_timeout(&smc->cmd_done, msecs_to_jiffies(SMC_TIMEOUT_MS)) <= 0) {
82
+
dev_err(smc->dev, "Command timed out (%llx)", msg);
83
+
return -ETIMEDOUT;
84
+
}
85
+
86
+
if (FIELD_GET(SMC_ID, smc->cmd_ret) != smc->msg_id) {
87
+
dev_err(smc->dev, "Command sequence mismatch (expected %d, got %d)\n",
88
+
smc->msg_id, (unsigned int)FIELD_GET(SMC_ID, smc->cmd_ret));
89
+
return -EIO;
90
+
}
91
+
92
+
result = FIELD_GET(SMC_RESULT, smc->cmd_ret);
93
+
if (result)
94
+
return -EIO;
95
+
96
+
if (ret_data)
97
+
*ret_data = FIELD_GET(SMC_DATA, smc->cmd_ret);
98
+
99
+
return FIELD_GET(SMC_SIZE, smc->cmd_ret);
100
+
}
101
+
102
+
static int apple_smc_cmd(struct apple_smc *smc, u64 cmd, u64 arg,
103
+
u64 size, u64 wsize, u32 *ret_data)
104
+
{
105
+
guard(mutex)(&smc->mutex);
106
+
107
+
return apple_smc_cmd_locked(smc, cmd, arg, size, wsize, ret_data);
108
+
}
109
+
110
+
static int apple_smc_rw_locked(struct apple_smc *smc, smc_key key,
111
+
const void *wbuf, size_t wsize,
112
+
void *rbuf, size_t rsize)
113
+
{
114
+
u64 smc_size, smc_wsize;
115
+
u32 rdata;
116
+
int ret;
117
+
u64 cmd;
118
+
119
+
lockdep_assert_held(&smc->mutex);
120
+
121
+
if (rsize > SMC_MAX_SIZE)
122
+
return -EINVAL;
123
+
if (wsize > SMC_MAX_SIZE)
124
+
return -EINVAL;
125
+
126
+
if (rsize && wsize) {
127
+
cmd = SMC_MSG_RW_KEY;
128
+
memcpy_toio(smc->shmem.iomem, wbuf, wsize);
129
+
smc_size = rsize;
130
+
smc_wsize = wsize;
131
+
} else if (wsize && !rsize) {
132
+
cmd = SMC_MSG_WRITE_KEY;
133
+
memcpy_toio(smc->shmem.iomem, wbuf, wsize);
134
+
/*
135
+
* Setting size to the length we want to write and wsize to 0
136
+
* looks silly but that's how the SMC protocol works ¯\_(ツ)_/¯
137
+
*/
138
+
smc_size = wsize;
139
+
smc_wsize = 0;
140
+
} else if (!wsize && rsize) {
141
+
cmd = SMC_MSG_READ_KEY;
142
+
smc_size = rsize;
143
+
smc_wsize = 0;
144
+
} else {
145
+
return -EINVAL;
146
+
}
147
+
148
+
ret = apple_smc_cmd_locked(smc, cmd, key, smc_size, smc_wsize, &rdata);
149
+
if (ret < 0)
150
+
return ret;
151
+
152
+
if (rsize) {
153
+
/*
154
+
* Small data <= 4 bytes is returned as part of the reply
155
+
* message which is sent over the mailbox FIFO. Everything
156
+
* bigger has to be copied from SRAM which is mapped as
157
+
* Device memory.
158
+
*/
159
+
if (rsize <= 4)
160
+
memcpy(rbuf, &rdata, rsize);
161
+
else
162
+
memcpy_fromio(rbuf, smc->shmem.iomem, rsize);
163
+
}
164
+
165
+
return ret;
166
+
}
167
+
168
+
int apple_smc_read(struct apple_smc *smc, smc_key key, void *buf, size_t size)
169
+
{
170
+
guard(mutex)(&smc->mutex);
171
+
172
+
return apple_smc_rw_locked(smc, key, NULL, 0, buf, size);
173
+
}
174
+
EXPORT_SYMBOL(apple_smc_read);
175
+
176
+
int apple_smc_write(struct apple_smc *smc, smc_key key, void *buf, size_t size)
177
+
{
178
+
guard(mutex)(&smc->mutex);
179
+
180
+
return apple_smc_rw_locked(smc, key, buf, size, NULL, 0);
181
+
}
182
+
EXPORT_SYMBOL(apple_smc_write);
183
+
184
+
int apple_smc_rw(struct apple_smc *smc, smc_key key, void *wbuf, size_t wsize,
185
+
void *rbuf, size_t rsize)
186
+
{
187
+
guard(mutex)(&smc->mutex);
188
+
189
+
return apple_smc_rw_locked(smc, key, wbuf, wsize, rbuf, rsize);
190
+
}
191
+
EXPORT_SYMBOL(apple_smc_rw);
192
+
193
+
int apple_smc_get_key_by_index(struct apple_smc *smc, int index, smc_key *key)
194
+
{
195
+
int ret;
196
+
197
+
ret = apple_smc_cmd(smc, SMC_MSG_GET_KEY_BY_INDEX, index, 0, 0, key);
198
+
199
+
*key = swab32(*key);
200
+
return ret;
201
+
}
202
+
EXPORT_SYMBOL(apple_smc_get_key_by_index);
203
+
204
+
int apple_smc_get_key_info(struct apple_smc *smc, smc_key key, struct apple_smc_key_info *info)
205
+
{
206
+
u8 key_info[6];
207
+
int ret;
208
+
209
+
ret = apple_smc_cmd(smc, SMC_MSG_GET_KEY_INFO, key, 0, 0, NULL);
210
+
if (ret >= 0 && info) {
211
+
memcpy_fromio(key_info, smc->shmem.iomem, sizeof(key_info));
212
+
info->size = key_info[0];
213
+
info->type_code = get_unaligned_be32(&key_info[1]);
214
+
info->flags = key_info[5];
215
+
}
216
+
return ret;
217
+
}
218
+
EXPORT_SYMBOL(apple_smc_get_key_info);
219
+
220
+
int apple_smc_enter_atomic(struct apple_smc *smc)
221
+
{
222
+
guard(mutex)(&smc->mutex);
223
+
224
+
/*
225
+
* Disable notifications since this is called before shutdown and no
226
+
* notification handler will be able to handle the notification
227
+
* using atomic operations only. Also ignore any failure here
228
+
* because we're about to shut down or reboot anyway.
229
+
* We can't use apple_smc_write_flag here since that would try to lock
230
+
* smc->mutex again.
231
+
*/
232
+
const u8 flag = 0;
233
+
234
+
apple_smc_rw_locked(smc, SMC_KEY(NTAP), &flag, sizeof(flag), NULL, 0);
235
+
236
+
smc->atomic_mode = true;
237
+
238
+
return 0;
239
+
}
240
+
EXPORT_SYMBOL(apple_smc_enter_atomic);
241
+
242
+
int apple_smc_write_atomic(struct apple_smc *smc, smc_key key, void *buf, size_t size)
243
+
{
244
+
guard(spinlock_irqsave)(&smc->lock);
245
+
u8 result;
246
+
int ret;
247
+
u64 msg;
248
+
249
+
if (size > SMC_MAX_SIZE || size == 0)
250
+
return -EINVAL;
251
+
252
+
if (smc->boot_stage != APPLE_SMC_INITIALIZED)
253
+
return -EIO;
254
+
if (!smc->atomic_mode)
255
+
return -EIO;
256
+
257
+
memcpy_toio(smc->shmem.iomem, buf, size);
258
+
smc->msg_id = (smc->msg_id + 1) & 0xf;
259
+
msg = (FIELD_PREP(SMC_MSG, SMC_MSG_WRITE_KEY) |
260
+
FIELD_PREP(SMC_SIZE, size) |
261
+
FIELD_PREP(SMC_ID, smc->msg_id) |
262
+
FIELD_PREP(SMC_DATA, key));
263
+
smc->atomic_pending = true;
264
+
265
+
ret = apple_rtkit_send_message(smc->rtk, SMC_ENDPOINT, msg, NULL, true);
266
+
if (ret < 0) {
267
+
dev_err(smc->dev, "Failed to send command (%d)\n", ret);
268
+
return ret;
269
+
}
270
+
271
+
while (smc->atomic_pending) {
272
+
ret = apple_rtkit_poll(smc->rtk);
273
+
if (ret < 0) {
274
+
dev_err(smc->dev, "RTKit poll failed (%llx)", msg);
275
+
return ret;
276
+
}
277
+
udelay(100);
278
+
}
279
+
280
+
if (FIELD_GET(SMC_ID, smc->cmd_ret) != smc->msg_id) {
281
+
dev_err(smc->dev, "Command sequence mismatch (expected %d, got %d)\n",
282
+
smc->msg_id, (unsigned int)FIELD_GET(SMC_ID, smc->cmd_ret));
283
+
return -EIO;
284
+
}
285
+
286
+
result = FIELD_GET(SMC_RESULT, smc->cmd_ret);
287
+
if (result)
288
+
return -EIO;
289
+
290
+
return FIELD_GET(SMC_SIZE, smc->cmd_ret);
291
+
}
292
+
EXPORT_SYMBOL(apple_smc_write_atomic);
293
+
294
+
static void apple_smc_rtkit_crashed(void *cookie, const void *bfr, size_t bfr_len)
295
+
{
296
+
struct apple_smc *smc = cookie;
297
+
298
+
smc->boot_stage = APPLE_SMC_ERROR_CRASHED;
299
+
dev_err(smc->dev, "SMC crashed! Your system will reboot in a few seconds...\n");
300
+
}
301
+
302
+
static int apple_smc_rtkit_shmem_setup(void *cookie, struct apple_rtkit_shmem *bfr)
303
+
{
304
+
struct apple_smc *smc = cookie;
305
+
size_t bfr_end;
306
+
307
+
if (!bfr->iova) {
308
+
dev_err(smc->dev, "RTKit wants a RAM buffer\n");
309
+
return -EIO;
310
+
}
311
+
312
+
if (check_add_overflow(bfr->iova, bfr->size - 1, &bfr_end))
313
+
return -EFAULT;
314
+
315
+
if (bfr->iova < smc->sram->start || bfr->iova > smc->sram->end ||
316
+
bfr_end > smc->sram->end) {
317
+
dev_err(smc->dev, "RTKit buffer request outside SRAM region: [0x%llx, 0x%llx]\n",
318
+
(unsigned long long)bfr->iova,
319
+
(unsigned long long)bfr_end);
320
+
return -EFAULT;
321
+
}
322
+
323
+
bfr->iomem = smc->sram_base + (bfr->iova - smc->sram->start);
324
+
bfr->is_mapped = true;
325
+
326
+
return 0;
327
+
}
328
+
329
+
static bool apple_smc_rtkit_recv_early(void *cookie, u8 endpoint, u64 message)
330
+
{
331
+
struct apple_smc *smc = cookie;
332
+
333
+
if (endpoint != SMC_ENDPOINT) {
334
+
dev_warn(smc->dev, "Received message for unknown endpoint 0x%x\n", endpoint);
335
+
return false;
336
+
}
337
+
338
+
if (smc->boot_stage == APPLE_SMC_BOOTING) {
339
+
int ret;
340
+
341
+
smc->shmem.iova = message;
342
+
smc->shmem.size = SMC_SHMEM_SIZE;
343
+
ret = apple_smc_rtkit_shmem_setup(smc, &smc->shmem);
344
+
if (ret < 0) {
345
+
smc->boot_stage = APPLE_SMC_ERROR_NO_SHMEM;
346
+
dev_err(smc->dev, "Failed to initialize shared memory (%d)\n", ret);
347
+
} else {
348
+
smc->boot_stage = APPLE_SMC_INITIALIZED;
349
+
}
350
+
complete(&smc->init_done);
351
+
} else if (FIELD_GET(SMC_MSG, message) == SMC_MSG_NOTIFICATION) {
352
+
/* Handle these in the RTKit worker thread */
353
+
return false;
354
+
} else {
355
+
smc->cmd_ret = message;
356
+
if (smc->atomic_pending)
357
+
smc->atomic_pending = false;
358
+
else
359
+
complete(&smc->cmd_done);
360
+
}
361
+
362
+
return true;
363
+
}
364
+
365
+
static void apple_smc_rtkit_recv(void *cookie, u8 endpoint, u64 message)
366
+
{
367
+
struct apple_smc *smc = cookie;
368
+
369
+
if (endpoint != SMC_ENDPOINT) {
370
+
dev_warn(smc->dev, "Received message for unknown endpoint 0x%x\n", endpoint);
371
+
return;
372
+
}
373
+
374
+
if (FIELD_GET(SMC_MSG, message) != SMC_MSG_NOTIFICATION) {
375
+
dev_warn(smc->dev, "Received unknown message from worker: 0x%llx\n", message);
376
+
return;
377
+
}
378
+
379
+
blocking_notifier_call_chain(&smc->event_handlers, FIELD_GET(SMC_DATA, message), NULL);
380
+
}
381
+
382
+
static const struct apple_rtkit_ops apple_smc_rtkit_ops = {
383
+
.crashed = apple_smc_rtkit_crashed,
384
+
.recv_message = apple_smc_rtkit_recv,
385
+
.recv_message_early = apple_smc_rtkit_recv_early,
386
+
.shmem_setup = apple_smc_rtkit_shmem_setup,
387
+
};
388
+
389
+
static void apple_smc_rtkit_shutdown(void *data)
390
+
{
391
+
struct apple_smc *smc = data;
392
+
393
+
/* Shut down SMC firmware, if it's not completely wedged */
394
+
if (apple_rtkit_is_running(smc->rtk))
395
+
apple_rtkit_quiesce(smc->rtk);
396
+
}
397
+
398
+
static void apple_smc_disable_notifications(void *data)
399
+
{
400
+
struct apple_smc *smc = data;
401
+
402
+
apple_smc_write_flag(smc, SMC_KEY(NTAP), false);
403
+
}
404
+
405
+
static int apple_smc_probe(struct platform_device *pdev)
406
+
{
407
+
struct device *dev = &pdev->dev;
408
+
struct apple_smc *smc;
409
+
u32 count;
410
+
int ret;
411
+
412
+
smc = devm_kzalloc(dev, sizeof(*smc), GFP_KERNEL);
413
+
if (!smc)
414
+
return -ENOMEM;
415
+
416
+
smc->dev = &pdev->dev;
417
+
smc->sram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &smc->sram);
418
+
if (IS_ERR(smc->sram_base))
419
+
return dev_err_probe(dev, PTR_ERR(smc->sram_base), "Failed to map SRAM region");
420
+
421
+
smc->rtk = devm_apple_rtkit_init(dev, smc, NULL, 0, &apple_smc_rtkit_ops);
422
+
if (IS_ERR(smc->rtk))
423
+
return dev_err_probe(dev, PTR_ERR(smc->rtk), "Failed to initialize RTKit");
424
+
425
+
smc->boot_stage = APPLE_SMC_BOOTING;
426
+
ret = apple_rtkit_wake(smc->rtk);
427
+
if (ret)
428
+
return dev_err_probe(dev, ret, "Failed to wake up SMC");
429
+
430
+
ret = devm_add_action_or_reset(dev, apple_smc_rtkit_shutdown, smc);
431
+
if (ret)
432
+
return dev_err_probe(dev, ret, "Failed to register rtkit shutdown action");
433
+
434
+
ret = apple_rtkit_start_ep(smc->rtk, SMC_ENDPOINT);
435
+
if (ret)
436
+
return dev_err_probe(dev, ret, "Failed to start SMC endpoint");
437
+
438
+
init_completion(&smc->init_done);
439
+
init_completion(&smc->cmd_done);
440
+
441
+
ret = apple_rtkit_send_message(smc->rtk, SMC_ENDPOINT,
442
+
FIELD_PREP(SMC_MSG, SMC_MSG_INITIALIZE), NULL, false);
443
+
if (ret)
444
+
return dev_err_probe(dev, ret, "Failed to send init message");
445
+
446
+
if (wait_for_completion_timeout(&smc->init_done, msecs_to_jiffies(SMC_TIMEOUT_MS)) == 0) {
447
+
dev_err(dev, "Timed out initializing SMC");
448
+
return -ETIMEDOUT;
449
+
}
450
+
451
+
if (smc->boot_stage != APPLE_SMC_INITIALIZED) {
452
+
dev_err(dev, "SMC failed to boot successfully, boot stage=%d\n", smc->boot_stage);
453
+
return -EIO;
454
+
}
455
+
456
+
dev_set_drvdata(&pdev->dev, smc);
457
+
BLOCKING_INIT_NOTIFIER_HEAD(&smc->event_handlers);
458
+
459
+
ret = apple_smc_read_u32(smc, SMC_KEY(#KEY), &count);
460
+
if (ret)
461
+
return dev_err_probe(smc->dev, ret, "Failed to get key count");
462
+
smc->key_count = be32_to_cpu(count);
463
+
464
+
/* Enable notifications */
465
+
apple_smc_write_flag(smc, SMC_KEY(NTAP), true);
466
+
ret = devm_add_action_or_reset(dev, apple_smc_disable_notifications, smc);
467
+
if (ret)
468
+
return dev_err_probe(dev, ret, "Failed to register notification disable action");
469
+
470
+
ret = devm_mfd_add_devices(smc->dev, PLATFORM_DEVID_NONE,
471
+
apple_smc_devs, ARRAY_SIZE(apple_smc_devs),
472
+
NULL, 0, NULL);
473
+
if (ret)
474
+
return dev_err_probe(smc->dev, ret, "Failed to register sub-devices");
475
+
476
+
477
+
return 0;
478
+
}
479
+
480
+
static const struct of_device_id apple_smc_of_match[] = {
481
+
{ .compatible = "apple,smc" },
482
+
{},
483
+
};
484
+
MODULE_DEVICE_TABLE(of, apple_smc_of_match);
485
+
486
+
static struct platform_driver apple_smc_driver = {
487
+
.driver = {
488
+
.name = "macsmc",
489
+
.of_match_table = apple_smc_of_match,
490
+
},
491
+
.probe = apple_smc_probe,
492
+
};
493
+
module_platform_driver(apple_smc_driver);
494
+
495
+
MODULE_AUTHOR("Hector Martin <marcan@marcan.st>");
496
+
MODULE_AUTHOR("Sven Peter <sven@kernel.org>");
497
+
MODULE_LICENSE("Dual MIT/GPL");
498
+
MODULE_DESCRIPTION("Apple SMC driver");
+28
-18
drivers/mfd/vexpress-sysreg.c
+28
-18
drivers/mfd/vexpress-sysreg.c
···
11
11
#include <linux/module.h>
12
12
#include <linux/of_platform.h>
13
13
#include <linux/platform_device.h>
14
+
#include <linux/property.h>
14
15
#include <linux/slab.h>
15
16
#include <linux/stat.h>
16
17
···
38
37
39
38
/* The sysreg block is just a random collection of various functions... */
40
39
41
-
static struct bgpio_pdata vexpress_sysreg_sys_led_pdata = {
42
-
.label = "sys_led",
43
-
.base = -1,
44
-
.ngpio = 8,
40
+
static const struct property_entry vexpress_sysreg_sys_led_props[] = {
41
+
PROPERTY_ENTRY_STRING("label", "sys_led"),
42
+
PROPERTY_ENTRY_U32("ngpios", 8),
43
+
{ }
45
44
};
46
45
47
-
static struct bgpio_pdata vexpress_sysreg_sys_mci_pdata = {
48
-
.label = "sys_mci",
49
-
.base = -1,
50
-
.ngpio = 2,
46
+
static const struct software_node vexpress_sysreg_sys_led_swnode = {
47
+
.properties = vexpress_sysreg_sys_led_props,
51
48
};
52
49
53
-
static struct bgpio_pdata vexpress_sysreg_sys_flash_pdata = {
54
-
.label = "sys_flash",
55
-
.base = -1,
56
-
.ngpio = 1,
50
+
static const struct property_entry vexpress_sysreg_sys_mci_props[] = {
51
+
PROPERTY_ENTRY_STRING("label", "sys_mci"),
52
+
PROPERTY_ENTRY_U32("ngpios", 2),
53
+
{ }
54
+
};
55
+
56
+
static const struct software_node vexpress_sysreg_sys_mci_swnode = {
57
+
.properties = vexpress_sysreg_sys_mci_props,
58
+
};
59
+
60
+
static const struct property_entry vexpress_sysreg_sys_flash_props[] = {
61
+
PROPERTY_ENTRY_STRING("label", "sys_flash"),
62
+
PROPERTY_ENTRY_U32("ngpios", 1),
63
+
{ }
64
+
};
65
+
66
+
static const struct software_node vexpress_sysreg_sys_flash_swnode = {
67
+
.properties = vexpress_sysreg_sys_flash_props,
57
68
};
58
69
59
70
static struct mfd_cell vexpress_sysreg_cells[] = {
···
74
61
.of_compatible = "arm,vexpress-sysreg,sys_led",
75
62
.num_resources = 1,
76
63
.resources = &DEFINE_RES_MEM_NAMED(SYS_LED, 0x4, "dat"),
77
-
.platform_data = &vexpress_sysreg_sys_led_pdata,
78
-
.pdata_size = sizeof(vexpress_sysreg_sys_led_pdata),
64
+
.swnode = &vexpress_sysreg_sys_led_swnode,
79
65
}, {
80
66
.name = "basic-mmio-gpio",
81
67
.of_compatible = "arm,vexpress-sysreg,sys_mci",
82
68
.num_resources = 1,
83
69
.resources = &DEFINE_RES_MEM_NAMED(SYS_MCI, 0x4, "dat"),
84
-
.platform_data = &vexpress_sysreg_sys_mci_pdata,
85
-
.pdata_size = sizeof(vexpress_sysreg_sys_mci_pdata),
70
+
.swnode = &vexpress_sysreg_sys_mci_swnode,
86
71
}, {
87
72
.name = "basic-mmio-gpio",
88
73
.of_compatible = "arm,vexpress-sysreg,sys_flash",
89
74
.num_resources = 1,
90
75
.resources = &DEFINE_RES_MEM_NAMED(SYS_FLASH, 0x4, "dat"),
91
-
.platform_data = &vexpress_sysreg_sys_flash_pdata,
92
-
.pdata_size = sizeof(vexpress_sysreg_sys_flash_pdata),
76
+
.swnode = &vexpress_sysreg_sys_flash_swnode,
93
77
}, {
94
78
.name = "vexpress-syscfg",
95
79
.num_resources = 1,
+5
-8
drivers/misc/ti_fpc202.c
+5
-8
drivers/misc/ti_fpc202.c
···
118
118
gpiod_set_value(priv->en_gpio, enable);
119
119
}
120
120
121
-
static void fpc202_gpio_set(struct gpio_chip *chip, unsigned int offset,
122
-
int value)
121
+
static int fpc202_gpio_set(struct gpio_chip *chip, unsigned int offset,
122
+
int value)
123
123
{
124
124
struct fpc202_priv *priv = gpiochip_get_data(chip);
125
125
int ret;
126
126
u8 val;
127
127
128
-
if (fpc202_gpio_get_dir(offset) == GPIO_LINE_DIRECTION_IN)
129
-
return;
130
-
131
128
ret = fpc202_read(priv, FPC202_REG_OUT_A_OUT_B_VAL);
132
129
if (ret < 0) {
133
130
dev_err(&priv->client->dev, "Failed to set GPIO %d value! err %d\n", offset, ret);
134
-
return;
131
+
return ret;
135
132
}
136
133
137
134
val = (u8)ret;
···
138
141
else
139
142
val &= ~BIT(offset - FPC202_GPIO_P0_S0_OUT_A);
140
143
141
-
fpc202_write(priv, FPC202_REG_OUT_A_OUT_B_VAL, val);
144
+
return fpc202_write(priv, FPC202_REG_OUT_A_OUT_B_VAL, val);
142
145
}
143
146
144
147
static int fpc202_gpio_get(struct gpio_chip *chip, unsigned int offset)
···
333
336
priv->gpio.base = -1;
334
337
priv->gpio.direction_input = fpc202_gpio_direction_input;
335
338
priv->gpio.direction_output = fpc202_gpio_direction_output;
336
-
priv->gpio.set = fpc202_gpio_set;
339
+
priv->gpio.set_rv = fpc202_gpio_set;
337
340
priv->gpio.get = fpc202_gpio_get;
338
341
priv->gpio.ngpio = FPC202_GPIO_COUNT;
339
342
priv->gpio.parent = dev;
+22
-13
drivers/platform/cznic/turris-omnia-mcu-gpio.c
+22
-13
drivers/platform/cznic/turris-omnia-mcu-gpio.c
···
439
439
return 0;
440
440
}
441
441
442
-
static void omnia_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
442
+
static int omnia_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
443
443
{
444
444
const struct omnia_gpio *gpio = &omnia_gpios[offset];
445
445
struct omnia_mcu *mcu = gpiochip_get_data(gc);
446
446
u16 val, mask;
447
447
448
448
if (!gpio->ctl_cmd)
449
-
return;
449
+
return -EINVAL;
450
450
451
451
mask = BIT(gpio->ctl_bit);
452
452
val = value ? mask : 0;
453
453
454
-
omnia_ctl_cmd(mcu, gpio->ctl_cmd, val, mask);
454
+
return omnia_ctl_cmd(mcu, gpio->ctl_cmd, val, mask);
455
455
}
456
456
457
-
static void omnia_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
458
-
unsigned long *bits)
457
+
static int omnia_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
458
+
unsigned long *bits)
459
459
{
460
460
unsigned long ctl = 0, ctl_mask = 0, ext_ctl = 0, ext_ctl_mask = 0;
461
461
struct omnia_mcu *mcu = gpiochip_get_data(gc);
462
462
unsigned int i;
463
+
int err;
463
464
464
465
for_each_set_bit(i, mask, ARRAY_SIZE(omnia_gpios)) {
465
466
unsigned long *field, *field_mask;
···
489
488
490
489
guard(mutex)(&mcu->lock);
491
490
492
-
if (ctl_mask)
493
-
omnia_ctl_cmd_locked(mcu, OMNIA_CMD_GENERAL_CONTROL,
494
-
ctl, ctl_mask);
491
+
if (ctl_mask) {
492
+
err = omnia_ctl_cmd_locked(mcu, OMNIA_CMD_GENERAL_CONTROL,
493
+
ctl, ctl_mask);
494
+
if (err)
495
+
return err;
496
+
}
495
497
496
-
if (ext_ctl_mask)
497
-
omnia_ctl_cmd_locked(mcu, OMNIA_CMD_EXT_CONTROL,
498
-
ext_ctl, ext_ctl_mask);
498
+
if (ext_ctl_mask) {
499
+
err = omnia_ctl_cmd_locked(mcu, OMNIA_CMD_EXT_CONTROL,
500
+
ext_ctl, ext_ctl_mask);
501
+
if (err)
502
+
return err;
503
+
}
504
+
505
+
return 0;
499
506
}
500
507
501
508
static bool omnia_gpio_available(struct omnia_mcu *mcu,
···
1024
1015
mcu->gc.direction_output = omnia_gpio_direction_output;
1025
1016
mcu->gc.get = omnia_gpio_get;
1026
1017
mcu->gc.get_multiple = omnia_gpio_get_multiple;
1027
-
mcu->gc.set = omnia_gpio_set;
1028
-
mcu->gc.set_multiple = omnia_gpio_set_multiple;
1018
+
mcu->gc.set_rv = omnia_gpio_set;
1019
+
mcu->gc.set_multiple_rv = omnia_gpio_set_multiple;
1029
1020
mcu->gc.init_valid_mask = omnia_gpio_init_valid_mask;
1030
1021
mcu->gc.can_sleep = true;
1031
1022
mcu->gc.names = omnia_mcu_gpio_names;
+9
drivers/power/reset/Kconfig
+9
drivers/power/reset/Kconfig
···
128
128
129
129
Say Y here if you have a Buffalo LinkStation LS421D/E.
130
130
131
+
config POWER_RESET_MACSMC
132
+
tristate "Apple SMC reset/power-off driver"
133
+
depends on MFD_MACSMC
134
+
help
135
+
This driver supports reset and power-off on Apple Mac machines
136
+
that implement this functionality via the SMC.
137
+
138
+
Say Y here if you have an Apple Silicon Mac.
139
+
131
140
config POWER_RESET_MSM
132
141
bool "Qualcomm MSM power-off driver"
133
142
depends on ARCH_QCOM
+1
drivers/power/reset/Makefile
+1
drivers/power/reset/Makefile
···
13
13
obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o
14
14
obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
15
15
obj-$(CONFIG_POWER_RESET_LINKSTATION) += linkstation-poweroff.o
16
+
obj-$(CONFIG_POWER_RESET_MACSMC) += macsmc-reboot.o
16
17
obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
17
18
obj-$(CONFIG_POWER_RESET_MT6323) += mt6323-poweroff.o
18
19
obj-$(CONFIG_POWER_RESET_QCOM_PON) += qcom-pon.o
+290
drivers/power/reset/macsmc-reboot.c
+290
drivers/power/reset/macsmc-reboot.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only OR MIT
2
+
/*
3
+
* Apple SMC Reboot/Poweroff Handler
4
+
* Copyright The Asahi Linux Contributors
5
+
*/
6
+
7
+
#include <linux/delay.h>
8
+
#include <linux/mfd/core.h>
9
+
#include <linux/mfd/macsmc.h>
10
+
#include <linux/mod_devicetable.h>
11
+
#include <linux/module.h>
12
+
#include <linux/nvmem-consumer.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/reboot.h>
15
+
#include <linux/slab.h>
16
+
17
+
struct macsmc_reboot_nvmem {
18
+
struct nvmem_cell *shutdown_flag;
19
+
struct nvmem_cell *boot_stage;
20
+
struct nvmem_cell *boot_error_count;
21
+
struct nvmem_cell *panic_count;
22
+
};
23
+
24
+
static const char * const nvmem_names[] = {
25
+
"shutdown_flag",
26
+
"boot_stage",
27
+
"boot_error_count",
28
+
"panic_count",
29
+
};
30
+
31
+
enum boot_stage {
32
+
BOOT_STAGE_SHUTDOWN = 0x00, /* Clean shutdown */
33
+
BOOT_STAGE_IBOOT_DONE = 0x2f, /* Last stage of bootloader */
34
+
BOOT_STAGE_KERNEL_STARTED = 0x30, /* Normal OS booting */
35
+
};
36
+
37
+
struct macsmc_reboot {
38
+
struct device *dev;
39
+
struct apple_smc *smc;
40
+
struct notifier_block reboot_notify;
41
+
42
+
union {
43
+
struct macsmc_reboot_nvmem nvm;
44
+
struct nvmem_cell *nvm_cells[ARRAY_SIZE(nvmem_names)];
45
+
};
46
+
};
47
+
48
+
/* Helpers to read/write a u8 given a struct nvmem_cell */
49
+
static int nvmem_cell_get_u8(struct nvmem_cell *cell)
50
+
{
51
+
size_t len;
52
+
void *bfr;
53
+
u8 val;
54
+
55
+
bfr = nvmem_cell_read(cell, &len);
56
+
if (IS_ERR(bfr))
57
+
return PTR_ERR(bfr);
58
+
59
+
if (len < 1) {
60
+
kfree(bfr);
61
+
return -EINVAL;
62
+
}
63
+
64
+
val = *(u8 *)bfr;
65
+
kfree(bfr);
66
+
return val;
67
+
}
68
+
69
+
static int nvmem_cell_set_u8(struct nvmem_cell *cell, u8 val)
70
+
{
71
+
return nvmem_cell_write(cell, &val, sizeof(val));
72
+
}
73
+
74
+
/*
75
+
* SMC 'MBSE' key actions:
76
+
*
77
+
* 'offw' - shutdown warning
78
+
* 'slpw' - sleep warning
79
+
* 'rest' - restart warning
80
+
* 'off1' - shutdown (needs PMU bit set to stay on)
81
+
* 'susp' - suspend
82
+
* 'phra' - restart ("PE Halt Restart Action"?)
83
+
* 'panb' - panic beginning
84
+
* 'pane' - panic end
85
+
*/
86
+
87
+
static int macsmc_prepare_atomic(struct sys_off_data *data)
88
+
{
89
+
struct macsmc_reboot *reboot = data->cb_data;
90
+
91
+
dev_info(reboot->dev, "Preparing SMC for atomic mode\n");
92
+
93
+
apple_smc_enter_atomic(reboot->smc);
94
+
return NOTIFY_OK;
95
+
}
96
+
97
+
static int macsmc_power_off(struct sys_off_data *data)
98
+
{
99
+
struct macsmc_reboot *reboot = data->cb_data;
100
+
101
+
dev_info(reboot->dev, "Issuing power off (off1)\n");
102
+
103
+
if (apple_smc_write_u32_atomic(reboot->smc, SMC_KEY(MBSE), SMC_KEY(off1)) < 0) {
104
+
dev_err(reboot->dev, "Failed to issue MBSE = off1 (power_off)\n");
105
+
} else {
106
+
mdelay(100);
107
+
WARN_ONCE(1, "Unable to power off system\n");
108
+
}
109
+
110
+
return NOTIFY_OK;
111
+
}
112
+
113
+
static int macsmc_restart(struct sys_off_data *data)
114
+
{
115
+
struct macsmc_reboot *reboot = data->cb_data;
116
+
117
+
dev_info(reboot->dev, "Issuing restart (phra)\n");
118
+
119
+
if (apple_smc_write_u32_atomic(reboot->smc, SMC_KEY(MBSE), SMC_KEY(phra)) < 0) {
120
+
dev_err(reboot->dev, "Failed to issue MBSE = phra (restart)\n");
121
+
} else {
122
+
mdelay(100);
123
+
WARN_ONCE(1, "Unable to restart system\n");
124
+
}
125
+
126
+
return NOTIFY_OK;
127
+
}
128
+
129
+
static int macsmc_reboot_notify(struct notifier_block *this, unsigned long action, void *data)
130
+
{
131
+
struct macsmc_reboot *reboot = container_of(this, struct macsmc_reboot, reboot_notify);
132
+
u8 shutdown_flag;
133
+
u32 val;
134
+
135
+
switch (action) {
136
+
case SYS_RESTART:
137
+
val = SMC_KEY(rest);
138
+
shutdown_flag = 0;
139
+
break;
140
+
case SYS_POWER_OFF:
141
+
val = SMC_KEY(offw);
142
+
shutdown_flag = 1;
143
+
break;
144
+
default:
145
+
return NOTIFY_DONE;
146
+
}
147
+
148
+
dev_info(reboot->dev, "Preparing for reboot (%p4ch)\n", &val);
149
+
150
+
/* On the Mac Mini, this will turn off the LED for power off */
151
+
if (apple_smc_write_u32(reboot->smc, SMC_KEY(MBSE), val) < 0)
152
+
dev_err(reboot->dev, "Failed to issue MBSE = %p4ch (reboot_prepare)\n", &val);
153
+
154
+
/* Set the boot_stage to 0, which means we're doing a clean shutdown/reboot. */
155
+
if (reboot->nvm.boot_stage &&
156
+
nvmem_cell_set_u8(reboot->nvm.boot_stage, BOOT_STAGE_SHUTDOWN) < 0)
157
+
dev_err(reboot->dev, "Failed to write boot_stage\n");
158
+
159
+
/*
160
+
* Set the PMU flag to actually reboot into the off state.
161
+
* Without this, the device will just reboot. We make it optional in case it is no longer
162
+
* necessary on newer hardware.
163
+
*/
164
+
if (reboot->nvm.shutdown_flag &&
165
+
nvmem_cell_set_u8(reboot->nvm.shutdown_flag, shutdown_flag) < 0)
166
+
dev_err(reboot->dev, "Failed to write shutdown_flag\n");
167
+
168
+
return NOTIFY_OK;
169
+
}
170
+
171
+
static void macsmc_power_init_error_counts(struct macsmc_reboot *reboot)
172
+
{
173
+
int boot_error_count, panic_count;
174
+
175
+
if (!reboot->nvm.boot_error_count || !reboot->nvm.panic_count)
176
+
return;
177
+
178
+
boot_error_count = nvmem_cell_get_u8(reboot->nvm.boot_error_count);
179
+
if (boot_error_count < 0) {
180
+
dev_err(reboot->dev, "Failed to read boot_error_count (%d)\n", boot_error_count);
181
+
return;
182
+
}
183
+
184
+
panic_count = nvmem_cell_get_u8(reboot->nvm.panic_count);
185
+
if (panic_count < 0) {
186
+
dev_err(reboot->dev, "Failed to read panic_count (%d)\n", panic_count);
187
+
return;
188
+
}
189
+
190
+
if (!boot_error_count && !panic_count)
191
+
return;
192
+
193
+
dev_warn(reboot->dev, "PMU logged %d boot error(s) and %d panic(s)\n",
194
+
boot_error_count, panic_count);
195
+
196
+
if (nvmem_cell_set_u8(reboot->nvm.panic_count, 0) < 0)
197
+
dev_err(reboot->dev, "Failed to reset panic_count\n");
198
+
if (nvmem_cell_set_u8(reboot->nvm.boot_error_count, 0) < 0)
199
+
dev_err(reboot->dev, "Failed to reset boot_error_count\n");
200
+
}
201
+
202
+
static int macsmc_reboot_probe(struct platform_device *pdev)
203
+
{
204
+
struct apple_smc *smc = dev_get_drvdata(pdev->dev.parent);
205
+
struct macsmc_reboot *reboot;
206
+
int ret, i;
207
+
208
+
reboot = devm_kzalloc(&pdev->dev, sizeof(*reboot), GFP_KERNEL);
209
+
if (!reboot)
210
+
return -ENOMEM;
211
+
212
+
reboot->dev = &pdev->dev;
213
+
reboot->smc = smc;
214
+
215
+
platform_set_drvdata(pdev, reboot);
216
+
217
+
for (i = 0; i < ARRAY_SIZE(nvmem_names); i++) {
218
+
struct nvmem_cell *cell;
219
+
220
+
cell = devm_nvmem_cell_get(&pdev->dev,
221
+
nvmem_names[i]);
222
+
if (IS_ERR(cell)) {
223
+
if (PTR_ERR(cell) == -EPROBE_DEFER)
224
+
return -EPROBE_DEFER;
225
+
dev_warn(&pdev->dev, "Missing NVMEM cell %s (%ld)\n",
226
+
nvmem_names[i], PTR_ERR(cell));
227
+
/* Non fatal, we'll deal with it */
228
+
cell = NULL;
229
+
}
230
+
reboot->nvm_cells[i] = cell;
231
+
}
232
+
233
+
/* Set the boot_stage to indicate we're running the OS kernel */
234
+
if (reboot->nvm.boot_stage &&
235
+
nvmem_cell_set_u8(reboot->nvm.boot_stage, BOOT_STAGE_KERNEL_STARTED) < 0)
236
+
dev_err(reboot->dev, "Failed to write boot_stage\n");
237
+
238
+
/* Display and clear the error counts */
239
+
macsmc_power_init_error_counts(reboot);
240
+
241
+
reboot->reboot_notify.notifier_call = macsmc_reboot_notify;
242
+
243
+
ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_POWER_OFF_PREPARE,
244
+
SYS_OFF_PRIO_HIGH, macsmc_prepare_atomic, reboot);
245
+
if (ret)
246
+
return dev_err_probe(&pdev->dev, ret,
247
+
"Failed to register power-off prepare handler\n");
248
+
ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_POWER_OFF, SYS_OFF_PRIO_HIGH,
249
+
macsmc_power_off, reboot);
250
+
if (ret)
251
+
return dev_err_probe(&pdev->dev, ret,
252
+
"Failed to register power-off handler\n");
253
+
254
+
ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART_PREPARE,
255
+
SYS_OFF_PRIO_HIGH, macsmc_prepare_atomic, reboot);
256
+
if (ret)
257
+
return dev_err_probe(&pdev->dev, ret,
258
+
"Failed to register restart prepare handler\n");
259
+
ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
260
+
macsmc_restart, reboot);
261
+
if (ret)
262
+
return dev_err_probe(&pdev->dev, ret, "Failed to register restart handler\n");
263
+
264
+
ret = devm_register_reboot_notifier(&pdev->dev, &reboot->reboot_notify);
265
+
if (ret)
266
+
return dev_err_probe(&pdev->dev, ret, "Failed to register reboot notifier\n");
267
+
268
+
dev_info(&pdev->dev, "Handling reboot and poweroff requests via SMC\n");
269
+
270
+
return 0;
271
+
}
272
+
273
+
static const struct of_device_id macsmc_reboot_of_table[] = {
274
+
{ .compatible = "apple,smc-reboot", },
275
+
{}
276
+
};
277
+
MODULE_DEVICE_TABLE(of, macsmc_reboot_of_table);
278
+
279
+
static struct platform_driver macsmc_reboot_driver = {
280
+
.driver = {
281
+
.name = "macsmc-reboot",
282
+
.of_match_table = macsmc_reboot_of_table,
283
+
},
284
+
.probe = macsmc_reboot_probe,
285
+
};
286
+
module_platform_driver(macsmc_reboot_driver);
287
+
288
+
MODULE_LICENSE("Dual MIT/GPL");
289
+
MODULE_DESCRIPTION("Apple SMC reboot/poweroff driver");
290
+
MODULE_AUTHOR("Hector Martin <marcan@marcan.st>");
+56
-22
drivers/pwm/pwm-adp5585.c
+56
-22
drivers/pwm/pwm-adp5585.c
···
33
33
#define ADP5585_PWM_MIN_PERIOD_NS (2ULL * NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ)
34
34
#define ADP5585_PWM_MAX_PERIOD_NS (2ULL * 0xffff * NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ)
35
35
36
+
struct adp5585_pwm_chip {
37
+
unsigned int pwm_cfg;
38
+
unsigned int pwm_offt_low;
39
+
unsigned int pwm_ont_low;
40
+
};
41
+
42
+
struct adp5585_pwm {
43
+
const struct adp5585_pwm_chip *info;
44
+
struct regmap *regmap;
45
+
unsigned int ext_cfg;
46
+
};
47
+
36
48
static int pwm_adp5585_request(struct pwm_chip *chip, struct pwm_device *pwm)
37
49
{
38
-
struct regmap *regmap = pwmchip_get_drvdata(chip);
50
+
struct adp5585_pwm *adp5585_pwm = pwmchip_get_drvdata(chip);
39
51
40
52
/* Configure the R3 pin as PWM output. */
41
-
return regmap_update_bits(regmap, ADP5585_PIN_CONFIG_C,
53
+
return regmap_update_bits(adp5585_pwm->regmap, adp5585_pwm->ext_cfg,
42
54
ADP5585_R3_EXTEND_CFG_MASK,
43
55
ADP5585_R3_EXTEND_CFG_PWM_OUT);
44
56
}
45
57
46
58
static void pwm_adp5585_free(struct pwm_chip *chip, struct pwm_device *pwm)
47
59
{
48
-
struct regmap *regmap = pwmchip_get_drvdata(chip);
60
+
struct adp5585_pwm *adp5585_pwm = pwmchip_get_drvdata(chip);
49
61
50
-
regmap_update_bits(regmap, ADP5585_PIN_CONFIG_C,
62
+
regmap_update_bits(adp5585_pwm->regmap, adp5585_pwm->ext_cfg,
51
63
ADP5585_R3_EXTEND_CFG_MASK,
52
64
ADP5585_R3_EXTEND_CFG_GPIO4);
53
65
}
···
68
56
struct pwm_device *pwm,
69
57
const struct pwm_state *state)
70
58
{
71
-
struct regmap *regmap = pwmchip_get_drvdata(chip);
59
+
struct adp5585_pwm *adp5585_pwm = pwmchip_get_drvdata(chip);
60
+
const struct adp5585_pwm_chip *info = adp5585_pwm->info;
61
+
struct regmap *regmap = adp5585_pwm->regmap;
72
62
u64 period, duty_cycle;
73
63
u32 on, off;
74
64
__le16 val;
75
65
int ret;
76
66
77
67
if (!state->enabled) {
78
-
regmap_clear_bits(regmap, ADP5585_GENERAL_CFG, ADP5585_OSC_EN);
79
-
regmap_clear_bits(regmap, ADP5585_PWM_CFG, ADP5585_PWM_EN);
68
+
regmap_clear_bits(regmap, info->pwm_cfg, ADP5585_PWM_EN);
80
69
return 0;
81
70
}
82
71
···
98
85
off = div_u64(period, NSEC_PER_SEC / ADP5585_PWM_OSC_FREQ_HZ) - on;
99
86
100
87
val = cpu_to_le16(off);
101
-
ret = regmap_bulk_write(regmap, ADP5585_PWM_OFFT_LOW, &val, 2);
88
+
ret = regmap_bulk_write(regmap, info->pwm_offt_low, &val, 2);
102
89
if (ret)
103
90
return ret;
104
91
105
92
val = cpu_to_le16(on);
106
-
ret = regmap_bulk_write(regmap, ADP5585_PWM_ONT_LOW, &val, 2);
93
+
ret = regmap_bulk_write(regmap, info->pwm_ont_low, &val, 2);
107
94
if (ret)
108
95
return ret;
109
96
110
97
/* Enable PWM in continuous mode and no external AND'ing. */
111
-
ret = regmap_update_bits(regmap, ADP5585_PWM_CFG,
98
+
ret = regmap_update_bits(regmap, info->pwm_cfg,
112
99
ADP5585_PWM_IN_AND | ADP5585_PWM_MODE |
113
100
ADP5585_PWM_EN, ADP5585_PWM_EN);
114
101
if (ret)
115
102
return ret;
116
103
117
-
ret = regmap_set_bits(regmap, ADP5585_GENERAL_CFG, ADP5585_OSC_EN);
118
-
if (ret)
119
-
return ret;
120
-
121
-
return regmap_set_bits(regmap, ADP5585_PWM_CFG, ADP5585_PWM_EN);
104
+
return regmap_set_bits(regmap, info->pwm_cfg, ADP5585_PWM_EN);
122
105
}
123
106
124
107
static int pwm_adp5585_get_state(struct pwm_chip *chip,
125
108
struct pwm_device *pwm,
126
109
struct pwm_state *state)
127
110
{
128
-
struct regmap *regmap = pwmchip_get_drvdata(chip);
111
+
struct adp5585_pwm *adp5585_pwm = pwmchip_get_drvdata(chip);
112
+
const struct adp5585_pwm_chip *info = adp5585_pwm->info;
113
+
struct regmap *regmap = adp5585_pwm->regmap;
129
114
unsigned int on, off;
130
115
unsigned int val;
131
116
__le16 on_off;
132
117
int ret;
133
118
134
-
ret = regmap_bulk_read(regmap, ADP5585_PWM_OFFT_LOW, &on_off, 2);
119
+
ret = regmap_bulk_read(regmap, info->pwm_offt_low, &on_off, 2);
135
120
if (ret)
136
121
return ret;
137
122
off = le16_to_cpu(on_off);
138
123
139
-
ret = regmap_bulk_read(regmap, ADP5585_PWM_ONT_LOW, &on_off, 2);
124
+
ret = regmap_bulk_read(regmap, info->pwm_ont_low, &on_off, 2);
140
125
if (ret)
141
126
return ret;
142
127
on = le16_to_cpu(on_off);
···
144
133
145
134
state->polarity = PWM_POLARITY_NORMAL;
146
135
147
-
regmap_read(regmap, ADP5585_PWM_CFG, &val);
136
+
regmap_read(regmap, info->pwm_cfg, &val);
148
137
state->enabled = !!(val & ADP5585_PWM_EN);
149
138
150
139
return 0;
···
159
148
160
149
static int adp5585_pwm_probe(struct platform_device *pdev)
161
150
{
151
+
const struct platform_device_id *id = platform_get_device_id(pdev);
162
152
struct device *dev = &pdev->dev;
163
153
struct adp5585_dev *adp5585 = dev_get_drvdata(dev->parent);
154
+
struct adp5585_pwm *adp5585_pwm;
164
155
struct pwm_chip *chip;
165
156
int ret;
166
157
167
-
chip = devm_pwmchip_alloc(dev, ADP5585_PWM_CHAN_NUM, 0);
158
+
chip = devm_pwmchip_alloc(dev, ADP5585_PWM_CHAN_NUM,
159
+
sizeof(*adp5585_pwm));
168
160
if (IS_ERR(chip))
169
161
return PTR_ERR(chip);
170
162
163
+
adp5585_pwm = pwmchip_get_drvdata(chip);
164
+
adp5585_pwm->regmap = adp5585->regmap;
165
+
adp5585_pwm->ext_cfg = adp5585->regs->ext_cfg;
166
+
167
+
adp5585_pwm->info = (const struct adp5585_pwm_chip *)id->driver_data;
168
+
if (!adp5585_pwm->info)
169
+
return -ENODEV;
170
+
171
171
device_set_of_node_from_dev(dev, dev->parent);
172
172
173
-
pwmchip_set_drvdata(chip, adp5585->regmap);
174
173
chip->ops = &adp5585_pwm_ops;
175
174
176
175
ret = devm_pwmchip_add(dev, chip);
···
190
169
return 0;
191
170
}
192
171
172
+
static const struct adp5585_pwm_chip adp5589_pwm_chip_info = {
173
+
.pwm_cfg = ADP5585_PWM_CFG,
174
+
.pwm_offt_low = ADP5585_PWM_OFFT_LOW,
175
+
.pwm_ont_low = ADP5585_PWM_ONT_LOW,
176
+
};
177
+
178
+
static const struct adp5585_pwm_chip adp5585_pwm_chip_info = {
179
+
.pwm_cfg = ADP5589_PWM_CFG,
180
+
.pwm_offt_low = ADP5589_PWM_OFFT_LOW,
181
+
.pwm_ont_low = ADP5589_PWM_ONT_LOW,
182
+
};
183
+
193
184
static const struct platform_device_id adp5585_pwm_id_table[] = {
194
-
{ "adp5585-pwm" },
185
+
{ "adp5585-pwm", (kernel_ulong_t)&adp5585_pwm_chip_info },
186
+
{ "adp5589-pwm", (kernel_ulong_t)&adp5589_pwm_chip_info },
195
187
{ /* Sentinel */ }
196
188
};
197
189
MODULE_DEVICE_TABLE(platform, adp5585_pwm_id_table);
+1
-2
drivers/soc/apple/rtkit.c
+1
-2
drivers/soc/apple/rtkit.c
···
279
279
dev_dbg(rtk->dev, "RTKit: buffer request for 0x%zx bytes at %pad\n",
280
280
buffer->size, &buffer->iova);
281
281
282
-
if (buffer->iova &&
283
-
(!rtk->ops->shmem_setup || !rtk->ops->shmem_destroy)) {
282
+
if (buffer->iova && !rtk->ops->shmem_setup) {
284
283
err = -EINVAL;
285
284
goto error;
286
285
}
+2
-3
drivers/usb/gadget/udc/pxa25x_udc.c
+2
-3
drivers/usb/gadget/udc/pxa25x_udc.c
···
2348
2348
dev->transceiver = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
2349
2349
2350
2350
if (gpio_is_valid(dev->mach->gpio_pullup)) {
2351
-
retval = devm_gpio_request(&pdev->dev, dev->mach->gpio_pullup,
2352
-
"pca25x_udc GPIO PULLUP");
2351
+
retval = devm_gpio_request_one(&pdev->dev, dev->mach->gpio_pullup,
2352
+
GPIOF_OUT_INIT_LOW, "pca25x_udc GPIO PULLUP");
2353
2353
if (retval) {
2354
2354
dev_dbg(&pdev->dev,
2355
2355
"can't get pullup gpio %d, err: %d\n",
2356
2356
dev->mach->gpio_pullup, retval);
2357
2357
goto err;
2358
2358
}
2359
-
gpio_direction_output(dev->mach->gpio_pullup, 0);
2360
2359
}
2361
2360
2362
2361
timer_setup(&dev->timer, udc_watchdog, 0);
+6
-37
include/linux/gpio.h
+6
-37
include/linux/gpio.h
···
13
13
#define __LINUX_GPIO_H
14
14
15
15
#include <linux/types.h>
16
+
#ifdef CONFIG_GPIOLIB
17
+
#include <linux/gpio/consumer.h>
18
+
#endif
19
+
20
+
#ifdef CONFIG_GPIOLIB_LEGACY
16
21
17
22
struct device;
18
23
···
26
21
#define GPIOF_OUT_INIT_LOW ((0 << 0) | (0 << 1))
27
22
#define GPIOF_OUT_INIT_HIGH ((0 << 0) | (1 << 1))
28
23
29
-
/**
30
-
* struct gpio - a structure describing a GPIO with configuration
31
-
* @gpio: the GPIO number
32
-
* @flags: GPIO configuration as specified by GPIOF_*
33
-
* @label: a literal description string of this GPIO
34
-
*/
35
-
struct gpio {
36
-
unsigned gpio;
37
-
unsigned long flags;
38
-
const char *label;
39
-
};
40
-
41
24
#ifdef CONFIG_GPIOLIB
42
-
43
-
#include <linux/gpio/consumer.h>
44
-
45
25
/*
46
26
* "valid" GPIO numbers are nonnegative and may be passed to
47
27
* setup routines like gpio_request(). Only some valid numbers
···
46
56
* at a small performance cost for non-inlined operations and some
47
57
* extra memory (for code and for per-GPIO table entries).
48
58
*/
49
-
50
-
/*
51
-
* At the end we want all GPIOs to be dynamically allocated from 0.
52
-
* However, some legacy drivers still perform fixed allocation.
53
-
* Until they are all fixed, leave 0-512 space for them.
54
-
*/
55
-
#define GPIO_DYNAMIC_BASE 512
56
-
/*
57
-
* Define the maximum of the possible GPIO in the global numberspace.
58
-
* While the GPIO base and numbers are positive, we limit it with signed
59
-
* maximum as a lot of code is using negative values for special cases.
60
-
*/
61
-
#define GPIO_DYNAMIC_MAX INT_MAX
62
59
63
60
/* Always use the library code for GPIO management calls,
64
61
* or when sleeping may be involved.
···
87
110
88
111
int gpio_request_one(unsigned gpio, unsigned long flags, const char *label);
89
112
90
-
int devm_gpio_request(struct device *dev, unsigned gpio, const char *label);
91
113
int devm_gpio_request_one(struct device *dev, unsigned gpio,
92
114
unsigned long flags, const char *label);
93
115
···
164
188
return -EINVAL;
165
189
}
166
190
167
-
static inline int devm_gpio_request(struct device *dev, unsigned gpio,
168
-
const char *label)
169
-
{
170
-
WARN_ON(1);
171
-
return -EINVAL;
172
-
}
173
-
174
191
static inline int devm_gpio_request_one(struct device *dev, unsigned gpio,
175
192
unsigned long flags, const char *label)
176
193
{
···
172
203
}
173
204
174
205
#endif /* ! CONFIG_GPIOLIB */
175
-
206
+
#endif /* CONFIG_GPIOLIB_LEGACY */
176
207
#endif /* __LINUX_GPIO_H */
+3
-2
include/linux/gpio/consumer.h
+3
-2
include/linux/gpio/consumer.h
···
181
181
enum gpiod_flags flags,
182
182
const char *label);
183
183
184
-
bool gpiod_is_equal(struct gpio_desc *desc, struct gpio_desc *other);
184
+
bool gpiod_is_equal(const struct gpio_desc *desc,
185
+
const struct gpio_desc *other);
185
186
186
187
#else /* CONFIG_GPIOLIB */
187
188
···
552
551
}
553
552
554
553
static inline bool
555
-
gpiod_is_equal(struct gpio_desc *desc, struct gpio_desc *other)
554
+
gpiod_is_equal(const struct gpio_desc *desc, const struct gpio_desc *other)
556
555
{
557
556
WARN_ON(desc || other);
558
557
return false;
+1
-6
include/linux/gpio/driver.h
+1
-6
include/linux/gpio/driver.h
···
718
718
/* get driver data */
719
719
void *gpiochip_get_data(struct gpio_chip *gc);
720
720
721
-
struct bgpio_pdata {
722
-
const char *label;
723
-
int base;
724
-
int ngpio;
725
-
};
726
-
727
721
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
728
722
729
723
int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
···
744
750
#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
745
751
#define BGPIOF_NO_SET_ON_INPUT BIT(6)
746
752
#define BGPIOF_PINCTRL_BACKEND BIT(7) /* Call pinctrl direction setters */
753
+
#define BGPIOF_NO_INPUT BIT(8) /* only output */
747
754
748
755
#ifdef CONFIG_GPIOLIB_IRQCHIP
749
756
int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
+120
include/linux/gpio/generic.h
+120
include/linux/gpio/generic.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
3
+
#ifndef __LINUX_GPIO_GENERIC_H
4
+
#define __LINUX_GPIO_GENERIC_H
5
+
6
+
#include <linux/cleanup.h>
7
+
#include <linux/gpio/driver.h>
8
+
#include <linux/spinlock.h>
9
+
10
+
struct device;
11
+
12
+
/**
13
+
* struct gpio_generic_chip_config - Generic GPIO chip configuration data
14
+
* @dev: Parent device of the new GPIO chip (compulsory).
15
+
* @sz: Size (width) of the MMIO registers in bytes, typically 1, 2 or 4.
16
+
* @dat: MMIO address for the register to READ the value of the GPIO lines, it
17
+
* is expected that a 1 in the corresponding bit in this register means
18
+
* the line is asserted.
19
+
* @set: MMIO address for the register to SET the value of the GPIO lines, it
20
+
* is expected that we write the line with 1 in this register to drive
21
+
* the GPIO line high.
22
+
* @clr: MMIO address for the register to CLEAR the value of the GPIO lines,
23
+
* it is expected that we write the line with 1 in this register to
24
+
* drive the GPIO line low. It is allowed to leave this address as NULL,
25
+
* in that case the SET register will be assumed to also clear the GPIO
26
+
* lines, by actively writing the line with 0.
27
+
* @dirout: MMIO address for the register to set the line as OUTPUT. It is
28
+
* assumed that setting a line to 1 in this register will turn that
29
+
* line into an output line. Conversely, setting the line to 0 will
30
+
* turn that line into an input.
31
+
* @dirin: MMIO address for the register to set this line as INPUT. It is
32
+
* assumed that setting a line to 1 in this register will turn that
33
+
* line into an input line. Conversely, setting the line to 0 will
34
+
* turn that line into an output.
35
+
* @flags: Different flags that will affect the behaviour of the device, such
36
+
* as endianness etc.
37
+
*/
38
+
struct gpio_generic_chip_config {
39
+
struct device *dev;
40
+
unsigned long sz;
41
+
void __iomem *dat;
42
+
void __iomem *set;
43
+
void __iomem *clr;
44
+
void __iomem *dirout;
45
+
void __iomem *dirin;
46
+
unsigned long flags;
47
+
};
48
+
49
+
/**
50
+
* struct gpio_generic_chip - Generic GPIO chip implementation.
51
+
* @gc: The underlying struct gpio_chip object, implementing low-level GPIO
52
+
* chip routines.
53
+
*/
54
+
struct gpio_generic_chip {
55
+
struct gpio_chip gc;
56
+
};
57
+
58
+
/**
59
+
* gpio_generic_chip_init() - Initialize a generic GPIO chip.
60
+
* @chip: Generic GPIO chip to set up.
61
+
* @cfg: Generic GPIO chip configuration.
62
+
*
63
+
* Returns 0 on success, negative error number on failure.
64
+
*/
65
+
static inline int
66
+
gpio_generic_chip_init(struct gpio_generic_chip *chip,
67
+
const struct gpio_generic_chip_config *cfg)
68
+
{
69
+
return bgpio_init(&chip->gc, cfg->dev, cfg->sz, cfg->dat, cfg->set,
70
+
cfg->clr, cfg->dirout, cfg->dirin, cfg->flags);
71
+
}
72
+
73
+
/**
74
+
* gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO chip.
75
+
* @chip: Generic GPIO chip to use.
76
+
* @offset: Hardware offset of the line to set.
77
+
* @value: New GPIO line value.
78
+
*
79
+
* Some modules using the generic GPIO chip, need to set line values in their
80
+
* direction setters but they don't have access to the gpio-mmio symbols so
81
+
* they use the function pointer in struct gpio_chip directly. This is not
82
+
* optimal and can lead to crashes at run-time in some instances. This wrapper
83
+
* provides a safe interface for users.
84
+
*
85
+
* Returns: 0 on success, negative error number of failure.
86
+
*/
87
+
static inline int
88
+
gpio_generic_chip_set(struct gpio_generic_chip *chip, unsigned int offset,
89
+
int value)
90
+
{
91
+
if (WARN_ON(!chip->gc.set_rv))
92
+
return -EOPNOTSUPP;
93
+
94
+
return chip->gc.set_rv(&chip->gc, offset, value);
95
+
}
96
+
97
+
#define gpio_generic_chip_lock(gen_gc) \
98
+
raw_spin_lock(&(gen_gc)->gc.bgpio_lock)
99
+
100
+
#define gpio_generic_chip_unlock(gen_gc) \
101
+
raw_spin_unlock(&(gen_gc)->gc.bgpio_lock)
102
+
103
+
#define gpio_generic_chip_lock_irqsave(gen_gc, flags) \
104
+
raw_spin_lock_irqsave(&(gen_gc)->gc.bgpio_lock, flags)
105
+
106
+
#define gpio_generic_chip_unlock_irqrestore(gen_gc, flags) \
107
+
raw_spin_unlock_irqrestore(&(gen_gc)->gc.bgpio_lock, flags)
108
+
109
+
DEFINE_LOCK_GUARD_1(gpio_generic_lock,
110
+
struct gpio_generic_chip,
111
+
gpio_generic_chip_lock(_T->lock),
112
+
gpio_generic_chip_unlock(_T->lock))
113
+
114
+
DEFINE_LOCK_GUARD_1(gpio_generic_lock_irqsave,
115
+
struct gpio_generic_chip,
116
+
gpio_generic_chip_lock_irqsave(_T->lock, _T->flags),
117
+
gpio_generic_chip_unlock_irqrestore(_T->lock, _T->flags),
118
+
unsigned long flags)
119
+
120
+
#endif /* __LINUX_GPIO_GENERIC_H */
+109
-9
include/linux/mfd/adp5585.h
+109
-9
include/linux/mfd/adp5585.h
···
10
10
#define __MFD_ADP5585_H_
11
11
12
12
#include <linux/bits.h>
13
+
#include <linux/notifier.h>
13
14
14
15
#define ADP5585_ID 0x00
15
16
#define ADP5585_MAN_ID_VALUE 0x20
16
17
#define ADP5585_MAN_ID_MASK GENMASK(7, 4)
18
+
#define ADP5585_REV_ID_MASK GENMASK(3, 0)
17
19
#define ADP5585_INT_STATUS 0x01
20
+
#define ADP5585_OVRFLOW_INT BIT(2)
21
+
#define ADP5585_EVENT_INT BIT(0)
18
22
#define ADP5585_STATUS 0x02
23
+
#define ADP5585_EC_MASK GENMASK(4, 0)
19
24
#define ADP5585_FIFO_1 0x03
25
+
#define ADP5585_KEV_EV_PRESS_MASK BIT(7)
26
+
#define ADP5585_KEY_EVENT_MASK GENMASK(6, 0)
20
27
#define ADP5585_FIFO_2 0x04
21
28
#define ADP5585_FIFO_3 0x05
22
29
#define ADP5585_FIFO_4 0x06
···
39
32
#define ADP5585_FIFO_14 0x10
40
33
#define ADP5585_FIFO_15 0x11
41
34
#define ADP5585_FIFO_16 0x12
35
+
#define ADP5585_EV_MAX (ADP5585_FIFO_16 - ADP5585_FIFO_1 + 1)
42
36
#define ADP5585_GPI_INT_STAT_A 0x13
43
37
#define ADP5585_GPI_INT_STAT_B 0x14
44
38
#define ADP5585_GPI_STATUS_A 0x15
···
68
60
#define ADP5585_GPIO_DIRECTION_A 0x27
69
61
#define ADP5585_GPIO_DIRECTION_B 0x28
70
62
#define ADP5585_RESET1_EVENT_A 0x29
63
+
#define ADP5585_RESET_EV_PRESS BIT(7)
71
64
#define ADP5585_RESET1_EVENT_B 0x2a
72
65
#define ADP5585_RESET1_EVENT_C 0x2b
73
66
#define ADP5585_RESET2_EVENT_A 0x2c
···
113
104
#define ADP5585_INT_CFG BIT(1)
114
105
#define ADP5585_RST_CFG BIT(0)
115
106
#define ADP5585_INT_EN 0x3c
107
+
#define ADP5585_OVRFLOW_IEN BIT(2)
108
+
#define ADP5585_EVENT_IEN BIT(0)
116
109
117
110
#define ADP5585_MAX_REG ADP5585_INT_EN
118
111
119
-
/*
120
-
* Bank 0 covers pins "GPIO 1/R0" to "GPIO 6/R5", numbered 0 to 5 by the
121
-
* driver, and bank 1 covers pins "GPIO 7/C0" to "GPIO 11/C4", numbered 6 to
122
-
* 10. Some variants of the ADP5585 don't support "GPIO 6/R5". As the driver
123
-
* uses identical GPIO numbering for all variants to avoid confusion, GPIO 5 is
124
-
* marked as reserved in the device tree for variants that don't support it.
125
-
*/
126
-
#define ADP5585_BANK(n) ((n) >= 6 ? 1 : 0)
127
-
#define ADP5585_BIT(n) ((n) >= 6 ? BIT((n) - 6) : BIT(n))
112
+
#define ADP5585_PIN_MAX 11
113
+
#define ADP5585_MAX_UNLOCK_TIME_SEC 7
114
+
#define ADP5585_KEY_EVENT_START 1
115
+
#define ADP5585_KEY_EVENT_END 25
116
+
#define ADP5585_GPI_EVENT_START 37
117
+
#define ADP5585_GPI_EVENT_END 47
118
+
#define ADP5585_ROW5_KEY_EVENT_START 1
119
+
#define ADP5585_ROW5_KEY_EVENT_END 30
120
+
#define ADP5585_PWM_OUT 3
121
+
#define ADP5585_RESET1_OUT 4
122
+
#define ADP5585_RESET2_OUT 9
123
+
#define ADP5585_ROW5 5
124
+
125
+
/* ADP5589 */
126
+
#define ADP5589_MAN_ID_VALUE 0x10
127
+
#define ADP5589_GPI_STATUS_A 0x16
128
+
#define ADP5589_GPI_STATUS_C 0x18
129
+
#define ADP5589_RPULL_CONFIG_A 0x19
130
+
#define ADP5589_GPI_INT_LEVEL_A 0x1e
131
+
#define ADP5589_GPI_EVENT_EN_A 0x21
132
+
#define ADP5589_DEBOUNCE_DIS_A 0x27
133
+
#define ADP5589_GPO_DATA_OUT_A 0x2a
134
+
#define ADP5589_GPO_OUT_MODE_A 0x2d
135
+
#define ADP5589_GPIO_DIRECTION_A 0x30
136
+
#define ADP5589_UNLOCK1 0x33
137
+
#define ADP5589_UNLOCK_EV_PRESS BIT(7)
138
+
#define ADP5589_UNLOCK_TIMERS 0x36
139
+
#define ADP5589_UNLOCK_TIMER GENMASK(2, 0)
140
+
#define ADP5589_LOCK_CFG 0x37
141
+
#define ADP5589_LOCK_EN BIT(0)
142
+
#define ADP5589_RESET1_EVENT_A 0x38
143
+
#define ADP5589_RESET2_EVENT_A 0x3B
144
+
#define ADP5589_RESET_CFG 0x3D
145
+
#define ADP5585_RESET2_POL BIT(7)
146
+
#define ADP5585_RESET1_POL BIT(6)
147
+
#define ADP5585_RST_PASSTHRU_EN BIT(5)
148
+
#define ADP5585_RESET_TRIG_TIME GENMASK(4, 2)
149
+
#define ADP5585_PULSE_WIDTH GENMASK(1, 0)
150
+
#define ADP5589_PWM_OFFT_LOW 0x3e
151
+
#define ADP5589_PWM_ONT_LOW 0x40
152
+
#define ADP5589_PWM_CFG 0x42
153
+
#define ADP5589_POLL_PTIME_CFG 0x48
154
+
#define ADP5589_PIN_CONFIG_A 0x49
155
+
#define ADP5589_PIN_CONFIG_D 0x4C
156
+
#define ADP5589_GENERAL_CFG 0x4d
157
+
#define ADP5589_INT_EN 0x4e
158
+
#define ADP5589_MAX_REG ADP5589_INT_EN
159
+
160
+
#define ADP5589_PIN_MAX 19
161
+
#define ADP5589_KEY_EVENT_START 1
162
+
#define ADP5589_KEY_EVENT_END 88
163
+
#define ADP5589_GPI_EVENT_START 97
164
+
#define ADP5589_GPI_EVENT_END 115
165
+
#define ADP5589_UNLOCK_WILDCARD 127
166
+
#define ADP5589_RESET2_OUT 12
128
167
129
168
struct regmap;
130
169
170
+
enum adp5585_variant {
171
+
ADP5585_00 = 1,
172
+
ADP5585_01,
173
+
ADP5585_02,
174
+
ADP5585_03,
175
+
ADP5585_04,
176
+
ADP5589_00,
177
+
ADP5589_01,
178
+
ADP5589_02,
179
+
ADP5585_MAX
180
+
};
181
+
182
+
struct adp5585_regs {
183
+
unsigned int gen_cfg;
184
+
unsigned int ext_cfg;
185
+
unsigned int int_en;
186
+
unsigned int poll_ptime_cfg;
187
+
unsigned int reset_cfg;
188
+
unsigned int reset1_event_a;
189
+
unsigned int reset2_event_a;
190
+
unsigned int pin_cfg_a;
191
+
};
192
+
131
193
struct adp5585_dev {
194
+
struct device *dev;
132
195
struct regmap *regmap;
196
+
const struct adp5585_regs *regs;
197
+
struct blocking_notifier_head event_notifier;
198
+
unsigned long *pin_usage;
199
+
unsigned int n_pins;
200
+
unsigned int reset2_out;
201
+
enum adp5585_variant variant;
202
+
unsigned int id;
203
+
bool has_unlock;
204
+
bool has_pin6;
205
+
int irq;
206
+
unsigned int ev_poll_time;
207
+
unsigned int unlock_time;
208
+
unsigned int unlock_keys[2];
209
+
unsigned int nkeys_unlock;
210
+
unsigned int reset1_keys[3];
211
+
unsigned int nkeys_reset1;
212
+
unsigned int reset2_keys[2];
213
+
unsigned int nkeys_reset2;
214
+
u8 reset_cfg;
133
215
};
134
216
135
217
#endif
+279
include/linux/mfd/macsmc.h
+279
include/linux/mfd/macsmc.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2
+
/*
3
+
* Apple SMC (System Management Controller) core definitions
4
+
*
5
+
* Copyright (C) The Asahi Linux Contributors
6
+
*/
7
+
8
+
#ifndef _LINUX_MFD_MACSMC_H
9
+
#define _LINUX_MFD_MACSMC_H
10
+
11
+
#include <linux/soc/apple/rtkit.h>
12
+
13
+
/**
14
+
* typedef smc_key - Alias for u32 to be used for SMC keys
15
+
*
16
+
* SMC keys are 32bit integers containing packed ASCII characters in natural
17
+
* integer order, i.e. 0xAABBCCDD, which represent the FourCC ABCD.
18
+
* The SMC driver is designed with this assumption and ensures the right
19
+
* endianness is used when these are stored to memory and sent to or received
20
+
* from the actual SMC firmware (which can be done in either shared memory or
21
+
* as 64bit mailbox message on Apple Silicon).
22
+
* Internally, SMC stores these keys in a table sorted lexicographically and
23
+
* allows resolving an index into this table to the corresponding SMC key.
24
+
* Thus, storing keys as u32 is very convenient as it allows to e.g. use
25
+
* normal comparison operators which directly map to the natural order used
26
+
* by SMC firmware.
27
+
*
28
+
* This simple type alias is introduced to allow easy recognition of SMC key
29
+
* variables and arguments.
30
+
*/
31
+
typedef u32 smc_key;
32
+
33
+
/**
34
+
* SMC_KEY - Convert FourCC SMC keys in source code to smc_key
35
+
*
36
+
* This macro can be used to easily define FourCC SMC keys in source code
37
+
* and convert these to u32 / smc_key, e.g. SMC_KEY(NTAP) will expand to
38
+
* 0x4e544150.
39
+
*
40
+
* @s: FourCC SMC key to be converted
41
+
*/
42
+
#define SMC_KEY(s) (smc_key)(_SMC_KEY(#s))
43
+
#define _SMC_KEY(s) (((s)[0] << 24) | ((s)[1] << 16) | ((s)[2] << 8) | (s)[3])
44
+
45
+
#define APPLE_SMC_READABLE BIT(7)
46
+
#define APPLE_SMC_WRITABLE BIT(6)
47
+
#define APPLE_SMC_FUNCTION BIT(4)
48
+
49
+
/**
50
+
* struct apple_smc_key_info - Information for a SMC key as returned by SMC
51
+
* @type_code: FourCC code indicating the type for this key.
52
+
* Known types:
53
+
* ch8*: ASCII string
54
+
* flag: Boolean, 1 or 0
55
+
* flt: 32-bit single-precision IEEE 754 float
56
+
* hex: Binary data
57
+
* ioft: 64bit Unsigned fixed-point intger (48.16)
58
+
* {si,ui}{8,16,32,64}: Signed/Unsigned 8-/16-/32-/64-bit integer
59
+
* @size: Size of the buffer associated with this key
60
+
* @flags: Bitfield encoding flags (APPLE_SMC_{READABLE,WRITABLE,FUNCTION})
61
+
*/
62
+
struct apple_smc_key_info {
63
+
u32 type_code;
64
+
u8 size;
65
+
u8 flags;
66
+
};
67
+
68
+
/**
69
+
* enum apple_smc_boot_stage - SMC boot stage
70
+
* @APPLE_SMC_BOOTING: SMC is booting
71
+
* @APPLE_SMC_INITIALIZED: SMC is initialized and ready to use
72
+
* @APPLE_SMC_ERROR_NO_SHMEM: Shared memory could not be initialized during boot
73
+
* @APPLE_SMC_ERROR_CRASHED: SMC has crashed
74
+
*/
75
+
enum apple_smc_boot_stage {
76
+
APPLE_SMC_BOOTING,
77
+
APPLE_SMC_INITIALIZED,
78
+
APPLE_SMC_ERROR_NO_SHMEM,
79
+
APPLE_SMC_ERROR_CRASHED
80
+
};
81
+
82
+
/**
83
+
* struct apple_smc
84
+
* @dev: Underlying device struct for the physical backend device
85
+
* @key_count: Number of available SMC keys
86
+
* @first_key: First valid SMC key
87
+
* @last_key: Last valid SMC key
88
+
* @event_handlers: Notifier call chain for events received from SMC
89
+
* @rtk: Pointer to Apple RTKit instance
90
+
* @init_done: Completion for initialization
91
+
* @boot_stage: Current boot stage of SMC
92
+
* @sram: Pointer to SRAM resource
93
+
* @sram_base: SRAM base address
94
+
* @shmem: RTKit shared memory structure for SRAM
95
+
* @msg_id: Current message id for commands, will be incremented for each command
96
+
* @atomic_mode: Flag set when atomic mode is entered
97
+
* @atomic_pending: Flag indicating pending atomic command
98
+
* @cmd_done: Completion for command execution in non-atomic mode
99
+
* @cmd_ret: Return value from SMC for last command
100
+
* @mutex: Mutex for non-atomic mode
101
+
* @lock: Spinlock for atomic mode
102
+
*/
103
+
struct apple_smc {
104
+
struct device *dev;
105
+
106
+
u32 key_count;
107
+
smc_key first_key;
108
+
smc_key last_key;
109
+
110
+
struct blocking_notifier_head event_handlers;
111
+
112
+
struct apple_rtkit *rtk;
113
+
114
+
struct completion init_done;
115
+
enum apple_smc_boot_stage boot_stage;
116
+
117
+
struct resource *sram;
118
+
void __iomem *sram_base;
119
+
struct apple_rtkit_shmem shmem;
120
+
121
+
unsigned int msg_id;
122
+
123
+
bool atomic_mode;
124
+
bool atomic_pending;
125
+
struct completion cmd_done;
126
+
u64 cmd_ret;
127
+
128
+
struct mutex mutex;
129
+
spinlock_t lock;
130
+
};
131
+
132
+
/**
133
+
* apple_smc_read - Read size bytes from given SMC key into buf
134
+
* @smc: Pointer to apple_smc struct
135
+
* @key: smc_key to be read
136
+
* @buf: Buffer into which size bytes of data will be read from SMC
137
+
* @size: Number of bytes to be read into buf
138
+
*
139
+
* Return: Zero on success, negative errno on error
140
+
*/
141
+
int apple_smc_read(struct apple_smc *smc, smc_key key, void *buf, size_t size);
142
+
143
+
/**
144
+
* apple_smc_write - Write size bytes into given SMC key from buf
145
+
* @smc: Pointer to apple_smc struct
146
+
* @key: smc_key data will be written to
147
+
* @buf: Buffer from which size bytes of data will be written to SMC
148
+
* @size: Number of bytes to be written
149
+
*
150
+
* Return: Zero on success, negative errno on error
151
+
*/
152
+
int apple_smc_write(struct apple_smc *smc, smc_key key, void *buf, size_t size);
153
+
154
+
/**
155
+
* apple_smc_enter_atomic - Enter atomic mode to be able to use apple_smc_write_atomic
156
+
* @smc: Pointer to apple_smc struct
157
+
*
158
+
* This function switches the SMC backend to atomic mode which allows the
159
+
* use of apple_smc_write_atomic while disabling *all* other functions.
160
+
* This is only used for shutdown/reboot which requires writing to a SMC
161
+
* key from atomic context.
162
+
*
163
+
* Return: Zero on success, negative errno on error
164
+
*/
165
+
int apple_smc_enter_atomic(struct apple_smc *smc);
166
+
167
+
/**
168
+
* apple_smc_write_atomic - Write size bytes into given SMC key from buf without sleeping
169
+
* @smc: Pointer to apple_smc struct
170
+
* @key: smc_key data will be written to
171
+
* @buf: Buffer from which size bytes of data will be written to SMC
172
+
* @size: Number of bytes to be written
173
+
*
174
+
* Note that this function will fail if apple_smc_enter_atomic hasn't been
175
+
* called before.
176
+
*
177
+
* Return: Zero on success, negative errno on error
178
+
*/
179
+
int apple_smc_write_atomic(struct apple_smc *smc, smc_key key, void *buf, size_t size);
180
+
181
+
/**
182
+
* apple_smc_rw - Write and then read using the given SMC key
183
+
* @smc: Pointer to apple_smc struct
184
+
* @key: smc_key data will be written to
185
+
* @wbuf: Buffer from which size bytes of data will be written to SMC
186
+
* @wsize: Number of bytes to be written
187
+
* @rbuf: Buffer to which size bytes of data will be read from SMC
188
+
* @rsize: Number of bytes to be read
189
+
*
190
+
* Return: Zero on success, negative errno on error
191
+
*/
192
+
int apple_smc_rw(struct apple_smc *smc, smc_key key, void *wbuf, size_t wsize,
193
+
void *rbuf, size_t rsize);
194
+
195
+
/**
196
+
* apple_smc_get_key_by_index - Given an index return the corresponding SMC key
197
+
* @smc: Pointer to apple_smc struct
198
+
* @index: Index to be resolved
199
+
* @key: Buffer for SMC key to be returned
200
+
*
201
+
* Return: Zero on success, negative errno on error
202
+
*/
203
+
int apple_smc_get_key_by_index(struct apple_smc *smc, int index, smc_key *key);
204
+
205
+
/**
206
+
* apple_smc_get_key_info - Get key information from SMC
207
+
* @smc: Pointer to apple_smc struct
208
+
* @key: Key to acquire information for
209
+
* @info: Pointer to struct apple_smc_key_info which will be filled
210
+
*
211
+
* Return: Zero on success, negative errno on error
212
+
*/
213
+
int apple_smc_get_key_info(struct apple_smc *smc, smc_key key, struct apple_smc_key_info *info);
214
+
215
+
/**
216
+
* apple_smc_key_exists - Check if the given SMC key exists
217
+
* @smc: Pointer to apple_smc struct
218
+
* @key: smc_key to be checked
219
+
*
220
+
* Return: True if the key exists, false otherwise
221
+
*/
222
+
static inline bool apple_smc_key_exists(struct apple_smc *smc, smc_key key)
223
+
{
224
+
return apple_smc_get_key_info(smc, key, NULL) >= 0;
225
+
}
226
+
227
+
#define APPLE_SMC_TYPE_OPS(type) \
228
+
static inline int apple_smc_read_##type(struct apple_smc *smc, smc_key key, type *p) \
229
+
{ \
230
+
int ret = apple_smc_read(smc, key, p, sizeof(*p)); \
231
+
return (ret < 0) ? ret : ((ret != sizeof(*p)) ? -EINVAL : 0); \
232
+
} \
233
+
static inline int apple_smc_write_##type(struct apple_smc *smc, smc_key key, type p) \
234
+
{ \
235
+
return apple_smc_write(smc, key, &p, sizeof(p)); \
236
+
} \
237
+
static inline int apple_smc_write_##type##_atomic(struct apple_smc *smc, smc_key key, type p) \
238
+
{ \
239
+
return apple_smc_write_atomic(smc, key, &p, sizeof(p)); \
240
+
} \
241
+
static inline int apple_smc_rw_##type(struct apple_smc *smc, smc_key key, \
242
+
type w, type *r) \
243
+
{ \
244
+
int ret = apple_smc_rw(smc, key, &w, sizeof(w), r, sizeof(*r)); \
245
+
return (ret < 0) ? ret : ((ret != sizeof(*r)) ? -EINVAL : 0); \
246
+
}
247
+
248
+
APPLE_SMC_TYPE_OPS(u64)
249
+
APPLE_SMC_TYPE_OPS(u32)
250
+
APPLE_SMC_TYPE_OPS(u16)
251
+
APPLE_SMC_TYPE_OPS(u8)
252
+
APPLE_SMC_TYPE_OPS(s64)
253
+
APPLE_SMC_TYPE_OPS(s32)
254
+
APPLE_SMC_TYPE_OPS(s16)
255
+
APPLE_SMC_TYPE_OPS(s8)
256
+
257
+
static inline int apple_smc_read_flag(struct apple_smc *smc, smc_key key, bool *flag)
258
+
{
259
+
u8 val;
260
+
int ret = apple_smc_read_u8(smc, key, &val);
261
+
262
+
if (ret < 0)
263
+
return ret;
264
+
265
+
*flag = val ? true : false;
266
+
return ret;
267
+
}
268
+
269
+
static inline int apple_smc_write_flag(struct apple_smc *smc, smc_key key, bool state)
270
+
{
271
+
return apple_smc_write_u8(smc, key, state ? 1 : 0);
272
+
}
273
+
274
+
static inline int apple_smc_write_flag_atomic(struct apple_smc *smc, smc_key key, bool state)
275
+
{
276
+
return apple_smc_write_u8_atomic(smc, key, state ? 1 : 0);
277
+
}
278
+
279
+
#endif