Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/display: dp: change drm_dp_dpcd_read_link_status() return value
drm_dp_dpcd_read_link_status() follows the "return error code or number
of bytes read" protocol, with the code returning less bytes than
requested in case of some errors. However most of the drivers
interpreted that as "return error code in case of any error". Switch
drm_dp_dpcd_read_link_status() to drm_dp_dpcd_read_data() and make it
follow that protocol too.
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250324-drm-rework-dpcd-access-v4-2-e80ff89593df@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Dmitry Baryshkov
and committed by
Dmitry Baryshkov
fcbb93f1
d8343e11
+28
-43
+4
-4
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+4
-4
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
···
458
458
u8 link_status[DP_LINK_STATUS_SIZE];
459
459
struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
460
460
461
-
if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
462
-
<= 0)
461
+
if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux,
462
+
link_status) < 0)
463
463
return false;
464
464
if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
465
465
return false;
···
616
616
drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
617
617
618
618
if (drm_dp_dpcd_read_link_status(dp_info->aux,
619
-
dp_info->link_status) <= 0) {
619
+
dp_info->link_status) < 0) {
620
620
DRM_ERROR("displayport link status failed\n");
621
621
break;
622
622
}
···
681
681
drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
682
682
683
683
if (drm_dp_dpcd_read_link_status(dp_info->aux,
684
-
dp_info->link_status) <= 0) {
684
+
dp_info->link_status) < 0) {
685
685
DRM_ERROR("displayport link status failed\n");
686
686
break;
687
687
}
+1
-1
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+1
-1
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+3
-4
drivers/gpu/drm/display/drm_dp_helper.c
+3
-4
drivers/gpu/drm/display/drm_dp_helper.c
···
778
778
* @aux: DisplayPort AUX channel
779
779
* @status: buffer to store the link status in (must be at least 6 bytes)
780
780
*
781
-
* Returns the number of bytes transferred on success or a negative error
782
-
* code on failure.
781
+
* Returns a negative error code on failure or 0 on success.
783
782
*/
784
783
int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
785
784
u8 status[DP_LINK_STATUS_SIZE])
786
785
{
787
-
return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
788
-
DP_LINK_STATUS_SIZE);
786
+
return drm_dp_dpcd_read_data(aux, DP_LANE0_1_STATUS, status,
787
+
DP_LINK_STATUS_SIZE);
789
788
}
790
789
EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
791
790
+2
-2
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
+2
-2
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
···
188
188
drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
189
189
190
190
ret = drm_dp_dpcd_read_link_status(&dp->aux, lane_status);
191
-
if (ret != DP_LINK_STATUS_SIZE) {
191
+
if (ret) {
192
192
drm_err(dp->dev, "Get lane status failed\n");
193
193
return ret;
194
194
}
···
236
236
drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
237
237
238
238
ret = drm_dp_dpcd_read_link_status(&dp->aux, lane_status);
239
-
if (ret != DP_LINK_STATUS_SIZE) {
239
+
if (ret) {
240
240
drm_err(dp->dev, "get lane status failed\n");
241
241
break;
242
242
}
+5
-19
drivers/gpu/drm/msm/dp/dp_ctrl.c
+5
-19
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
1099
1099
return ret == 1;
1100
1100
}
1101
1101
1102
-
static int msm_dp_ctrl_read_link_status(struct msm_dp_ctrl_private *ctrl,
1103
-
u8 *link_status)
1104
-
{
1105
-
int ret = 0, len;
1106
-
1107
-
len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1108
-
if (len != DP_LINK_STATUS_SIZE) {
1109
-
DRM_ERROR("DP link status read failed, err: %d\n", len);
1110
-
ret = -EINVAL;
1111
-
}
1112
-
1113
-
return ret;
1114
-
}
1115
-
1116
1102
static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl,
1117
1103
int *training_step)
1118
1104
{
···
1125
1139
for (tries = 0; tries < maximum_retries; tries++) {
1126
1140
drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1127
1141
1128
-
ret = msm_dp_ctrl_read_link_status(ctrl, link_status);
1142
+
ret = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1129
1143
if (ret)
1130
1144
return ret;
1131
1145
···
1237
1251
for (tries = 0; tries <= maximum_retries; tries++) {
1238
1252
drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1239
1253
1240
-
ret = msm_dp_ctrl_read_link_status(ctrl, link_status);
1254
+
ret = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1241
1255
if (ret)
1242
1256
return ret;
1243
1257
···
1790
1804
u8 link_status[DP_LINK_STATUS_SIZE];
1791
1805
int num_lanes = ctrl->link->link_params.num_lanes;
1792
1806
1793
-
msm_dp_ctrl_read_link_status(ctrl, link_status);
1807
+
drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1794
1808
1795
1809
return drm_dp_channel_eq_ok(link_status, num_lanes);
1796
1810
}
···
1848
1862
if (!msm_dp_catalog_link_is_connected(ctrl->catalog))
1849
1863
break;
1850
1864
1851
-
msm_dp_ctrl_read_link_status(ctrl, link_status);
1865
+
drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1852
1866
1853
1867
rc = msm_dp_ctrl_link_rate_down_shift(ctrl);
1854
1868
if (rc < 0) { /* already in RBR = 1.6G */
···
1873
1887
if (!msm_dp_catalog_link_is_connected(ctrl->catalog))
1874
1888
break;
1875
1889
1876
-
msm_dp_ctrl_read_link_status(ctrl, link_status);
1890
+
drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1877
1891
1878
1892
if (!drm_dp_clock_recovery_ok(link_status,
1879
1893
ctrl->link->link_params.num_lanes))
+9
-9
drivers/gpu/drm/msm/dp/dp_link.c
+9
-9
drivers/gpu/drm/msm/dp/dp_link.c
···
714
714
715
715
static int msm_dp_link_parse_sink_status_field(struct msm_dp_link_private *link)
716
716
{
717
-
int len;
717
+
int ret;
718
718
719
719
link->prev_sink_count = link->msm_dp_link.sink_count;
720
-
len = drm_dp_read_sink_count(link->aux);
721
-
if (len < 0) {
720
+
ret = drm_dp_read_sink_count(link->aux);
721
+
if (ret < 0) {
722
722
DRM_ERROR("DP parse sink count failed\n");
723
-
return len;
723
+
return ret;
724
724
}
725
-
link->msm_dp_link.sink_count = len;
725
+
link->msm_dp_link.sink_count = ret;
726
726
727
-
len = drm_dp_dpcd_read_link_status(link->aux,
728
-
link->link_status);
729
-
if (len < DP_LINK_STATUS_SIZE) {
727
+
ret = drm_dp_dpcd_read_link_status(link->aux,
728
+
link->link_status);
729
+
if (ret < 0) {
730
730
DRM_ERROR("DP link status read failed\n");
731
-
return len;
731
+
return ret;
732
732
}
733
733
734
734
return msm_dp_link_parse_request(link);
+4
-4
drivers/gpu/drm/radeon/atombios_dp.c
+4
-4
drivers/gpu/drm/radeon/atombios_dp.c
···
501
501
u8 link_status[DP_LINK_STATUS_SIZE];
502
502
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
503
503
504
-
if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
505
-
<= 0)
504
+
if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux,
505
+
link_status) < 0)
506
506
return false;
507
507
if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
508
508
return false;
···
678
678
drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
679
679
680
680
if (drm_dp_dpcd_read_link_status(dp_info->aux,
681
-
dp_info->link_status) <= 0) {
681
+
dp_info->link_status) < 0) {
682
682
DRM_ERROR("displayport link status failed\n");
683
683
break;
684
684
}
···
741
741
drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
742
742
743
743
if (drm_dp_dpcd_read_link_status(dp_info->aux,
744
-
dp_info->link_status) <= 0) {
744
+
dp_info->link_status) < 0) {
745
745
DRM_ERROR("displayport link status failed\n");
746
746
break;
747
747
}