Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: make normalize reg addr to common func for soc v1
Normalize registers address to local xcc address for sdma v7_1.
Merge normalize register address function to an common function
for soc v1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Likun Gao
and committed by
Alex Deucher
fcc4fc75
382dd7d2
+45
-42
+4
-25
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+4
-25
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
···
59
59
(SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
60
60
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
61
61
62
-
#define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */
63
-
#define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */
64
-
#define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */
65
-
#define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */
66
-
#define NORMALIZE_XCC_REG_OFFSET(offset) \
67
-
(offset & 0xFFFF)
68
-
69
62
static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);
70
63
static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev);
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64
static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev);
···
221
228
adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs;
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229
}
223
230
224
-
static uint32_t gfx_v12_1_normalize_xcc_reg_offset(uint32_t reg)
225
-
{
226
-
uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);
227
-
228
-
/* If it is an XCC reg, normalize the reg to keep
229
-
lower 16 bits in local xcc */
230
-
231
-
if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) ||
232
-
((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH)))
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-
return normalized_reg;
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-
else
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-
return reg;
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-
}
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-
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static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
239
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int mem_space, int opt, uint32_t addr0,
240
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uint32_t addr1, uint32_t ref,
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uint32_t mask, uint32_t inv)
242
235
{
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if (mem_space == 0) {
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-
addr0 = gfx_v12_1_normalize_xcc_reg_offset(addr0);
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-
addr1 = gfx_v12_1_normalize_xcc_reg_offset(addr1);
237
+
addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0);
238
+
addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1);
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}
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
···
3405
3426
{
3406
3427
struct amdgpu_device *adev = ring->adev;
3407
3428
3408
-
reg = gfx_v12_1_normalize_xcc_reg_offset(reg);
3429
+
reg = soc_v1_0_normalize_xcc_reg_offset(reg);
3409
3430
3410
3431
amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3411
3432
amdgpu_ring_write(ring, 0 | /* src: register*/
···
3425
3446
{
3426
3447
uint32_t cmd = 0;
3427
3448
3428
-
reg = gfx_v12_1_normalize_xcc_reg_offset(reg);
3449
+
reg = soc_v1_0_normalize_xcc_reg_offset(reg);
3429
3450
3430
3451
switch (ring->funcs->type) {
3431
3452
case AMDGPU_RING_TYPE_KIQ:
+7
-15
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
+7
-15
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
···
45
45
#define MES_EOP_SIZE 2048
46
46
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47
#define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000
48
-
#define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */
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-
#define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */
50
-
#define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */
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-
#define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */
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48
#define XCC_MID_MASK 0x41000000
53
-
54
-
#define NORMALIZE_XCC_REG_OFFSET(offset) \
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-
(offset & 0x3FFFF)
56
49
57
50
static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring)
58
51
{
···
501
508
static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id,
502
509
struct RRMT_OPTION *rrmt_opt)
503
510
{
504
-
uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);
511
+
uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
505
512
506
-
if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) ||
507
-
((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) {
513
+
if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) {
508
514
rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg);
509
515
rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ?
510
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MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD;
···
540
548
&misc_pkt.read_reg.rrmt_opt);
541
549
if (misc_pkt.read_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
542
550
misc_pkt.read_reg.reg_offset =
543
-
NORMALIZE_XCC_REG_OFFSET(misc_pkt.read_reg.reg_offset);
551
+
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset);
544
552
}
545
553
break;
546
554
case MES_MISC_OP_WRITE_REG:
···
552
560
&misc_pkt.write_reg.rrmt_opt);
553
561
if (misc_pkt.write_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
554
562
misc_pkt.write_reg.reg_offset =
555
-
NORMALIZE_XCC_REG_OFFSET(misc_pkt.write_reg.reg_offset);
563
+
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset);
556
564
}
557
565
break;
558
566
case MES_MISC_OP_WRM_REG_WAIT:
···
567
575
&misc_pkt.wait_reg_mem.rrmt_opt1);
568
576
if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
569
577
misc_pkt.wait_reg_mem.reg_offset1 =
570
-
NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset1);
578
+
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
571
579
}
572
580
break;
573
581
case MES_MISC_OP_WRM_REG_WR_WAIT:
···
586
594
587
595
if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
588
596
misc_pkt.wait_reg_mem.reg_offset1 =
589
-
NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset1);
597
+
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
590
598
}
591
599
if (misc_pkt.wait_reg_mem.rrmt_opt2.mode != MES_RRMT_MODE_REMOTE_MID) {
592
600
misc_pkt.wait_reg_mem.reg_offset2 =
593
-
NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset2);
601
+
soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset2);
594
602
}
595
603
break;
596
604
case MES_MISC_OP_SET_SHADER_DEBUGGER:
+3
-2
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+3
-2
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
···
42
42
#include "sdma_v7_1.h"
43
43
#include "v12_structs.h"
44
44
#include "mes_userqueue.h"
45
+
#include "soc_v1_0.h"
45
46
46
47
MODULE_FIRMWARE("amdgpu/sdma_7_1_0.bin");
47
48
···
1221
1220
* Use Register WRITE command instead, which OPCODE is same as SRBM WRITE
1222
1221
*/
1223
1222
amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE));
1224
-
amdgpu_ring_write(ring, reg << 2);
1223
+
amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2);
1225
1224
amdgpu_ring_write(ring, val);
1226
1225
}
1227
1226
···
1230
1229
{
1231
1230
amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1232
1231
SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1233
-
amdgpu_ring_write(ring, reg << 2);
1232
+
amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2);
1234
1233
amdgpu_ring_write(ring, 0);
1235
1234
amdgpu_ring_write(ring, val); /* reference */
1236
1235
amdgpu_ring_write(ring, mask); /* mask */
+29
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
+29
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
···
34
34
#include "gc/gc_12_1_0_sh_mask.h"
35
35
#include "mp/mp_15_0_8_offset.h"
36
36
37
+
#define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */
38
+
#define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */
39
+
#define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */
40
+
#define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */
41
+
#define NORMALIZE_XCC_REG_OFFSET(offset) \
42
+
(offset & 0xFFFF)
43
+
37
44
/* Initialized doorbells for amdgpu including multimedia
38
45
* KFD can use all the rest in 2M doorbell bar */
39
46
static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev)
···
790
783
amdgpu_ip_map_init(adev);
791
784
792
785
return 0;
786
+
}
787
+
788
+
bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg)
789
+
{
790
+
if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) ||
791
+
((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH)))
792
+
return true;
793
+
else
794
+
return false;
795
+
}
796
+
797
+
uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg)
798
+
{
799
+
uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);
800
+
801
+
/* If it is an XCC reg, normalize the reg to keep
802
+
* lower 16 bits in local xcc */
803
+
804
+
if (soc_v1_0_normalize_xcc_reg_range(normalized_reg))
805
+
return normalized_reg;
806
+
else
807
+
return reg;
793
808
}