Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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os
linux
Merge tag 'thead-dt-for-v6.13' of https://github.com/pdp7/linux into soc/dt
T-HEAD Devicetrees for v6.13
Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. The
yaml binding and pinctrl-th1520 driver has been merged into next by
Linus W and will be included in the 6.13 pinctrl PR.
The TH1520 GPIO controllers are already supported by the gpio-dwapb
driver. This PR improves GPIO support by adding GPIO ranges and GPIO
line names for the BeagleV Ahead and LicheePi 4A boards. Support is
added for the built-in LEDs on the Ahead board.
Signed-off-by: Drew Fustini <drew@pdp7.com>
* tag 'thead-dt-for-v6.13' of https://github.com/pdp7/linux:
riscv: dts: thead: remove enabled property for spi0
riscv: dts: thead: Add missing GPIO clock-names
riscv: dtb: thead: Add BeagleV Ahead LEDs
riscv: dts: thead: Add TH1520 pinctrl settings for UART0
riscv: dts: thead: Add Lichee Pi 4M GPIO line names
riscv: dts: thead: Adjust TH1520 GPIO labels
riscv: dts: thead: Add TH1520 GPIO ranges
riscv: dts: thead: Add TH1520 pin control nodes
+202
-23
+82
-4
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+82
-4
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
···
7
7
/dts-v1/;
8
8
9
9
#include "th1520.dtsi"
10
+
#include <dt-bindings/gpio/gpio.h>
11
+
#include <dt-bindings/leds/common.h>
10
12
11
13
/ {
12
14
model = "BeagleV Ahead";
···
19
17
gpio1 = &gpio1;
20
18
gpio2 = &gpio2;
21
19
gpio3 = &gpio3;
20
+
gpio4 = &gpio4;
21
+
gpio5 = &aogpio;
22
22
serial0 = &uart0;
23
23
serial1 = &uart1;
24
24
serial2 = &uart2;
···
37
33
memory@0 {
38
34
device_type = "memory";
39
35
reg = <0x0 0x00000000 0x1 0x00000000>;
36
+
};
40
37
38
+
leds {
39
+
pinctrl-names = "default";
40
+
pinctrl-0 = <&led_pins>;
41
+
compatible = "gpio-leds";
42
+
43
+
led-1 {
44
+
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
45
+
color = <LED_COLOR_ID_BLUE>;
46
+
label = "led1";
47
+
};
48
+
49
+
led-2 {
50
+
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
51
+
color = <LED_COLOR_ID_BLUE>;
52
+
label = "led2";
53
+
};
54
+
55
+
led-3 {
56
+
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
57
+
color = <LED_COLOR_ID_BLUE>;
58
+
label = "led3";
59
+
};
60
+
61
+
led-4 {
62
+
gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
63
+
color = <LED_COLOR_ID_BLUE>;
64
+
label = "led4";
65
+
};
66
+
67
+
led-5 {
68
+
gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
69
+
color = <LED_COLOR_ID_BLUE>;
70
+
label = "led5";
71
+
};
41
72
};
42
73
};
43
74
···
98
59
status = "okay";
99
60
};
100
61
62
+
&padctrl_aosys {
63
+
led_pins: led-0 {
64
+
led-pins {
65
+
pins = "AUDIO_PA8", /* GPIO4_8 */
66
+
"AUDIO_PA9", /* GPIO4_9 */
67
+
"AUDIO_PA10", /* GPIO4_10 */
68
+
"AUDIO_PA11", /* GPIO4_11 */
69
+
"AUDIO_PA12"; /* GPIO4_12 */
70
+
bias-disable;
71
+
drive-strength = <3>;
72
+
input-disable;
73
+
input-schmitt-disable;
74
+
slew-rate = <0>;
75
+
};
76
+
};
77
+
};
78
+
79
+
&padctrl0_apsys {
80
+
uart0_pins: uart0-0 {
81
+
tx-pins {
82
+
pins = "UART0_TXD";
83
+
function = "uart";
84
+
bias-disable;
85
+
drive-strength = <3>;
86
+
input-disable;
87
+
input-schmitt-disable;
88
+
slew-rate = <0>;
89
+
};
90
+
91
+
rx-pins {
92
+
pins = "UART0_RXD";
93
+
function = "uart";
94
+
bias-pull-up;
95
+
drive-strength = <1>;
96
+
input-enable;
97
+
input-schmitt-enable;
98
+
slew-rate = <0>;
99
+
};
100
+
};
101
+
};
102
+
101
103
&sdio0 {
102
104
bus-width = <4>;
103
105
max-frequency = <198000000>;
···
146
66
};
147
67
148
68
&uart0 {
149
-
status = "okay";
150
-
};
151
-
152
-
&spi0 {
69
+
pinctrl-names = "default";
70
+
pinctrl-0 = <&uart0_pins>;
153
71
status = "okay";
154
72
};
+39
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+39
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
···
25
25
clock-frequency = <32768>;
26
26
};
27
27
28
+
&aogpio {
29
+
gpio-line-names = "", "", "",
30
+
"GPIO00",
31
+
"GPIO04";
32
+
};
33
+
28
34
&dmac0 {
29
35
status = "okay";
30
36
};
···
43
37
no-sdio;
44
38
no-sd;
45
39
status = "okay";
40
+
};
41
+
42
+
&gpio0 {
43
+
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
44
+
"", "", "", "", "", "", "", "", "", "",
45
+
"", "", "", "",
46
+
"GPIO07",
47
+
"GPIO08",
48
+
"",
49
+
"GPIO01",
50
+
"GPIO02";
51
+
};
52
+
53
+
&gpio1 {
54
+
gpio-line-names = "", "", "",
55
+
"GPIO11",
56
+
"GPIO12",
57
+
"GPIO13",
58
+
"GPIO14",
59
+
"", "", "", "", "", "", "", "", "", "",
60
+
"", "", "", "", "",
61
+
"GPIO06";
62
+
};
63
+
64
+
&gpio2 {
65
+
gpio-line-names = "GPIO03",
66
+
"GPIO05";
67
+
};
68
+
69
+
&gpio3 {
70
+
gpio-line-names = "", "",
71
+
"GPIO09",
72
+
"GPIO10";
46
73
};
47
74
48
75
&sdio0 {
+27
-3
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+27
-3
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
···
14
14
gpio1 = &gpio1;
15
15
gpio2 = &gpio2;
16
16
gpio3 = &gpio3;
17
+
gpio4 = &gpio4;
18
+
gpio5 = &aogpio;
17
19
serial0 = &uart0;
18
20
serial1 = &uart1;
19
21
serial2 = &uart2;
···
30
28
};
31
29
};
32
30
33
-
&uart0 {
34
-
status = "okay";
31
+
&padctrl0_apsys {
32
+
uart0_pins: uart0-0 {
33
+
tx-pins {
34
+
pins = "UART0_TXD";
35
+
function = "uart";
36
+
bias-disable;
37
+
drive-strength = <3>;
38
+
input-disable;
39
+
input-schmitt-disable;
40
+
slew-rate = <0>;
41
+
};
42
+
43
+
rx-pins {
44
+
pins = "UART0_RXD";
45
+
function = "uart";
46
+
bias-disable;
47
+
drive-strength = <1>;
48
+
input-enable;
49
+
input-schmitt-enable;
50
+
slew-rate = <0>;
51
+
};
52
+
};
35
53
};
36
54
37
-
&spi0 {
55
+
&uart0 {
56
+
pinctrl-names = "default";
57
+
pinctrl-0 = <&uart0_pins>;
38
58
status = "okay";
39
59
};
+54
-16
arch/riscv/boot/dts/thead/th1520.dtsi
+54
-16
arch/riscv/boot/dts/thead/th1520.dtsi
···
216
216
#clock-cells = <0>;
217
217
};
218
218
219
+
aonsys_clk: clock-73728000 {
220
+
compatible = "fixed-clock";
221
+
clock-frequency = <73728000>;
222
+
clock-output-names = "aonsys_clk";
223
+
#clock-cells = <0>;
224
+
};
225
+
219
226
soc {
220
227
compatible = "simple-bus";
221
228
interrupt-parent = <&plic>;
···
323
316
status = "disabled";
324
317
};
325
318
326
-
gpio2: gpio@ffe7f34000 {
319
+
gpio@ffe7f34000 {
327
320
compatible = "snps,dw-apb-gpio";
328
321
reg = <0xff 0xe7f34000 0x0 0x1000>;
329
322
#address-cells = <1>;
330
323
#size-cells = <0>;
331
324
clocks = <&clk CLK_GPIO2>;
325
+
clock-names = "bus";
332
326
333
-
portc: gpio-controller@0 {
327
+
gpio2: gpio-controller@0 {
334
328
compatible = "snps,dw-apb-gpio-port";
335
329
gpio-controller;
336
330
#gpio-cells = <2>;
337
331
ngpios = <32>;
332
+
gpio-ranges = <&padctrl0_apsys 0 0 32>;
338
333
reg = <0>;
339
334
interrupt-controller;
340
335
#interrupt-cells = <2>;
···
344
335
};
345
336
};
346
337
347
-
gpio3: gpio@ffe7f38000 {
338
+
gpio@ffe7f38000 {
348
339
compatible = "snps,dw-apb-gpio";
349
340
reg = <0xff 0xe7f38000 0x0 0x1000>;
350
341
#address-cells = <1>;
351
342
#size-cells = <0>;
352
343
clocks = <&clk CLK_GPIO3>;
344
+
clock-names = "bus";
353
345
354
-
portd: gpio-controller@0 {
346
+
gpio3: gpio-controller@0 {
355
347
compatible = "snps,dw-apb-gpio-port";
356
348
gpio-controller;
357
349
#gpio-cells = <2>;
358
-
ngpios = <32>;
350
+
ngpios = <23>;
351
+
gpio-ranges = <&padctrl0_apsys 0 32 23>;
359
352
reg = <0>;
360
353
interrupt-controller;
361
354
#interrupt-cells = <2>;
···
365
354
};
366
355
};
367
356
368
-
gpio0: gpio@ffec005000 {
357
+
padctrl1_apsys: pinctrl@ffe7f3c000 {
358
+
compatible = "thead,th1520-pinctrl";
359
+
reg = <0xff 0xe7f3c000 0x0 0x1000>;
360
+
clocks = <&clk CLK_PADCTRL1>;
361
+
thead,pad-group = <2>;
362
+
};
363
+
364
+
gpio@ffec005000 {
369
365
compatible = "snps,dw-apb-gpio";
370
366
reg = <0xff 0xec005000 0x0 0x1000>;
371
367
#address-cells = <1>;
372
368
#size-cells = <0>;
373
369
clocks = <&clk CLK_GPIO0>;
370
+
clock-names = "bus";
374
371
375
-
porta: gpio-controller@0 {
372
+
gpio0: gpio-controller@0 {
376
373
compatible = "snps,dw-apb-gpio-port";
377
374
gpio-controller;
378
375
#gpio-cells = <2>;
379
376
ngpios = <32>;
377
+
gpio-ranges = <&padctrl1_apsys 0 0 32>;
380
378
reg = <0>;
381
379
interrupt-controller;
382
380
#interrupt-cells = <2>;
···
393
373
};
394
374
};
395
375
396
-
gpio1: gpio@ffec006000 {
376
+
gpio@ffec006000 {
397
377
compatible = "snps,dw-apb-gpio";
398
378
reg = <0xff 0xec006000 0x0 0x1000>;
399
379
#address-cells = <1>;
400
380
#size-cells = <0>;
401
381
clocks = <&clk CLK_GPIO1>;
382
+
clock-names = "bus";
402
383
403
-
portb: gpio-controller@0 {
384
+
gpio1: gpio-controller@0 {
404
385
compatible = "snps,dw-apb-gpio-port";
405
386
gpio-controller;
406
387
#gpio-cells = <2>;
407
-
ngpios = <32>;
388
+
ngpios = <31>;
389
+
gpio-ranges = <&padctrl1_apsys 0 32 31>;
408
390
reg = <0>;
409
391
interrupt-controller;
410
392
#interrupt-cells = <2>;
411
393
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
412
394
};
395
+
};
396
+
397
+
padctrl0_apsys: pinctrl@ffec007000 {
398
+
compatible = "thead,th1520-pinctrl";
399
+
reg = <0xff 0xec007000 0x0 0x1000>;
400
+
clocks = <&clk CLK_PADCTRL0>;
401
+
thead,pad-group = <3>;
413
402
};
414
403
415
404
uart2: serial@ffec010000 {
···
549
520
status = "disabled";
550
521
};
551
522
552
-
ao_gpio0: gpio@fffff41000 {
523
+
gpio@fffff41000 {
553
524
compatible = "snps,dw-apb-gpio";
554
525
reg = <0xff 0xfff41000 0x0 0x1000>;
555
526
#address-cells = <1>;
556
527
#size-cells = <0>;
557
528
558
-
porte: gpio-controller@0 {
529
+
aogpio: gpio-controller@0 {
559
530
compatible = "snps,dw-apb-gpio-port";
560
531
gpio-controller;
561
532
#gpio-cells = <2>;
562
-
ngpios = <32>;
533
+
ngpios = <16>;
534
+
gpio-ranges = <&padctrl_aosys 0 9 16>;
563
535
reg = <0>;
564
536
interrupt-controller;
565
537
#interrupt-cells = <2>;
···
568
538
};
569
539
};
570
540
571
-
ao_gpio1: gpio@fffff52000 {
541
+
padctrl_aosys: pinctrl@fffff4a000 {
542
+
compatible = "thead,th1520-pinctrl";
543
+
reg = <0xff 0xfff4a000 0x0 0x2000>;
544
+
clocks = <&aonsys_clk>;
545
+
thead,pad-group = <1>;
546
+
};
547
+
548
+
gpio@fffff52000 {
572
549
compatible = "snps,dw-apb-gpio";
573
550
reg = <0xff 0xfff52000 0x0 0x1000>;
574
551
#address-cells = <1>;
575
552
#size-cells = <0>;
576
553
577
-
portf: gpio-controller@0 {
554
+
gpio4: gpio-controller@0 {
578
555
compatible = "snps,dw-apb-gpio-port";
579
556
gpio-controller;
580
557
#gpio-cells = <2>;
581
-
ngpios = <32>;
558
+
ngpios = <23>;
559
+
gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
582
560
reg = <0>;
583
561
interrupt-controller;
584
562
#interrupt-cells = <2>;