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drm/amd/display: Enable CM low mem power optimization

[WHY & HOW]
MPC MCM low mem power optimization still causes color distortion on
first SCE enablement, only forces light sleep for it.

DPP low memory power optimization still needs this bit to save power.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Yihan Zhu <yihan.zhu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Yihan Zhu and committed by
Alex Deucher
fcfc6cee ef71bb41

+9 -6
+8 -5
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
··· 71 71 { 72 72 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 73 73 74 + /* 74 75 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) { 75 76 if (power_on) { 76 77 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0); 77 78 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5); 78 79 } else if (!mpc->ctx->dc->debug.disable_mem_low_power) { 79 - ASSERT(false); 80 - /* TODO: change to mpc 81 - * dpp_base->ctx->dc->optimized_required = true; 82 - * dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; 83 - */ 80 + //TODO: change to mpc 81 + dpp_base->ctx->dc->optimized_required = true; 82 + dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; 84 83 } 85 84 } else { 86 85 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, 87 86 MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1); 88 87 } 88 + */ 89 + 90 + REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, 91 + MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1); 89 92 } 90 93 91 94 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
+1 -1
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
··· 724 724 .i2c = true, 725 725 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 726 726 .dscl = true, 727 - .cm = false, 727 + .cm = true, 728 728 .mpc = true, 729 729 .optc = true, 730 730 .vpg = true,