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EDAC/altera: Handle OCRAM ECC enable after warm reset

The OCRAM ECC is always enabled either by the BootROM or by the Secure Device
Manager (SDM) during a power-on reset on SoCFPGA.

However, during a warm reset, the OCRAM content is retained to preserve data,
while the control and status registers are reset to their default values. As
a result, ECC must be explicitly re-enabled after a warm reset.

Fixes: 17e47dc6db4f ("EDAC/altera: Add Stratix10 OCRAM ECC support")
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111080801.1279401-1-niravkumarlaxmidas.rabara@altera.com

authored by

Niravkumar L Rabara and committed by
Borislav Petkov (AMD) fd3ecda3 2cf95b9b

+15 -3
+15 -3
drivers/edac/altera_edac.c
··· 1184 1184 if (ret) 1185 1185 return ret; 1186 1186 1187 - /* Verify OCRAM has been initialized */ 1187 + /* 1188 + * Verify that OCRAM has been initialized. 1189 + * During a warm reset, OCRAM contents are retained, but the control 1190 + * and status registers are reset to their default values. Therefore, 1191 + * ECC must be explicitly re-enabled in the control register. 1192 + * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set. 1193 + */ 1188 1194 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, 1189 - (base + ALTR_A10_ECC_INITSTAT_OFST))) 1190 - return -ENODEV; 1195 + (base + ALTR_A10_ECC_INITSTAT_OFST))) { 1196 + if (!ecc_test_bits(ALTR_A10_ECC_EN, 1197 + (base + ALTR_A10_ECC_CTRL_OFST))) 1198 + ecc_set_bits(ALTR_A10_ECC_EN, 1199 + (base + ALTR_A10_ECC_CTRL_OFST)); 1200 + else 1201 + return -ENODEV; 1202 + } 1191 1203 1192 1204 /* Enable IRQ on Single Bit Error */ 1193 1205 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));