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drm/msm/dsi/phy: fix hardware revision

The hardware revision for TSMC 3nm-based Qualcomm SOCs should be 7.2,
this can be confirmed from REG_DSI_7nm_PHY_CMN_REVISION_ID0, the value
is 0x27, which means hardware revision is 7.2

No functional change.

Fixes: 1337d7ebfb6d ("drm/msm/dsi/phy: Add support for SM8750")
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/707414/
Link: https://lore.kernel.org/r/20260226122958.22555-2-mitltlatltl@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Pengyu Luo and committed by
Dmitry Baryshkov fd941c78 7403e87c

+11 -11
+11 -11
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
··· 51 51 #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) 52 52 /* Hardware is V5.2 */ 53 53 #define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) 54 - /* Hardware is V7.0 */ 55 - #define DSI_PHY_7NM_QUIRK_V7_0 BIT(5) 54 + /* Hardware is V7.2 */ 55 + #define DSI_PHY_7NM_QUIRK_V7_2 BIT(5) 56 56 57 57 struct dsi_pll_config { 58 58 bool enable_ssc; ··· 143 143 144 144 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { 145 145 config->pll_clock_inverters = 0x28; 146 - } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { 146 + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) { 147 147 if (pll_freq < 163000000ULL) 148 148 config->pll_clock_inverters = 0xa0; 149 149 else if (pll_freq < 175000000ULL) ··· 284 284 } 285 285 286 286 if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || 287 - (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { 287 + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) { 288 288 if (pll->vco_current_rate < 1557000000ULL) 289 289 vco_config_1 = 0x08; 290 290 else ··· 699 699 case MSM_DSI_PHY_MASTER: 700 700 pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; 701 701 /* v7.0: Enable ATB_EN0 and alternate clock output to external phy */ 702 - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) 702 + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2) 703 703 writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5); 704 704 break; 705 705 case MSM_DSI_PHY_SLAVE: ··· 987 987 /* Request for REFGEN READY */ 988 988 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || 989 989 (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || 990 - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { 990 + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) { 991 991 writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); 992 992 udelay(500); 993 993 } ··· 1021 1021 lane_ctrl0 = 0x1f; 1022 1022 } 1023 1023 1024 - if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { 1024 + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) { 1025 1025 if (phy->cphy_mode) { 1026 1026 /* TODO: different for second phy */ 1027 1027 vreg_ctrl_0 = 0x57; ··· 1097 1097 1098 1098 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ 1099 1099 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || 1100 - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) || 1100 + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2) || 1101 1101 (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20) 1102 1102 writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4); 1103 1103 ··· 1213 1213 /* Turn off REFGEN Vote */ 1214 1214 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || 1215 1215 (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || 1216 - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { 1216 + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) { 1217 1217 writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); 1218 1218 wmb(); 1219 1219 /* Delay to ensure HW removes vote before PHY shut down */ ··· 1502 1502 #endif 1503 1503 .io_start = { 0xae95000, 0xae97000 }, 1504 1504 .num_dsi_phy = 2, 1505 - .quirks = DSI_PHY_7NM_QUIRK_V7_0, 1505 + .quirks = DSI_PHY_7NM_QUIRK_V7_2, 1506 1506 }; 1507 1507 1508 1508 const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = { ··· 1525 1525 #endif 1526 1526 .io_start = { 0x9ac1000, 0x9ac4000 }, 1527 1527 .num_dsi_phy = 2, 1528 - .quirks = DSI_PHY_7NM_QUIRK_V7_0, 1528 + .quirks = DSI_PHY_7NM_QUIRK_V7_2, 1529 1529 };