bnxt_en: Update FW interface to 1.10.3.151

+153 -18

2 changed files

expand all

drivers

infiniband

bnxt_re

main.c

include

linux

bnxt

hsi.h

+2 -2

drivers/infiniband/hw/bnxt_re/main.c

··· 595 595 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VNIC_CFG); 596 596 597 597 req.flags = cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE); 598 - req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_RAW_QP_ID | 598 + req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_QP_ID | 599 599 VNIC_CFG_REQ_ENABLES_MRU); 600 600 req.vnic_id = cpu_to_le16(rdev->mirror_vnic_id); 601 - req.raw_qp_id = cpu_to_le32(qp_id); 601 + req.qp_id = cpu_to_le32(qp_id); 602 602 req.mru = cpu_to_le16(rdev->netdev->mtu + VLAN_ETH_HLEN); 603 603 604 604 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), NULL,

+151 -16

include/linux/bnxt/hsi.h

··· 187 187 #define HWRM_RING_QCFG 0x63UL 188 188 #define HWRM_RESERVED5 0x64UL 189 189 #define HWRM_RESERVED6 0x65UL 190 + #define HWRM_PORT_ADSM_QSTATES 0x66UL 191 + #define HWRM_PORT_EVENTS_LOG 0x67UL 190 192 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 191 193 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 192 194 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL ··· 237 235 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 238 236 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 239 237 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 240 - #define HWRM_RESERVED7 0xbaUL 238 + #define HWRM_PORT_QSTATS_EXT_PFC_ADV 0xbaUL 241 239 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 242 240 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 243 241 #define HWRM_PORT_ECN_QSTATS 0xbdUL ··· 273 271 #define HWRM_PORT_EP_TX_CFG 0xdbUL 274 272 #define HWRM_PORT_CFG 0xdcUL 275 273 #define HWRM_PORT_QCFG 0xddUL 274 + #define HWRM_PORT_DSC_COLLECTION 0xdeUL 276 275 #define HWRM_PORT_MAC_QCAPS 0xdfUL 277 276 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 278 277 #define HWRM_REG_POWER_QUERY 0xe1UL ··· 283 280 #define HWRM_MONITOR_PAX_HISTOGRAM_COLLECT 0xe5UL 284 281 #define HWRM_STAT_QUERY_ROCE_STATS 0xe6UL 285 282 #define HWRM_STAT_QUERY_ROCE_STATS_EXT 0xe7UL 283 + #define HWRM_MONITOR_DEVICE_HEALTH 0xe8UL 286 284 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 287 285 #define HWRM_WOL_FILTER_FREE 0xf1UL 288 286 #define HWRM_WOL_FILTER_QCFG 0xf2UL ··· 644 640 #define HWRM_VERSION_MAJOR 1 645 641 #define HWRM_VERSION_MINOR 10 646 642 #define HWRM_VERSION_UPDATE 3 647 - #define HWRM_VERSION_RSVD 133 648 - #define HWRM_VERSION_STR "1.10.3.133" 643 + #define HWRM_VERSION_RSVD 151 644 + #define HWRM_VERSION_STR "1.10.3.151" 649 645 650 646 /* hwrm_ver_get_input (size:192b/24B) */ 651 647 struct hwrm_ver_get_input { ··· 1420 1416 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DB_DROP 0x8UL 1421 1417 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MD_TEMP 0x9UL 1422 1418 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 0xaUL 1423 - #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 1419 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_L2_TX_RING 0xbUL 1420 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_L2_TX_RING 1424 1421 }; 1425 1422 1426 1423 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ ··· 1939 1934 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_COMPLIANCE_SUPPORTED 0x100UL 1940 1935 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MULTI_L2_DB_SUPPORTED 0x200UL 1941 1936 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_SECURE_ATS_SUPPORTED 0x400UL 1942 - #define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_STATS_SUPPORTED 0x800UL 1937 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_DATA_SUPPORTED 0x800UL 1938 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_CMPL_TS_SUPPORTED 0x1000UL 1939 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_ST_SUPPORTED 0x2000UL 1943 1940 __le16 max_roce_vfs; 1944 1941 __le16 max_crypto_rx_flow_filters; 1945 1942 u8 unused_3[3]; ··· 4448 4441 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4449 4442 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4450 4443 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4451 - #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4444 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_224 0x7d3UL 4445 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_224 0xfa3UL 4446 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_224 0x1f43UL 4447 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_224 4452 4448 __le16 auto_link_speeds2_mask; 4453 4449 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4454 4450 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL ··· 4467 4457 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4468 4458 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4469 4459 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 0x2000UL 4470 - u8 unused_2[6]; 4460 + __le16 auto_link_speeds2_ext_mask; 4461 + #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_200GB_PAM4_224 0x1UL 4462 + #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_400GB_PAM4_224 0x2UL 4463 + #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_800GB_PAM4_224 0x4UL 4464 + u8 unused_2[4]; 4471 4465 }; 4472 4466 4473 4467 /* hwrm_port_phy_cfg_output (size:128b/16B) */ ··· 4505 4491 u8 unused_0[6]; 4506 4492 }; 4507 4493 4508 - /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 4494 + /* hwrm_port_phy_qcfg_output (size:896b/112B) */ 4509 4495 struct hwrm_port_phy_qcfg_output { 4510 4496 __le16 error_code; 4511 4497 __le16 req_type; ··· 4515 4501 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4516 4502 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4517 4503 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4518 - #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 4504 + #define PORT_PHY_QCFG_RESP_LINK_NO_SD 0x3UL 4505 + #define PORT_PHY_QCFG_RESP_LINK_NO_LOCK 0x4UL 4506 + #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_NO_LOCK 4519 4507 u8 active_fec_signal_mode; 4520 4508 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4521 4509 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4522 4510 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4523 4511 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4524 4512 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4525 - #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 4513 + #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_224 0x3UL 4514 + #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_224 4526 4515 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4527 4516 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4528 4517 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) ··· 4716 4699 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8 0x3bUL 4717 4700 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8 0x3cUL 4718 4701 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL 4719 - #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 4702 + #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEDR4 0x3eUL 4703 + #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEFR4 0x3fUL 4704 + #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEFR4 4720 4705 u8 media_type; 4721 4706 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4722 4707 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL ··· 4878 4859 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4879 4860 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4880 4861 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4881 - #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4862 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_224 0x7d3UL 4863 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_224 0xfa3UL 4864 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_224 0x1f43UL 4865 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_224 4882 4866 __le16 auto_link_speeds2; 4883 4867 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4884 4868 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL ··· 4898 4876 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4899 4877 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4900 4878 u8 active_lanes; 4879 + u8 rsvd1; 4880 + __le16 support_speeds2_ext; 4881 + #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_200GB_PAM4_224 0x1UL 4882 + #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_400GB_PAM4_224 0x2UL 4883 + #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_800GB_PAM4_224 0x4UL 4884 + __le16 auto_link_speeds2_ext; 4885 + #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_200GB_PAM4_224 0x1UL 4886 + #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_400GB_PAM4_224 0x2UL 4887 + #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_800GB_PAM4_224 0x4UL 4888 + u8 rsvd2[3]; 4901 4889 u8 valid; 4902 4890 }; 4903 4891 ··· 5510 5478 u8 unused_0[6]; 5511 5479 }; 5512 5480 5513 - /* hwrm_port_phy_qcaps_output (size:320b/40B) */ 5481 + /* hwrm_port_phy_qcaps_output (size:384b/48B) */ 5514 5482 struct hwrm_port_phy_qcaps_output { 5515 5483 __le16 error_code; 5516 5484 __le16 req_type; ··· 5595 5563 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5596 5564 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5597 5565 #define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED 0x10UL 5566 + #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_ADV_STATS_SUPPORTED 0x20UL 5567 + #define PORT_PHY_QCAPS_RESP_FLAGS2_ADSM_REPORT_SUPPORTED 0x40UL 5568 + #define PORT_PHY_QCAPS_RESP_FLAGS2_PM_EVENT_LOG_SUPPORTED 0x80UL 5569 + #define PORT_PHY_QCAPS_RESP_FLAGS2_FDRSTAT_CMD_SUPPORTED 0x100UL 5598 5570 u8 internal_port_cnt; 5599 5571 u8 unused_0; 5600 5572 __le16 supported_speeds2_force_mode; ··· 5631 5595 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5632 5596 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5633 5597 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5634 - u8 unused_1[3]; 5598 + __le16 supported_speeds2_ext_force_mode; 5599 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_200GB_PAM4_224 0x1UL 5600 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_400GB_PAM4_224 0x2UL 5601 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_800GB_PAM4_224 0x4UL 5602 + __le16 supported_speeds2_ext_auto_mode; 5603 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_200GB_PAM4_224 0x1UL 5604 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_400GB_PAM4_224 0x2UL 5605 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_800GB_PAM4_224 0x4UL 5606 + u8 unused_1[7]; 5635 5607 u8 valid; 5636 5608 }; 5637 5609 ··· 6093 6049 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6094 6050 u8 unused_4[3]; 6095 6051 u8 valid; 6052 + }; 6053 + 6054 + /* hwrm_port_phy_fdrstat_input (size:192b/24B) */ 6055 + struct hwrm_port_phy_fdrstat_input { 6056 + __le16 req_type; 6057 + __le16 cmpl_ring; 6058 + __le16 seq_id; 6059 + __le16 target_id; 6060 + __le64 resp_addr; 6061 + __le16 port_id; 6062 + __le16 rsvd[2]; 6063 + __le16 ops; 6064 + #define PORT_PHY_FDRSTAT_REQ_OPS_START 0x0UL 6065 + #define PORT_PHY_FDRSTAT_REQ_OPS_STOP 0x1UL 6066 + #define PORT_PHY_FDRSTAT_REQ_OPS_CLEAR 0x2UL 6067 + #define PORT_PHY_FDRSTAT_REQ_OPS_COUNTER 0x3UL 6068 + #define PORT_PHY_FDRSTAT_REQ_OPS_LAST PORT_PHY_FDRSTAT_REQ_OPS_COUNTER 6069 + }; 6070 + 6071 + /* hwrm_port_phy_fdrstat_output (size:3072b/384B) */ 6072 + struct hwrm_port_phy_fdrstat_output { 6073 + __le16 error_code; 6074 + __le16 req_type; 6075 + __le16 seq_id; 6076 + __le16 resp_len; 6077 + __le64 start_time; 6078 + __le64 end_time; 6079 + __le64 cmic_start_time; 6080 + __le64 cmic_end_time; 6081 + __le64 accumulated_uncorrected_codewords; 6082 + __le64 accumulated_corrected_codewords; 6083 + __le64 accumulated_total_codewords; 6084 + __le64 accumulated_symbol_errors; 6085 + __le64 accumulated_codewords_err_s[17]; 6086 + __le64 uncorrected_codewords; 6087 + __le64 corrected_codewords; 6088 + __le64 total_codewords; 6089 + __le64 symbol_errors; 6090 + __le64 codewords_err_s[17]; 6091 + __le32 window_size; 6092 + __le16 unused_0[1]; 6093 + u8 unused_1; 6094 + u8 valid; 6095 + }; 6096 + 6097 + /* hwrm_port_phy_fdrstat_cmd_err (size:64b/8B) */ 6098 + struct hwrm_port_phy_fdrstat_cmd_err { 6099 + u8 code; 6100 + #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_UNKNOWN 0x0UL 6101 + #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED 0x1UL 6102 + #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_LAST PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED 6103 + u8 unused_0[7]; 6096 6104 }; 6097 6105 6098 6106 /* hwrm_port_mac_qcaps_input (size:192b/24B) */ ··· 7008 6912 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 7009 6913 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 7010 6914 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 6915 + #define VNIC_CFG_REQ_FLAGS_DEST_QP 0x100UL 7011 6916 __le32 enables; 7012 6917 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 7013 6918 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL ··· 7020 6923 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 7021 6924 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 7022 6925 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 7023 - #define VNIC_CFG_REQ_ENABLES_RAW_QP_ID 0x400UL 6926 + #define VNIC_CFG_REQ_ENABLES_QP_ID 0x400UL 7024 6927 __le16 vnic_id; 7025 6928 __le16 dflt_ring_grp; 7026 6929 __le16 rss_rule; ··· 7040 6943 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 7041 6944 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 7042 6945 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 7043 - __le32 raw_qp_id; 6946 + __le32 qp_id; 7044 6947 }; 7045 6948 7046 6949 /* hwrm_vnic_cfg_output (size:128b/16B) */ ··· 7506 7409 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 7507 7410 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 7508 7411 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 7412 + #define RING_ALLOC_REQ_FLAGS_DPI_ROCE_MANAGED 0x10UL 7413 + #define RING_ALLOC_REQ_FLAGS_TIMER_RESET 0x20UL 7509 7414 __le64 page_tbl_addr; 7510 7415 __le32 fbo; 7511 7416 u8 page_size; ··· 7682 7583 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7683 7584 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7684 7585 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7586 + #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TMR_RESET_ON_ALLOC 0x200UL 7685 7587 __le32 nq_params; 7686 7588 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7687 7589 __le16 num_cmpl_dma_aggr_min; ··· 10425 10325 __le16 instance; 10426 10326 __le16 unused_1; 10427 10327 u8 seg_flags; 10328 + #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_LIVE_DATA 0x1UL 10329 + #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_CRASHED_DATA 0x2UL 10330 + #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_NO_COMPRESS 0x4UL 10428 10331 u8 unused_2; 10429 10332 __le16 unused_3; 10430 10333 __le32 unused_4; ··· 11026 10923 #define NVM_SET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x8UL 11027 10924 #define NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x9UL 11028 10925 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 10926 + u8 unused_0[7]; 10927 + }; 10928 + 10929 + /* hwrm_nvm_defrag_input (size:192b/24B) */ 10930 + struct hwrm_nvm_defrag_input { 10931 + __le16 req_type; 10932 + __le16 cmpl_ring; 10933 + __le16 seq_id; 10934 + __le16 target_id; 10935 + __le64 resp_addr; 10936 + __le32 flags; 10937 + #define NVM_DEFRAG_REQ_FLAGS_DEFRAG 0x1UL 10938 + u8 unused_0[4]; 10939 + }; 10940 + 10941 + /* hwrm_nvm_defrag_output (size:128b/16B) */ 10942 + struct hwrm_nvm_defrag_output { 10943 + __le16 error_code; 10944 + __le16 req_type; 10945 + __le16 seq_id; 10946 + __le16 resp_len; 10947 + u8 unused_0[7]; 10948 + u8 valid; 10949 + }; 10950 + 10951 + /* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ 10952 + struct hwrm_nvm_defrag_cmd_err { 10953 + u8 code; 10954 + #define NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN 0x0UL 10955 + #define NVM_DEFRAG_CMD_ERR_CODE_FAIL 0x1UL 10956 + #define NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL 0x2UL 10957 + #define NVM_DEFRAG_CMD_ERR_CODE_LAST NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL 11029 10958 u8 unused_0[7]; 11030 10959 }; 11031 10960

Configure Feed

Configure Feed