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serial: msm: Rename UART_* defines to MSM_UART_*

Using UART_* to name defines is a bit problematic. When trying to do
unrelated cleanup which also involved tweaking header inclusion logic,
caused UART_CSR from serial_reg.h to leak into msm's namespace which is
also among msm defines. Thus, rename all UART_* ones to MSM_UART_* to
eliminate possibility of collisions.

Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20220624205424.12686-3-ilpo.jarvinen@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Ilpo Järvinen and committed by
Greg Kroah-Hartman fddbab7b 24b5596a

+240 -241
+240 -241
drivers/tty/serial/msm_serial.c
··· 29 29 #include <linux/of_device.h> 30 30 #include <linux/wait.h> 31 31 32 - #define UART_MR1 0x0000 32 + #define MSM_UART_MR1 0x0000 33 33 34 - #define UART_MR1_AUTO_RFR_LEVEL0 0x3F 35 - #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 36 - #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 37 - #define UART_MR1_RX_RDY_CTL BIT(7) 38 - #define UART_MR1_CTS_CTL BIT(6) 34 + #define MSM_UART_MR1_AUTO_RFR_LEVEL0 0x3F 35 + #define MSM_UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 36 + #define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 37 + #define MSM_UART_MR1_RX_RDY_CTL BIT(7) 38 + #define MSM_UART_MR1_CTS_CTL BIT(6) 39 39 40 - #define UART_MR2 0x0004 41 - #define UART_MR2_ERROR_MODE BIT(6) 42 - #define UART_MR2_BITS_PER_CHAR 0x30 43 - #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) 44 - #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) 45 - #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) 46 - #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) 47 - #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) 48 - #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) 49 - #define UART_MR2_PARITY_MODE_NONE 0x0 50 - #define UART_MR2_PARITY_MODE_ODD 0x1 51 - #define UART_MR2_PARITY_MODE_EVEN 0x2 52 - #define UART_MR2_PARITY_MODE_SPACE 0x3 53 - #define UART_MR2_PARITY_MODE 0x3 40 + #define MSM_UART_MR2 0x0004 41 + #define MSM_UART_MR2_ERROR_MODE BIT(6) 42 + #define MSM_UART_MR2_BITS_PER_CHAR 0x30 43 + #define MSM_UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) 44 + #define MSM_UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) 45 + #define MSM_UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) 46 + #define MSM_UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) 47 + #define MSM_UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) 48 + #define MSM_UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) 49 + #define MSM_UART_MR2_PARITY_MODE_NONE 0x0 50 + #define MSM_UART_MR2_PARITY_MODE_ODD 0x1 51 + #define MSM_UART_MR2_PARITY_MODE_EVEN 0x2 52 + #define MSM_UART_MR2_PARITY_MODE_SPACE 0x3 53 + #define MSM_UART_MR2_PARITY_MODE 0x3 54 54 55 - #define UART_CSR 0x0008 55 + #define MSM_UART_CSR 0x0008 56 56 57 - #define UART_TF 0x000C 57 + #define MSM_UART_TF 0x000C 58 58 #define UARTDM_TF 0x0070 59 59 60 - #define UART_CR 0x0010 61 - #define UART_CR_CMD_NULL (0 << 4) 62 - #define UART_CR_CMD_RESET_RX (1 << 4) 63 - #define UART_CR_CMD_RESET_TX (2 << 4) 64 - #define UART_CR_CMD_RESET_ERR (3 << 4) 65 - #define UART_CR_CMD_RESET_BREAK_INT (4 << 4) 66 - #define UART_CR_CMD_START_BREAK (5 << 4) 67 - #define UART_CR_CMD_STOP_BREAK (6 << 4) 68 - #define UART_CR_CMD_RESET_CTS (7 << 4) 69 - #define UART_CR_CMD_RESET_STALE_INT (8 << 4) 70 - #define UART_CR_CMD_PACKET_MODE (9 << 4) 71 - #define UART_CR_CMD_MODE_RESET (12 << 4) 72 - #define UART_CR_CMD_SET_RFR (13 << 4) 73 - #define UART_CR_CMD_RESET_RFR (14 << 4) 74 - #define UART_CR_CMD_PROTECTION_EN (16 << 4) 75 - #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) 76 - #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) 77 - #define UART_CR_CMD_FORCE_STALE (4 << 8) 78 - #define UART_CR_CMD_RESET_TX_READY (3 << 8) 79 - #define UART_CR_TX_DISABLE BIT(3) 80 - #define UART_CR_TX_ENABLE BIT(2) 81 - #define UART_CR_RX_DISABLE BIT(1) 82 - #define UART_CR_RX_ENABLE BIT(0) 83 - #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) 60 + #define MSM_UART_CR 0x0010 61 + #define MSM_UART_CR_CMD_NULL (0 << 4) 62 + #define MSM_UART_CR_CMD_RESET_RX (1 << 4) 63 + #define MSM_UART_CR_CMD_RESET_TX (2 << 4) 64 + #define MSM_UART_CR_CMD_RESET_ERR (3 << 4) 65 + #define MSM_UART_CR_CMD_RESET_BREAK_INT (4 << 4) 66 + #define MSM_UART_CR_CMD_START_BREAK (5 << 4) 67 + #define MSM_UART_CR_CMD_STOP_BREAK (6 << 4) 68 + #define MSM_UART_CR_CMD_RESET_CTS (7 << 4) 69 + #define MSM_UART_CR_CMD_RESET_STALE_INT (8 << 4) 70 + #define MSM_UART_CR_CMD_PACKET_MODE (9 << 4) 71 + #define MSM_UART_CR_CMD_MODE_RESET (12 << 4) 72 + #define MSM_UART_CR_CMD_SET_RFR (13 << 4) 73 + #define MSM_UART_CR_CMD_RESET_RFR (14 << 4) 74 + #define MSM_UART_CR_CMD_PROTECTION_EN (16 << 4) 75 + #define MSM_UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) 76 + #define MSM_UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) 77 + #define MSM_UART_CR_CMD_FORCE_STALE (4 << 8) 78 + #define MSM_UART_CR_CMD_RESET_TX_READY (3 << 8) 79 + #define MSM_UART_CR_TX_DISABLE BIT(3) 80 + #define MSM_UART_CR_TX_ENABLE BIT(2) 81 + #define MSM_UART_CR_RX_DISABLE BIT(1) 82 + #define MSM_UART_CR_RX_ENABLE BIT(0) 83 + #define MSM_UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) 84 84 85 - #define UART_IMR 0x0014 86 - #define UART_IMR_TXLEV BIT(0) 87 - #define UART_IMR_RXSTALE BIT(3) 88 - #define UART_IMR_RXLEV BIT(4) 89 - #define UART_IMR_DELTA_CTS BIT(5) 90 - #define UART_IMR_CURRENT_CTS BIT(6) 91 - #define UART_IMR_RXBREAK_START BIT(10) 85 + #define MSM_UART_IMR 0x0014 86 + #define MSM_UART_IMR_TXLEV BIT(0) 87 + #define MSM_UART_IMR_RXSTALE BIT(3) 88 + #define MSM_UART_IMR_RXLEV BIT(4) 89 + #define MSM_UART_IMR_DELTA_CTS BIT(5) 90 + #define MSM_UART_IMR_CURRENT_CTS BIT(6) 91 + #define MSM_UART_IMR_RXBREAK_START BIT(10) 92 92 93 - #define UART_IPR_RXSTALE_LAST 0x20 94 - #define UART_IPR_STALE_LSB 0x1F 95 - #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 96 - #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 93 + #define MSM_UART_IPR_RXSTALE_LAST 0x20 94 + #define MSM_UART_IPR_STALE_LSB 0x1F 95 + #define MSM_UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 96 + #define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 97 97 98 - #define UART_IPR 0x0018 99 - #define UART_TFWR 0x001C 100 - #define UART_RFWR 0x0020 101 - #define UART_HCR 0x0024 98 + #define MSM_UART_IPR 0x0018 99 + #define MSM_UART_TFWR 0x001C 100 + #define MSM_UART_RFWR 0x0020 101 + #define MSM_UART_HCR 0x0024 102 102 103 - #define UART_MREG 0x0028 104 - #define UART_NREG 0x002C 105 - #define UART_DREG 0x0030 106 - #define UART_MNDREG 0x0034 107 - #define UART_IRDA 0x0038 108 - #define UART_MISR_MODE 0x0040 109 - #define UART_MISR_RESET 0x0044 110 - #define UART_MISR_EXPORT 0x0048 111 - #define UART_MISR_VAL 0x004C 112 - #define UART_TEST_CTRL 0x0050 103 + #define MSM_UART_MREG 0x0028 104 + #define MSM_UART_NREG 0x002C 105 + #define MSM_UART_DREG 0x0030 106 + #define MSM_UART_MNDREG 0x0034 107 + #define MSM_UART_IRDA 0x0038 108 + #define MSM_UART_MISR_MODE 0x0040 109 + #define MSM_UART_MISR_RESET 0x0044 110 + #define MSM_UART_MISR_EXPORT 0x0048 111 + #define MSM_UART_MISR_VAL 0x004C 112 + #define MSM_UART_TEST_CTRL 0x0050 113 113 114 - #define UART_SR 0x0008 115 - #define UART_SR_HUNT_CHAR BIT(7) 116 - #define UART_SR_RX_BREAK BIT(6) 117 - #define UART_SR_PAR_FRAME_ERR BIT(5) 118 - #define UART_SR_OVERRUN BIT(4) 119 - #define UART_SR_TX_EMPTY BIT(3) 120 - #define UART_SR_TX_READY BIT(2) 121 - #define UART_SR_RX_FULL BIT(1) 122 - #define UART_SR_RX_READY BIT(0) 114 + #define MSM_UART_SR 0x0008 115 + #define MSM_UART_SR_HUNT_CHAR BIT(7) 116 + #define MSM_UART_SR_RX_BREAK BIT(6) 117 + #define MSM_UART_SR_PAR_FRAME_ERR BIT(5) 118 + #define MSM_UART_SR_OVERRUN BIT(4) 119 + #define MSM_UART_SR_TX_EMPTY BIT(3) 120 + #define MSM_UART_SR_TX_READY BIT(2) 121 + #define MSM_UART_SR_RX_FULL BIT(1) 122 + #define MSM_UART_SR_RX_READY BIT(0) 123 123 124 - #define UART_RF 0x000C 124 + #define MSM_UART_RF 0x000C 125 125 #define UARTDM_RF 0x0070 126 - #define UART_MISR 0x0010 127 - #define UART_ISR 0x0014 128 - #define UART_ISR_TX_READY BIT(7) 126 + #define MSM_UART_MISR 0x0010 127 + #define MSM_UART_ISR 0x0014 128 + #define MSM_UART_ISR_TX_READY BIT(7) 129 129 130 130 #define UARTDM_RXFS 0x50 131 131 #define UARTDM_RXFS_BUF_SHIFT 0x7 ··· 203 203 */ 204 204 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) 205 205 { 206 - msm_write(port, 0x06, UART_MREG); 207 - msm_write(port, 0xF1, UART_NREG); 208 - msm_write(port, 0x0F, UART_DREG); 209 - msm_write(port, 0x1A, UART_MNDREG); 206 + msm_write(port, 0x06, MSM_UART_MREG); 207 + msm_write(port, 0xF1, MSM_UART_NREG); 208 + msm_write(port, 0x0F, MSM_UART_DREG); 209 + msm_write(port, 0x1A, MSM_UART_MNDREG); 210 210 port->uartclk = 1843200; 211 211 } 212 212 ··· 215 215 */ 216 216 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) 217 217 { 218 - msm_write(port, 0x18, UART_MREG); 219 - msm_write(port, 0xF6, UART_NREG); 220 - msm_write(port, 0x0F, UART_DREG); 221 - msm_write(port, 0x0A, UART_MNDREG); 218 + msm_write(port, 0x18, MSM_UART_MREG); 219 + msm_write(port, 0xF6, MSM_UART_NREG); 220 + msm_write(port, 0x0F, MSM_UART_DREG); 221 + msm_write(port, 0x0A, MSM_UART_MNDREG); 222 222 port->uartclk = 1843200; 223 223 } 224 224 ··· 395 395 { 396 396 unsigned int timeout = 500000; 397 397 398 - while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) { 399 - if (msm_read(port, UART_ISR) & UART_ISR_TX_READY) 398 + while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) { 399 + if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY) 400 400 break; 401 401 udelay(1); 402 402 if (!timeout--) 403 403 break; 404 404 } 405 - msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); 405 + msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR); 406 406 } 407 407 408 408 static void msm_stop_tx(struct uart_port *port) 409 409 { 410 410 struct msm_port *msm_port = to_msm_port(port); 411 411 412 - msm_port->imr &= ~UART_IMR_TXLEV; 413 - msm_write(port, msm_port->imr, UART_IMR); 412 + msm_port->imr &= ~MSM_UART_IMR_TXLEV; 413 + msm_write(port, msm_port->imr, MSM_UART_IMR); 414 414 } 415 415 416 416 static void msm_start_tx(struct uart_port *port) ··· 422 422 if (dma->count) 423 423 return; 424 424 425 - msm_port->imr |= UART_IMR_TXLEV; 426 - msm_write(port, msm_port->imr, UART_IMR); 425 + msm_port->imr |= MSM_UART_IMR_TXLEV; 426 + msm_write(port, msm_port->imr, MSM_UART_IMR); 427 427 } 428 428 429 429 static void msm_reset_dm_count(struct uart_port *port, int count) ··· 459 459 msm_write(port, val, UARTDM_DMEN); 460 460 461 461 if (msm_port->is_uartdm > UARTDM_1P3) { 462 - msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 463 - msm_write(port, UART_CR_TX_ENABLE, UART_CR); 462 + msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); 463 + msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR); 464 464 } 465 465 466 466 count = dma->count - state.residue; ··· 471 471 xmit->tail &= UART_XMIT_SIZE - 1; 472 472 473 473 /* Restore "Tx FIFO below watermark" interrupt */ 474 - msm_port->imr |= UART_IMR_TXLEV; 475 - msm_write(port, msm_port->imr, UART_IMR); 474 + msm_port->imr |= MSM_UART_IMR_TXLEV; 475 + msm_write(port, msm_port->imr, MSM_UART_IMR); 476 476 477 477 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 478 478 uart_write_wakeup(port); ··· 519 519 * Using DMA complete for Tx FIFO reload, no need for 520 520 * "Tx FIFO below watermark" one, disable it 521 521 */ 522 - msm_port->imr &= ~UART_IMR_TXLEV; 523 - msm_write(port, msm_port->imr, UART_IMR); 522 + msm_port->imr &= ~MSM_UART_IMR_TXLEV; 523 + msm_write(port, msm_port->imr, MSM_UART_IMR); 524 524 525 525 dma->count = count; 526 526 ··· 562 562 val &= ~dma->enable_bit; 563 563 msm_write(port, val, UARTDM_DMEN); 564 564 565 - if (msm_read(port, UART_SR) & UART_SR_OVERRUN) { 565 + if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) { 566 566 port->icount.overrun++; 567 567 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 568 - msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 568 + msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 569 569 } 570 570 571 571 count = msm_read(port, UARTDM_RX_TOTAL_SNAP); ··· 587 587 continue; 588 588 } 589 589 590 - if (!(port->read_status_mask & UART_SR_RX_BREAK)) 590 + if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 591 591 flag = TTY_NORMAL; 592 592 593 593 spin_unlock_irqrestore(&port->lock, flags); ··· 641 641 * Using DMA for FIFO off-load, no need for "Rx FIFO over 642 642 * watermark" or "stale" interrupts, disable them 643 643 */ 644 - msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 644 + msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE); 645 645 646 646 /* 647 647 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3), 648 648 * we need RXSTALE to flush input DMA fifo to memory 649 649 */ 650 650 if (msm_port->is_uartdm < UARTDM_1P4) 651 - msm_port->imr |= UART_IMR_RXSTALE; 651 + msm_port->imr |= MSM_UART_IMR_RXSTALE; 652 652 653 - msm_write(uart, msm_port->imr, UART_IMR); 653 + msm_write(uart, msm_port->imr, MSM_UART_IMR); 654 654 655 655 dma->count = UARTDM_RX_SIZE; 656 656 657 657 dma_async_issue_pending(dma->chan); 658 658 659 - msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); 660 - msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 659 + msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 660 + msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 661 661 662 662 val = msm_read(uart, UARTDM_DMEN); 663 663 val |= dma->enable_bit; ··· 679 679 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN), 680 680 * receiver must be reset. 681 681 */ 682 - msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR); 683 - msm_write(uart, UART_CR_RX_ENABLE, UART_CR); 682 + msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); 683 + msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR); 684 684 685 - msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); 685 + msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 686 686 msm_write(uart, 0xFFFFFF, UARTDM_DMRX); 687 - msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 687 + msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 688 688 689 689 /* Re-enable RX interrupts */ 690 - msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE); 691 - msm_write(uart, msm_port->imr, UART_IMR); 690 + msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE; 691 + msm_write(uart, msm_port->imr, MSM_UART_IMR); 692 692 } 693 693 694 694 static void msm_stop_rx(struct uart_port *port) ··· 696 696 struct msm_port *msm_port = to_msm_port(port); 697 697 struct msm_dma *dma = &msm_port->rx_dma; 698 698 699 - msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 700 - msm_write(port, msm_port->imr, UART_IMR); 699 + msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE); 700 + msm_write(port, msm_port->imr, MSM_UART_IMR); 701 701 702 702 if (dma->chan) 703 703 msm_stop_dma(port, dma); ··· 707 707 { 708 708 struct msm_port *msm_port = to_msm_port(port); 709 709 710 - msm_port->imr |= UART_IMR_DELTA_CTS; 711 - msm_write(port, msm_port->imr, UART_IMR); 710 + msm_port->imr |= MSM_UART_IMR_DELTA_CTS; 711 + msm_write(port, msm_port->imr, MSM_UART_IMR); 712 712 } 713 713 714 714 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr) ··· 719 719 int count = 0; 720 720 struct msm_port *msm_port = to_msm_port(port); 721 721 722 - if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 722 + if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) { 723 723 port->icount.overrun++; 724 724 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 725 - msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 725 + msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 726 726 } 727 727 728 - if (misr & UART_IMR_RXSTALE) { 728 + if (misr & MSM_UART_IMR_RXSTALE) { 729 729 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 730 730 msm_port->old_snap_state; 731 731 msm_port->old_snap_state = 0; 732 732 } else { 733 - count = 4 * (msm_read(port, UART_RFWR)); 733 + count = 4 * (msm_read(port, MSM_UART_RFWR)); 734 734 msm_port->old_snap_state += count; 735 735 } 736 736 ··· 742 742 unsigned char buf[4]; 743 743 int sysrq, r_count, i; 744 744 745 - sr = msm_read(port, UART_SR); 746 - if ((sr & UART_SR_RX_READY) == 0) { 745 + sr = msm_read(port, MSM_UART_SR); 746 + if ((sr & MSM_UART_SR_RX_READY) == 0) { 747 747 msm_port->old_snap_state -= count; 748 748 break; 749 749 } ··· 762 762 continue; 763 763 } 764 764 765 - if (!(port->read_status_mask & UART_SR_RX_BREAK)) 765 + if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 766 766 flag = TTY_NORMAL; 767 767 768 768 spin_unlock(&port->lock); ··· 776 776 777 777 tty_flip_buffer_push(tport); 778 778 779 - if (misr & (UART_IMR_RXSTALE)) 780 - msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 779 + if (misr & (MSM_UART_IMR_RXSTALE)) 780 + msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 781 781 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 782 - msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 782 + msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 783 783 784 784 /* Try to use DMA */ 785 785 msm_start_rx_dma(msm_port); ··· 795 795 * Handle overrun. My understanding of the hardware is that overrun 796 796 * is not tied to the RX buffer, so we handle the case out of band. 797 797 */ 798 - if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 798 + if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) { 799 799 port->icount.overrun++; 800 800 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 801 - msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 801 + msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 802 802 } 803 803 804 804 /* and now the main RX loop */ 805 - while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 805 + while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) { 806 806 unsigned int c; 807 807 char flag = TTY_NORMAL; 808 808 int sysrq; 809 809 810 - c = msm_read(port, UART_RF); 810 + c = msm_read(port, MSM_UART_RF); 811 811 812 - if (sr & UART_SR_RX_BREAK) { 812 + if (sr & MSM_UART_SR_RX_BREAK) { 813 813 port->icount.brk++; 814 814 if (uart_handle_break(port)) 815 815 continue; 816 - } else if (sr & UART_SR_PAR_FRAME_ERR) { 816 + } else if (sr & MSM_UART_SR_PAR_FRAME_ERR) { 817 817 port->icount.frame++; 818 818 } else { 819 819 port->icount.rx++; ··· 822 822 /* Mask conditions we're ignorning. */ 823 823 sr &= port->read_status_mask; 824 824 825 - if (sr & UART_SR_RX_BREAK) 825 + if (sr & MSM_UART_SR_RX_BREAK) 826 826 flag = TTY_BREAK; 827 - else if (sr & UART_SR_PAR_FRAME_ERR) 827 + else if (sr & MSM_UART_SR_PAR_FRAME_ERR) 828 828 flag = TTY_FRAME; 829 829 830 830 spin_unlock(&port->lock); ··· 848 848 if (msm_port->is_uartdm) 849 849 tf = port->membase + UARTDM_TF; 850 850 else 851 - tf = port->membase + UART_TF; 851 + tf = port->membase + MSM_UART_TF; 852 852 853 853 if (tx_count && msm_port->is_uartdm) 854 854 msm_reset_dm_count(port, tx_count); ··· 857 857 int i; 858 858 char buf[4] = { 0 }; 859 859 860 - if (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 860 + if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 861 861 break; 862 862 863 863 if (msm_port->is_uartdm) ··· 898 898 if (msm_port->is_uartdm) 899 899 tf = port->membase + UARTDM_TF; 900 900 else 901 - tf = port->membase + UART_TF; 901 + tf = port->membase + MSM_UART_TF; 902 902 903 903 buf[0] = port->x_char; 904 904 ··· 942 942 943 943 static void msm_handle_delta_cts(struct uart_port *port) 944 944 { 945 - msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 945 + msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); 946 946 port->icount.cts++; 947 947 wake_up_interruptible(&port->state->port.delta_msr_wait); 948 948 } ··· 957 957 u32 val; 958 958 959 959 spin_lock_irqsave(&port->lock, flags); 960 - misr = msm_read(port, UART_MISR); 961 - msm_write(port, 0, UART_IMR); /* disable interrupt */ 960 + misr = msm_read(port, MSM_UART_MISR); 961 + msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */ 962 962 963 - if (misr & UART_IMR_RXBREAK_START) { 963 + if (misr & MSM_UART_IMR_RXBREAK_START) { 964 964 msm_port->break_detected = true; 965 - msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR); 965 + msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR); 966 966 } 967 967 968 - if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 968 + if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) { 969 969 if (dma->count) { 970 - val = UART_CR_CMD_STALE_EVENT_DISABLE; 971 - msm_write(port, val, UART_CR); 972 - val = UART_CR_CMD_RESET_STALE_INT; 973 - msm_write(port, val, UART_CR); 970 + val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE; 971 + msm_write(port, val, MSM_UART_CR); 972 + val = MSM_UART_CR_CMD_RESET_STALE_INT; 973 + msm_write(port, val, MSM_UART_CR); 974 974 /* 975 975 * Flush DMA input fifo to memory, this will also 976 976 * trigger DMA RX completion ··· 982 982 msm_handle_rx(port); 983 983 } 984 984 } 985 - if (misr & UART_IMR_TXLEV) 985 + if (misr & MSM_UART_IMR_TXLEV) 986 986 msm_handle_tx(port); 987 - if (misr & UART_IMR_DELTA_CTS) 987 + if (misr & MSM_UART_IMR_DELTA_CTS) 988 988 msm_handle_delta_cts(port); 989 989 990 - msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 990 + msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */ 991 991 spin_unlock_irqrestore(&port->lock, flags); 992 992 993 993 return IRQ_HANDLED; ··· 995 995 996 996 static unsigned int msm_tx_empty(struct uart_port *port) 997 997 { 998 - return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 998 + return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 999 999 } 1000 1000 1001 1001 static unsigned int msm_get_mctrl(struct uart_port *port) ··· 1009 1009 unsigned int mr; 1010 1010 1011 1011 /* reset everything */ 1012 - msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 1013 - msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 1014 - msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 1015 - msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 1016 - msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 1017 - msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 1018 - mr = msm_read(port, UART_MR1); 1019 - mr &= ~UART_MR1_RX_RDY_CTL; 1020 - msm_write(port, mr, UART_MR1); 1012 + msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); 1013 + msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); 1014 + msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 1015 + msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR); 1016 + msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); 1017 + msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); 1018 + mr = msm_read(port, MSM_UART_MR1); 1019 + mr &= ~MSM_UART_MR1_RX_RDY_CTL; 1020 + msm_write(port, mr, MSM_UART_MR1); 1021 1021 1022 1022 /* Disable DM modes */ 1023 1023 if (msm_port->is_uartdm) ··· 1028 1028 { 1029 1029 unsigned int mr; 1030 1030 1031 - mr = msm_read(port, UART_MR1); 1031 + mr = msm_read(port, MSM_UART_MR1); 1032 1032 1033 1033 if (!(mctrl & TIOCM_RTS)) { 1034 - mr &= ~UART_MR1_RX_RDY_CTL; 1035 - msm_write(port, mr, UART_MR1); 1036 - msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 1034 + mr &= ~MSM_UART_MR1_RX_RDY_CTL; 1035 + msm_write(port, mr, MSM_UART_MR1); 1036 + msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); 1037 1037 } else { 1038 - mr |= UART_MR1_RX_RDY_CTL; 1039 - msm_write(port, mr, UART_MR1); 1038 + mr |= MSM_UART_MR1_RX_RDY_CTL; 1039 + msm_write(port, mr, MSM_UART_MR1); 1040 1040 } 1041 1041 } 1042 1042 1043 1043 static void msm_break_ctl(struct uart_port *port, int break_ctl) 1044 1044 { 1045 1045 if (break_ctl) 1046 - msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 1046 + msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR); 1047 1047 else 1048 - msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 1048 + msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR); 1049 1049 } 1050 1050 1051 1051 struct msm_baud_map { ··· 1142 1142 *saved_flags = flags; 1143 1143 port->uartclk = rate; 1144 1144 1145 - msm_write(port, entry->code, UART_CSR); 1145 + msm_write(port, entry->code, MSM_UART_CSR); 1146 1146 1147 1147 /* RX stale watermark */ 1148 1148 rxstale = entry->rxstale; 1149 - watermark = UART_IPR_STALE_LSB & rxstale; 1149 + watermark = MSM_UART_IPR_STALE_LSB & rxstale; 1150 1150 if (msm_port->is_uartdm) { 1151 - mask = UART_DM_IPR_STALE_TIMEOUT_MSB; 1151 + mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB; 1152 1152 } else { 1153 - watermark |= UART_IPR_RXSTALE_LAST; 1154 - mask = UART_IPR_STALE_TIMEOUT_MSB; 1153 + watermark |= MSM_UART_IPR_RXSTALE_LAST; 1154 + mask = MSM_UART_IPR_STALE_TIMEOUT_MSB; 1155 1155 } 1156 1156 1157 1157 watermark |= mask & (rxstale << 2); 1158 1158 1159 - msm_write(port, watermark, UART_IPR); 1159 + msm_write(port, watermark, MSM_UART_IPR); 1160 1160 1161 1161 /* set RX watermark */ 1162 1162 watermark = (port->fifosize * 3) / 4; 1163 - msm_write(port, watermark, UART_RFWR); 1163 + msm_write(port, watermark, MSM_UART_RFWR); 1164 1164 1165 1165 /* set TX watermark */ 1166 - msm_write(port, 10, UART_TFWR); 1166 + msm_write(port, 10, MSM_UART_TFWR); 1167 1167 1168 - msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 1168 + msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR); 1169 1169 msm_reset(port); 1170 1170 1171 1171 /* Enable RX and TX */ 1172 - msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR); 1172 + msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR); 1173 1173 1174 1174 /* turn on RX and CTS interrupts */ 1175 - msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 1176 - UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START; 1175 + msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE | 1176 + MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START; 1177 1177 1178 - msm_write(port, msm_port->imr, UART_IMR); 1178 + msm_write(port, msm_port->imr, MSM_UART_IMR); 1179 1179 1180 1180 if (msm_port->is_uartdm) { 1181 - msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 1181 + msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 1182 1182 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1183 - msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 1183 + msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 1184 1184 } 1185 1185 1186 1186 return baud; ··· 1212 1212 rfr_level = port->fifosize; 1213 1213 1214 1214 /* set automatic RFR level */ 1215 - data = msm_read(port, UART_MR1); 1215 + data = msm_read(port, MSM_UART_MR1); 1216 1216 1217 1217 if (msm_port->is_uartdm) 1218 - mask = UART_DM_MR1_AUTO_RFR_LEVEL1; 1218 + mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1; 1219 1219 else 1220 - mask = UART_MR1_AUTO_RFR_LEVEL1; 1220 + mask = MSM_UART_MR1_AUTO_RFR_LEVEL1; 1221 1221 1222 1222 data &= ~mask; 1223 - data &= ~UART_MR1_AUTO_RFR_LEVEL0; 1223 + data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0; 1224 1224 data |= mask & (rfr_level << 2); 1225 - data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 1226 - msm_write(port, data, UART_MR1); 1225 + data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 1226 + msm_write(port, data, MSM_UART_MR1); 1227 1227 1228 1228 if (msm_port->is_uartdm) { 1229 1229 msm_request_tx_dma(msm_port, msm_port->uart.mapbase); ··· 1252 1252 struct msm_port *msm_port = to_msm_port(port); 1253 1253 1254 1254 msm_port->imr = 0; 1255 - msm_write(port, 0, UART_IMR); /* disable interrupts */ 1255 + msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */ 1256 1256 1257 1257 if (msm_port->is_uartdm) 1258 1258 msm_release_dma(msm_port); ··· 1282 1282 tty_termios_encode_baud_rate(termios, baud, baud); 1283 1283 1284 1284 /* calculate parity */ 1285 - mr = msm_read(port, UART_MR2); 1286 - mr &= ~UART_MR2_PARITY_MODE; 1285 + mr = msm_read(port, MSM_UART_MR2); 1286 + mr &= ~MSM_UART_MR2_PARITY_MODE; 1287 1287 if (termios->c_cflag & PARENB) { 1288 1288 if (termios->c_cflag & PARODD) 1289 - mr |= UART_MR2_PARITY_MODE_ODD; 1289 + mr |= MSM_UART_MR2_PARITY_MODE_ODD; 1290 1290 else if (termios->c_cflag & CMSPAR) 1291 - mr |= UART_MR2_PARITY_MODE_SPACE; 1291 + mr |= MSM_UART_MR2_PARITY_MODE_SPACE; 1292 1292 else 1293 - mr |= UART_MR2_PARITY_MODE_EVEN; 1293 + mr |= MSM_UART_MR2_PARITY_MODE_EVEN; 1294 1294 } 1295 1295 1296 1296 /* calculate bits per char */ 1297 - mr &= ~UART_MR2_BITS_PER_CHAR; 1297 + mr &= ~MSM_UART_MR2_BITS_PER_CHAR; 1298 1298 switch (termios->c_cflag & CSIZE) { 1299 1299 case CS5: 1300 - mr |= UART_MR2_BITS_PER_CHAR_5; 1300 + mr |= MSM_UART_MR2_BITS_PER_CHAR_5; 1301 1301 break; 1302 1302 case CS6: 1303 - mr |= UART_MR2_BITS_PER_CHAR_6; 1303 + mr |= MSM_UART_MR2_BITS_PER_CHAR_6; 1304 1304 break; 1305 1305 case CS7: 1306 - mr |= UART_MR2_BITS_PER_CHAR_7; 1306 + mr |= MSM_UART_MR2_BITS_PER_CHAR_7; 1307 1307 break; 1308 1308 case CS8: 1309 1309 default: 1310 - mr |= UART_MR2_BITS_PER_CHAR_8; 1310 + mr |= MSM_UART_MR2_BITS_PER_CHAR_8; 1311 1311 break; 1312 1312 } 1313 1313 1314 1314 /* calculate stop bits */ 1315 - mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 1315 + mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO); 1316 1316 if (termios->c_cflag & CSTOPB) 1317 - mr |= UART_MR2_STOP_BIT_LEN_TWO; 1317 + mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO; 1318 1318 else 1319 - mr |= UART_MR2_STOP_BIT_LEN_ONE; 1319 + mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE; 1320 1320 1321 1321 /* set parity, bits per char, and stop bit */ 1322 - msm_write(port, mr, UART_MR2); 1322 + msm_write(port, mr, MSM_UART_MR2); 1323 1323 1324 1324 /* calculate and set hardware flow control */ 1325 - mr = msm_read(port, UART_MR1); 1326 - mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 1325 + mr = msm_read(port, MSM_UART_MR1); 1326 + mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL); 1327 1327 if (termios->c_cflag & CRTSCTS) { 1328 - mr |= UART_MR1_CTS_CTL; 1329 - mr |= UART_MR1_RX_RDY_CTL; 1328 + mr |= MSM_UART_MR1_CTS_CTL; 1329 + mr |= MSM_UART_MR1_RX_RDY_CTL; 1330 1330 } 1331 - msm_write(port, mr, UART_MR1); 1331 + msm_write(port, mr, MSM_UART_MR1); 1332 1332 1333 1333 /* Configure status bits to ignore based on termio flags. */ 1334 1334 port->read_status_mask = 0; 1335 1335 if (termios->c_iflag & INPCK) 1336 - port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 1336 + port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR; 1337 1337 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1338 - port->read_status_mask |= UART_SR_RX_BREAK; 1338 + port->read_status_mask |= MSM_UART_SR_RX_BREAK; 1339 1339 1340 1340 uart_update_timeout(port, termios->c_cflag, baud); 1341 1341 ··· 1439 1439 static int msm_poll_get_char_single(struct uart_port *port) 1440 1440 { 1441 1441 struct msm_port *msm_port = to_msm_port(port); 1442 - unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF; 1442 + unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF; 1443 1443 1444 - if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) 1444 + if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) 1445 1445 return NO_POLL_CHAR; 1446 1446 1447 1447 return msm_read(port, rf_reg) & 0xff; ··· 1459 1459 c = sp[sizeof(slop) - count]; 1460 1460 count--; 1461 1461 /* Or if FIFO is empty */ 1462 - } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) { 1462 + } else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) { 1463 1463 /* 1464 1464 * If RX packing buffer has less than a word, force stale to 1465 1465 * push contents into RX FIFO ··· 1467 1467 count = msm_read(port, UARTDM_RXFS); 1468 1468 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; 1469 1469 if (count) { 1470 - msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR); 1470 + msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR); 1471 1471 slop = msm_read(port, UARTDM_RF); 1472 1472 c = sp[0]; 1473 1473 count--; 1474 - msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 1474 + msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 1475 1475 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1476 - msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, 1477 - UART_CR); 1476 + msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 1478 1477 } else { 1479 1478 c = NO_POLL_CHAR; 1480 1479 } ··· 1494 1495 struct msm_port *msm_port = to_msm_port(port); 1495 1496 1496 1497 /* Disable all interrupts */ 1497 - imr = msm_read(port, UART_IMR); 1498 - msm_write(port, 0, UART_IMR); 1498 + imr = msm_read(port, MSM_UART_IMR); 1499 + msm_write(port, 0, MSM_UART_IMR); 1499 1500 1500 1501 if (msm_port->is_uartdm) 1501 1502 c = msm_poll_get_char_dm(port); ··· 1503 1504 c = msm_poll_get_char_single(port); 1504 1505 1505 1506 /* Enable interrupts */ 1506 - msm_write(port, imr, UART_IMR); 1507 + msm_write(port, imr, MSM_UART_IMR); 1507 1508 1508 1509 return c; 1509 1510 } ··· 1514 1515 struct msm_port *msm_port = to_msm_port(port); 1515 1516 1516 1517 /* Disable all interrupts */ 1517 - imr = msm_read(port, UART_IMR); 1518 - msm_write(port, 0, UART_IMR); 1518 + imr = msm_read(port, MSM_UART_IMR); 1519 + msm_write(port, 0, MSM_UART_IMR); 1519 1520 1520 1521 if (msm_port->is_uartdm) 1521 1522 msm_reset_dm_count(port, 1); 1522 1523 1523 1524 /* Wait until FIFO is empty */ 1524 - while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1525 + while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1525 1526 cpu_relax(); 1526 1527 1527 1528 /* Write a character */ 1528 - msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 1529 + msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF); 1529 1530 1530 1531 /* Wait until FIFO is empty */ 1531 - while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1532 + while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1532 1533 cpu_relax(); 1533 1534 1534 1535 /* Enable interrupts */ 1535 - msm_write(port, imr, UART_IMR); 1536 + msm_write(port, imr, MSM_UART_IMR); 1536 1537 } 1537 1538 #endif 1538 1539 ··· 1590 1591 }, 1591 1592 }; 1592 1593 1593 - #define UART_NR ARRAY_SIZE(msm_uart_ports) 1594 + #define MSM_UART_NR ARRAY_SIZE(msm_uart_ports) 1594 1595 1595 1596 static inline struct uart_port *msm_get_port_from_line(unsigned int line) 1596 1597 { ··· 1611 1612 if (is_uartdm) 1612 1613 tf = port->membase + UARTDM_TF; 1613 1614 else 1614 - tf = port->membase + UART_TF; 1615 + tf = port->membase + MSM_UART_TF; 1615 1616 1616 1617 /* Account for newlines that will get a carriage return added */ 1617 1618 for (i = 0; i < count; i++) ··· 1657 1658 } 1658 1659 } 1659 1660 1660 - while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1661 + while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1661 1662 cpu_relax(); 1662 1663 1663 1664 iowrite32_rep(tf, buf, 1); ··· 1676 1677 struct uart_port *port; 1677 1678 struct msm_port *msm_port; 1678 1679 1679 - BUG_ON(co->index < 0 || co->index >= UART_NR); 1680 + BUG_ON(co->index < 0 || co->index >= MSM_UART_NR); 1680 1681 1681 1682 port = msm_get_port_from_line(co->index); 1682 1683 msm_port = to_msm_port(port); ··· 1692 1693 int parity = 'n'; 1693 1694 int flow = 'n'; 1694 1695 1695 - if (unlikely(co->index >= UART_NR || co->index < 0)) 1696 + if (unlikely(co->index >= MSM_UART_NR || co->index < 0)) 1696 1697 return -ENXIO; 1697 1698 1698 1699 port = msm_get_port_from_line(co->index); ··· 1773 1774 .owner = THIS_MODULE, 1774 1775 .driver_name = "msm_serial", 1775 1776 .dev_name = "ttyMSM", 1776 - .nr = UART_NR, 1777 + .nr = MSM_UART_NR, 1777 1778 .cons = MSM_CONSOLE, 1778 1779 }; 1779 1780 ··· 1803 1804 if (line < 0) 1804 1805 line = atomic_inc_return(&msm_uart_next_id) - 1; 1805 1806 1806 - if (unlikely(line < 0 || line >= UART_NR)) 1807 + if (unlikely(line < 0 || line >= MSM_UART_NR)) 1807 1808 return -ENXIO; 1808 1809 1809 1810 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);