Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"The majority of this batch is conversion of the PWM period and duty
cycle to 64-bit unsigned integers, which is required so that some
types of hardware can generate the full range of signals that they're
capable of.
The remainder is mostly minor fixes and cleanups"
* tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: bcm-iproc: handle clk_get_rate() return
pwm: Replace HTTP links with HTTPS ones
pwm: omap-dmtimer: Repair pwm_omap_dmtimer_chip's broken kerneldoc header
pwm: mediatek: Provide missing kerneldoc description for 'soc' arg
pwm: bcm-kona: Remove impossible comparison when validating duty cycle
pwm: bcm-iproc: Remove impossible comparison when validating duty cycle
pwm: iqs620a: Use lowercase hexadecimal literals for consistency
pwm: Convert period and duty cycle to u64
clk: pwm: Use 64-bit division function
backlight: pwm_bl: Use 64-bit division function
pwm: sun4i: Use nsecs_to_jiffies to avoid a division
pwm: sifive: Use 64-bit division macro
pwm: iqs620a: Use 64-bit division
pwm: imx27: Use 64-bit division macro
pwm: imx-tpm: Use 64-bit division macro
pwm: clps711x: Use 64-bit division macro
hwmon: pwm-fan: Use 64-bit division macro
drm/i915: Use 64-bit division macro
+56
-44
+6
-1
drivers/clk/clk-pwm.c
+6
-1
drivers/clk/clk-pwm.c
···
89
89
}
90
90
91
91
if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
92
-
clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period;
92
+
clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
93
+
94
+
if (!clk_pwm->fixed_rate) {
95
+
dev_err(&pdev->dev, "fixed_rate cannot be zero\n");
96
+
return -EINVAL;
97
+
}
93
98
94
99
if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
95
100
pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {
+1
-1
drivers/gpu/drm/i915/display/intel_panel.c
+1
-1
drivers/gpu/drm/i915/display/intel_panel.c
···
1929
1929
return retval;
1930
1930
}
1931
1931
1932
-
level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100,
1932
+
level = DIV_ROUND_UP_ULL(pwm_get_duty_cycle(panel->backlight.pwm) * 100,
1933
1933
CRC_PMIC_PWM_PERIOD_NS);
1934
1934
panel->backlight.level =
1935
1935
intel_panel_compute_brightness(connector, level);
+1
-1
drivers/hwmon/pwm-fan.c
+1
-1
drivers/hwmon/pwm-fan.c
···
447
447
return 0;
448
448
449
449
pwm_get_args(ctx->pwm, &pargs);
450
-
duty = DIV_ROUND_UP(ctx->pwm_value * (pargs.period - 1), MAX_PWM);
450
+
duty = DIV_ROUND_UP_ULL(ctx->pwm_value * (pargs.period - 1), MAX_PWM);
451
451
ret = pwm_config(ctx->pwm, duty, pargs.period);
452
452
if (ret)
453
453
return ret;
+7
-7
drivers/pwm/core.c
+7
-7
drivers/pwm/core.c
···
510
510
last->period > s2.period &&
511
511
last->period <= state->period)
512
512
dev_warn(chip->dev,
513
-
".apply didn't pick the best available period (requested: %u, applied: %u, possible: %u)\n",
513
+
".apply didn't pick the best available period (requested: %llu, applied: %llu, possible: %llu)\n",
514
514
state->period, s2.period, last->period);
515
515
516
516
if (state->enabled && state->period < s2.period)
517
517
dev_warn(chip->dev,
518
-
".apply is supposed to round down period (requested: %u, applied: %u)\n",
518
+
".apply is supposed to round down period (requested: %llu, applied: %llu)\n",
519
519
state->period, s2.period);
520
520
521
521
if (state->enabled &&
···
524
524
last->duty_cycle > s2.duty_cycle &&
525
525
last->duty_cycle <= state->duty_cycle)
526
526
dev_warn(chip->dev,
527
-
".apply didn't pick the best available duty cycle (requested: %u/%u, applied: %u/%u, possible: %u/%u)\n",
527
+
".apply didn't pick the best available duty cycle (requested: %llu/%llu, applied: %llu/%llu, possible: %llu/%llu)\n",
528
528
state->duty_cycle, state->period,
529
529
s2.duty_cycle, s2.period,
530
530
last->duty_cycle, last->period);
531
531
532
532
if (state->enabled && state->duty_cycle < s2.duty_cycle)
533
533
dev_warn(chip->dev,
534
-
".apply is supposed to round down duty_cycle (requested: %u/%u, applied: %u/%u)\n",
534
+
".apply is supposed to round down duty_cycle (requested: %llu/%llu, applied: %llu/%llu)\n",
535
535
state->duty_cycle, state->period,
536
536
s2.duty_cycle, s2.period);
537
537
···
558
558
(s1.enabled && s1.period != last->period) ||
559
559
(s1.enabled && s1.duty_cycle != last->duty_cycle)) {
560
560
dev_err(chip->dev,
561
-
".apply is not idempotent (ena=%d pol=%d %u/%u) -> (ena=%d pol=%d %u/%u)\n",
561
+
".apply is not idempotent (ena=%d pol=%d %llu/%llu) -> (ena=%d pol=%d %llu/%llu)\n",
562
562
s1.enabled, s1.polarity, s1.duty_cycle, s1.period,
563
563
last->enabled, last->polarity, last->duty_cycle,
564
564
last->period);
···
1284
1284
if (state.enabled)
1285
1285
seq_puts(s, " enabled");
1286
1286
1287
-
seq_printf(s, " period: %u ns", state.period);
1288
-
seq_printf(s, " duty: %u ns", state.duty_cycle);
1287
+
seq_printf(s, " period: %llu ns", state.period);
1288
+
seq_printf(s, " duty: %llu ns", state.duty_cycle);
1289
1289
seq_printf(s, " polarity: %s",
1290
1290
state.polarity ? "inverse" : "normal");
1291
1291
+8
-4
drivers/pwm/pwm-bcm-iproc.c
+8
-4
drivers/pwm/pwm-bcm-iproc.c
···
85
85
u64 tmp, multi, rate;
86
86
u32 value, prescale;
87
87
88
-
rate = clk_get_rate(ip->clk);
89
-
90
88
value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
91
89
92
90
if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm)))
···
96
98
state->polarity = PWM_POLARITY_NORMAL;
97
99
else
98
100
state->polarity = PWM_POLARITY_INVERSED;
101
+
102
+
rate = clk_get_rate(ip->clk);
103
+
if (rate == 0) {
104
+
state->period = 0;
105
+
state->duty_cycle = 0;
106
+
return;
107
+
}
99
108
100
109
value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
101
110
prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
···
148
143
value = rate * state->duty_cycle;
149
144
duty = div64_u64(value, div);
150
145
151
-
if (period < IPROC_PWM_PERIOD_MIN ||
152
-
duty < IPROC_PWM_DUTY_CYCLE_MIN)
146
+
if (period < IPROC_PWM_PERIOD_MIN)
153
147
return -EINVAL;
154
148
155
149
if (period <= IPROC_PWM_PERIOD_MAX &&
+1
-1
drivers/pwm/pwm-bcm-kona.c
+1
-1
drivers/pwm/pwm-bcm-kona.c
···
138
138
dc = div64_u64(val, div);
139
139
140
140
/* If duty_ns or period_ns are not achievable then return */
141
-
if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN)
141
+
if (pc < PERIOD_COUNT_MIN)
142
142
return -EINVAL;
143
143
144
144
/* If pc and dc are in bounds, the calculation is done */
+1
-1
drivers/pwm/pwm-clps711x.c
+1
-1
drivers/pwm/pwm-clps711x.c
···
43
43
static unsigned int clps711x_get_duty(struct pwm_device *pwm, unsigned int v)
44
44
{
45
45
/* Duty cycle 0..15 max */
46
-
return DIV_ROUND_CLOSEST(v * 0xf, pwm->args.period);
46
+
return DIV64_U64_ROUND_CLOSEST(v * 0xf, pwm->args.period);
47
47
}
48
48
49
49
static int clps711x_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+1
-1
drivers/pwm/pwm-imx-tpm.c
+1
-1
drivers/pwm/pwm-imx-tpm.c
···
124
124
real_state->duty_cycle = state->duty_cycle;
125
125
126
126
tmp = (u64)p->mod * real_state->duty_cycle;
127
-
p->val = DIV_ROUND_CLOSEST_ULL(tmp, real_state->period);
127
+
p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
128
128
129
129
real_state->polarity = state->polarity;
130
130
real_state->enabled = state->enabled;
+1
-1
drivers/pwm/pwm-imx27.c
+1
-1
drivers/pwm/pwm-imx27.c
···
202
202
sr = readl(imx->mmio_base + MX3_PWMSR);
203
203
fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
204
204
if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
205
-
period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
205
+
period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
206
206
NSEC_PER_MSEC);
207
207
msleep(period_ms);
208
208
+8
-7
drivers/pwm/pwm-iqs620a.c
+8
-7
drivers/pwm/pwm-iqs620a.c
···
25
25
#include <linux/regmap.h>
26
26
#include <linux/slab.h>
27
27
28
-
#define IQS620_PWR_SETTINGS 0xD2
28
+
#define IQS620_PWR_SETTINGS 0xd2
29
29
#define IQS620_PWR_SETTINGS_PWM_OUT BIT(7)
30
30
31
-
#define IQS620_PWM_DUTY_CYCLE 0xD8
31
+
#define IQS620_PWM_DUTY_CYCLE 0xd8
32
32
33
33
#define IQS620_PWM_PERIOD_NS 1000000
34
34
···
46
46
{
47
47
struct iqs620_pwm_private *iqs620_pwm;
48
48
struct iqs62x_core *iqs62x;
49
-
int duty_scale, ret;
49
+
u64 duty_scale;
50
+
int ret;
50
51
51
52
if (state->polarity != PWM_POLARITY_NORMAL)
52
53
return -ENOTSUPP;
···
70
69
* For lower duty cycles (e.g. 0), the PWM output is simply disabled to
71
70
* allow an external pull-down resistor to hold the GPIO3/LTX pin low.
72
71
*/
73
-
duty_scale = state->duty_cycle * 256 / IQS620_PWM_PERIOD_NS;
72
+
duty_scale = div_u64(state->duty_cycle * 256, IQS620_PWM_PERIOD_NS);
74
73
75
74
mutex_lock(&iqs620_pwm->lock);
76
75
···
82
81
}
83
82
84
83
if (duty_scale) {
85
-
u8 duty_val = min(duty_scale - 1, 0xFF);
84
+
u8 duty_val = min_t(u64, duty_scale - 1, 0xff);
86
85
87
86
ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
88
87
duty_val);
···
94
93
95
94
if (state->enabled && duty_scale) {
96
95
ret = regmap_update_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
97
-
IQS620_PWR_SETTINGS_PWM_OUT, 0xFF);
96
+
IQS620_PWR_SETTINGS_PWM_OUT, 0xff);
98
97
if (ret)
99
98
goto err_mutex;
100
99
}
···
160
159
161
160
ret = regmap_update_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
162
161
IQS620_PWR_SETTINGS_PWM_OUT,
163
-
iqs620_pwm->out_en ? 0xFF : 0);
162
+
iqs620_pwm->out_en ? 0xff : 0);
164
163
165
164
err_mutex:
166
165
mutex_unlock(&iqs620_pwm->lock);
+1
drivers/pwm/pwm-mediatek.c
+1
drivers/pwm/pwm-mediatek.c
+2
-2
drivers/pwm/pwm-omap-dmtimer.c
+2
-2
drivers/pwm/pwm-omap-dmtimer.c
···
14
14
* with a timer counter that goes up. When it overflows it gets
15
15
* reloaded with the load value and the pwm output goes up.
16
16
* When counter matches with match register, the output goes down.
17
-
* Reference Manual: http://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
17
+
* Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
18
18
*
19
19
* Limitations:
20
20
* - When PWM is stopped, timer counter gets stopped immediately. This
···
58
58
* @mutex: Mutex to protect pwm apply state
59
59
* @dm_timer: Pointer to omap dm timer.
60
60
* @pdata: Pointer to omap dm timer ops.
61
-
* dm_timer_pdev: Pointer to omap dm timer platform device
61
+
* @dm_timer_pdev: Pointer to omap dm timer platform device
62
62
*/
63
63
struct pwm_omap_dmtimer_chip {
64
64
struct pwm_chip chip;
+1
-1
drivers/pwm/pwm-sifive.c
+1
-1
drivers/pwm/pwm-sifive.c
···
181
181
* consecutively
182
182
*/
183
183
num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
184
-
frac = DIV_ROUND_CLOSEST_ULL(num, state->period);
184
+
frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
185
185
/* The hardware cannot generate a 100% duty cycle */
186
186
frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
187
187
+1
-1
drivers/pwm/pwm-stm32-lp.c
+1
-1
drivers/pwm/pwm-stm32-lp.c
+1
-1
drivers/pwm/pwm-sun4i.c
+1
-1
drivers/pwm/pwm-sun4i.c
···
285
285
val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
286
286
sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
287
287
sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
288
-
usecs_to_jiffies(cstate.period / 1000 + 1);
288
+
nsecs_to_jiffies(cstate.period + 1000);
289
289
290
290
if (state->polarity != PWM_POLARITY_NORMAL)
291
291
ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
+1
-1
drivers/pwm/pwm-tiecap.c
+1
-1
drivers/pwm/pwm-tiecap.c
+1
-1
drivers/pwm/pwm-tiehrpwm.c
+1
-1
drivers/pwm/pwm-tiehrpwm.c
+4
-4
drivers/pwm/sysfs.c
+4
-4
drivers/pwm/sysfs.c
···
42
42
43
43
pwm_get_state(pwm, &state);
44
44
45
-
return sprintf(buf, "%u\n", state.period);
45
+
return sprintf(buf, "%llu\n", state.period);
46
46
}
47
47
48
48
static ssize_t period_store(struct device *child,
···
52
52
struct pwm_export *export = child_to_pwm_export(child);
53
53
struct pwm_device *pwm = export->pwm;
54
54
struct pwm_state state;
55
-
unsigned int val;
55
+
u64 val;
56
56
int ret;
57
57
58
-
ret = kstrtouint(buf, 0, &val);
58
+
ret = kstrtou64(buf, 0, &val);
59
59
if (ret)
60
60
return ret;
61
61
···
77
77
78
78
pwm_get_state(pwm, &state);
79
79
80
-
return sprintf(buf, "%u\n", state.duty_cycle);
80
+
return sprintf(buf, "%llu\n", state.duty_cycle);
81
81
}
82
82
83
83
static ssize_t duty_cycle_store(struct device *child,
+2
-1
drivers/video/backlight/pwm_bl.c
+2
-1
drivers/video/backlight/pwm_bl.c
···
601
601
pb->scale = data->max_brightness;
602
602
}
603
603
604
-
pb->lth_brightness = data->lth_brightness * (state.period / pb->scale);
604
+
pb->lth_brightness = data->lth_brightness * (div_u64(state.period,
605
+
pb->scale));
605
606
606
607
props.type = BACKLIGHT_RAW;
607
608
props.max_brightness = data->max_brightness;
+1
-1
drivers/video/fbdev/ssd1307fb.c
+1
-1
drivers/video/fbdev/ssd1307fb.c
+6
-6
include/linux/pwm.h
+6
-6
include/linux/pwm.h
···
39
39
* current PWM hardware state.
40
40
*/
41
41
struct pwm_args {
42
-
unsigned int period;
42
+
u64 period;
43
43
enum pwm_polarity polarity;
44
44
};
45
45
···
56
56
* @enabled: PWM enabled status
57
57
*/
58
58
struct pwm_state {
59
-
unsigned int period;
60
-
unsigned int duty_cycle;
59
+
u64 period;
60
+
u64 duty_cycle;
61
61
enum pwm_polarity polarity;
62
62
bool enabled;
63
63
};
···
107
107
return state.enabled;
108
108
}
109
109
110
-
static inline void pwm_set_period(struct pwm_device *pwm, unsigned int period)
110
+
static inline void pwm_set_period(struct pwm_device *pwm, u64 period)
111
111
{
112
112
if (pwm)
113
113
pwm->state.period = period;
114
114
}
115
115
116
-
static inline unsigned int pwm_get_period(const struct pwm_device *pwm)
116
+
static inline u64 pwm_get_period(const struct pwm_device *pwm)
117
117
{
118
118
struct pwm_state state;
119
119
···
128
128
pwm->state.duty_cycle = duty;
129
129
}
130
130
131
-
static inline unsigned int pwm_get_duty_cycle(const struct pwm_device *pwm)
131
+
static inline u64 pwm_get_duty_cycle(const struct pwm_device *pwm)
132
132
{
133
133
struct pwm_state state;
134
134