tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/display: Adjust static-ness of resource functions

[Why]
Register definitions are asic-specific, so functions that use registers of
a particular asic should be static, to be exposed in asic-specific function
pointer structures.

[How]
- make register-definition-using functions static
- make some functions non-static, for future use
- remove duplicate function definition

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Joshua Aberback and committed by
Alex Deucher fe04afad bcca6298

+18 -13
-1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
··· 95 95 struct dc_context *ctx, uint32_t inst); 96 96 void dcn20_dsc_destroy(struct display_stream_compressor **dsc); 97 97 98 - void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb); 99 98 void dcn20_cap_soc_clocks( 100 99 struct _vcs_dpi_soc_bounding_box_st *bb, 101 100 struct pp_smu_nv_clock_table max_clocks);
+15 -12
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
··· 871 871 *dpp = NULL; 872 872 } 873 873 874 - struct dpp *dcn30_dpp_create( 874 + static struct dpp *dcn30_dpp_create( 875 875 struct dc_context *ctx, 876 876 uint32_t inst) 877 877 { ··· 889 889 kfree(dpp); 890 890 return NULL; 891 891 } 892 - struct output_pixel_processor *dcn30_opp_create( 892 + 893 + static struct output_pixel_processor *dcn30_opp_create( 893 894 struct dc_context *ctx, uint32_t inst) 894 895 { 895 896 struct dcn20_opp *opp = ··· 906 905 return &opp->base; 907 906 } 908 907 909 - struct dce_aux *dcn30_aux_engine_create( 908 + static struct dce_aux *dcn30_aux_engine_create( 910 909 struct dc_context *ctx, 911 910 uint32_t inst) 912 911 { ··· 925 924 926 925 return &aux_engine->base; 927 926 } 927 + 928 928 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 929 929 930 930 static const struct dce_i2c_registers i2c_hw_regs[] = { ··· 945 943 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 946 944 }; 947 945 948 - struct dce_i2c_hw *dcn30_i2c_hw_create( 946 + static struct dce_i2c_hw *dcn30_i2c_hw_create( 949 947 struct dc_context *ctx, 950 948 uint32_t inst) 951 949 { ··· 960 958 961 959 return dce_i2c_hw; 962 960 } 961 + 963 962 static struct mpc *dcn30_mpc_create( 964 963 struct dc_context *ctx, 965 964 int num_mpcc, ··· 1011 1008 return &hubbub3->base; 1012 1009 } 1013 1010 1014 - struct timing_generator *dcn30_timing_generator_create( 1011 + static struct timing_generator *dcn30_timing_generator_create( 1015 1012 struct dc_context *ctx, 1016 1013 uint32_t instance) 1017 1014 { ··· 1045 1042 .flags.bits.IS_TPS4_CAPABLE = true 1046 1043 }; 1047 1044 1048 - struct link_encoder *dcn30_link_encoder_create( 1045 + static struct link_encoder *dcn30_link_encoder_create( 1049 1046 const struct encoder_init_data *enc_init_data) 1050 1047 { 1051 1048 struct dcn20_link_encoder *enc20 = ··· 1066 1063 return &enc20->enc10.base; 1067 1064 } 1068 1065 1069 - struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1066 + static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1070 1067 { 1071 1068 struct dce_panel_cntl *panel_cntl = 1072 1069 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); ··· 1314 1311 dcn_dccg_destroy(&pool->base.dccg); 1315 1312 } 1316 1313 1317 - struct hubp *dcn30_hubp_create( 1314 + static struct hubp *dcn30_hubp_create( 1318 1315 struct dc_context *ctx, 1319 1316 uint32_t inst) 1320 1317 { ··· 1333 1330 return NULL; 1334 1331 } 1335 1332 1336 - bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1333 + static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1337 1334 { 1338 1335 int i; 1339 1336 uint32_t pipe_count = pool->res_cap->num_dwb; ··· 1358 1355 return true; 1359 1356 } 1360 1357 1361 - bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1358 + static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1362 1359 { 1363 1360 int i; 1364 1361 uint32_t pipe_count = pool->res_cap->num_dwb; ··· 2295 2292 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2296 2293 } 2297 2294 2298 - static void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2295 + void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2299 2296 { 2300 2297 unsigned int i, j; 2301 2298 unsigned int num_states = 0; ··· 2686 2683 if (!resource_construct(num_virtual_links, dc, &pool->base, 2687 2684 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2688 2685 &res_create_funcs : &res_create_maximus_funcs))) 2689 - goto create_fail; 2686 + goto create_fail; 2690 2687 2691 2688 /* HW Sequencer and Plane caps */ 2692 2689 dcn30_hw_sequencer_construct(dc);
+3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
··· 79 79 struct dc *dc, 80 80 struct dc_state *new_ctx, 81 81 struct dc_stream_state *dc_stream); 82 + 83 + void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); 84 + 82 85 #endif /* _DCN30_RESOURCE_H_ */