+28 -11

Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml

reviewed

··· 21 21 - qcom,soundwire-v1.5.1 22 22 - qcom,soundwire-v1.6.0 23 23 - qcom,soundwire-v1.7.0 24 24 + - qcom,soundwire-v2.0.0 24 25 25 26 reg: 26 27 maxItems: 1 ··· 81 80 or applicable for the respective data port. 82 81 More info in MIPI Alliance SoundWire 1.0 Specifications. 83 82 minItems: 3 84 84 - maxItems: 8 83 83 + maxItems: 16 85 84 86 85 qcom,ports-sinterval-low: 87 86 $ref: /schemas/types.yaml#/definitions/uint8-array 88 87 description: 89 89 - Sample interval low of each data port. 88 88 + Sample interval (only lowest byte) of each data port. 90 89 Out ports followed by In ports. Used for Sample Interval calculation. 91 90 Value of 0xff indicates that this option is not implemented 92 91 or applicable for the respective data port. 93 92 More info in MIPI Alliance SoundWire 1.0 Specifications. 94 93 minItems: 3 95 95 - maxItems: 8 94 94 + maxItems: 16 95 95 + 96 96 + qcom,ports-sinterval: 97 97 + $ref: /schemas/types.yaml#/definitions/uint16-array 98 98 + description: 99 99 + Sample interval of each data port. 100 100 + Out ports followed by In ports. Used for Sample Interval calculation. 101 101 + Value of 0xffff indicates that this option is not implemented 102 102 + or applicable for the respective data port. 103 103 + More info in MIPI Alliance SoundWire 1.0 Specifications. 104 104 + minItems: 3 105 105 + maxItems: 16 96 106 97 107 qcom,ports-offset1: 98 108 $ref: /schemas/types.yaml#/definitions/uint8-array ··· 114 102 or applicable for the respective data port. 115 103 More info in MIPI Alliance SoundWire 1.0 Specifications. 116 104 minItems: 3 117 117 - maxItems: 8 105 105 + maxItems: 16 118 106 119 107 qcom,ports-offset2: 120 108 $ref: /schemas/types.yaml#/definitions/uint8-array ··· 125 113 or applicable for the respective data port. 126 114 More info in MIPI Alliance SoundWire 1.0 Specifications. 127 115 minItems: 3 128 128 - maxItems: 8 116 116 + maxItems: 16 129 117 130 118 qcom,ports-lane-control: 131 119 $ref: /schemas/types.yaml#/definitions/uint8-array ··· 136 124 or applicable for the respective data port. 137 125 More info in MIPI Alliance SoundWire 1.0 Specifications. 138 126 minItems: 3 139 139 - maxItems: 8 127 127 + maxItems: 16 140 128 141 129 qcom,ports-block-pack-mode: 142 130 $ref: /schemas/types.yaml#/definitions/uint8-array ··· 149 137 or applicable for the respective data port. 150 138 More info in MIPI Alliance SoundWire 1.0 Specifications. 151 139 minItems: 3 152 152 - maxItems: 8 140 140 + maxItems: 16 153 141 items: 154 142 oneOf: 155 143 - minimum: 0 ··· 166 154 or applicable for the respective data port. 167 155 More info in MIPI Alliance SoundWire 1.0 Specifications. 168 156 minItems: 3 169 169 - maxItems: 8 157 157 + maxItems: 16 170 158 items: 171 159 oneOf: 172 160 - minimum: 0 ··· 183 171 or applicable for the respective data port. 184 172 More info in MIPI Alliance SoundWire 1.0 Specifications. 185 173 minItems: 3 186 186 - maxItems: 8 174 174 + maxItems: 16 187 175 items: 188 176 oneOf: 189 177 - minimum: 0 ··· 199 187 or applicable for the respective data port. 200 188 More info in MIPI Alliance SoundWire 1.0 Specifications. 201 189 minItems: 3 202 202 - maxItems: 8 190 190 + maxItems: 16 203 191 items: 204 192 oneOf: 205 193 - minimum: 0 ··· 231 219 - '#size-cells' 232 220 - qcom,dout-ports 233 221 - qcom,din-ports 234 234 - - qcom,ports-sinterval-low 235 222 - qcom,ports-offset1 236 223 - qcom,ports-offset2 224 224 + 225 225 + oneOf: 226 226 + - required: 227 227 + - qcom,ports-sinterval-low 228 228 + - required: 229 229 + - qcom,ports-sinterval 237 230 238 231 additionalProperties: false 239 232

+1

drivers/soundwire/Kconfig

reviewed

··· 37 37 select SOUNDWIRE_GENERIC_ALLOCATION 38 38 select AUXILIARY_BUS 39 39 depends on ACPI && SND_SOC 40 40 + depends on SND_SOC_SOF_HDA_MLINK || !SND_SOC_SOF_HDA_MLINK 40 41 help 41 42 SoundWire Intel Master driver. 42 43 If you have an Intel platform which has a SoundWire Master then

+2 -1

drivers/soundwire/Makefile

reviewed

··· 24 24 obj-$(CONFIG_SOUNDWIRE_CADENCE) += soundwire-cadence.o 25 25 26 26 #Intel driver 27 27 - soundwire-intel-y := intel.o intel_auxdevice.o intel_init.o dmi-quirks.o \ 27 27 + soundwire-intel-y := intel.o intel_ace2x.o intel_ace2x_debugfs.o \ 28 28 + intel_auxdevice.o intel_init.o dmi-quirks.o \ 28 29 intel_bus_common.o 29 30 obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel.o 30 31

+6 -3

drivers/soundwire/amd_manager.c

reviewed

··· 972 972 return 0; 973 973 } 974 974 975 975 - static int amd_sdw_manager_remove(struct platform_device *pdev) 975 975 + static void amd_sdw_manager_remove(struct platform_device *pdev) 976 976 { 977 977 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev); 978 978 + int ret; 978 979 979 980 pm_runtime_disable(&pdev->dev); 980 981 cancel_work_sync(&amd_manager->probe_work); 981 982 amd_disable_sdw_interrupts(amd_manager); 982 983 sdw_bus_master_delete(&amd_manager->bus); 983 983 - return amd_disable_sdw_manager(amd_manager); 984 984 + ret = amd_disable_sdw_manager(amd_manager); 985 985 + if (ret) 986 986 + dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret)); 984 987 } 985 988 986 989 static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager) ··· 1197 1194 1198 1195 static struct platform_driver amd_sdw_driver = { 1199 1196 .probe = &amd_sdw_manager_probe, 1200 1200 - .remove = &amd_sdw_manager_remove, 1197 1197 + .remove_new = &amd_sdw_manager_remove, 1201 1198 .driver = { 1202 1199 .name = "amd_sdw_manager", 1203 1200 .pm = &amd_pm,

+20 -10

drivers/soundwire/bus.c

reviewed

··· 69 69 return -EINVAL; 70 70 } 71 71 72 72 - mutex_init(&bus->msg_lock); 73 73 - mutex_init(&bus->bus_lock); 72 72 + /* 73 73 + * Give each bus_lock and msg_lock a unique key so that lockdep won't 74 74 + * trigger a deadlock warning when the locks of several buses are 75 75 + * grabbed during configuration of a multi-bus stream. 76 76 + */ 77 77 + lockdep_register_key(&bus->msg_lock_key); 78 78 + __mutex_init(&bus->msg_lock, "msg_lock", &bus->msg_lock_key); 79 79 + 80 80 + lockdep_register_key(&bus->bus_lock_key); 81 81 + __mutex_init(&bus->bus_lock, "bus_lock", &bus->bus_lock_key); 82 82 + 74 83 INIT_LIST_HEAD(&bus->slaves); 75 84 INIT_LIST_HEAD(&bus->m_rt_list); 76 85 ··· 190 181 sdw_master_device_del(bus); 191 182 192 183 sdw_bus_debugfs_exit(bus); 184 184 + lockdep_unregister_key(&bus->bus_lock_key); 185 185 + lockdep_unregister_key(&bus->msg_lock_key); 193 186 ida_free(&sdw_bus_ida, bus->id); 194 187 } 195 188 EXPORT_SYMBOL(sdw_bus_master_delete); ··· 779 768 780 769 /* After xfer of msg, restore dev_num */ 781 770 slave->dev_num = slave->dev_num_sticky; 771 771 + 772 772 + if (bus->ops && bus->ops->new_peripheral_assigned) 773 773 + bus->ops->new_peripheral_assigned(bus, dev_num); 782 774 783 775 return 0; 784 776 } ··· 1602 1588 unsigned long port; 1603 1589 bool slave_notify; 1604 1590 u8 sdca_cascade = 0; 1605 1605 - u8 buf, buf2[2], _buf, _buf2[2]; 1591 1591 + u8 buf, buf2[2]; 1606 1592 bool parity_check; 1607 1593 bool parity_quirk; 1608 1594 ··· 1759 1745 "SDW_SCP_INT1 recheck read failed:%d\n", ret); 1760 1746 goto io_err; 1761 1747 } 1762 1762 - _buf = ret; 1748 1748 + buf = ret; 1763 1749 1764 1764 - ret = sdw_nread_no_pm(slave, SDW_SCP_INTSTAT2, 2, _buf2); 1750 1750 + ret = sdw_nread_no_pm(slave, SDW_SCP_INTSTAT2, 2, buf2); 1765 1751 if (ret < 0) { 1766 1752 dev_err(&slave->dev, 1767 1753 "SDW_SCP_INT2/3 recheck read failed:%d\n", ret); ··· 1779 1765 } 1780 1766 1781 1767 /* 1782 1782 - * Make sure no interrupts are pending, but filter to limit loop 1783 1783 - * to interrupts identified in the first status read 1768 1768 + * Make sure no interrupts are pending 1784 1769 */ 1785 1785 - buf &= _buf; 1786 1786 - buf2[0] &= _buf2[0]; 1787 1787 - buf2[1] &= _buf2[1]; 1788 1770 stat = buf || buf2[0] || buf2[1] || sdca_cascade; 1789 1771 1790 1772 /*

+34 -16

drivers/soundwire/cadence_master.c

reviewed

··· 283 283 return ret; 284 284 } 285 285 286 286 + /** 287 287 + * sdw_cdns_config_update() - Update configurations 288 288 + * @cdns: Cadence instance 289 289 + */ 290 290 + void sdw_cdns_config_update(struct sdw_cdns *cdns) 291 291 + { 292 292 + /* commit changes */ 293 293 + cdns_writel(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT); 294 294 + } 295 295 + EXPORT_SYMBOL(sdw_cdns_config_update); 296 296 + 297 297 + /** 298 298 + * sdw_cdns_config_update_set_wait() - wait until configuration update bit is self-cleared 299 299 + * @cdns: Cadence instance 300 300 + */ 301 301 + int sdw_cdns_config_update_set_wait(struct sdw_cdns *cdns) 302 302 + { 303 303 + /* the hardware recommendation is to wait at least 300us */ 304 304 + return cdns_set_wait(cdns, CDNS_MCP_CONFIG_UPDATE, 305 305 + CDNS_MCP_CONFIG_UPDATE_BIT, 0); 306 306 + } 307 307 + EXPORT_SYMBOL(sdw_cdns_config_update_set_wait); 308 308 + 286 309 /* 287 310 * debugfs 288 311 */ ··· 456 433 CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR); 457 434 458 435 /* commit changes */ 459 459 - cdns_updatel(cdns, CDNS_MCP_CONFIG_UPDATE, 460 460 - CDNS_MCP_CONFIG_UPDATE_BIT, 461 461 - CDNS_MCP_CONFIG_UPDATE_BIT); 436 436 + ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT); 437 437 + if (ret < 0) 438 438 + goto unlock; 462 439 463 440 /* do a broadcast dummy read to avoid bus clashes */ 464 441 ret = sdw_bread_no_pm_unlocked(&cdns->bus, 0xf, SDW_SCP_DEVID_0); ··· 470 447 0); 471 448 472 449 /* commit changes */ 473 473 - cdns_updatel(cdns, CDNS_MCP_CONFIG_UPDATE, 474 474 - CDNS_MCP_CONFIG_UPDATE_BIT, 475 475 - CDNS_MCP_CONFIG_UPDATE_BIT); 476 476 - 477 477 - /* Continue bus operation with parity error injection disabled */ 478 478 - mutex_unlock(&bus->bus_lock); 450 450 + ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT); 451 451 + if (ret < 0) 452 452 + goto unlock; 479 453 480 454 /* Userspace changed the hardware state behind the kernel's back */ 481 455 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 456 456 + 457 457 + unlock: 458 458 + /* Continue bus operation with parity error injection disabled */ 459 459 + mutex_unlock(&bus->bus_lock); 482 460 483 461 /* 484 462 * allow Master device to enter pm_runtime suspend. This may ··· 1140 1116 CDNS_MCP_CONTROL_HW_RST); 1141 1117 1142 1118 /* commit changes */ 1143 1143 - cdns_updatel(cdns, CDNS_MCP_CONFIG_UPDATE, 1144 1144 - CDNS_MCP_CONFIG_UPDATE_BIT, 1145 1145 - CDNS_MCP_CONFIG_UPDATE_BIT); 1146 1146 - 1147 1147 - /* don't wait here */ 1148 1148 - return 0; 1149 1149 - 1119 1119 + return cdns_config_update(cdns); 1150 1120 } 1151 1121 EXPORT_SYMBOL(sdw_cdns_exit_reset); 1152 1122

+5

drivers/soundwire/cadence_master.h

reviewed

··· 14 14 */ 15 15 #define CDNS_MCP_IP_MAX_CMD_LEN 32 16 16 17 17 + #define SDW_CADENCE_MCP_IP_OFFSET 0x4000 18 18 + 17 19 /** 18 20 * struct sdw_cdns_pdi: PDI (Physical Data Interface) instance 19 21 * ··· 198 196 199 197 void sdw_cdns_check_self_clearing_bits(struct sdw_cdns *cdns, const char *string, 200 198 bool initial_delay, int reset_iterations); 199 199 + 200 200 + void sdw_cdns_config_update(struct sdw_cdns *cdns); 201 201 + int sdw_cdns_config_update_set_wait(struct sdw_cdns *cdns); 201 202 202 203 #endif /* __SDW_CADENCE_H */

+10 -2

drivers/soundwire/debugfs.c

reviewed

··· 56 56 if (!buf) 57 57 return -ENOMEM; 58 58 59 59 - ret = pm_runtime_resume_and_get(&slave->dev); 59 59 + ret = pm_runtime_get_sync(&slave->dev); 60 60 if (ret < 0 && ret != -EACCES) { 61 61 + pm_runtime_put_noidle(&slave->dev); 61 62 kfree(buf); 62 63 return ret; 63 64 } ··· 86 85 87 86 /* SCP registers */ 88 87 ret += scnprintf(buf + ret, RD_BUF - ret, "\nSCP\n"); 89 89 - for (i = SDW_SCP_INT1; i <= SDW_SCP_BANKDELAY; i++) 88 88 + for (i = SDW_SCP_INT1; i <= SDW_SCP_BUS_CLOCK_BASE; i++) 90 89 ret += sdw_sprintf(slave, buf, ret, i); 91 90 for (i = SDW_SCP_DEVID_0; i <= SDW_SCP_DEVID_5; i++) 92 91 ret += sdw_sprintf(slave, buf, ret, i); 92 92 + for (i = SDW_SCP_FRAMECTRL_B0; i <= SDW_SCP_BUSCLOCK_SCALE_B0; i++) 93 93 + ret += sdw_sprintf(slave, buf, ret, i); 94 94 + for (i = SDW_SCP_FRAMECTRL_B1; i <= SDW_SCP_BUSCLOCK_SCALE_B1; i++) 95 95 + ret += sdw_sprintf(slave, buf, ret, i); 96 96 + for (i = SDW_SCP_PHY_OUT_CTRL_0; i <= SDW_SCP_PHY_OUT_CTRL_7; i++) 97 97 + ret += sdw_sprintf(slave, buf, ret, i); 98 98 + 93 99 94 100 /* 95 101 * SCP Bank 0/1 registers are read-only and cannot be

+3 -7

drivers/soundwire/generic_bandwidth_allocation.c

reviewed

··· 139 139 { 140 140 struct sdw_master_runtime *m_rt; 141 141 int hstop = bus->params.col - 1; 142 142 - int block_offset, port_bo, i; 142 142 + int port_bo, i; 143 143 144 144 /* Run loop for all groups to compute transport parameters */ 145 145 for (i = 0; i < count; i++) { 146 146 port_bo = 1; 147 147 - block_offset = 1; 148 147 149 148 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 150 150 - sdw_compute_master_ports(m_rt, &params[i], 151 151 - port_bo, hstop); 149 149 + sdw_compute_master_ports(m_rt, &params[i], port_bo, hstop); 152 150 153 153 - block_offset += m_rt->ch_count * 154 154 - m_rt->stream->params.bps; 155 155 - port_bo = block_offset; 151 151 + port_bo += m_rt->ch_count * m_rt->stream->params.bps; 156 152 } 157 153 158 154 hstop = hstop - params[i].hwidth;

+7 -50

drivers/soundwire/intel.c

reviewed

··· 260 260 { 261 261 void __iomem *shim = sdw->link_res->shim; 262 262 unsigned int link_id = sdw->instance; 263 263 - u16 ioctl = 0, act = 0; 263 263 + u16 ioctl = 0, act; 264 264 265 265 /* Initialize Shim */ 266 266 ioctl |= SDW_SHIM_IOCTL_BKE; ··· 281 281 282 282 intel_shim_glue_to_master_ip(sdw); 283 283 284 284 + act = intel_readw(shim, SDW_SHIM_CTMCTL(link_id)); 284 285 u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS); 285 286 act |= SDW_SHIM_CTMCTL_DACTQE; 286 287 act |= SDW_SHIM_CTMCTL_DODS; ··· 644 643 } 645 644 646 645 static int intel_params_stream(struct sdw_intel *sdw, 647 647 - int stream, 646 646 + struct snd_pcm_substream *substream, 648 647 struct snd_soc_dai *dai, 649 648 struct snd_pcm_hw_params *hw_params, 650 649 int link_id, int alh_stream_id) ··· 652 651 struct sdw_intel_link_res *res = sdw->link_res; 653 652 struct sdw_intel_stream_params_data params_data; 654 653 655 655 - params_data.stream = stream; /* direction */ 654 654 + params_data.substream = substream; 656 655 params_data.dai = dai; 657 656 params_data.hw_params = hw_params; 658 657 params_data.link_id = link_id; ··· 662 661 return res->ops->params_stream(res->dev, 663 662 &params_data); 664 663 return -EIO; 665 665 - } 666 666 - 667 667 - static int intel_free_stream(struct sdw_intel *sdw, 668 668 - int stream, 669 669 - struct snd_soc_dai *dai, 670 670 - int link_id) 671 671 - { 672 672 - struct sdw_intel_link_res *res = sdw->link_res; 673 673 - struct sdw_intel_stream_free_data free_data; 674 674 - 675 675 - free_data.stream = stream; /* direction */ 676 676 - free_data.dai = dai; 677 677 - free_data.link_id = link_id; 678 678 - 679 679 - if (res->ops && res->ops->free_stream && res->dev) 680 680 - return res->ops->free_stream(res->dev, 681 681 - &free_data); 682 682 - 683 683 - return 0; 684 664 } 685 665 686 666 /* ··· 709 727 dai_runtime->pdi = pdi; 710 728 711 729 /* Inform DSP about PDI stream number */ 712 712 - ret = intel_params_stream(sdw, substream->stream, dai, params, 730 730 + ret = intel_params_stream(sdw, substream, dai, params, 713 731 sdw->instance, 714 732 pdi->intel_alh_id); 715 733 if (ret) ··· 786 804 sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi); 787 805 788 806 /* Inform DSP about PDI stream number */ 789 789 - ret = intel_params_stream(sdw, substream->stream, dai, 807 807 + ret = intel_params_stream(sdw, substream, dai, 790 808 hw_params, 791 809 sdw->instance, 792 810 dai_runtime->pdi->intel_alh_id); ··· 799 817 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 800 818 { 801 819 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 802 802 - struct sdw_intel *sdw = cdns_to_intel(cdns); 803 820 struct sdw_cdns_dai_runtime *dai_runtime; 804 821 int ret; 805 822 ··· 816 835 if (ret < 0) { 817 836 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 818 837 dai_runtime->stream->name, ret); 819 819 - return ret; 820 820 - } 821 821 - 822 822 - ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance); 823 823 - if (ret < 0) { 824 824 - dev_err(dai->dev, "intel_free_stream: failed %d\n", ret); 825 838 return ret; 826 839 } 827 840 ··· 846 871 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 847 872 { 848 873 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 849 849 - struct sdw_intel *sdw = cdns_to_intel(cdns); 850 850 - struct sdw_intel_link_res *res = sdw->link_res; 851 874 struct sdw_cdns_dai_runtime *dai_runtime; 852 875 int ret = 0; 853 853 - 854 854 - /* 855 855 - * The .trigger callback is used to send required IPC to audio 856 856 - * firmware. The .free_stream callback will still be called 857 857 - * by intel_free_stream() in the TRIGGER_SUSPEND case. 858 858 - */ 859 859 - if (res->ops && res->ops->trigger) 860 860 - res->ops->trigger(dai, cmd, substream->stream); 861 876 862 877 dai_runtime = cdns->dai_runtime_array[dai->id]; 863 878 if (!dai_runtime) { ··· 868 903 869 904 dai_runtime->suspended = true; 870 905 871 871 - ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance); 872 906 break; 873 907 874 908 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ··· 913 949 */ 914 950 for_each_component_dais(component, dai) { 915 951 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 916 916 - struct sdw_intel *sdw = cdns_to_intel(cdns); 917 952 struct sdw_cdns_dai_runtime *dai_runtime; 918 918 - int ret; 919 953 920 954 dai_runtime = cdns->dai_runtime_array[dai->id]; 921 955 ··· 923 961 if (dai_runtime->suspended) 924 962 continue; 925 963 926 926 - if (dai_runtime->paused) { 964 964 + if (dai_runtime->paused) 927 965 dai_runtime->suspended = true; 928 928 - 929 929 - ret = intel_free_stream(sdw, dai_runtime->direction, dai, sdw->instance); 930 930 - if (ret < 0) 931 931 - return ret; 932 932 - } 933 966 } 934 967 935 968 return 0;

+16

drivers/soundwire/intel.h

reviewed

··· 4 4 #ifndef __SDW_INTEL_LOCAL_H 5 5 #define __SDW_INTEL_LOCAL_H 6 6 7 7 + struct hdac_bus; 8 8 + 7 9 /** 8 10 * struct sdw_intel_link_res - Soundwire Intel link resource structure, 9 11 * typically populated by the controller driver. 10 12 * @hw_ops: platform-specific ops 11 13 * @mmio_base: mmio base of SoundWire registers 12 14 * @registers: Link IO registers base 15 15 + * @ip_offset: offset for MCP_IP registers 13 16 * @shim: Audio shim pointer 17 17 + * @shim_vs: Audio vendor-specific shim pointer 14 18 * @alh: ALH (Audio Link Hub) pointer 15 19 * @irq: Interrupt line 16 20 * @ops: Shim callback ops ··· 25 21 * @link_mask: global mask needed for power-up/down sequences 26 22 * @cdns: Cadence master descriptor 27 23 * @list: used to walk-through all masters exposed by the same controller 24 24 + * @hbus: hdac_bus pointer, needed for power management 28 25 */ 29 26 struct sdw_intel_link_res { 30 27 const struct sdw_intel_hw_ops *hw_ops; 31 28 32 29 void __iomem *mmio_base; /* not strictly needed, useful for debug */ 33 30 void __iomem *registers; 31 31 + u32 ip_offset; 34 32 void __iomem *shim; 33 33 + void __iomem *shim_vs; 35 34 void __iomem *alh; 36 35 int irq; 37 36 const struct sdw_intel_ops *ops; ··· 45 38 u32 link_mask; 46 39 struct sdw_cdns *cdns; 47 40 struct list_head list; 41 41 + struct hdac_bus *hbus; 48 42 }; 49 43 50 44 struct sdw_intel { ··· 94 86 #define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \ 95 87 (sdw)->link_res->hw_ops->cb) 96 88 #define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb) 89 89 + 90 90 + #ifdef CONFIG_DEBUG_FS 91 91 + void intel_ace2x_debugfs_init(struct sdw_intel *sdw); 92 92 + void intel_ace2x_debugfs_exit(struct sdw_intel *sdw); 93 93 + #else 94 94 + static inline void intel_ace2x_debugfs_init(struct sdw_intel *sdw) {} 95 95 + static inline void intel_ace2x_debugfs_exit(struct sdw_intel *sdw) {} 96 96 + #endif 97 97 98 98 static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw) 99 99 {

+393

drivers/soundwire/intel_ace2x.c

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 2 + // Copyright(c) 2023 Intel Corporation. All rights reserved. 3 3 + 4 4 + /* 5 5 + * Soundwire Intel ops for LunarLake 6 6 + */ 7 7 + 8 8 + #include <linux/acpi.h> 9 9 + #include <linux/device.h> 10 10 + #include <linux/soundwire/sdw_registers.h> 11 11 + #include <linux/soundwire/sdw.h> 12 12 + #include <linux/soundwire/sdw_intel.h> 13 13 + #include <sound/hda-mlink.h> 14 14 + #include "cadence_master.h" 15 15 + #include "bus.h" 16 16 + #include "intel.h" 17 17 + 18 18 + /* 19 19 + * shim vendor-specific (vs) ops 20 20 + */ 21 21 + 22 22 + static void intel_shim_vs_init(struct sdw_intel *sdw) 23 23 + { 24 24 + void __iomem *shim_vs = sdw->link_res->shim_vs; 25 25 + u16 act = 0; 26 26 + 27 27 + u16p_replace_bits(&act, 0x1, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS); 28 28 + act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE; 29 29 + act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DODS; 30 30 + intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL, act); 31 31 + usleep_range(10, 15); 32 32 + } 33 33 + 34 34 + static int intel_shim_check_wake(struct sdw_intel *sdw) 35 35 + { 36 36 + void __iomem *shim_vs; 37 37 + u16 wake_sts; 38 38 + 39 39 + shim_vs = sdw->link_res->shim_vs; 40 40 + wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS); 41 41 + 42 42 + return wake_sts & SDW_SHIM2_INTEL_VS_WAKEEN_PWS; 43 43 + } 44 44 + 45 45 + static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 46 46 + { 47 47 + void __iomem *shim_vs = sdw->link_res->shim_vs; 48 48 + u16 wake_en; 49 49 + u16 wake_sts; 50 50 + 51 51 + wake_en = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN); 52 52 + 53 53 + if (wake_enable) { 54 54 + /* Enable the wakeup */ 55 55 + wake_en |= SDW_SHIM2_INTEL_VS_WAKEEN_PWE; 56 56 + intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en); 57 57 + } else { 58 58 + /* Disable the wake up interrupt */ 59 59 + wake_en &= ~SDW_SHIM2_INTEL_VS_WAKEEN_PWE; 60 60 + intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKEEN, wake_en); 61 61 + 62 62 + /* Clear wake status (W1C) */ 63 63 + wake_sts = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS); 64 64 + wake_sts |= SDW_SHIM2_INTEL_VS_WAKEEN_PWS; 65 65 + intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_WAKESTS, wake_sts); 66 66 + } 67 67 + } 68 68 + 69 69 + static int intel_link_power_up(struct sdw_intel *sdw) 70 70 + { 71 71 + struct sdw_bus *bus = &sdw->cdns.bus; 72 72 + struct sdw_master_prop *prop = &bus->prop; 73 73 + u32 *shim_mask = sdw->link_res->shim_mask; 74 74 + unsigned int link_id = sdw->instance; 75 75 + u32 syncprd; 76 76 + int ret; 77 77 + 78 78 + mutex_lock(sdw->link_res->shim_lock); 79 79 + 80 80 + if (!*shim_mask) { 81 81 + /* we first need to program the SyncPRD/CPU registers */ 82 82 + dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n"); 83 83 + 84 84 + if (prop->mclk_freq % 6000000) 85 85 + syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 86 86 + else 87 87 + syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; 88 88 + 89 89 + ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd); 90 90 + if (ret < 0) { 91 91 + dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n", 92 92 + __func__, ret); 93 93 + goto out; 94 94 + } 95 95 + } 96 96 + 97 97 + ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id); 98 98 + if (ret < 0) { 99 99 + dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n", 100 100 + __func__, ret); 101 101 + goto out; 102 102 + } 103 103 + 104 104 + if (!*shim_mask) { 105 105 + /* SYNCPU will change once link is active */ 106 106 + ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus); 107 107 + if (ret < 0) { 108 108 + dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n", 109 109 + __func__, ret); 110 110 + goto out; 111 111 + } 112 112 + } 113 113 + 114 114 + *shim_mask |= BIT(link_id); 115 115 + 116 116 + sdw->cdns.link_up = true; 117 117 + 118 118 + intel_shim_vs_init(sdw); 119 119 + 120 120 + out: 121 121 + mutex_unlock(sdw->link_res->shim_lock); 122 122 + 123 123 + return ret; 124 124 + } 125 125 + 126 126 + static int intel_link_power_down(struct sdw_intel *sdw) 127 127 + { 128 128 + u32 *shim_mask = sdw->link_res->shim_mask; 129 129 + unsigned int link_id = sdw->instance; 130 130 + int ret; 131 131 + 132 132 + mutex_lock(sdw->link_res->shim_lock); 133 133 + 134 134 + sdw->cdns.link_up = false; 135 135 + 136 136 + *shim_mask &= ~BIT(link_id); 137 137 + 138 138 + ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id); 139 139 + if (ret < 0) { 140 140 + dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n", 141 141 + __func__, ret); 142 142 + 143 143 + /* 144 144 + * we leave the sdw->cdns.link_up flag as false since we've disabled 145 145 + * the link at this point and cannot handle interrupts any longer. 146 146 + */ 147 147 + } 148 148 + 149 149 + mutex_unlock(sdw->link_res->shim_lock); 150 150 + 151 151 + return ret; 152 152 + } 153 153 + 154 154 + static void intel_sync_arm(struct sdw_intel *sdw) 155 155 + { 156 156 + unsigned int link_id = sdw->instance; 157 157 + 158 158 + mutex_lock(sdw->link_res->shim_lock); 159 159 + 160 160 + hdac_bus_eml_sdw_sync_arm_unlocked(sdw->link_res->hbus, link_id); 161 161 + 162 162 + mutex_unlock(sdw->link_res->shim_lock); 163 163 + } 164 164 + 165 165 + static int intel_sync_go_unlocked(struct sdw_intel *sdw) 166 166 + { 167 167 + int ret; 168 168 + 169 169 + ret = hdac_bus_eml_sdw_sync_go_unlocked(sdw->link_res->hbus); 170 170 + if (ret < 0) 171 171 + dev_err(sdw->cdns.dev, "%s: SyncGO clear failed: %d\n", __func__, ret); 172 172 + 173 173 + return ret; 174 174 + } 175 175 + 176 176 + static int intel_sync_go(struct sdw_intel *sdw) 177 177 + { 178 178 + int ret; 179 179 + 180 180 + mutex_lock(sdw->link_res->shim_lock); 181 181 + 182 182 + ret = intel_sync_go_unlocked(sdw); 183 183 + 184 184 + mutex_unlock(sdw->link_res->shim_lock); 185 185 + 186 186 + return ret; 187 187 + } 188 188 + 189 189 + static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw) 190 190 + { 191 191 + return hdac_bus_eml_sdw_check_cmdsync_unlocked(sdw->link_res->hbus); 192 192 + } 193 193 + 194 194 + /* 195 195 + * DAI operations 196 196 + */ 197 197 + static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 198 198 + }; 199 199 + 200 200 + static const struct snd_soc_component_driver dai_component = { 201 201 + .name = "soundwire", 202 202 + }; 203 203 + 204 204 + /* 205 205 + * PDI routines 206 206 + */ 207 207 + static void intel_pdi_init(struct sdw_intel *sdw, 208 208 + struct sdw_cdns_stream_config *config) 209 209 + { 210 210 + void __iomem *shim = sdw->link_res->shim; 211 211 + int pcm_cap; 212 212 + 213 213 + /* PCM Stream Capability */ 214 214 + pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP); 215 215 + 216 216 + config->pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap); 217 217 + config->pcm_in = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); 218 218 + config->pcm_out = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); 219 219 + 220 220 + dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 221 221 + config->pcm_bd, config->pcm_in, config->pcm_out); 222 222 + } 223 223 + 224 224 + static int 225 225 + intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num) 226 226 + { 227 227 + void __iomem *shim = sdw->link_res->shim; 228 228 + 229 229 + /* zero based values for channel count in register */ 230 230 + return intel_readw(shim, SDW_SHIM2_PCMSYCHC(pdi_num)) + 1; 231 231 + } 232 232 + 233 233 + static void intel_pdi_get_ch_update(struct sdw_intel *sdw, 234 234 + struct sdw_cdns_pdi *pdi, 235 235 + unsigned int num_pdi, 236 236 + unsigned int *num_ch) 237 237 + { 238 238 + int ch_count = 0; 239 239 + int i; 240 240 + 241 241 + for (i = 0; i < num_pdi; i++) { 242 242 + pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num); 243 243 + ch_count += pdi->ch_count; 244 244 + pdi++; 245 245 + } 246 246 + 247 247 + *num_ch = ch_count; 248 248 + } 249 249 + 250 250 + static void intel_pdi_stream_ch_update(struct sdw_intel *sdw, 251 251 + struct sdw_cdns_streams *stream) 252 252 + { 253 253 + intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 254 254 + &stream->num_ch_bd); 255 255 + 256 256 + intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 257 257 + &stream->num_ch_in); 258 258 + 259 259 + intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 260 260 + &stream->num_ch_out); 261 261 + } 262 262 + 263 263 + static int intel_create_dai(struct sdw_cdns *cdns, 264 264 + struct snd_soc_dai_driver *dais, 265 265 + enum intel_pdi_type type, 266 266 + u32 num, u32 off, u32 max_ch) 267 267 + { 268 268 + int i; 269 269 + 270 270 + if (!num) 271 271 + return 0; 272 272 + 273 273 + for (i = off; i < (off + num); i++) { 274 274 + dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, 275 275 + "SDW%d Pin%d", 276 276 + cdns->instance, i); 277 277 + if (!dais[i].name) 278 278 + return -ENOMEM; 279 279 + 280 280 + if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 281 281 + dais[i].playback.channels_min = 1; 282 282 + dais[i].playback.channels_max = max_ch; 283 283 + } 284 284 + 285 285 + if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 286 286 + dais[i].capture.channels_min = 1; 287 287 + dais[i].capture.channels_max = max_ch; 288 288 + } 289 289 + 290 290 + dais[i].ops = &intel_pcm_dai_ops; 291 291 + } 292 292 + 293 293 + return 0; 294 294 + } 295 295 + 296 296 + static int intel_register_dai(struct sdw_intel *sdw) 297 297 + { 298 298 + struct sdw_cdns_dai_runtime **dai_runtime_array; 299 299 + struct sdw_cdns_stream_config config; 300 300 + struct sdw_cdns *cdns = &sdw->cdns; 301 301 + struct sdw_cdns_streams *stream; 302 302 + struct snd_soc_dai_driver *dais; 303 303 + int num_dai; 304 304 + int ret; 305 305 + int off = 0; 306 306 + 307 307 + /* Read the PDI config and initialize cadence PDI */ 308 308 + intel_pdi_init(sdw, &config); 309 309 + ret = sdw_cdns_pdi_init(cdns, config); 310 310 + if (ret) 311 311 + return ret; 312 312 + 313 313 + intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm); 314 314 + 315 315 + /* DAIs are created based on total number of PDIs supported */ 316 316 + num_dai = cdns->pcm.num_pdi; 317 317 + 318 318 + dai_runtime_array = devm_kcalloc(cdns->dev, num_dai, 319 319 + sizeof(struct sdw_cdns_dai_runtime *), 320 320 + GFP_KERNEL); 321 321 + if (!dai_runtime_array) 322 322 + return -ENOMEM; 323 323 + cdns->dai_runtime_array = dai_runtime_array; 324 324 + 325 325 + dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 326 326 + if (!dais) 327 327 + return -ENOMEM; 328 328 + 329 329 + /* Create PCM DAIs */ 330 330 + stream = &cdns->pcm; 331 331 + 332 332 + ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, 333 333 + off, stream->num_ch_in); 334 334 + if (ret) 335 335 + return ret; 336 336 + 337 337 + off += cdns->pcm.num_in; 338 338 + ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 339 339 + off, stream->num_ch_out); 340 340 + if (ret) 341 341 + return ret; 342 342 + 343 343 + off += cdns->pcm.num_out; 344 344 + ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 345 345 + off, stream->num_ch_bd); 346 346 + if (ret) 347 347 + return ret; 348 348 + 349 349 + return devm_snd_soc_register_component(cdns->dev, &dai_component, 350 350 + dais, num_dai); 351 351 + } 352 352 + 353 353 + static void intel_program_sdi(struct sdw_intel *sdw, int dev_num) 354 354 + { 355 355 + int ret; 356 356 + 357 357 + ret = hdac_bus_eml_sdw_set_lsdiid(sdw->link_res->hbus, sdw->instance, dev_num); 358 358 + if (ret < 0) 359 359 + dev_err(sdw->cdns.dev, "%s: could not set lsdiid for link %d %d\n", 360 360 + __func__, sdw->instance, dev_num); 361 361 + } 362 362 + 363 363 + const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = { 364 364 + .debugfs_init = intel_ace2x_debugfs_init, 365 365 + .debugfs_exit = intel_ace2x_debugfs_exit, 366 366 + 367 367 + .register_dai = intel_register_dai, 368 368 + 369 369 + .check_clock_stop = intel_check_clock_stop, 370 370 + .start_bus = intel_start_bus, 371 371 + .start_bus_after_reset = intel_start_bus_after_reset, 372 372 + .start_bus_after_clock_stop = intel_start_bus_after_clock_stop, 373 373 + .stop_bus = intel_stop_bus, 374 374 + 375 375 + .link_power_up = intel_link_power_up, 376 376 + .link_power_down = intel_link_power_down, 377 377 + 378 378 + .shim_check_wake = intel_shim_check_wake, 379 379 + .shim_wake = intel_shim_wake, 380 380 + 381 381 + .pre_bank_switch = intel_pre_bank_switch, 382 382 + .post_bank_switch = intel_post_bank_switch, 383 383 + 384 384 + .sync_arm = intel_sync_arm, 385 385 + .sync_go_unlocked = intel_sync_go_unlocked, 386 386 + .sync_go = intel_sync_go, 387 387 + .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked, 388 388 + 389 389 + .program_sdi = intel_program_sdi, 390 390 + }; 391 391 + EXPORT_SYMBOL_NS(sdw_intel_lnl_hw_ops, SOUNDWIRE_INTEL); 392 392 + 393 393 + MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK);

+147

drivers/soundwire/intel_ace2x_debugfs.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + // Copyright(c) 2023 Intel Corporation. All rights reserved. 3 3 + 4 4 + #include <linux/acpi.h> 5 5 + #include <linux/debugfs.h> 6 6 + #include <linux/delay.h> 7 7 + #include <linux/device.h> 8 8 + #include <linux/io.h> 9 9 + #include <linux/pm_runtime.h> 10 10 + #include <linux/soundwire/sdw.h> 11 11 + #include <linux/soundwire/sdw_intel.h> 12 12 + #include <linux/soundwire/sdw_registers.h> 13 13 + #include "bus.h" 14 14 + #include "cadence_master.h" 15 15 + #include "intel.h" 16 16 + 17 17 + /* 18 18 + * debugfs 19 19 + */ 20 20 + #ifdef CONFIG_DEBUG_FS 21 21 + 22 22 + #define RD_BUF (2 * PAGE_SIZE) 23 23 + 24 24 + static ssize_t intel_sprintf(void __iomem *mem, bool l, 25 25 + char *buf, size_t pos, unsigned int reg) 26 26 + { 27 27 + int value; 28 28 + 29 29 + if (l) 30 30 + value = intel_readl(mem, reg); 31 31 + else 32 32 + value = intel_readw(mem, reg); 33 33 + 34 34 + return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); 35 35 + } 36 36 + 37 37 + static int intel_reg_show(struct seq_file *s_file, void *data) 38 38 + { 39 39 + struct sdw_intel *sdw = s_file->private; 40 40 + void __iomem *s = sdw->link_res->shim; 41 41 + void __iomem *vs_s = sdw->link_res->shim_vs; 42 42 + ssize_t ret; 43 43 + u32 pcm_cap; 44 44 + int pcm_bd; 45 45 + char *buf; 46 46 + int j; 47 47 + 48 48 + buf = kzalloc(RD_BUF, GFP_KERNEL); 49 49 + if (!buf) 50 50 + return -ENOMEM; 51 51 + 52 52 + ret = scnprintf(buf, RD_BUF, "Register Value\n"); 53 53 + ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); 54 54 + 55 55 + ret += intel_sprintf(s, true, buf, ret, SDW_SHIM2_LECAP); 56 56 + ret += intel_sprintf(s, false, buf, ret, SDW_SHIM2_PCMSCAP); 57 57 + 58 58 + pcm_cap = intel_readw(s, SDW_SHIM2_PCMSCAP); 59 59 + pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap); 60 60 + 61 61 + for (j = 0; j < pcm_bd; j++) { 62 62 + ret += intel_sprintf(s, false, buf, ret, 63 63 + SDW_SHIM2_PCMSYCHM(j)); 64 64 + ret += intel_sprintf(s, false, buf, ret, 65 65 + SDW_SHIM2_PCMSYCHC(j)); 66 66 + } 67 67 + 68 68 + ret += scnprintf(buf + ret, RD_BUF - ret, "\nVS CLK controls\n"); 69 69 + ret += intel_sprintf(vs_s, true, buf, ret, SDW_SHIM2_INTEL_VS_LVSCTL); 70 70 + 71 71 + ret += scnprintf(buf + ret, RD_BUF - ret, "\nVS Wake registers\n"); 72 72 + ret += intel_sprintf(vs_s, false, buf, ret, SDW_SHIM2_INTEL_VS_WAKEEN); 73 73 + ret += intel_sprintf(vs_s, false, buf, ret, SDW_SHIM2_INTEL_VS_WAKESTS); 74 74 + 75 75 + ret += scnprintf(buf + ret, RD_BUF - ret, "\nVS IOCTL, ACTMCTL\n"); 76 76 + ret += intel_sprintf(vs_s, false, buf, ret, SDW_SHIM2_INTEL_VS_IOCTL); 77 77 + ret += intel_sprintf(vs_s, false, buf, ret, SDW_SHIM2_INTEL_VS_ACTMCTL); 78 78 + 79 79 + seq_printf(s_file, "%s", buf); 80 80 + kfree(buf); 81 81 + 82 82 + return 0; 83 83 + } 84 84 + DEFINE_SHOW_ATTRIBUTE(intel_reg); 85 85 + 86 86 + static int intel_set_m_datamode(void *data, u64 value) 87 87 + { 88 88 + struct sdw_intel *sdw = data; 89 89 + struct sdw_bus *bus = &sdw->cdns.bus; 90 90 + 91 91 + if (value > SDW_PORT_DATA_MODE_STATIC_1) 92 92 + return -EINVAL; 93 93 + 94 94 + /* Userspace changed the hardware state behind the kernel's back */ 95 95 + add_taint(TAINT_USER, LOCKDEP_STILL_OK); 96 96 + 97 97 + bus->params.m_data_mode = value; 98 98 + 99 99 + return 0; 100 100 + } 101 101 + DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL, 102 102 + intel_set_m_datamode, "%llu\n"); 103 103 + 104 104 + static int intel_set_s_datamode(void *data, u64 value) 105 105 + { 106 106 + struct sdw_intel *sdw = data; 107 107 + struct sdw_bus *bus = &sdw->cdns.bus; 108 108 + 109 109 + if (value > SDW_PORT_DATA_MODE_STATIC_1) 110 110 + return -EINVAL; 111 111 + 112 112 + /* Userspace changed the hardware state behind the kernel's back */ 113 113 + add_taint(TAINT_USER, LOCKDEP_STILL_OK); 114 114 + 115 115 + bus->params.s_data_mode = value; 116 116 + 117 117 + return 0; 118 118 + } 119 119 + DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL, 120 120 + intel_set_s_datamode, "%llu\n"); 121 121 + 122 122 + void intel_ace2x_debugfs_init(struct sdw_intel *sdw) 123 123 + { 124 124 + struct dentry *root = sdw->cdns.bus.debugfs; 125 125 + 126 126 + if (!root) 127 127 + return; 128 128 + 129 129 + sdw->debugfs = debugfs_create_dir("intel-sdw", root); 130 130 + 131 131 + debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, 132 132 + &intel_reg_fops); 133 133 + 134 134 + debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw, 135 135 + &intel_set_m_datamode_fops); 136 136 + 137 137 + debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw, 138 138 + &intel_set_s_datamode_fops); 139 139 + 140 140 + sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); 141 141 + } 142 142 + 143 143 + void intel_ace2x_debugfs_exit(struct sdw_intel *sdw) 144 144 + { 145 145 + debugfs_remove_recursive(sdw->debugfs); 146 146 + } 147 147 + #endif /* CONFIG_DEBUG_FS */

+17

drivers/soundwire/intel_auxdevice.c

reviewed

··· 60 60 return sdw->link_res->hw_ops->post_bank_switch(sdw); 61 61 } 62 62 63 63 + static void generic_new_peripheral_assigned(struct sdw_bus *bus, int dev_num) 64 64 + { 65 65 + struct sdw_cdns *cdns = bus_to_cdns(bus); 66 66 + struct sdw_intel *sdw = cdns_to_intel(cdns); 67 67 + 68 68 + /* paranoia check, this should never happen */ 69 69 + if (dev_num < INTEL_DEV_NUM_IDA_MIN || dev_num > SDW_MAX_DEVICES) { 70 70 + dev_err(bus->dev, "%s: invalid dev_num %d\n", __func__, dev_num); 71 71 + return; 72 72 + } 73 73 + 74 74 + if (sdw->link_res->hw_ops->program_sdi) 75 75 + sdw->link_res->hw_ops->program_sdi(sdw, dev_num); 76 76 + } 77 77 + 63 78 static int sdw_master_read_intel_prop(struct sdw_bus *bus) 64 79 { 65 80 struct sdw_master_prop *prop = &bus->prop; ··· 132 117 .pre_bank_switch = generic_pre_bank_switch, 133 118 .post_bank_switch = generic_post_bank_switch, 134 119 .read_ping_status = cdns_read_ping_status, 120 120 + .new_peripheral_assigned = generic_new_peripheral_assigned, 135 121 }; 136 122 137 123 /* ··· 160 144 sdw->link_res = &ldev->link_res; 161 145 cdns->dev = dev; 162 146 cdns->registers = sdw->link_res->registers; 147 147 + cdns->ip_offset = sdw->link_res->ip_offset; 163 148 cdns->instance = sdw->instance; 164 149 cdns->msg_count = 0; 165 150

+53 -43

drivers/soundwire/intel_bus_common.c

reviewed

··· 16 16 struct sdw_bus *bus = &cdns->bus; 17 17 int ret; 18 18 19 19 - ret = sdw_cdns_enable_interrupt(cdns, true); 20 20 - if (ret < 0) { 21 21 - dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret); 22 22 - return ret; 23 23 - } 24 24 - 25 19 /* 26 20 * follow recommended programming flows to avoid timeouts when 27 21 * gsync is enabled ··· 26 32 ret = sdw_cdns_init(cdns); 27 33 if (ret < 0) { 28 34 dev_err(dev, "%s: unable to initialize Cadence IP: %d\n", __func__, ret); 29 29 - goto err_interrupt; 35 35 + return ret; 30 36 } 31 37 32 32 - ret = sdw_cdns_exit_reset(cdns); 33 33 - if (ret < 0) { 34 34 - dev_err(dev, "%s: unable to exit bus reset sequence: %d\n", __func__, ret); 35 35 - goto err_interrupt; 36 36 - } 38 38 + sdw_cdns_config_update(cdns); 37 39 38 40 if (bus->multi_link) { 39 41 ret = sdw_intel_sync_go(sdw); 40 42 if (ret < 0) { 41 43 dev_err(dev, "%s: sync go failed: %d\n", __func__, ret); 42 42 - goto err_interrupt; 44 44 + return ret; 43 45 } 44 46 } 47 47 + 48 48 + ret = sdw_cdns_config_update_set_wait(cdns); 49 49 + if (ret < 0) { 50 50 + dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__); 51 51 + return ret; 52 52 + } 53 53 + 54 54 + ret = sdw_cdns_exit_reset(cdns); 55 55 + if (ret < 0) { 56 56 + dev_err(dev, "%s: unable to exit bus reset sequence: %d\n", __func__, ret); 57 57 + return ret; 58 58 + } 59 59 + 60 60 + ret = sdw_cdns_enable_interrupt(cdns, true); 61 61 + if (ret < 0) { 62 62 + dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret); 63 63 + return ret; 64 64 + } 65 65 + 45 66 sdw_cdns_check_self_clearing_bits(cdns, __func__, 46 67 true, INTEL_MASTER_RESET_ITERATIONS); 47 68 48 69 return 0; 49 49 - 50 50 - err_interrupt: 51 51 - sdw_cdns_enable_interrupt(cdns, false); 52 52 - return ret; 53 70 } 54 71 55 72 int intel_start_bus_after_reset(struct sdw_intel *sdw) ··· 91 86 status = SDW_UNATTACH_REQUEST_MASTER_RESET; 92 87 sdw_clear_slave_status(bus, status); 93 88 94 94 - ret = sdw_cdns_enable_interrupt(cdns, true); 95 95 - if (ret < 0) { 96 96 - dev_err(dev, "cannot enable interrupts during resume\n"); 97 97 - return ret; 98 98 - } 99 99 - 100 89 /* 101 90 * follow recommended programming flows to avoid 102 91 * timeouts when gsync is enabled ··· 114 115 ret = sdw_cdns_clock_restart(cdns, !clock_stop0); 115 116 if (ret < 0) { 116 117 dev_err(dev, "unable to restart clock during resume\n"); 117 117 - goto err_interrupt; 118 118 + if (!clock_stop0) 119 119 + sdw_cdns_enable_interrupt(cdns, false); 120 120 + return ret; 118 121 } 119 122 120 123 if (!clock_stop0) { 121 121 - ret = sdw_cdns_exit_reset(cdns); 122 122 - if (ret < 0) { 123 123 - dev_err(dev, "unable to exit bus reset sequence during resume\n"); 124 124 - goto err_interrupt; 125 125 - } 124 124 + sdw_cdns_config_update(cdns); 126 125 127 126 if (bus->multi_link) { 128 127 ret = sdw_intel_sync_go(sdw); 129 128 if (ret < 0) { 130 129 dev_err(sdw->cdns.dev, "sync go failed during resume\n"); 131 131 - goto err_interrupt; 130 130 + return ret; 132 131 } 133 132 } 133 133 + 134 134 + ret = sdw_cdns_config_update_set_wait(cdns); 135 135 + if (ret < 0) { 136 136 + dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__); 137 137 + return ret; 138 138 + } 139 139 + 140 140 + ret = sdw_cdns_exit_reset(cdns); 141 141 + if (ret < 0) { 142 142 + dev_err(dev, "unable to exit bus reset sequence during resume\n"); 143 143 + return ret; 144 144 + } 145 145 + 146 146 + ret = sdw_cdns_enable_interrupt(cdns, true); 147 147 + if (ret < 0) { 148 148 + dev_err(dev, "cannot enable interrupts during resume\n"); 149 149 + return ret; 150 150 + } 151 151 + 134 152 } 135 153 sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS); 136 154 137 155 return 0; 138 138 - 139 139 - err_interrupt: 140 140 - sdw_cdns_enable_interrupt(cdns, false); 141 141 - return ret; 142 156 } 143 157 144 158 void intel_check_clock_stop(struct sdw_intel *sdw) ··· 170 158 struct sdw_cdns *cdns = &sdw->cdns; 171 159 int ret; 172 160 161 161 + ret = sdw_cdns_clock_restart(cdns, false); 162 162 + if (ret < 0) { 163 163 + dev_err(dev, "%s: unable to restart clock: %d\n", __func__, ret); 164 164 + return ret; 165 165 + } 166 166 + 173 167 ret = sdw_cdns_enable_interrupt(cdns, true); 174 168 if (ret < 0) { 175 169 dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret); 176 170 return ret; 177 171 } 178 172 179 179 - ret = sdw_cdns_clock_restart(cdns, false); 180 180 - if (ret < 0) { 181 181 - dev_err(dev, "%s: unable to restart clock: %d\n", __func__, ret); 182 182 - sdw_cdns_enable_interrupt(cdns, false); 183 183 - return ret; 184 184 - } 185 185 - 186 186 - sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks", 187 187 - true, INTEL_MASTER_RESET_ITERATIONS); 173 173 + sdw_cdns_check_self_clearing_bits(cdns, __func__, true, INTEL_MASTER_RESET_ITERATIONS); 188 174 189 175 return 0; 190 176 }

+16 -5

drivers/soundwire/intel_init.c

reviewed

··· 63 63 link = &ldev->link_res; 64 64 link->hw_ops = res->hw_ops; 65 65 link->mmio_base = res->mmio_base; 66 66 - link->registers = res->mmio_base + SDW_LINK_BASE 67 67 - + (SDW_LINK_SIZE * link_id); 68 68 - link->shim = res->mmio_base + res->shim_base; 69 69 - link->alh = res->mmio_base + res->alh_base; 66 66 + if (!res->ext) { 67 67 + link->registers = res->mmio_base + SDW_LINK_BASE 68 68 + + (SDW_LINK_SIZE * link_id); 69 69 + link->ip_offset = 0; 70 70 + link->shim = res->mmio_base + res->shim_base; 71 71 + link->alh = res->mmio_base + res->alh_base; 72 72 + link->shim_lock = &ctx->shim_lock; 73 73 + } else { 74 74 + link->registers = res->mmio_base + SDW_IP_BASE(link_id); 75 75 + link->ip_offset = SDW_CADENCE_MCP_IP_OFFSET; 76 76 + link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id); 77 77 + link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id); 78 78 + link->shim_lock = res->eml_lock; 79 79 + } 70 80 71 81 link->ops = res->ops; 72 82 link->dev = res->dev; 73 83 74 84 link->clock_stop_quirks = res->clock_stop_quirks; 75 75 - link->shim_lock = &ctx->shim_lock; 76 85 link->shim_mask = &ctx->shim_mask; 77 86 link->link_mask = ctx->link_mask; 87 87 + 88 88 + link->hbus = res->hbus; 78 89 79 90 /* now follow the two-step init/add sequence */ 80 91 ret = auxiliary_device_init(auxdev);

+334 -166

drivers/soundwire/qcom.c

reviewed

··· 31 31 #define SWRM_VERSION_1_3_0 0x01030000 32 32 #define SWRM_VERSION_1_5_1 0x01050001 33 33 #define SWRM_VERSION_1_7_0 0x01070000 34 34 + #define SWRM_VERSION_2_0_0 0x02000000 34 35 #define SWRM_COMP_HW_VERSION 0x00 35 36 #define SWRM_COMP_CFG_ADDR 0x04 36 37 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) ··· 42 41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) 43 42 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) 44 43 #define SWRM_COMP_MASTER_ID 0x104 45 45 - #define SWRM_INTERRUPT_STATUS 0x200 44 44 + #define SWRM_V1_3_INTERRUPT_STATUS 0x200 45 45 + #define SWRM_V2_0_INTERRUPT_STATUS 0x5000 46 46 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) 47 47 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) 48 48 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) ··· 56 54 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) 57 55 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) 58 56 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) 59 59 - #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) 60 60 - #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) 61 61 - #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) 57 57 + #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) 58 58 + #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) 59 59 + #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) 60 60 + #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) 61 61 + #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) 62 62 #define SWRM_INTERRUPT_MAX 17 63 63 - #define SWRM_INTERRUPT_MASK_ADDR 0x204 64 64 - #define SWRM_INTERRUPT_CLEAR 0x208 65 65 - #define SWRM_INTERRUPT_CPU_EN 0x210 66 66 - #define SWRM_CMD_FIFO_WR_CMD 0x300 67 67 - #define SWRM_CMD_FIFO_RD_CMD 0x304 63 63 + #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 64 64 + #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 65 65 + #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 66 66 + #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 67 67 + #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 68 68 + #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 69 69 + #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 70 70 + #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 71 71 + #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 68 72 #define SWRM_CMD_FIFO_CMD 0x308 69 73 #define SWRM_CMD_FIFO_FLUSH 0x1 70 70 - #define SWRM_CMD_FIFO_STATUS 0x30C 74 74 + #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C 75 75 + #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 71 76 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) 72 77 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) 73 78 #define SWRM_CMD_FIFO_CFG_ADDR 0x314 74 79 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) 75 80 #define SWRM_RD_WR_CMD_RETRIES 0x7 76 76 - #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 81 81 + #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 82 82 + #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 77 83 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) 78 84 #define SWRM_ENUMERATOR_CFG_ADDR 0x500 79 85 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) ··· 105 95 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) 106 96 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) 107 97 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) 98 98 + #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) 108 99 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) 109 109 - #define SWR_MSTR_MAX_REG_ADDR (0x1740) 100 100 + #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 101 101 + #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac 102 102 + 103 103 + #define SWRM_V2_0_CLK_CTRL 0x5060 104 104 + #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) 105 105 + #define SWRM_V2_0_LINK_STATUS 0x5064 110 106 111 107 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 112 108 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 ··· 125 109 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ 126 110 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) 127 111 128 128 - #define MAX_FREQ_NUM 1 129 129 - #define TIMEOUT_MS 100 130 130 - #define QCOM_SWRM_MAX_RD_LEN 0x1 131 131 - #define QCOM_SDW_MAX_PORTS 14 132 132 - #define DEFAULT_CLK_FREQ 9600000 133 133 - #define SWRM_MAX_DAIS 0xF 134 134 - #define SWR_INVALID_PARAM 0xFF 135 135 - #define SWR_HSTOP_MAX_VAL 0xF 136 136 - #define SWR_HSTART_MIN_VAL 0x0 137 137 - #define SWR_BROADCAST_CMD_ID 0x0F 138 138 - #define SWR_MAX_CMD_ID 14 139 139 - #define MAX_FIFO_RD_RETRY 3 140 140 - #define SWR_OVERFLOW_RETRY_COUNT 30 141 141 - #define SWRM_LINK_STATUS_RETRY_CNT 100 112 112 + #define MAX_FREQ_NUM 1 113 113 + #define TIMEOUT_MS 100 114 114 + #define QCOM_SWRM_MAX_RD_LEN 0x1 115 115 + #define QCOM_SDW_MAX_PORTS 14 116 116 + #define DEFAULT_CLK_FREQ 9600000 117 117 + #define SWRM_MAX_DAIS 0xF 118 118 + #define SWR_INVALID_PARAM 0xFF 119 119 + #define SWR_HSTOP_MAX_VAL 0xF 120 120 + #define SWR_HSTART_MIN_VAL 0x0 121 121 + #define SWR_BROADCAST_CMD_ID 0x0F 122 122 + #define SWR_MAX_CMD_ID 14 123 123 + #define MAX_FIFO_RD_RETRY 3 124 124 + #define SWR_OVERFLOW_RETRY_COUNT 30 125 125 + #define SWRM_LINK_STATUS_RETRY_CNT 100 142 126 143 127 enum { 144 128 MASTER_ID_WSA = 1, ··· 147 131 }; 148 132 149 133 struct qcom_swrm_port_config { 150 150 - u8 si; 134 134 + u16 si; 151 135 u8 off1; 152 136 u8 off2; 153 137 u8 bp_mode; ··· 158 142 u8 lane_control; 159 143 }; 160 144 145 145 + /* 146 146 + * Internal IDs for different register layouts. Only few registers differ per 147 147 + * each variant, so the list of IDs below does not include all of registers. 148 148 + */ 149 149 + enum { 150 150 + SWRM_REG_FRAME_GEN_ENABLED, 151 151 + SWRM_REG_INTERRUPT_STATUS, 152 152 + SWRM_REG_INTERRUPT_MASK_ADDR, 153 153 + SWRM_REG_INTERRUPT_CLEAR, 154 154 + SWRM_REG_INTERRUPT_CPU_EN, 155 155 + SWRM_REG_CMD_FIFO_WR_CMD, 156 156 + SWRM_REG_CMD_FIFO_RD_CMD, 157 157 + SWRM_REG_CMD_FIFO_STATUS, 158 158 + SWRM_REG_CMD_FIFO_RD_FIFO_ADDR, 159 159 + }; 160 160 + 161 161 struct qcom_swrm_ctrl { 162 162 struct sdw_bus bus; 163 163 struct device *dev; 164 164 struct regmap *regmap; 165 165 + u32 max_reg; 166 166 + const unsigned int *reg_layout; 165 167 void __iomem *mmio; 166 168 struct reset_control *audio_cgcr; 167 169 #ifdef CONFIG_DEBUG_FS ··· 187 153 #endif 188 154 struct completion broadcast; 189 155 struct completion enumeration; 190 190 - struct work_struct slave_work; 191 156 /* Port alloc/free lock */ 192 157 struct mutex port_lock; 193 158 struct clk *hclk; 194 194 - u8 wr_cmd_id; 195 195 - u8 rd_cmd_id; 196 159 int irq; 197 160 unsigned int version; 198 161 int wake_irq; ··· 202 171 u32 intr_mask; 203 172 u8 rcmd_id; 204 173 u8 wcmd_id; 205 205 - struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS]; 174 174 + /* Port numbers are 1 - 14 */ 175 175 + struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1]; 206 176 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; 207 177 enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; 208 178 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); ··· 218 186 u32 default_cols; 219 187 u32 default_rows; 220 188 bool sw_clk_gate_required; 189 189 + u32 max_reg; 190 190 + const unsigned int *reg_layout; 191 191 + }; 192 192 + 193 193 + static const unsigned int swrm_v1_3_reg_layout[] = { 194 194 + [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS, 195 195 + [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS, 196 196 + [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR, 197 197 + [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR, 198 198 + [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN, 199 199 + [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD, 200 200 + [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD, 201 201 + [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS, 202 202 + [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR, 221 203 }; 222 204 223 205 static const struct qcom_swrm_data swrm_v1_3_data = { 224 206 .default_rows = 48, 225 207 .default_cols = 16, 208 208 + .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 209 209 + .reg_layout = swrm_v1_3_reg_layout, 226 210 }; 227 211 228 212 static const struct qcom_swrm_data swrm_v1_5_data = { 229 213 .default_rows = 50, 230 214 .default_cols = 16, 215 215 + .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 216 216 + .reg_layout = swrm_v1_3_reg_layout, 231 217 }; 232 218 233 219 static const struct qcom_swrm_data swrm_v1_6_data = { 234 220 .default_rows = 50, 235 221 .default_cols = 16, 236 222 .sw_clk_gate_required = true, 223 223 + .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 224 224 + .reg_layout = swrm_v1_3_reg_layout, 225 225 + }; 226 226 + 227 227 + static const unsigned int swrm_v2_0_reg_layout[] = { 228 228 + [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS, 229 229 + [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS, 230 230 + [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */ 231 231 + [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR, 232 232 + [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN, 233 233 + [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD, 234 234 + [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD, 235 235 + [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS, 236 236 + [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR, 237 237 + }; 238 238 + 239 239 + static const struct qcom_swrm_data swrm_v2_0_data = { 240 240 + .default_rows = 50, 241 241 + .default_cols = 16, 242 242 + .sw_clk_gate_required = true, 243 243 + .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR, 244 244 + .reg_layout = swrm_v2_0_reg_layout, 237 245 }; 238 246 239 247 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) ··· 350 278 return val; 351 279 } 352 280 353 353 - static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) 281 281 + static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) 354 282 { 355 283 u32 fifo_outstanding_data, value; 356 284 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 357 285 358 286 do { 359 287 /* Check for fifo underflow during read */ 360 360 - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 288 288 + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 289 289 + &value); 361 290 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); 362 291 363 292 /* Check if read data is available in read fifo */ ··· 369 296 } while (fifo_retry_count--); 370 297 371 298 if (fifo_outstanding_data == 0) { 372 372 - dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); 299 299 + dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); 373 300 return -EIO; 374 301 } 375 302 376 303 return 0; 377 304 } 378 305 379 379 - static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) 306 306 + static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) 380 307 { 381 308 u32 fifo_outstanding_cmds, value; 382 309 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 383 310 384 311 do { 385 312 /* Check for fifo overflow during write */ 386 386 - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 313 313 + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 314 314 + &value); 387 315 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 388 316 389 317 /* Check for space in write fifo before writing */ 390 390 - if (fifo_outstanding_cmds < swrm->wr_fifo_depth) 318 318 + if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) 391 319 return 0; 392 320 393 321 usleep_range(500, 510); 394 322 } while (fifo_retry_count--); 395 323 396 396 - if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { 397 397 - dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); 324 324 + if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { 325 325 + dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); 398 326 return -EIO; 399 327 } 400 328 401 329 return 0; 402 330 } 403 331 404 404 - static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, 332 332 + static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) 333 333 + { 334 334 + u32 fifo_outstanding_cmds, value; 335 335 + int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 336 336 + 337 337 + /* Check for fifo overflow during write */ 338 338 + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); 339 339 + fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 340 340 + 341 341 + if (fifo_outstanding_cmds) { 342 342 + while (fifo_retry_count) { 343 343 + usleep_range(500, 510); 344 344 + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); 345 345 + fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 346 346 + fifo_retry_count--; 347 347 + if (fifo_outstanding_cmds == 0) 348 348 + return true; 349 349 + } 350 350 + } else { 351 351 + return true; 352 352 + } 353 353 + 354 354 + 355 355 + return false; 356 356 + } 357 357 + 358 358 + static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, 405 359 u8 dev_addr, u16 reg_addr) 406 360 { 407 361 ··· 441 341 val = swrm_get_packed_reg_val(&cmd_id, cmd_data, 442 342 dev_addr, reg_addr); 443 343 } else { 444 444 - val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, 344 344 + val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, 445 345 dev_addr, reg_addr); 446 346 } 447 347 448 448 - if (swrm_wait_for_wr_fifo_avail(swrm)) 348 348 + if (swrm_wait_for_wr_fifo_avail(ctrl)) 449 349 return SDW_CMD_FAIL_OTHER; 450 350 451 351 if (cmd_id == SWR_BROADCAST_CMD_ID) 452 452 - reinit_completion(&swrm->broadcast); 352 352 + reinit_completion(&ctrl->broadcast); 453 353 454 354 /* Its assumed that write is okay as we do not get any status back */ 455 455 - swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); 355 355 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); 456 356 457 457 - if (swrm->version <= SWRM_VERSION_1_3_0) 357 357 + if (ctrl->version <= SWRM_VERSION_1_3_0) 458 358 usleep_range(150, 155); 459 359 460 360 if (cmd_id == SWR_BROADCAST_CMD_ID) { 361 361 + swrm_wait_for_wr_fifo_done(ctrl); 461 362 /* 462 363 * sleep for 10ms for MSM soundwire variant to allow broadcast 463 364 * command to complete. 464 365 */ 465 465 - ret = wait_for_completion_timeout(&swrm->broadcast, 366 366 + ret = wait_for_completion_timeout(&ctrl->broadcast, 466 367 msecs_to_jiffies(TIMEOUT_MS)); 467 368 if (!ret) 468 369 ret = SDW_CMD_IGNORED; ··· 476 375 return ret; 477 376 } 478 377 479 479 - static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, 378 378 + static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, 480 379 u8 dev_addr, u16 reg_addr, 481 380 u32 len, u8 *rval) 482 381 { 483 382 u32 cmd_data, cmd_id, val, retry_attempt = 0; 484 383 485 485 - val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); 384 384 + val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); 486 385 487 386 /* 488 387 * Check for outstanding cmd wrt. write fifo depth to avoid 489 388 * overflow as read will also increase write fifo cnt. 490 389 */ 491 491 - swrm_wait_for_wr_fifo_avail(swrm); 390 390 + swrm_wait_for_wr_fifo_avail(ctrl); 492 391 493 392 /* wait for FIFO RD to complete to avoid overflow */ 494 393 usleep_range(100, 105); 495 495 - swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 394 394 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); 496 395 /* wait for FIFO RD CMD complete to avoid overflow */ 497 396 usleep_range(250, 255); 498 397 499 499 - if (swrm_wait_for_rd_fifo_avail(swrm)) 398 398 + if (swrm_wait_for_rd_fifo_avail(ctrl)) 500 399 return SDW_CMD_FAIL_OTHER; 501 400 502 401 do { 503 503 - swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); 402 402 + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], 403 403 + &cmd_data); 504 404 rval[0] = cmd_data & 0xFF; 505 405 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); 506 406 507 507 - if (cmd_id != swrm->rcmd_id) { 407 407 + if (cmd_id != ctrl->rcmd_id) { 508 408 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { 509 409 /* wait 500 us before retry on fifo read failure */ 510 410 usleep_range(500, 505); 511 511 - swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 411 411 + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 512 412 SWRM_CMD_FIFO_FLUSH); 513 513 - swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 413 413 + ctrl->reg_write(ctrl, 414 414 + ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], 415 415 + val); 514 416 } 515 417 retry_attempt++; 516 418 } else { ··· 522 418 523 419 } while (retry_attempt < MAX_FIFO_RD_RETRY); 524 420 525 525 - dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ 421 421 + dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ 526 422 dev_num: 0x%x, cmd_data: 0x%x\n", 527 527 - reg_addr, swrm->rcmd_id, dev_addr, cmd_data); 423 423 + reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); 528 424 529 425 return SDW_CMD_IGNORED; 530 426 } ··· 615 511 616 512 sdw_extract_slave_id(bus, addr, &id); 617 513 found = false; 514 514 + ctrl->clock_stop_not_supported = false; 618 515 /* Now compare with entries */ 619 516 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { 620 517 if (sdw_compare_devid(slave, id) == 0) { 621 518 qcom_swrm_set_slave_dev_num(bus, slave, i); 519 519 + if (slave->prop.clk_stop_mode1) 520 520 + ctrl->clock_stop_not_supported = true; 521 521 + 622 522 found = true; 623 523 break; 624 524 } ··· 640 532 641 533 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) 642 534 { 643 643 - struct qcom_swrm_ctrl *swrm = dev_id; 535 535 + struct qcom_swrm_ctrl *ctrl = dev_id; 644 536 int ret; 645 537 646 646 - ret = pm_runtime_resume_and_get(swrm->dev); 538 538 + ret = pm_runtime_get_sync(ctrl->dev); 647 539 if (ret < 0 && ret != -EACCES) { 648 648 - dev_err_ratelimited(swrm->dev, 649 649 - "pm_runtime_resume_and_get failed in %s, ret %d\n", 540 540 + dev_err_ratelimited(ctrl->dev, 541 541 + "pm_runtime_get_sync failed in %s, ret %d\n", 650 542 __func__, ret); 543 543 + pm_runtime_put_noidle(ctrl->dev); 651 544 return ret; 652 545 } 653 546 654 654 - if (swrm->wake_irq > 0) { 655 655 - if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) 656 656 - disable_irq_nosync(swrm->wake_irq); 547 547 + if (ctrl->wake_irq > 0) { 548 548 + if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 549 549 + disable_irq_nosync(ctrl->wake_irq); 657 550 } 658 551 659 659 - pm_runtime_mark_last_busy(swrm->dev); 660 660 - pm_runtime_put_autosuspend(swrm->dev); 552 552 + pm_runtime_mark_last_busy(ctrl->dev); 553 553 + pm_runtime_put_autosuspend(ctrl->dev); 661 554 662 555 return IRQ_HANDLED; 663 556 } 664 557 665 558 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) 666 559 { 667 667 - struct qcom_swrm_ctrl *swrm = dev_id; 560 560 + struct qcom_swrm_ctrl *ctrl = dev_id; 668 561 u32 value, intr_sts, intr_sts_masked, slave_status; 669 562 u32 i; 670 563 int devnum; 671 564 int ret = IRQ_HANDLED; 672 672 - clk_prepare_enable(swrm->hclk); 565 565 + clk_prepare_enable(ctrl->hclk); 673 566 674 674 - swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 675 675 - intr_sts_masked = intr_sts & swrm->intr_mask; 567 567 + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], 568 568 + &intr_sts); 569 569 + intr_sts_masked = intr_sts & ctrl->intr_mask; 676 570 677 571 do { 678 572 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { ··· 684 574 685 575 switch (value) { 686 576 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: 687 687 - devnum = qcom_swrm_get_alert_slave_dev_num(swrm); 577 577 + devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); 688 578 if (devnum < 0) { 689 689 - dev_err_ratelimited(swrm->dev, 579 579 + dev_err_ratelimited(ctrl->dev, 690 580 "no slave alert found.spurious interrupt\n"); 691 581 } else { 692 692 - sdw_handle_slave_status(&swrm->bus, swrm->status); 582 582 + sdw_handle_slave_status(&ctrl->bus, ctrl->status); 693 583 } 694 584 695 585 break; 696 586 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: 697 587 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: 698 698 - dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n"); 699 699 - swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); 700 700 - if (swrm->slave_status == slave_status) { 701 701 - dev_dbg(swrm->dev, "Slave status not changed %x\n", 588 588 + dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); 589 589 + ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); 590 590 + if (ctrl->slave_status == slave_status) { 591 591 + dev_dbg(ctrl->dev, "Slave status not changed %x\n", 702 592 slave_status); 703 593 } else { 704 704 - qcom_swrm_get_device_status(swrm); 705 705 - qcom_swrm_enumerate(&swrm->bus); 706 706 - sdw_handle_slave_status(&swrm->bus, swrm->status); 594 594 + qcom_swrm_get_device_status(ctrl); 595 595 + qcom_swrm_enumerate(&ctrl->bus); 596 596 + sdw_handle_slave_status(&ctrl->bus, ctrl->status); 707 597 } 708 598 break; 709 599 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: 710 710 - dev_err_ratelimited(swrm->dev, 600 600 + dev_err_ratelimited(ctrl->dev, 711 601 "%s: SWR bus clsh detected\n", 712 602 __func__); 713 713 - swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 714 714 - swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 603 603 + ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 604 604 + ctrl->reg_write(ctrl, 605 605 + ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 606 606 + ctrl->intr_mask); 715 607 break; 716 608 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: 717 717 - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 718 718 - dev_err_ratelimited(swrm->dev, 609 609 + ctrl->reg_read(ctrl, 610 610 + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 611 611 + &value); 612 612 + dev_err_ratelimited(ctrl->dev, 719 613 "%s: SWR read FIFO overflow fifo status 0x%x\n", 720 614 __func__, value); 721 615 break; 722 616 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: 723 723 - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 724 724 - dev_err_ratelimited(swrm->dev, 617 617 + ctrl->reg_read(ctrl, 618 618 + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 619 619 + &value); 620 620 + dev_err_ratelimited(ctrl->dev, 725 621 "%s: SWR read FIFO underflow fifo status 0x%x\n", 726 622 __func__, value); 727 623 break; 728 624 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: 729 729 - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 730 730 - dev_err(swrm->dev, 625 625 + ctrl->reg_read(ctrl, 626 626 + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 627 627 + &value); 628 628 + dev_err(ctrl->dev, 731 629 "%s: SWR write FIFO overflow fifo status %x\n", 732 630 __func__, value); 733 733 - swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 631 631 + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 734 632 break; 735 633 case SWRM_INTERRUPT_STATUS_CMD_ERROR: 736 736 - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 737 737 - dev_err_ratelimited(swrm->dev, 634 634 + ctrl->reg_read(ctrl, 635 635 + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 636 636 + &value); 637 637 + dev_err_ratelimited(ctrl->dev, 738 638 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", 739 639 __func__, value); 740 740 - swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 640 640 + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 741 641 break; 742 642 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: 743 743 - dev_err_ratelimited(swrm->dev, 643 643 + dev_err_ratelimited(ctrl->dev, 744 644 "%s: SWR Port collision detected\n", 745 645 __func__); 746 746 - swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; 747 747 - swrm->reg_write(swrm, 748 748 - SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 646 646 + ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; 647 647 + ctrl->reg_write(ctrl, 648 648 + ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 649 649 + ctrl->intr_mask); 749 650 break; 750 651 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: 751 751 - dev_err_ratelimited(swrm->dev, 652 652 + dev_err_ratelimited(ctrl->dev, 752 653 "%s: SWR read enable valid mismatch\n", 753 654 __func__); 754 754 - swrm->intr_mask &= 655 655 + ctrl->intr_mask &= 755 656 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; 756 756 - swrm->reg_write(swrm, 757 757 - SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 657 657 + ctrl->reg_write(ctrl, 658 658 + ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 659 659 + ctrl->intr_mask); 758 660 break; 759 661 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: 760 760 - complete(&swrm->broadcast); 662 662 + complete(&ctrl->broadcast); 761 663 break; 762 664 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: 763 665 break; ··· 778 656 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: 779 657 break; 780 658 default: 781 781 - dev_err_ratelimited(swrm->dev, 659 659 + dev_err_ratelimited(ctrl->dev, 782 660 "%s: SWR unknown interrupt value: %d\n", 783 661 __func__, value); 784 662 ret = IRQ_NONE; 785 663 break; 786 664 } 787 665 } 788 788 - swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); 789 789 - swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 790 790 - intr_sts_masked = intr_sts & swrm->intr_mask; 666 666 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 667 667 + intr_sts); 668 668 + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], 669 669 + &intr_sts); 670 670 + intr_sts_masked = intr_sts & ctrl->intr_mask; 791 671 } while (intr_sts_masked); 792 672 793 793 - clk_disable_unprepare(swrm->hclk); 673 673 + clk_disable_unprepare(ctrl->hclk); 794 674 return ret; 675 675 + } 676 676 + 677 677 + static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) 678 678 + { 679 679 + int retry = SWRM_LINK_STATUS_RETRY_CNT; 680 680 + int comp_sts; 681 681 + 682 682 + do { 683 683 + ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts); 684 684 + 685 685 + if (comp_sts & SWRM_FRM_GEN_ENABLED) 686 686 + return true; 687 687 + 688 688 + usleep_range(500, 510); 689 689 + } while (retry--); 690 690 + 691 691 + dev_err(ctrl->dev, "%s: link status not %s\n", __func__, 692 692 + comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); 693 693 + 694 694 + return false; 795 695 } 796 696 797 697 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) ··· 833 689 834 690 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; 835 691 /* Mask soundwire interrupts */ 836 836 - ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, 837 837 - SWRM_INTERRUPT_STATUS_RMSK); 692 692 + if (ctrl->version < SWRM_VERSION_2_0_0) 693 693 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 694 694 + SWRM_INTERRUPT_STATUS_RMSK); 838 695 839 696 /* Configure No pings */ 840 697 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); 841 698 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); 842 699 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); 843 700 844 844 - if (ctrl->version >= SWRM_VERSION_1_7_0) { 701 701 + if (ctrl->version == SWRM_VERSION_1_7_0) { 845 702 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 846 703 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, 847 704 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); 705 705 + } else if (ctrl->version >= SWRM_VERSION_2_0_0) { 706 706 + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 707 707 + ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, 708 708 + SWRM_V2_0_CLK_CTRL_CLK_START); 848 709 } else { 849 710 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 850 711 } ··· 864 715 SWRM_RD_WR_CMD_RETRIES); 865 716 } 866 717 718 718 + /* COMP Enable */ 719 719 + ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); 720 720 + 721 721 + /* Set IRQ to PULSE */ 722 722 + ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 723 723 + SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK); 724 724 + 725 725 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 726 726 + 0xFFFFFFFF); 727 727 + 728 728 + /* enable CPU IRQs */ 729 729 + if (ctrl->mmio) { 730 730 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 731 731 + SWRM_INTERRUPT_STATUS_RMSK); 732 732 + } 733 733 + 867 734 /* Set IRQ to PULSE */ 868 735 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 869 736 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | 870 737 SWRM_COMP_CFG_ENABLE_MSK); 871 738 872 872 - /* enable CPU IRQs */ 873 873 - if (ctrl->mmio) { 874 874 - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, 875 875 - SWRM_INTERRUPT_STATUS_RMSK); 876 876 - } 739 739 + swrm_wait_for_frame_gen_enabled(ctrl); 877 740 ctrl->slave_status = 0; 878 741 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 879 742 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); ··· 967 806 968 807 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; 969 808 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; 970 970 - value |= pcfg->si; 809 809 + value |= pcfg->si & 0xff; 971 810 972 811 ret = ctrl->reg_write(ctrl, reg, value); 973 812 if (ret) 974 813 goto err; 814 814 + 815 815 + if (pcfg->si > 0xff) { 816 816 + value = (pcfg->si >> 8) & 0xff; 817 817 + reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); 818 818 + ret = ctrl->reg_write(ctrl, reg, value); 819 819 + if (ret) 820 820 + goto err; 821 821 + } 975 822 976 823 if (pcfg->lane_control != SWR_INVALID_PARAM) { 977 824 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); ··· 1259 1090 struct snd_soc_dai *codec_dai; 1260 1091 int ret, i; 1261 1092 1262 1262 - ret = pm_runtime_resume_and_get(ctrl->dev); 1093 1093 + ret = pm_runtime_get_sync(ctrl->dev); 1263 1094 if (ret < 0 && ret != -EACCES) { 1264 1095 dev_err_ratelimited(ctrl->dev, 1265 1265 - "pm_runtime_resume_and_get failed in %s, ret %d\n", 1096 1096 + "pm_runtime_get_sync failed in %s, ret %d\n", 1266 1097 __func__, ret); 1098 1098 + pm_runtime_put_noidle(ctrl->dev); 1267 1099 return ret; 1268 1100 } 1269 1101 ··· 1302 1132 { 1303 1133 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1304 1134 1135 1135 + swrm_wait_for_wr_fifo_done(ctrl); 1305 1136 sdw_release_stream(ctrl->sruntime[dai->id]); 1306 1137 ctrl->sruntime[dai->id] = NULL; 1307 1138 pm_runtime_mark_last_busy(ctrl->dev); ··· 1365 1194 struct device_node *np = ctrl->dev->of_node; 1366 1195 u8 off1[QCOM_SDW_MAX_PORTS]; 1367 1196 u8 off2[QCOM_SDW_MAX_PORTS]; 1368 1368 - u8 si[QCOM_SDW_MAX_PORTS]; 1197 1197 + u16 si[QCOM_SDW_MAX_PORTS]; 1369 1198 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; 1370 1199 u8 hstart[QCOM_SDW_MAX_PORTS]; 1371 1200 u8 hstop[QCOM_SDW_MAX_PORTS]; ··· 1373 1202 u8 blk_group_count[QCOM_SDW_MAX_PORTS]; 1374 1203 u8 lane_control[QCOM_SDW_MAX_PORTS]; 1375 1204 int i, ret, nports, val; 1205 1205 + bool si_16 = false; 1376 1206 1377 1207 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 1378 1208 ··· 1417 1245 return ret; 1418 1246 1419 1247 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", 1420 1420 - si, nports); 1421 1421 - if (ret) 1422 1422 - return ret; 1248 1248 + (u8 *)si, nports); 1249 1249 + if (ret) { 1250 1250 + ret = of_property_read_u16_array(np, "qcom,ports-sinterval", 1251 1251 + si, nports); 1252 1252 + if (ret) 1253 1253 + return ret; 1254 1254 + si_16 = true; 1255 1255 + } 1423 1256 1424 1257 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", 1425 1258 bp_mode, nports); ··· 1452 1275 1453 1276 for (i = 0; i < nports; i++) { 1454 1277 /* Valid port number range is from 1-14 */ 1455 1455 - ctrl->pconfig[i + 1].si = si[i]; 1278 1278 + if (si_16) 1279 1279 + ctrl->pconfig[i + 1].si = si[i]; 1280 1280 + else 1281 1281 + ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; 1456 1282 ctrl->pconfig[i + 1].off1 = off1[i]; 1457 1283 ctrl->pconfig[i + 1].off2 = off2[i]; 1458 1284 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; ··· 1472 1292 #ifdef CONFIG_DEBUG_FS 1473 1293 static int swrm_reg_show(struct seq_file *s_file, void *data) 1474 1294 { 1475 1475 - struct qcom_swrm_ctrl *swrm = s_file->private; 1295 1295 + struct qcom_swrm_ctrl *ctrl = s_file->private; 1476 1296 int reg, reg_val, ret; 1477 1297 1478 1478 - ret = pm_runtime_resume_and_get(swrm->dev); 1298 1298 + ret = pm_runtime_get_sync(ctrl->dev); 1479 1299 if (ret < 0 && ret != -EACCES) { 1480 1480 - dev_err_ratelimited(swrm->dev, 1481 1481 - "pm_runtime_resume_and_get failed in %s, ret %d\n", 1300 1300 + dev_err_ratelimited(ctrl->dev, 1301 1301 + "pm_runtime_get_sync failed in %s, ret %d\n", 1482 1302 __func__, ret); 1303 1303 + pm_runtime_put_noidle(ctrl->dev); 1483 1304 return ret; 1484 1305 } 1485 1306 1486 1486 - for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) { 1487 1487 - swrm->reg_read(swrm, reg, &reg_val); 1307 1307 + for (reg = 0; reg <= ctrl->max_reg; reg += 4) { 1308 1308 + ctrl->reg_read(ctrl, reg, &reg_val); 1488 1309 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); 1489 1310 } 1490 1490 - pm_runtime_mark_last_busy(swrm->dev); 1491 1491 - pm_runtime_put_autosuspend(swrm->dev); 1311 1311 + pm_runtime_mark_last_busy(ctrl->dev); 1312 1312 + pm_runtime_put_autosuspend(ctrl->dev); 1492 1313 1493 1314 1494 1315 return 0; ··· 1512 1331 return -ENOMEM; 1513 1332 1514 1333 data = of_device_get_match_data(dev); 1334 1334 + ctrl->max_reg = data->max_reg; 1335 1335 + ctrl->reg_layout = data->reg_layout; 1515 1336 ctrl->rows_index = sdw_find_row_index(data->default_rows); 1516 1337 ctrl->cols_index = sdw_find_col_index(data->default_cols); 1517 1338 #if IS_REACHABLE(CONFIG_SLIMBUS) ··· 1637 1454 pm_runtime_set_active(dev); 1638 1455 pm_runtime_enable(dev); 1639 1456 1640 1640 - /* Clk stop is not supported on WSA Soundwire masters */ 1641 1641 - if (ctrl->version <= SWRM_VERSION_1_3_0) { 1642 1642 - ctrl->clock_stop_not_supported = true; 1643 1643 - } else { 1644 1644 - ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val); 1645 1645 - if (val == MASTER_ID_WSA) 1646 1646 - ctrl->clock_stop_not_supported = true; 1647 1647 - } 1648 1648 - 1649 1457 #ifdef CONFIG_DEBUG_FS 1650 1458 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); 1651 1459 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, ··· 1661 1487 clk_disable_unprepare(ctrl->hclk); 1662 1488 1663 1489 return 0; 1664 1664 - } 1665 1665 - 1666 1666 - static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) 1667 1667 - { 1668 1668 - int retry = SWRM_LINK_STATUS_RETRY_CNT; 1669 1669 - int comp_sts; 1670 1670 - 1671 1671 - do { 1672 1672 - swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts); 1673 1673 - 1674 1674 - if (comp_sts & SWRM_FRM_GEN_ENABLED) 1675 1675 - return true; 1676 1676 - 1677 1677 - usleep_range(500, 510); 1678 1678 - } while (retry--); 1679 1679 - 1680 1680 - dev_err(swrm->dev, "%s: link status not %s\n", __func__, 1681 1681 - comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); 1682 1682 - 1683 1683 - return false; 1684 1490 } 1685 1491 1686 1492 static int __maybe_unused swrm_runtime_resume(struct device *dev) ··· 1694 1540 } else { 1695 1541 reset_control_reset(ctrl->audio_cgcr); 1696 1542 1697 1697 - if (ctrl->version >= SWRM_VERSION_1_7_0) { 1543 1543 + if (ctrl->version == SWRM_VERSION_1_7_0) { 1698 1544 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 1699 1545 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, 1700 1546 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); 1547 1547 + } else if (ctrl->version >= SWRM_VERSION_2_0_0) { 1548 1548 + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 1549 1549 + ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, 1550 1550 + SWRM_V2_0_CLK_CTRL_CLK_START); 1701 1551 } else { 1702 1552 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 1703 1553 } 1704 1704 - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, 1554 1554 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 1705 1555 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); 1706 1556 1707 1557 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1708 1708 - ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1709 1709 - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1558 1558 + if (ctrl->version < SWRM_VERSION_2_0_0) 1559 1559 + ctrl->reg_write(ctrl, 1560 1560 + ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 1561 1561 + ctrl->intr_mask); 1562 1562 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 1563 1563 + ctrl->intr_mask); 1710 1564 1711 1565 usleep_range(100, 105); 1712 1566 if (!swrm_wait_for_frame_gen_enabled(ctrl)) ··· 1733 1571 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1734 1572 int ret; 1735 1573 1574 1574 + swrm_wait_for_wr_fifo_done(ctrl); 1736 1575 if (!ctrl->clock_stop_not_supported) { 1737 1576 /* Mask bus clash interrupt */ 1738 1577 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1739 1739 - ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1740 1740 - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1578 1578 + if (ctrl->version < SWRM_VERSION_2_0_0) 1579 1579 + ctrl->reg_write(ctrl, 1580 1580 + ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 1581 1581 + ctrl->intr_mask); 1582 1582 + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 1583 1583 + ctrl->intr_mask); 1741 1584 /* Prepare slaves for clock stop */ 1742 1585 ret = sdw_bus_prep_clk_stop(&ctrl->bus); 1743 1586 if (ret < 0 && ret != -ENODATA) { ··· 1778 1611 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, 1779 1612 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, 1780 1613 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data }, 1614 1614 + { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data }, 1781 1615 {/* sentinel */}, 1782 1616 }; 1783 1617

+76 -85

drivers/soundwire/stream.c

reviewed

··· 1150 1150 *sdw_master_rt_alloc(struct sdw_bus *bus, 1151 1151 struct sdw_stream_runtime *stream) 1152 1152 { 1153 1153 - struct sdw_master_runtime *m_rt; 1153 1153 + struct sdw_master_runtime *m_rt, *walk_m_rt; 1154 1154 + struct list_head *insert_after; 1154 1155 1155 1156 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL); 1156 1157 if (!m_rt) ··· 1160 1159 /* Initialization of Master runtime handle */ 1161 1160 INIT_LIST_HEAD(&m_rt->port_list); 1162 1161 INIT_LIST_HEAD(&m_rt->slave_rt_list); 1163 1163 - list_add_tail(&m_rt->stream_node, &stream->master_list); 1162 1162 + 1163 1163 + /* 1164 1164 + * Add in order of bus id so that when taking the bus_lock 1165 1165 + * of multiple buses they will always be taken in the same 1166 1166 + * order to prevent a mutex deadlock. 1167 1167 + */ 1168 1168 + insert_after = &stream->master_list; 1169 1169 + list_for_each_entry_reverse(walk_m_rt, &stream->master_list, stream_node) { 1170 1170 + if (walk_m_rt->bus->id < bus->id) { 1171 1171 + insert_after = &walk_m_rt->stream_node; 1172 1172 + break; 1173 1173 + } 1174 1174 + } 1175 1175 + list_add(&m_rt->stream_node, insert_after); 1164 1176 1165 1177 list_add_tail(&m_rt->bus_node, &bus->m_rt_list); 1166 1178 ··· 1352 1338 bool update_params) 1353 1339 { 1354 1340 struct sdw_master_runtime *m_rt; 1355 1355 - struct sdw_bus *bus = NULL; 1341 1341 + struct sdw_bus *bus; 1356 1342 struct sdw_master_prop *prop; 1357 1343 struct sdw_bus_params params; 1358 1344 int ret; ··· 1369 1355 return -EINVAL; 1370 1356 } 1371 1357 1372 1372 - if (!update_params) 1373 1373 - goto program_params; 1358 1358 + if (update_params) { 1359 1359 + /* Increment cumulative bus bandwidth */ 1360 1360 + /* TODO: Update this during Device-Device support */ 1361 1361 + bus->params.bandwidth += m_rt->stream->params.rate * 1362 1362 + m_rt->ch_count * m_rt->stream->params.bps; 1374 1363 1375 1375 - /* Increment cumulative bus bandwidth */ 1376 1376 - /* TODO: Update this during Device-Device support */ 1377 1377 - bus->params.bandwidth += m_rt->stream->params.rate * 1378 1378 - m_rt->ch_count * m_rt->stream->params.bps; 1379 1379 - 1380 1380 - /* Compute params */ 1381 1381 - if (bus->compute_params) { 1382 1382 - ret = bus->compute_params(bus); 1383 1383 - if (ret < 0) { 1384 1384 - dev_err(bus->dev, "Compute params failed: %d\n", 1385 1385 - ret); 1386 1386 - goto restore_params; 1364 1364 + /* Compute params */ 1365 1365 + if (bus->compute_params) { 1366 1366 + ret = bus->compute_params(bus); 1367 1367 + if (ret < 0) { 1368 1368 + dev_err(bus->dev, "Compute params failed: %d\n", 1369 1369 + ret); 1370 1370 + goto restore_params; 1371 1371 + } 1387 1372 } 1388 1373 } 1389 1374 1390 1390 - program_params: 1391 1375 /* Program params */ 1392 1376 ret = sdw_program_params(bus, true); 1393 1377 if (ret < 0) { 1394 1378 dev_err(bus->dev, "Program params failed: %d\n", ret); 1395 1379 goto restore_params; 1396 1380 } 1397 1397 - } 1398 1398 - 1399 1399 - if (!bus) { 1400 1400 - pr_err("Configuration error in %s\n", __func__); 1401 1401 - return -EINVAL; 1402 1381 } 1403 1382 1404 1383 ret = do_bank_switch(stream); ··· 1474 1467 static int _sdw_enable_stream(struct sdw_stream_runtime *stream) 1475 1468 { 1476 1469 struct sdw_master_runtime *m_rt; 1477 1477 - struct sdw_bus *bus = NULL; 1470 1470 + struct sdw_bus *bus; 1478 1471 int ret; 1479 1472 1480 1473 /* Enable Master(s) and Slave(s) port(s) associated with stream */ ··· 1495 1488 "Enable port(s) failed ret: %d\n", ret); 1496 1489 return ret; 1497 1490 } 1498 1498 - } 1499 1499 - 1500 1500 - if (!bus) { 1501 1501 - pr_err("Configuration error in %s\n", __func__); 1502 1502 - return -EINVAL; 1503 1491 } 1504 1492 1505 1493 ret = do_bank_switch(stream); ··· 1866 1864 struct sdw_stream_runtime *stream) 1867 1865 { 1868 1866 struct sdw_master_runtime *m_rt; 1869 1869 - bool alloc_master_rt = true; 1867 1867 + bool alloc_master_rt = false; 1870 1868 int ret; 1871 1869 1872 1870 mutex_lock(&bus->bus_lock); ··· 1888 1886 * it first), if so skip allocation and go to configuration 1889 1887 */ 1890 1888 m_rt = sdw_master_rt_find(bus, stream); 1891 1891 - if (m_rt) { 1892 1892 - alloc_master_rt = false; 1893 1893 - goto skip_alloc_master_rt; 1894 1894 - } 1895 1895 - 1896 1896 - m_rt = sdw_master_rt_alloc(bus, stream); 1897 1889 if (!m_rt) { 1898 1898 - dev_err(bus->dev, "%s: Master runtime alloc failed for stream:%s\n", 1899 1899 - __func__, stream->name); 1900 1900 - ret = -ENOMEM; 1901 1901 - goto unlock; 1890 1890 + m_rt = sdw_master_rt_alloc(bus, stream); 1891 1891 + if (!m_rt) { 1892 1892 + dev_err(bus->dev, "%s: Master runtime alloc failed for stream:%s\n", 1893 1893 + __func__, stream->name); 1894 1894 + ret = -ENOMEM; 1895 1895 + goto unlock; 1896 1896 + } 1897 1897 + 1898 1898 + alloc_master_rt = true; 1902 1899 } 1903 1903 - skip_alloc_master_rt: 1904 1900 1905 1905 - if (sdw_master_port_allocated(m_rt)) 1906 1906 - goto skip_alloc_master_port; 1901 1901 + if (!sdw_master_port_allocated(m_rt)) { 1902 1902 + ret = sdw_master_port_alloc(m_rt, num_ports); 1903 1903 + if (ret) 1904 1904 + goto alloc_error; 1907 1905 1908 1908 - ret = sdw_master_port_alloc(m_rt, num_ports); 1909 1909 - if (ret) 1910 1910 - goto alloc_error; 1911 1911 - 1912 1912 - stream->m_rt_count++; 1913 1913 - 1914 1914 - skip_alloc_master_port: 1906 1906 + stream->m_rt_count++; 1907 1907 + } 1915 1908 1916 1909 ret = sdw_master_rt_config(m_rt, stream_config); 1917 1910 if (ret < 0) ··· 1987 1990 { 1988 1991 struct sdw_slave_runtime *s_rt; 1989 1992 struct sdw_master_runtime *m_rt; 1990 1990 - bool alloc_master_rt = true; 1991 1991 - bool alloc_slave_rt = true; 1993 1993 + bool alloc_master_rt = false; 1994 1994 + bool alloc_slave_rt = false; 1992 1995 1993 1996 int ret; 1994 1997 ··· 1999 2002 * and go to configuration 2000 2003 */ 2001 2004 m_rt = sdw_master_rt_find(slave->bus, stream); 2002 2002 - if (m_rt) { 2003 2003 - alloc_master_rt = false; 2004 2004 - goto skip_alloc_master_rt; 2005 2005 - } 2006 2006 - 2007 2007 - /* 2008 2008 - * If this API is invoked by Slave first then m_rt is not valid. 2009 2009 - * So, allocate m_rt and add Slave to it. 2010 2010 - */ 2011 2011 - m_rt = sdw_master_rt_alloc(slave->bus, stream); 2012 2005 if (!m_rt) { 2013 2013 - dev_err(&slave->dev, "%s: Master runtime alloc failed for stream:%s\n", 2014 2014 - __func__, stream->name); 2015 2015 - ret = -ENOMEM; 2016 2016 - goto unlock; 2006 2006 + /* 2007 2007 + * If this API is invoked by Slave first then m_rt is not valid. 2008 2008 + * So, allocate m_rt and add Slave to it. 2009 2009 + */ 2010 2010 + m_rt = sdw_master_rt_alloc(slave->bus, stream); 2011 2011 + if (!m_rt) { 2012 2012 + dev_err(&slave->dev, "%s: Master runtime alloc failed for stream:%s\n", 2013 2013 + __func__, stream->name); 2014 2014 + ret = -ENOMEM; 2015 2015 + goto unlock; 2016 2016 + } 2017 2017 + 2018 2018 + alloc_master_rt = true; 2017 2019 } 2018 2020 2019 2019 - skip_alloc_master_rt: 2020 2021 s_rt = sdw_slave_rt_find(slave, stream); 2021 2021 - if (s_rt) { 2022 2022 - alloc_slave_rt = false; 2023 2023 - goto skip_alloc_slave_rt; 2024 2024 - } 2025 2025 - 2026 2026 - s_rt = sdw_slave_rt_alloc(slave, m_rt); 2027 2022 if (!s_rt) { 2028 2028 - dev_err(&slave->dev, "Slave runtime alloc failed for stream:%s\n", stream->name); 2029 2029 - alloc_slave_rt = false; 2030 2030 - ret = -ENOMEM; 2031 2031 - goto alloc_error; 2023 2023 + s_rt = sdw_slave_rt_alloc(slave, m_rt); 2024 2024 + if (!s_rt) { 2025 2025 + dev_err(&slave->dev, "Slave runtime alloc failed for stream:%s\n", 2026 2026 + stream->name); 2027 2027 + ret = -ENOMEM; 2028 2028 + goto alloc_error; 2029 2029 + } 2030 2030 + 2031 2031 + alloc_slave_rt = true; 2032 2032 } 2033 2033 2034 2034 - skip_alloc_slave_rt: 2035 2035 - if (sdw_slave_port_allocated(s_rt)) 2036 2036 - goto skip_port_alloc; 2034 2034 + if (!sdw_slave_port_allocated(s_rt)) { 2035 2035 + ret = sdw_slave_port_alloc(slave, s_rt, num_ports); 2036 2036 + if (ret) 2037 2037 + goto alloc_error; 2038 2038 + } 2037 2039 2038 2038 - ret = sdw_slave_port_alloc(slave, s_rt, num_ports); 2039 2039 - if (ret) 2040 2040 - goto alloc_error; 2041 2041 - 2042 2042 - skip_port_alloc: 2043 2040 ret = sdw_master_rt_config(m_rt, stream_config); 2044 2041 if (ret) 2045 2042 goto unlock;

+5 -1

include/linux/soundwire/sdw.h

reviewed

··· 5 5 #define __SOUNDWIRE_H 6 6 7 7 #include <linux/bug.h> 8 8 + #include <linux/lockdep_types.h> 8 9 #include <linux/mod_devicetable.h> 9 10 #include <linux/bitfield.h> 10 11 ··· 847 846 * @post_bank_switch: Callback for post bank switch 848 847 * @read_ping_status: Read status from PING frames, reported with two bits per Device. 849 848 * Bits 31:24 are reserved. 849 849 + * @new_peripheral_assigned: Callback to handle enumeration of new peripheral. 850 850 */ 851 851 struct sdw_master_ops { 852 852 int (*read_prop)(struct sdw_bus *bus); ··· 862 860 int (*pre_bank_switch)(struct sdw_bus *bus); 863 861 int (*post_bank_switch)(struct sdw_bus *bus); 864 862 u32 (*read_ping_status)(struct sdw_bus *bus); 865 865 - 863 863 + void (*new_peripheral_assigned)(struct sdw_bus *bus, int dev_num); 866 864 }; 867 865 868 866 /** ··· 908 906 struct list_head slaves; 909 907 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); 910 908 struct mutex bus_lock; 909 909 + struct lock_class_key bus_lock_key; 911 910 struct mutex msg_lock; 911 911 + struct lock_class_key msg_lock_key; 912 912 int (*compute_params)(struct sdw_bus *bus); 913 913 const struct sdw_master_ops *ops; 914 914 const struct sdw_master_port_ops *port_ops;

+91 -3

include/linux/soundwire/sdw_intel.h

reviewed

··· 7 7 #include <linux/irqreturn.h> 8 8 #include <linux/soundwire/sdw.h> 9 9 10 10 + /********************************************************************* 11 11 + * cAVS and ACE1.x definitions 12 12 + *********************************************************************/ 13 13 + 10 14 #define SDW_SHIM_BASE 0x2C000 11 15 #define SDW_ALH_BASE 0x2C800 12 16 #define SDW_SHIM_BASE_ACE 0x38000 ··· 105 101 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 106 102 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 107 103 104 104 + /********************************************************************* 105 105 + * ACE2.x definitions for SHIM registers - only accessible when the 106 106 + * HDAudio extended link LCTL.SPA/CPA = 1. 107 107 + *********************************************************************/ 108 108 + /* x variable is link index */ 109 109 + #define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x)) 110 110 + #define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x)) 111 111 + #define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x)) 112 112 + 113 113 + /* SHIM2 Generic Registers */ 114 114 + /* Read-only capabilities */ 115 115 + #define SDW_SHIM2_LECAP 0x00 116 116 + #define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */ 117 117 + #define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */ 118 118 + 119 119 + /* PCM Stream capabilities */ 120 120 + #define SDW_SHIM2_PCMSCAP 0x10 121 121 + #define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */ 122 122 + #define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */ 123 123 + #define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */ 124 124 + 125 125 + /* Read-only PCM Stream Channel Count, y variable is stream */ 126 126 + #define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y))) 127 127 + #define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */ 128 128 + 129 129 + /* PCM Stream Channel Map */ 130 130 + #define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y))) 131 131 + #define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */ 132 132 + #define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */ 133 133 + #define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */ 134 134 + #define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */ 135 135 + 136 136 + /* SHIM2 vendor-specific registers */ 137 137 + #define SDW_SHIM2_INTEL_VS_LVSCTL 0x04 138 138 + #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26) 139 139 + #define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27) 140 140 + #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30) 141 141 + #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31) 142 142 + 143 143 + #define SDW_SHIM2_MLCS_XTAL_CLK 0x0 144 144 + #define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1 145 145 + #define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2 146 146 + #define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3 147 147 + #define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4 148 148 + 149 149 + #define SDW_SHIM2_INTEL_VS_WAKEEN 0x08 150 150 + #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0) 151 151 + 152 152 + #define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A 153 153 + #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0) 154 154 + 155 155 + #define SDW_SHIM2_INTEL_VS_IOCTL 0x0C 156 156 + #define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0) 157 157 + #define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1) 158 158 + #define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2) 159 159 + #define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3) 160 160 + #define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4) 161 161 + #define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5) 162 162 + #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6) 163 163 + #define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7) 164 164 + #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8) 165 165 + #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9) 166 166 + #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10) 167 167 + 168 168 + #define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E 169 169 + #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0) 170 170 + #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1) 171 171 + #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2) 172 172 + #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3) 173 173 + #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5) 174 174 + 108 175 /** 109 176 * struct sdw_intel_stream_params_data: configuration passed during 110 177 * the @params_stream callback, e.g. for interaction with DSP 111 178 * firmware. 112 179 */ 113 180 struct sdw_intel_stream_params_data { 114 114 - int stream; 181 181 + struct snd_pcm_substream *substream; 115 182 struct snd_soc_dai *dai; 116 183 struct snd_pcm_hw_params *hw_params; 117 184 int link_id; ··· 195 120 * firmware. 196 121 */ 197 122 struct sdw_intel_stream_free_data { 198 198 - int stream; 123 123 + struct snd_pcm_substream *substream; 199 124 struct snd_soc_dai *dai; 200 125 int link_id; 201 126 }; ··· 209 134 struct sdw_intel_stream_params_data *params_data); 210 135 int (*free_stream)(struct device *dev, 211 136 struct sdw_intel_stream_free_data *free_data); 212 212 - int (*trigger)(struct snd_soc_dai *dai, int cmd, int stream); 137 137 + int (*trigger)(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai); 213 138 }; 214 139 215 140 /** ··· 269 194 struct sdw_slave_id id; 270 195 }; 271 196 197 197 + struct hdac_bus; 198 198 + 272 199 /** 273 200 * struct sdw_intel_ctx - context allocated by the controller 274 201 * driver probe ··· 325 248 * DSP driver. The quirks are common for all links for now. 326 249 * @shim_base: sdw shim base. 327 250 * @alh_base: sdw alh base. 251 251 + * @ext: extended HDaudio link support 252 252 + * @hbus: hdac_bus pointer, needed for power management 253 253 + * @eml_lock: mutex protecting shared registers in the HDaudio multi-link 254 254 + * space 328 255 */ 329 256 struct sdw_intel_res { 330 257 const struct sdw_intel_hw_ops *hw_ops; ··· 343 262 u32 clock_stop_quirks; 344 263 u32 shim_base; 345 264 u32 alh_base; 265 265 + bool ext; 266 266 + struct hdac_bus *hbus; 267 267 + struct mutex *eml_lock; 346 268 }; 347 269 348 270 /* ··· 399 315 * @sync_go: helper for multi-link synchronization 400 316 * @sync_check_cmdsync_unlocked: helper for multi-link synchronization 401 317 * and bank switch - shim_lock is assumed to be locked at higher level 318 318 + * @program_sdi: helper for codec command/control based on dev_num 402 319 */ 403 320 struct sdw_intel_hw_ops { 404 321 void (*debugfs_init)(struct sdw_intel *sdw); ··· 426 341 int (*sync_go_unlocked)(struct sdw_intel *sdw); 427 342 int (*sync_go)(struct sdw_intel *sdw); 428 343 bool (*sync_check_cmdsync_unlocked)(struct sdw_intel *sdw); 344 344 + 345 345 + void (*program_sdi)(struct sdw_intel *sdw, int dev_num); 429 346 }; 430 347 431 348 extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops; 349 349 + extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops; 432 350 433 351 #endif

+28 -5

sound/soc/sof/intel/hda.c

reviewed

··· 94 94 struct sdw_intel_stream_params_data *params_data) 95 95 { 96 96 struct snd_soc_dai *d = params_data->dai; 97 97 - struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->stream); 97 97 + struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->substream->stream); 98 98 struct snd_sof_dai_config_data data = { 0 }; 99 99 100 100 data.dai_index = (params_data->link_id << 8) | d->id; ··· 158 158 159 159 static int hda_sdw_probe(struct snd_sof_dev *sdev) 160 160 { 161 161 + const struct sof_intel_dsp_desc *chip; 161 162 struct sof_intel_hda_dev *hdev; 162 163 struct sdw_intel_res res; 163 164 void *sdw; ··· 167 166 168 167 memset(&res, 0, sizeof(res)); 169 168 170 170 - res.hw_ops = &sdw_intel_cnl_hw_ops; 171 171 - res.mmio_base = sdev->bar[HDA_DSP_BAR]; 172 172 - res.shim_base = hdev->desc->sdw_shim_base; 173 173 - res.alh_base = hdev->desc->sdw_alh_base; 169 169 + chip = get_chip_info(sdev->pdata); 170 170 + if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) { 171 171 + res.mmio_base = sdev->bar[HDA_DSP_BAR]; 172 172 + res.hw_ops = &sdw_intel_cnl_hw_ops; 173 173 + res.shim_base = hdev->desc->sdw_shim_base; 174 174 + res.alh_base = hdev->desc->sdw_alh_base; 175 175 + res.ext = false; 176 176 + } else { 177 177 + /* 178 178 + * retrieve eml_lock needed to protect shared registers 179 179 + * in the HDaudio multi-link areas 180 180 + */ 181 181 + res.eml_lock = hdac_bus_eml_get_mutex(sof_to_bus(sdev), true, 182 182 + AZX_REG_ML_LEPTR_ID_SDW); 183 183 + if (!res.eml_lock) 184 184 + return -ENODEV; 185 185 + 186 186 + res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR]; 187 187 + /* 188 188 + * the SHIM and SoundWire register offsets are link-specific 189 189 + * and will be determined when adding auxiliary devices 190 190 + */ 191 191 + res.hw_ops = &sdw_intel_lnl_hw_ops; 192 192 + res.ext = true; 193 193 + } 174 194 res.irq = sdev->ipc_irq; 175 195 res.handle = hdev->info.handle; 176 196 res.parent = sdev->dev; 177 197 res.ops = &sdw_callback; 178 198 res.dev = sdev->dev; 179 199 res.clock_stop_quirks = sdw_clock_stop_quirks; 200 200 + res.hbus = sof_to_bus(sdev); 180 201 181 202 /* 182 203 * ops and arg fields are not populated for now,

+1

sound/soc/sof/intel/shim.h

reviewed

··· 21 21 SOF_INTEL_CAVS_2_0, /* IceLake, JasperLake */ 22 22 SOF_INTEL_CAVS_2_5, /* TigerLake, AlderLake */ 23 23 SOF_INTEL_ACE_1_0, /* MeteorLake */ 24 24 + SOF_INTEL_ACE_2_0, /* LunarLake */ 24 25 }; 25 26 26 27 /*