Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v6.12-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"Some driver specific fixes that came in during the merge window.
Lorenzo Bianconi did some extra testing on the recently added arioha
driver and found some issues, Alexander Dahl fixed some issues with
signal delays in the Atmel QSPI driver and Jinjie Ruan has been fixing
some nits with runtime PM cleanup"
* tag 'spi-fix-v6.12-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: atmel-quadspi: Avoid overwriting delay register settings
spi: airoha: remove read cache in airoha_snand_dirmap_read()
spi: spi-fsl-lpspi: Undo runtime PM changes at driver exit time
spi: atmel-quadspi: Undo runtime PM changes at driver exit time
spi: airoha: fix airoha_snand_{write,read}_data data_len estimation
spi: airoha: fix dirmap_{read,write} operations
+26
-33
+9
-6
drivers/spi/atmel-quadspi.c
+9
-6
drivers/spi/atmel-quadspi.c
···
375
375
* If the QSPI controller is set in regular SPI mode, set it in
376
376
* Serial Memory Mode (SMM).
377
377
*/
378
-
if (aq->mr != QSPI_MR_SMM) {
379
-
atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
380
-
aq->mr = QSPI_MR_SMM;
378
+
if (!(aq->mr & QSPI_MR_SMM)) {
379
+
aq->mr |= QSPI_MR_SMM;
380
+
atmel_qspi_write(aq->scr, aq, QSPI_MR);
381
381
}
382
382
383
383
/* Clear pending interrupts */
···
501
501
if (ret < 0)
502
502
return ret;
503
503
504
-
aq->scr = QSPI_SCR_SCBR(scbr);
504
+
aq->scr &= ~QSPI_SCR_SCBR_MASK;
505
+
aq->scr |= QSPI_SCR_SCBR(scbr);
505
506
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
506
507
507
508
pm_runtime_mark_last_busy(ctrl->dev.parent);
···
535
534
if (ret < 0)
536
535
return ret;
537
536
537
+
aq->scr &= ~QSPI_SCR_DLYBS_MASK;
538
538
aq->scr |= QSPI_SCR_DLYBS(cs_setup);
539
539
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
540
540
···
551
549
atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
552
550
553
551
/* Set the QSPI controller by default in Serial Memory Mode */
554
-
atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
555
-
aq->mr = QSPI_MR_SMM;
552
+
aq->mr |= QSPI_MR_SMM;
553
+
atmel_qspi_write(aq->mr, aq, QSPI_MR);
556
554
557
555
/* Enable the QSPI controller */
558
556
atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
···
723
721
clk_unprepare(aq->pclk);
724
722
725
723
pm_runtime_disable(&pdev->dev);
724
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
726
725
pm_runtime_put_noidle(&pdev->dev);
727
726
}
728
727
+16
-27
drivers/spi/spi-airoha-snfi.c
+16
-27
drivers/spi/spi-airoha-snfi.c
···
211
211
212
212
u8 *txrx_buf;
213
213
dma_addr_t dma_addr;
214
-
215
-
u64 cur_page_num;
216
-
bool data_need_update;
217
214
};
218
215
219
216
struct airoha_snand_ctrl {
···
402
405
for (i = 0; i < len; i += data_len) {
403
406
int err;
404
407
405
-
data_len = min(len, SPI_MAX_TRANSFER_SIZE);
408
+
data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
406
409
err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
407
410
if (err)
408
411
return err;
···
424
427
for (i = 0; i < len; i += data_len) {
425
428
int err;
426
429
427
-
data_len = min(len, SPI_MAX_TRANSFER_SIZE);
430
+
data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
428
431
err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
429
432
if (err)
430
433
return err;
···
641
644
u32 val, rd_mode;
642
645
int err;
643
646
644
-
if (!as_dev->data_need_update)
645
-
return len;
646
-
647
-
as_dev->data_need_update = false;
648
-
649
647
switch (op->cmd.opcode) {
650
648
case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
651
649
rd_mode = 1;
···
731
739
if (err)
732
740
return err;
733
741
734
-
err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
735
-
SPI_NFI_READ_FROM_CACHE_DONE);
742
+
/*
743
+
* SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
744
+
* of dirmap_read operation even if it is already set.
745
+
*/
746
+
err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
747
+
SPI_NFI_READ_FROM_CACHE_DONE,
748
+
SPI_NFI_READ_FROM_CACHE_DONE);
736
749
if (err)
737
750
return err;
738
751
···
867
870
if (err)
868
871
return err;
869
872
870
-
err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
871
-
SPI_NFI_LOAD_TO_CACHE_DONE);
873
+
/*
874
+
* SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
875
+
* of dirmap_write operation even if it is already set.
876
+
*/
877
+
err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
878
+
SPI_NFI_LOAD_TO_CACHE_DONE,
879
+
SPI_NFI_LOAD_TO_CACHE_DONE);
872
880
if (err)
873
881
return err;
874
882
···
887
885
static int airoha_snand_exec_op(struct spi_mem *mem,
888
886
const struct spi_mem_op *op)
889
887
{
890
-
struct airoha_snand_dev *as_dev = spi_get_ctldata(mem->spi);
891
888
u8 data[8], cmd, opcode = op->cmd.opcode;
892
889
struct airoha_snand_ctrl *as_ctrl;
893
890
int i, err;
894
891
895
892
as_ctrl = spi_controller_get_devdata(mem->spi->controller);
896
-
if (opcode == SPI_NAND_OP_PROGRAM_EXECUTE &&
897
-
op->addr.val == as_dev->cur_page_num) {
898
-
as_dev->data_need_update = true;
899
-
} else if (opcode == SPI_NAND_OP_PAGE_READ) {
900
-
if (!as_dev->data_need_update &&
901
-
op->addr.val == as_dev->cur_page_num)
902
-
return 0;
903
-
904
-
as_dev->data_need_update = true;
905
-
as_dev->cur_page_num = op->addr.val;
906
-
}
907
893
908
894
/* switch to manual mode */
909
895
err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
···
976
986
if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
977
987
return -ENOMEM;
978
988
979
-
as_dev->data_need_update = true;
980
989
spi_set_ctldata(spi, as_dev);
981
990
982
991
return 0;