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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: spacemit: support K1 USB2.0 PHY controller
The SpacemiT K1 SoC includes three USB ports:
- One USB2.0 OTG port
- One USB2.0 host-only port
- One USB3.0 port with an integrated USB2.0 DRD interface
Each of these ports is connected to a USB2.0 PHY responsible for USB2
transmission.
This commit adds support for the SpacemiT K1 USB2.0 PHY, which is
compliant with the USB 2.0 specification and supports both 8-bit 60MHz
and 16-bit 30MHz parallel interfaces.
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Ze Huang
and committed by
Vinod Koul
fe4bc1a0
61b84d5b
+217
+1
drivers/phy/Kconfig
+1
drivers/phy/Kconfig
···
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source "drivers/phy/samsung/Kconfig"
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source "drivers/phy/socionext/Kconfig"
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source "drivers/phy/sophgo/Kconfig"
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source "drivers/phy/spacemit/Kconfig"
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source "drivers/phy/st/Kconfig"
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source "drivers/phy/starfive/Kconfig"
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source "drivers/phy/sunplus/Kconfig"
+1
drivers/phy/Makefile
+1
drivers/phy/Makefile
+13
drivers/phy/spacemit/Kconfig
+13
drivers/phy/spacemit/Kconfig
···
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Phy drivers for SpacemiT platforms
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#
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config PHY_SPACEMIT_K1_USB2
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tristate "SpacemiT K1 USB 2.0 PHY support"
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depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF
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depends on COMMON_CLK
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depends on USB_COMMON
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select GENERIC_PHY
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help
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Enable this to support K1 USB 2.0 PHY driver. This driver takes care of
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enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver.
+2
drivers/phy/spacemit/Makefile
+2
drivers/phy/spacemit/Makefile
+200
drivers/phy/spacemit/phy-k1-usb2.c
+200
drivers/phy/spacemit/phy-k1-usb2.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SpacemiT K1 USB 2.0 PHY driver
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*
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* Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd
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* Copyright (C) 2025 Ze Huang <huang.ze@linux.dev>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/usb/of.h>
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+
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#define PHY_RST_MODE_CTRL 0x04
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#define PHY_PLL_RDY BIT(0)
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#define PHY_CLK_CDR_EN BIT(1)
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#define PHY_CLK_PLL_EN BIT(2)
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#define PHY_CLK_MAC_EN BIT(3)
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#define PHY_MAC_RSTN BIT(5)
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#define PHY_CDR_RSTN BIT(6)
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#define PHY_PLL_RSTN BIT(7)
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/*
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* hs line state sel (Bit 13):
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* - 1 (Default): Internal HS line state is set to 01 when usb_hs_tx_en is valid.
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* - 0: Internal HS line state is always driven by usb_hs_lstate.
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*
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* fs line state sel (Bit 14):
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* - 1 (Default): FS line state is determined by the output data
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* (usb_fs_datain/b).
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* - 0: FS line state is always determined by the input data (dmo/dpo).
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*/
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#define PHY_HS_LINE_TX_MODE BIT(13)
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#define PHY_FS_LINE_TX_MODE BIT(14)
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#define PHY_INIT_MODE_BITS (PHY_FS_LINE_TX_MODE | PHY_HS_LINE_TX_MODE)
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#define PHY_CLK_ENABLE_BITS (PHY_CLK_PLL_EN | PHY_CLK_CDR_EN | \
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PHY_CLK_MAC_EN)
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#define PHY_DEASSERT_RST_BITS (PHY_PLL_RSTN | PHY_CDR_RSTN | \
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PHY_MAC_RSTN)
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#define PHY_TX_HOST_CTRL 0x10
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#define PHY_HST_DISC_AUTO_CLR BIT(2) /* autoclear hs host disc when re-connect */
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#define PHY_HSTXP_HW_CTRL 0x34
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#define PHY_HSTXP_RSTN BIT(2) /* generate reset for clock hstxp */
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#define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */
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#define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */
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#define PHY_PLL_DIV_CFG 0x98
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#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
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#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
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#define PHY_FDIV_FRACT_20_21 BIT(12) /* fdiv_reg<21>, <20>, bit21 == bit20 */
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/*
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* freq_sel<1:0>
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* if ref clk freq=24.0MHz-->freq_sel<2:0> == 3b'001, then internal divider value == 80
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*/
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#define PHY_FDIV_FRACT_0_1 GENMASK(14, 13)
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/*
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* pll divider value selection
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* 1: divider value will choose internal default value ,dependent on freq_sel<1:0>
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* 0: divider value will be over ride by fdiv_reg<21:0>
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*/
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#define PHY_DIV_LOCAL_EN BIT(15)
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#define PHY_SEL_FREQ_24MHZ 0x01
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#define FDIV_REG_MASK (PHY_FDIV_FRACT_20_21 | PHY_FDIV_FRACT_16_19 | \
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PHY_FDIV_FRACT_8_15)
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#define FDIV_REG_VAL 0x1ec4 /* 0x100 selects 24MHz, rest are default */
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#define K1_USB2PHY_RESET_TIME_MS 50
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struct spacemit_usb2phy {
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struct phy *phy;
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struct clk *clk;
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struct regmap *regmap_base;
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};
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static const struct regmap_config phy_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x200,
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};
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static int spacemit_usb2phy_init(struct phy *phy)
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{
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struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
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struct regmap *map = sphy->regmap_base;
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u32 val;
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int ret;
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ret = clk_enable(sphy->clk);
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if (ret) {
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dev_err(&phy->dev, "failed to enable clock\n");
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clk_disable(sphy->clk);
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return ret;
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}
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/*
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* make sure the usb controller is not under reset process before
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* any configuration
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*/
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usleep_range(150, 200);
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/* 24M ref clk */
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val = FIELD_PREP(FDIV_REG_MASK, FDIV_REG_VAL) |
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FIELD_PREP(PHY_FDIV_FRACT_0_1, PHY_SEL_FREQ_24MHZ) |
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PHY_DIV_LOCAL_EN;
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regmap_write(map, PHY_PLL_DIV_CFG, val);
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ret = regmap_read_poll_timeout(map, PHY_RST_MODE_CTRL, val,
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(val & PHY_PLL_RDY),
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500, K1_USB2PHY_RESET_TIME_MS * 1000);
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if (ret) {
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dev_err(&phy->dev, "wait PLLREADY timeout\n");
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clk_disable(sphy->clk);
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return ret;
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}
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/* release usb2 phy internal reset and enable clock gating */
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val = (PHY_INIT_MODE_BITS | PHY_CLK_ENABLE_BITS | PHY_DEASSERT_RST_BITS);
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regmap_write(map, PHY_RST_MODE_CTRL, val);
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val = (PHY_HSTXP_RSTN | PHY_CLK_HSTXP_EN | PHY_HSTXP_MODE);
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regmap_write(map, PHY_HSTXP_HW_CTRL, val);
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/* auto clear host disc */
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regmap_update_bits(map, PHY_TX_HOST_CTRL, PHY_HST_DISC_AUTO_CLR,
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PHY_HST_DISC_AUTO_CLR);
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return 0;
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}
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static int spacemit_usb2phy_exit(struct phy *phy)
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{
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struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
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clk_disable(sphy->clk);
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return 0;
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}
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static const struct phy_ops spacemit_usb2phy_ops = {
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.init = spacemit_usb2phy_init,
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.exit = spacemit_usb2phy_exit,
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.owner = THIS_MODULE,
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};
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static int spacemit_usb2phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct spacemit_usb2phy *sphy;
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void __iomem *base;
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sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
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if (!sphy)
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return -ENOMEM;
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sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL);
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if (IS_ERR(sphy->clk))
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return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n");
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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sphy->regmap_base = devm_regmap_init_mmio(dev, base, &phy_regmap_config);
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if (IS_ERR(sphy->regmap_base))
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return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n");
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sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops);
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if (IS_ERR(sphy->phy))
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return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n");
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phy_set_drvdata(sphy->phy, sphy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id spacemit_usb2phy_dt_match[] = {
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{ .compatible = "spacemit,k1-usb2-phy", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match);
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static struct platform_driver spacemit_usb2_phy_driver = {
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.probe = spacemit_usb2phy_probe,
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.driver = {
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.name = "spacemit-usb2-phy",
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.of_match_table = spacemit_usb2phy_dt_match,
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},
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};
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module_platform_driver(spacemit_usb2_phy_driver);
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MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver");
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MODULE_LICENSE("GPL");