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r8169: add RTL_GIGA_MAC_VER_LAST to facilitate adding support for new chip versions

Add a new mac_version enum value RTL_GIGA_MAC_VER_LAST. Benefit is that
when adding support for a new chip version we have to touch less code,
except something changes fundamentally.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/06991f47-2aec-4aa2-8918-2c6e79332303@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Heiner Kallweit and committed by
Jakub Kicinski fe733618 2b065c09

+16 -15
+2 -1
drivers/net/ethernet/realtek/r8169.h
··· 73 73 RTL_GIGA_MAC_VER_66, 74 74 RTL_GIGA_MAC_VER_70, 75 75 RTL_GIGA_MAC_VER_71, 76 - RTL_GIGA_MAC_NONE 76 + RTL_GIGA_MAC_NONE, 77 + RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1 77 78 }; 78 79 79 80 struct rtl8169_private;
+14 -14
drivers/net/ethernet/realtek/r8169_main.c
··· 1289 1289 case RTL_GIGA_MAC_VER_31: 1290 1290 r8168dp_2_mdio_write(tp, location, val); 1291 1291 break; 1292 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 1292 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1293 1293 r8168g_mdio_write(tp, location, val); 1294 1294 break; 1295 1295 default: ··· 1304 1304 case RTL_GIGA_MAC_VER_28: 1305 1305 case RTL_GIGA_MAC_VER_31: 1306 1306 return r8168dp_2_mdio_read(tp, location); 1307 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 1307 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1308 1308 return r8168g_mdio_read(tp, location); 1309 1309 default: 1310 1310 return r8169_mdio_read(tp, location); ··· 1656 1656 break; 1657 1657 case RTL_GIGA_MAC_VER_34: 1658 1658 case RTL_GIGA_MAC_VER_37: 1659 - case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_71: 1659 + case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST: 1660 1660 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1661 1661 break; 1662 1662 default: ··· 2129 2129 tp->tx_lpi_timer = timer_val; 2130 2130 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2131 2131 break; 2132 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2132 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2133 2133 tp->tx_lpi_timer = timer_val; 2134 2134 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2135 2135 break; ··· 2491 2491 case RTL_GIGA_MAC_VER_61: 2492 2492 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2493 2493 break; 2494 - case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: 2494 + case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2495 2495 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2496 2496 RX_PAUSE_SLOT_ON); 2497 2497 break; ··· 2623 2623 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2624 2624 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2625 2625 break; 2626 - case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: 2626 + case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2627 2627 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2628 2628 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2629 2629 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); ··· 2898 2898 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2899 2899 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2900 2900 break; 2901 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 2901 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 2902 2902 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2903 2903 break; 2904 2904 default: ··· 2912 2912 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2913 2913 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2914 2914 break; 2915 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 2915 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 2916 2916 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2917 2917 break; 2918 2918 default: ··· 2950 2950 2951 2951 switch (tp->mac_version) { 2952 2952 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2953 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2953 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2954 2954 /* reset ephy tx/rx disable timer */ 2955 2955 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2956 2956 /* chip can trigger L1.2 */ ··· 2962 2962 } else { 2963 2963 switch (tp->mac_version) { 2964 2964 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2965 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2965 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2966 2966 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2967 2967 break; 2968 2968 default: ··· 4094 4094 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4095 4095 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4096 4096 break; 4097 - case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 4097 + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 4098 4098 rtl_enable_rxdvgate(tp); 4099 4099 fsleep(2000); 4100 4100 break; ··· 4251 4251 4252 4252 switch (tp->mac_version) { 4253 4253 case RTL_GIGA_MAC_VER_34: 4254 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 4254 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 4255 4255 padto = max_t(unsigned int, padto, ETH_ZLEN); 4256 4256 break; 4257 4257 default: ··· 5302 5302 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5303 5303 rtl_hw_init_8168g(tp); 5304 5304 break; 5305 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 5305 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5306 5306 rtl_hw_init_8125(tp); 5307 5307 break; 5308 5308 default: ··· 5327 5327 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5328 5328 return JUMBO_6K; 5329 5329 /* RTL8125/8126 */ 5330 - case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 5330 + case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5331 5331 return JUMBO_16K; 5332 5332 default: 5333 5333 return JUMBO_9K;