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iommu/vt-d: Fix intel iommu iotlb sync hardlockup and retry

During the qi_check_fault process after an IOMMU ITE event, requests at
odd-numbered positions in the queue are set to QI_ABORT, only satisfying
single-request submissions. However, qi_submit_sync now supports multiple
simultaneous submissions, and can't guarantee that the wait_desc will be
at an odd-numbered position. Therefore, if an item times out, IOMMU can't
re-initiate the request, resulting in an infinite polling wait.

This modifies the process by setting the status of all requests already
fetched by IOMMU and recorded as QI_IN_USE status (including wait_desc
requests) to QI_ABORT, thus enabling multiple requests to be resubmitted.

Fixes: 8a1d82462540 ("iommu/vt-d: Multiple descriptors per qi_submit_sync()")
Cc: stable@vger.kernel.org
Signed-off-by: Guanghui Feng <guanghuifeng@linux.alibaba.com>
Tested-by: Shuai Xue <xueshuai@linux.alibaba.com>
Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
Reviewed-by: Samiullah Khawaja <skhawaja@google.com>
Link: https://lore.kernel.org/r/20260306101516.3885775-1-guanghuifeng@linux.alibaba.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Fixes: 8a1d82462540 ("iommu/vt-d: Multiple descriptors per qi_submit_sync()")
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

authored by

Guanghui Feng and committed by
Joerg Roedel
fe89277c f338e773

+1 -2
+1 -2
drivers/iommu/intel/dmar.c
··· 1314 1314 if (fault & DMA_FSTS_ITE) { 1315 1315 head = readl(iommu->reg + DMAR_IQH_REG); 1316 1316 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; 1317 - head |= 1; 1318 1317 tail = readl(iommu->reg + DMAR_IQT_REG); 1319 1318 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; 1320 1319 ··· 1330 1331 do { 1331 1332 if (qi->desc_status[head] == QI_IN_USE) 1332 1333 qi->desc_status[head] = QI_ABORT; 1333 - head = (head - 2 + QI_LENGTH) % QI_LENGTH; 1334 + head = (head - 1 + QI_LENGTH) % QI_LENGTH; 1334 1335 } while (head != tail); 1335 1336 1336 1337 /*