Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: qcom: llcc: Add llcc configuration support for the SA8775p platform
Add llcc configuration support for the SA8775p platform.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20240529101534.3166507-3-quic_tengfan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Tengfei Fan
and committed by
Bjorn Andersson
fed15196
f5dbad39
+35
+35
drivers/soc/qcom/llcc-qcom.c
+35
drivers/soc/qcom/llcc-qcom.c
···
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LLCC_COMMON_STATUS0,
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};
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+
static const struct llcc_slice_config sa8775p_data[] = {
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{LLCC_CPUSS, 1, 2048, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 1, 0, 0},
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{LLCC_VIDSC0, 2, 512, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_CPUSS1, 3, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_CPUHWT, 5, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_AUDIO, 6, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0},
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{LLCC_CMPT, 10, 4096, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_GPUHTW, 11, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_GPU, 12, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 1, 0},
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{LLCC_MMUHWT, 13, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0},
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{LLCC_CMPTDMA, 15, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_DISP, 16, 4096, 2, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_VIDFW, 17, 3072, 1, 0, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_AUDHW, 22, 1024, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 0, 0, 0},
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{LLCC_CVP, 28, 256, 3, 1, 0x00FF, 0x0, 0, 0, 0, 1, 0, 0, 0},
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{LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0},
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{LLCC_WRCACHE, 31, 512, 1, 1, 0x00FF, 0x0, 0, 0, 0, 0, 1, 0, 0},
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};
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+
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static const struct llcc_slice_config sc7180_data[] = {
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{ LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
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{ LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
···
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},
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};
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+
static const struct qcom_llcc_config sa8775p_cfg[] = {
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{
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.sct_data = sa8775p_data,
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.size = ARRAY_SIZE(sa8775p_data),
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.need_llcc_cfg = true,
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.reg_offset = llcc_v2_1_reg_offset,
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.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
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},
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};
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+
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static const struct qcom_llcc_config sc7180_cfg[] = {
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{
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.sct_data = sc7180_data,
···
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static const struct qcom_sct_config qdu1000_cfgs = {
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.llcc_config = qdu1000_cfg,
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.num_config = ARRAY_SIZE(qdu1000_cfg),
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};
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static const struct qcom_sct_config sa8775p_cfgs = {
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.llcc_config = sa8775p_cfg,
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.num_config = ARRAY_SIZE(sa8775p_cfg),
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};
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static const struct qcom_sct_config sc7180_cfgs = {
···
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static const struct of_device_id qcom_llcc_of_match[] = {
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{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
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{ .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs },
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{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
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{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
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{ .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },