tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"This is a largeish batch of fixes, mostly because I missed -rc2 due to
travel/vacation. So in number these are a bit more than ideal unless
you amortize them over two -rcs.

Quick breakdown:
- Defconfig updates
- Making multi_v7_defconfig useful on more hardware to encourage
single-image usage
- Davinci and nomadik updates due to new code merged this merge
window
- Fixes for UART on Samsung platforms, both PM and clock-related
- A handful of warning fixes from defconfig builds, including for
max8925 backlight and pxamci (both with appropriate acks)
- Exynos5440 fixes for LPAE configuration, PM
- ...plus a bunch of other smaller changes all over the place

I expect to switch to regressions-or-severe-bugs-only fixes from here
on out"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
mfd: max8925: fix dt code for backlight
ARM: omap5: Only select errata 798181 if SMP
ARM: EXYNOS: Update CONFIG_ARCH_NR_GPIO for Exynos
ARM: EXYNOS: Fix low level debug support
ARM: SAMSUNG: Save/restore only selected uart's registers
ARM: SAMSUNG: Add SAMSUNG_PM config option to select pm
ARM: S3C24XX: Add missing clkdev entries for s3c2440 UART
ARM: multi_v7_defconfig: Select USB chipidea driver
ARM: pxa: propagate errors from regulator_enable() to pxamci
ARM: zynq: fix compilation warning
ARM: keystone: fix compilation warning
ARM: highbank: Only touch common coherency control register fields
ARM: footbridge: fix overlapping PCI mappings
dmaengine: shdma: fix a build failure on platforms with no DMA support
ARM: STi: Set correct ARM ERRATAs.
ARM: dts: STi: Fix pinconf setup for STiH416 serial2
ARM: nomadik: configure for NO_HZ and HRTIMERS
ARM: nomadik: update defconfig base
ARM: nomadik: Update MMC defconfigs
ARM: davinci: defconfig: enable EDMA driver
...

Linus Torvalds fef36a7a db8cbfad

+307 -196
+1
Documentation/devicetree/bindings/clock/imx27-clock.txt
··· 98 98 fpm 83 99 99 mpll_osc_sel 84 100 100 mpll_sel 85 101 + spll_gate 86 101 102 102 103 Examples: 103 104
+1 -2
arch/arm/Kconfig
··· 1600 1600 config ARCH_NR_GPIO 1601 1601 int 1602 1602 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1603 - default 512 if SOC_OMAP5 1604 - default 512 if ARCH_KEYSTONE 1603 + default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 1605 1604 default 392 if ARCH_U8500 1606 1605 default 352 if ARCH_VT8500 1607 1606 default 288 if ARCH_SUNXI
+1 -1
arch/arm/boot/dts/imx28-apx4devkit.dts
··· 147 147 reg = <0x0a>; 148 148 VDDA-supply = <&reg_3p3v>; 149 149 VDDIO-supply = <&reg_3p3v>; 150 - 150 + clocks = <&saif0>; 151 151 }; 152 152 153 153 pcf8563: rtc@51 {
+1 -1
arch/arm/boot/dts/imx28-evk.dts
··· 195 195 reg = <0x0a>; 196 196 VDDA-supply = <&reg_3p3v>; 197 197 VDDIO-supply = <&reg_3p3v>; 198 - 198 + clocks = <&saif0>; 199 199 }; 200 200 201 201 at24@51 {
+1 -1
arch/arm/boot/dts/imx28-m28evk.dts
··· 184 184 reg = <0x0a>; 185 185 VDDA-supply = <&reg_3p3v>; 186 186 VDDIO-supply = <&reg_3p3v>; 187 - 187 + clocks = <&saif0>; 188 188 }; 189 189 190 190 eeprom: eeprom@51 {
+1
arch/arm/boot/dts/imx28.dtsi
··· 837 837 compatible = "fsl,imx28-saif"; 838 838 reg = <0x80042000 0x2000>; 839 839 interrupts = <59 80>; 840 + #clock-cells = <0>; 840 841 clocks = <&clks 53>; 841 842 dmas = <&dma_apbx 4>; 842 843 dma-names = "rx-tx";
+12 -1
arch/arm/boot/dts/imx51-babbage.dts
··· 61 61 mux-int-port = <2>; 62 62 mux-ext-port = <3>; 63 63 }; 64 + 65 + clocks { 66 + clk_26M: codec_clock { 67 + compatible = "fixed-clock"; 68 + reg=<0>; 69 + #clock-cells = <0>; 70 + clock-frequency = <26000000>; 71 + gpios = <&gpio4 26 1>; 72 + }; 73 + }; 64 74 }; 65 75 66 76 &esdhc1 { ··· 239 229 MX51_PAD_EIM_A27__GPIO2_21 0x5 240 230 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 241 231 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 232 + MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 242 233 >; 243 234 }; 244 235 }; ··· 266 255 sgtl5000: codec@0a { 267 256 compatible = "fsl,sgtl5000"; 268 257 reg = <0x0a>; 269 - clock-frequency = <26000000>; 258 + clocks = <&clk_26M>; 270 259 VDDA-supply = <&vdig_reg>; 271 260 VDDIO-supply = <&vvideo_reg>; 272 261 };
+1 -1
arch/arm/boot/dts/imx53-mba53.dts
··· 27 27 28 28 backlight { 29 29 compatible = "pwm-backlight"; 30 - pwms = <&pwm2 0 50000 0 0>; 30 + pwms = <&pwm2 0 50000>; 31 31 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; 32 32 default-brightness-level = <10>; 33 33 enable-gpios = <&gpio7 7 0>;
+16 -16
arch/arm/boot/dts/imx53.dtsi
··· 725 725 uart1 { 726 726 pinctrl_uart1_1: uart1grp-1 { 727 727 fsl,pins = < 728 - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5 729 - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5 728 + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 729 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 730 730 >; 731 731 }; 732 732 733 733 pinctrl_uart1_2: uart1grp-2 { 734 734 fsl,pins = < 735 - MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5 736 - MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 735 + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 736 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 737 737 >; 738 738 }; 739 739 ··· 748 748 uart2 { 749 749 pinctrl_uart2_1: uart2grp-1 { 750 750 fsl,pins = < 751 - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 752 - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 751 + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 752 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 753 753 >; 754 754 }; 755 755 ··· 766 766 uart3 { 767 767 pinctrl_uart3_1: uart3grp-1 { 768 768 fsl,pins = < 769 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 770 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 771 - MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5 772 - MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5 769 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 770 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 771 + MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 772 + MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 773 773 >; 774 774 }; 775 775 776 776 pinctrl_uart3_2: uart3grp-2 { 777 777 fsl,pins = < 778 - MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 779 - MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 778 + MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 779 + MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 780 780 >; 781 781 }; 782 782 ··· 785 785 uart4 { 786 786 pinctrl_uart4_1: uart4grp-1 { 787 787 fsl,pins = < 788 - MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5 789 - MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5 788 + MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 789 + MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 790 790 >; 791 791 }; 792 792 }; ··· 794 794 uart5 { 795 795 pinctrl_uart5_1: uart5grp-1 { 796 796 fsl,pins = < 797 - MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5 798 - MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5 797 + MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 798 + MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4 799 799 >; 800 800 }; 801 801 };
+9 -1
arch/arm/boot/dts/stih416-pinctrl.dtsi
··· 166 166 reg = <0x9000 0x100>; 167 167 st,bank-name = "PIO31"; 168 168 }; 169 + 170 + serial2-oe { 171 + pinctrl_serial2_oe: serial2-1 { 172 + st,pins { 173 + output-enable = <&PIO11 3 ALT2 OUT>; 174 + }; 175 + }; 176 + }; 177 + 169 178 }; 170 179 171 180 pin-controller-rear { ··· 227 218 st,pins { 228 219 tx = <&PIO17 4 ALT2 OUT>; 229 220 rx = <&PIO17 5 ALT2 IN>; 230 - output-enable = <&PIO11 3 ALT2 OUT>; 231 221 }; 232 222 }; 233 223 };
+1 -1
arch/arm/boot/dts/stih416.dtsi
··· 79 79 interrupts = <0 197 0>; 80 80 clocks = <&CLK_S_ICN_REG_0>; 81 81 pinctrl-names = "default"; 82 - pinctrl-0 = <&pinctrl_serial2>; 82 + pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; 83 83 }; 84 84 85 85 /* SBC_UART1 */
+6
arch/arm/boot/dts/twl4030.dtsi
··· 47 47 regulator-max-microvolt = <3150000>; 48 48 }; 49 49 50 + vmmc2: regulator-vmmc2 { 51 + compatible = "ti,twl4030-vmmc2"; 52 + regulator-min-microvolt = <1850000>; 53 + regulator-max-microvolt = <3150000>; 54 + }; 55 + 50 56 vusb1v5: regulator-vusb1v5 { 51 57 compatible = "ti,twl4030-vusb1v5"; 52 58 };
+4 -4
arch/arm/boot/dts/vf610.dtsi
··· 442 442 compatible = "fsl,mvf600-fec"; 443 443 reg = <0x400d0000 0x1000>; 444 444 interrupts = <0 78 0x04>; 445 - clocks = <&clks VF610_CLK_ENET>, 446 - <&clks VF610_CLK_ENET>, 445 + clocks = <&clks VF610_CLK_ENET0>, 446 + <&clks VF610_CLK_ENET0>, 447 447 <&clks VF610_CLK_ENET>; 448 448 clock-names = "ipg", "ahb", "ptp"; 449 449 status = "disabled"; ··· 453 453 compatible = "fsl,mvf600-fec"; 454 454 reg = <0x400d1000 0x1000>; 455 455 interrupts = <0 79 0x04>; 456 - clocks = <&clks VF610_CLK_ENET>, 457 - <&clks VF610_CLK_ENET>, 456 + clocks = <&clks VF610_CLK_ENET1>, 457 + <&clks VF610_CLK_ENET1>, 458 458 <&clks VF610_CLK_ENET>; 459 459 clock-names = "ipg", "ahb", "ptp"; 460 460 status = "disabled";
-1
arch/arm/common/edma.c
··· 26 26 #include <linux/io.h> 27 27 #include <linux/slab.h> 28 28 #include <linux/edma.h> 29 - #include <linux/err.h> 30 29 #include <linux/of_address.h> 31 30 #include <linux/of_device.h> 32 31 #include <linux/of_dma.h>
+2
arch/arm/configs/da8xx_omapl_defconfig
··· 102 102 CONFIG_SND_DAVINCI_SOC=m 103 103 # CONFIG_HID_SUPPORT is not set 104 104 # CONFIG_USB_SUPPORT is not set 105 + CONFIG_DMADEVICES=y 106 + CONFIG_TI_EDMA=y 105 107 CONFIG_EXT2_FS=y 106 108 CONFIG_EXT3_FS=y 107 109 CONFIG_XFS_FS=m
+2
arch/arm/configs/davinci_all_defconfig
··· 162 162 CONFIG_LEDS_TRIGGER_TIMER=m 163 163 CONFIG_LEDS_TRIGGER_HEARTBEAT=m 164 164 CONFIG_RTC_CLASS=y 165 + CONFIG_DMADEVICES=y 166 + CONFIG_TI_EDMA=y 165 167 CONFIG_EXT2_FS=y 166 168 CONFIG_EXT3_FS=y 167 169 CONFIG_XFS_FS=m
+5 -1
arch/arm/configs/multi_v7_defconfig
··· 53 53 CONFIG_IP_PNP_DHCP=y 54 54 CONFIG_DEVTMPFS=y 55 55 CONFIG_DEVTMPFS_MOUNT=y 56 + CONFIG_OMAP_OCP2SCP=y 56 57 CONFIG_BLK_DEV_SD=y 57 58 CONFIG_ATA=y 58 59 CONFIG_SATA_AHCI_PLATFORM=y ··· 62 61 CONFIG_NETDEVICES=y 63 62 CONFIG_SUN4I_EMAC=y 64 63 CONFIG_NET_CALXEDA_XGMAC=y 64 + CONFIG_KS8851=y 65 65 CONFIG_SMSC911X=y 66 66 CONFIG_STMMAC_ETH=y 67 67 CONFIG_MDIO_SUN4I=y ··· 91 89 CONFIG_I2C_SIRF=y 92 90 CONFIG_I2C_TEGRA=y 93 91 CONFIG_SPI=y 92 + CONFIG_SPI_OMAP24XX=y 94 93 CONFIG_SPI_PL022=y 95 94 CONFIG_SPI_SIRF=y 96 95 CONFIG_SPI_TEGRA114=y ··· 114 111 CONFIG_USB=y 115 112 CONFIG_USB_XHCI_HCD=y 116 113 CONFIG_USB_EHCI_HCD=y 117 - CONFIG_USB_EHCI_MXC=y 118 114 CONFIG_USB_EHCI_TEGRA=y 119 115 CONFIG_USB_EHCI_HCD_PLATFORM=y 120 116 CONFIG_USB_ISP1760_HCD=y 121 117 CONFIG_USB_STORAGE=y 118 + CONFIG_USB_CHIPIDEA=y 119 + CONFIG_USB_CHIPIDEA_HOST=y 122 120 CONFIG_AB8500_USB=y 123 121 CONFIG_NOP_USB_XCEIV=y 124 122 CONFIG_OMAP_USB2=y
+5 -2
arch/arm/configs/nhk8815_defconfig
··· 1 1 # CONFIG_LOCALVERSION_AUTO is not set 2 2 # CONFIG_SWAP is not set 3 3 CONFIG_SYSVIPC=y 4 + CONFIG_NO_HZ_IDLE=y 5 + CONFIG_HIGH_RES_TIMERS=y 4 6 CONFIG_IKCONFIG=y 5 7 CONFIG_IKCONFIG_PROC=y 6 8 CONFIG_LOG_BUF_SHIFT=14 ··· 50 48 CONFIG_MTD=y 51 49 CONFIG_MTD_TESTS=m 52 50 CONFIG_MTD_CMDLINE_PARTS=y 53 - CONFIG_MTD_CHAR=y 54 51 CONFIG_MTD_BLOCK=y 55 52 CONFIG_MTD_NAND_ECC_SMC=y 56 53 CONFIG_MTD_NAND=y ··· 95 94 CONFIG_I2C_NOMADIK=y 96 95 CONFIG_DEBUG_GPIO=y 97 96 # CONFIG_HWMON is not set 97 + CONFIG_REGULATOR=y 98 98 CONFIG_MMC=y 99 - CONFIG_MMC_CLKGATE=y 99 + CONFIG_MMC_UNSAFE_RESUME=y 100 + # CONFIG_MMC_BLOCK_BOUNCE is not set 100 101 CONFIG_MMC_ARMMMCI=y 101 102 CONFIG_NEW_LEDS=y 102 103 CONFIG_LEDS_CLASS=y
+1 -1
arch/arm/mach-davinci/board-dm365-evm.c
··· 505 505 /* 506 506 * Amplifiers on the board 507 507 */ 508 - struct ths7303_platform_data ths7303_pdata = { 508 + static struct ths7303_platform_data ths7303_pdata = { 509 509 .ch_1 = 3, 510 510 .ch_2 = 3, 511 511 .ch_3 = 3,
+1 -1
arch/arm/mach-davinci/dm355.c
··· 860 860 }, 861 861 }; 862 862 863 - struct venc_platform_data dm355_venc_pdata = { 863 + static struct venc_platform_data dm355_venc_pdata = { 864 864 .setup_pinmux = dm355_vpbe_setup_pinmux, 865 865 .setup_clock = dm355_venc_setup_clock, 866 866 };
+1 -1
arch/arm/mach-davinci/dm365.c
··· 1349 1349 }, 1350 1350 }; 1351 1351 1352 - struct venc_platform_data dm365_venc_pdata = { 1352 + static struct venc_platform_data dm365_venc_pdata = { 1353 1353 .setup_pinmux = dm365_vpbe_setup_pinmux, 1354 1354 .setup_clock = dm365_venc_setup_clock, 1355 1355 };
+1
arch/arm/mach-exynos/Kconfig
··· 92 92 bool "SAMSUNG EXYNOS5440" 93 93 default y 94 94 depends on ARCH_EXYNOS5 95 + select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 95 96 select ARCH_HAS_OPP 96 97 select HAVE_ARM_ARCH_TIMER 97 98 select AUTO_ZRELADDR
+1 -1
arch/arm/mach-exynos/Makefile
··· 14 14 15 15 obj-$(CONFIG_ARCH_EXYNOS) += common.o 16 16 17 - obj-$(CONFIG_PM) += pm.o 17 + obj-$(CONFIG_S5P_PM) += pm.o 18 18 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o 19 19 obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20 20
-26
arch/arm/mach-exynos/common.c
··· 58 58 59 59 static void exynos4_map_io(void); 60 60 static void exynos5_map_io(void); 61 - static void exynos5440_map_io(void); 62 61 static int exynos_init(void); 63 62 64 63 static struct cpu_table cpu_ids[] __initdata = { ··· 94 95 }, { 95 96 .idcode = EXYNOS5440_SOC_ID, 96 97 .idmask = EXYNOS5_SOC_MASK, 97 - .map_io = exynos5440_map_io, 98 98 .init = exynos_init, 99 99 .name = name_exynos5440, 100 100 }, ··· 146 148 .virtual = (unsigned long)S5P_VA_GIC_DIST, 147 149 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), 148 150 .length = SZ_64K, 149 - .type = MT_DEVICE, 150 - }, { 151 - .virtual = (unsigned long)S3C_VA_UART, 152 - .pfn = __phys_to_pfn(EXYNOS4_PA_UART), 153 - .length = SZ_512K, 154 151 .type = MT_DEVICE, 155 152 }, { 156 153 .virtual = (unsigned long)S5P_VA_CMU, ··· 261 268 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), 262 269 .length = SZ_64K, 263 270 .type = MT_DEVICE, 264 - }, { 265 - .virtual = (unsigned long)S3C_VA_UART, 266 - .pfn = __phys_to_pfn(EXYNOS5_PA_UART), 267 - .length = SZ_512K, 268 - .type = MT_DEVICE, 269 - }, 270 - }; 271 - 272 - static struct map_desc exynos5440_iodesc0[] __initdata = { 273 - { 274 - .virtual = (unsigned long)S3C_VA_UART, 275 - .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0), 276 - .length = SZ_512K, 277 - .type = MT_DEVICE, 278 271 }, 279 272 }; 280 273 ··· 365 386 366 387 if (soc_is_exynos5250()) 367 388 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); 368 - } 369 - 370 - static void __init exynos5440_map_io(void) 371 - { 372 - iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); 373 389 } 374 390 375 391 void __init exynos_init_time(void)
-1
arch/arm/mach-exynos/common.h
··· 97 97 }; 98 98 99 99 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); 100 - extern void s3c_cpu_resume(void); 101 100 102 101 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
+1
arch/arm/mach-exynos/cpuidle.c
··· 25 25 #include <mach/regs-pmu.h> 26 26 27 27 #include <plat/cpu.h> 28 + #include <plat/pm.h> 28 29 29 30 #include "common.h" 30 31
+5
arch/arm/mach-exynos/include/mach/memory.h
··· 15 15 16 16 #define PLAT_PHYS_OFFSET UL(0x40000000) 17 17 18 + #ifndef CONFIG_ARM_LPAE 18 19 /* Maximum of 256MiB in one bank */ 19 20 #define MAX_PHYSMEM_BITS 32 20 21 #define SECTION_SIZE_BITS 28 22 + #else 23 + #define MAX_PHYSMEM_BITS 36 24 + #define SECTION_SIZE_BITS 31 25 + #endif 21 26 22 27 #endif /* __ASM_ARCH_MEMORY_H */
+6
arch/arm/mach-exynos/pm.c
··· 217 217 struct clk *pll_base; 218 218 unsigned int tmp; 219 219 220 + if (soc_is_exynos5440()) 221 + return 0; 222 + 220 223 s3c_pm_init(); 221 224 222 225 /* All wakeup disable */ ··· 343 340 344 341 static __init int exynos_pm_syscore_init(void) 345 342 { 343 + if (soc_is_exynos5440()) 344 + return 0; 345 + 346 346 register_syscore_ops(&exynos_pm_syscore_ops); 347 347 return 0; 348 348 }
-2
arch/arm/mach-footbridge/dc21285.c
··· 276 276 277 277 sys->mem_offset = DC21285_PCI_MEM; 278 278 279 - pci_ioremap_io(0, DC21285_PCI_IO); 280 - 281 279 pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); 282 280 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 283 281
+4 -3
arch/arm/mach-highbank/highbank.c
··· 115 115 { 116 116 struct resource *res; 117 117 int reg = -1; 118 + u32 val; 118 119 struct device *dev = __dev; 119 120 120 121 if (event != BUS_NOTIFY_ADD_DEVICE) ··· 142 141 return NOTIFY_DONE; 143 142 144 143 if (of_property_read_bool(dev->of_node, "dma-coherent")) { 145 - writel(0xff31, sregs_base + reg); 144 + val = readl(sregs_base + reg); 145 + writel(val | 0xff01, sregs_base + reg); 146 146 set_dma_ops(dev, &arm_coherent_dma_ops); 147 - } else 148 - writel(0, sregs_base + reg); 147 + } 149 148 150 149 return NOTIFY_OK; 151 150 }
+3 -2
arch/arm/mach-imx/clk-imx6q.c
··· 199 199 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", }; 200 200 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 201 201 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 202 - static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 202 + static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 203 + static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 203 204 static const char *vdo_axi_sels[] = { "axi", "ahb", }; 204 205 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 205 206 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", ··· 393 392 clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 394 393 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 395 394 clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); 396 - clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels)); 395 + clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels)); 397 396 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 398 397 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 399 398 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
+2
arch/arm/mach-imx/clk-vf610.c
··· 183 183 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); 184 184 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); 185 185 clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); 186 + clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0)); 187 + clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1)); 186 188 187 189 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); 188 190
+1 -1
arch/arm/mach-imx/mx27.h
··· 135 135 #define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) 136 136 #define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) 137 137 #define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) 138 - #define MX27_INT_SDHC (NR_IRQS_LEGACY + 7) 138 + #define MX27_INT_MSHC (NR_IRQS_LEGACY + 7) 139 139 #define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) 140 140 #define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) 141 141 #define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
+1 -1
arch/arm/mach-keystone/keystone.c
··· 49 49 NULL, 50 50 }; 51 51 52 - void keystone_restart(char mode, const char *cmd) 52 + void keystone_restart(enum reboot_mode mode, const char *cmd) 53 53 { 54 54 u32 val; 55 55
+1 -1
arch/arm/mach-omap2/Kconfig
··· 62 62 select HAVE_SMP 63 63 select COMMON_CLK 64 64 select HAVE_ARM_ARCH_TIMER 65 - select ARM_ERRATA_798181 65 + select ARM_ERRATA_798181 if SMP 66 66 67 67 config SOC_AM33XX 68 68 bool "AM33XX support"
+22 -1
arch/arm/mach-omap2/board-generic.c
··· 15 15 #include <linux/of_irq.h> 16 16 #include <linux/of_platform.h> 17 17 #include <linux/irqdomain.h> 18 + #include <linux/clk.h> 18 19 19 20 #include <asm/mach/arch.h> 20 21 ··· 36 35 { } 37 36 }; 38 37 38 + /* 39 + * Create alias for USB host PHY clock. 40 + * Remove this when clock phandle can be provided via DT 41 + */ 42 + static void __init legacy_init_ehci_clk(char *clkname) 43 + { 44 + int ret; 45 + 46 + ret = clk_add_alias("main_clk", NULL, clkname, NULL); 47 + if (ret) { 48 + pr_err("%s:Failed to add main_clk alias to %s :%d\n", 49 + __func__, clkname, ret); 50 + } 51 + } 52 + 39 53 static void __init omap_generic_init(void) 40 54 { 41 55 omap_sdrc_init(NULL, NULL); ··· 61 45 * HACK: call display setup code for selected boards to enable omapdss. 62 46 * This will be removed when omapdss supports DT. 63 47 */ 64 - if (of_machine_is_compatible("ti,omap4-panda")) 48 + if (of_machine_is_compatible("ti,omap4-panda")) { 65 49 omap4_panda_display_init_of(); 50 + legacy_init_ehci_clk("auxclk3_ck"); 51 + 52 + } 66 53 else if (of_machine_is_compatible("ti,omap4-sdp")) 67 54 omap_4430sdp_display_init_of(); 55 + else if (of_machine_is_compatible("ti,omap5-uevm")) 56 + legacy_init_ehci_clk("auxclk1_ck"); 68 57 } 69 58 70 59 #ifdef CONFIG_SOC_OMAP2420
+13 -4
arch/arm/mach-pxa/em-x270.c
··· 477 477 /* USB Hub power-on and reset */ 478 478 gpio_direction_output(usb_hub_reset, 1); 479 479 gpio_direction_output(GPIO9_USB_VBUS_EN, 0); 480 - regulator_enable(em_x270_usb_ldo); 480 + err = regulator_enable(em_x270_usb_ldo); 481 + if (err) 482 + goto err_free_rst_gpio; 483 + 481 484 gpio_set_value(usb_hub_reset, 0); 482 485 gpio_set_value(usb_hub_reset, 1); 483 486 regulator_disable(em_x270_usb_ldo); 484 - regulator_enable(em_x270_usb_ldo); 487 + err = regulator_enable(em_x270_usb_ldo); 488 + if (err) 489 + goto err_free_rst_gpio; 490 + 485 491 gpio_set_value(usb_hub_reset, 0); 486 492 gpio_set_value(GPIO9_USB_VBUS_EN, 1); 487 493 488 494 return 0; 489 495 496 + err_free_rst_gpio: 497 + gpio_free(usb_hub_reset); 490 498 err_free_vbus_gpio: 491 499 gpio_free(GPIO9_USB_VBUS_EN); 492 500 err_free_usb_ldo: ··· 600 592 return err; 601 593 } 602 594 603 - static void em_x270_mci_setpower(struct device *dev, unsigned int vdd) 595 + static int em_x270_mci_setpower(struct device *dev, unsigned int vdd) 604 596 { 605 597 struct pxamci_platform_data* p_d = dev->platform_data; 606 598 ··· 608 600 int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000; 609 601 610 602 regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV); 611 - regulator_enable(em_x270_sdio_ldo); 603 + return regulator_enable(em_x270_sdio_ldo); 612 604 } else { 613 605 regulator_disable(em_x270_sdio_ldo); 614 606 } 607 + return 0; 615 608 } 616 609 617 610 static void em_x270_mci_exit(struct device *dev, void *data)
+2 -1
arch/arm/mach-pxa/mainstone.c
··· 408 408 return err; 409 409 } 410 410 411 - static void mainstone_mci_setpower(struct device *dev, unsigned int vdd) 411 + static int mainstone_mci_setpower(struct device *dev, unsigned int vdd) 412 412 { 413 413 struct pxamci_platform_data* p_d = dev->platform_data; 414 414 ··· 420 420 printk(KERN_DEBUG "%s: off\n", __func__); 421 421 MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON; 422 422 } 423 + return 0; 423 424 } 424 425 425 426 static void mainstone_mci_exit(struct device *dev, void *data)
+2 -1
arch/arm/mach-pxa/pcm990-baseboard.c
··· 335 335 return err; 336 336 } 337 337 338 - static void pcm990_mci_setpower(struct device *dev, unsigned int vdd) 338 + static int pcm990_mci_setpower(struct device *dev, unsigned int vdd) 339 339 { 340 340 struct pxamci_platform_data *p_d = dev->platform_data; 341 341 u8 val; ··· 348 348 val &= ~PCM990_CTRL_MMC2PWR; 349 349 350 350 pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5); 351 + return 0; 351 352 } 352 353 353 354 static void pcm990_mci_exit(struct device *dev, void *data)
+3 -1
arch/arm/mach-pxa/poodle.c
··· 258 258 return err; 259 259 } 260 260 261 - static void poodle_mci_setpower(struct device *dev, unsigned int vdd) 261 + static int poodle_mci_setpower(struct device *dev, unsigned int vdd) 262 262 { 263 263 struct pxamci_platform_data* p_d = dev->platform_data; 264 264 ··· 270 270 gpio_set_value(POODLE_GPIO_SD_PWR1, 0); 271 271 gpio_set_value(POODLE_GPIO_SD_PWR, 0); 272 272 } 273 + 274 + return 0; 273 275 } 274 276 275 277 static void poodle_mci_exit(struct device *dev, void *data)
+3 -1
arch/arm/mach-pxa/spitz.c
··· 598 598 * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to 599 599 * give the card a chance to fully insert/eject. 600 600 */ 601 - static void spitz_mci_setpower(struct device *dev, unsigned int vdd) 601 + static int spitz_mci_setpower(struct device *dev, unsigned int vdd) 602 602 { 603 603 struct pxamci_platform_data* p_d = dev->platform_data; 604 604 ··· 606 606 spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V); 607 607 else 608 608 spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0); 609 + 610 + return 0; 609 611 } 610 612 611 613 static struct pxamci_platform_data spitz_mci_platform_data = {
+2 -1
arch/arm/mach-pxa/stargate2.c
··· 734 734 * 735 735 * Very simple control. Either it is on or off and is controlled by 736 736 * a gpio pin */ 737 - static void stargate2_mci_setpower(struct device *dev, unsigned int vdd) 737 + static int stargate2_mci_setpower(struct device *dev, unsigned int vdd) 738 738 { 739 739 gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd); 740 + return 0; 740 741 } 741 742 742 743 static void stargate2_mci_exit(struct device *dev, void *data)
+98 -63
arch/arm/mach-s3c24xx/clock-s3c2410.c
··· 119 119 } 120 120 }; 121 121 122 - static struct clk init_clocks[] = { 123 - { 124 - .name = "lcd", 125 - .parent = &clk_h, 126 - .enable = s3c2410_clkcon_enable, 127 - .ctrlbit = S3C2410_CLKCON_LCDC, 128 - }, { 129 - .name = "gpio", 130 - .parent = &clk_p, 131 - .enable = s3c2410_clkcon_enable, 132 - .ctrlbit = S3C2410_CLKCON_GPIO, 133 - }, { 134 - .name = "usb-host", 135 - .parent = &clk_h, 136 - .enable = s3c2410_clkcon_enable, 137 - .ctrlbit = S3C2410_CLKCON_USBH, 138 - }, { 139 - .name = "usb-device", 140 - .parent = &clk_h, 141 - .enable = s3c2410_clkcon_enable, 142 - .ctrlbit = S3C2410_CLKCON_USBD, 143 - }, { 144 - .name = "timers", 145 - .parent = &clk_p, 146 - .enable = s3c2410_clkcon_enable, 147 - .ctrlbit = S3C2410_CLKCON_PWMT, 148 - }, { 149 - .name = "uart", 150 - .devname = "s3c2410-uart.0", 151 - .parent = &clk_p, 152 - .enable = s3c2410_clkcon_enable, 153 - .ctrlbit = S3C2410_CLKCON_UART0, 154 - }, { 155 - .name = "uart", 156 - .devname = "s3c2410-uart.1", 157 - .parent = &clk_p, 158 - .enable = s3c2410_clkcon_enable, 159 - .ctrlbit = S3C2410_CLKCON_UART1, 160 - }, { 161 - .name = "uart", 162 - .devname = "s3c2410-uart.2", 163 - .parent = &clk_p, 164 - .enable = s3c2410_clkcon_enable, 165 - .ctrlbit = S3C2410_CLKCON_UART2, 166 - }, { 167 - .name = "rtc", 168 - .parent = &clk_p, 169 - .enable = s3c2410_clkcon_enable, 170 - .ctrlbit = S3C2410_CLKCON_RTC, 171 - }, { 172 - .name = "watchdog", 173 - .parent = &clk_p, 174 - .ctrlbit = 0, 175 - }, { 176 - .name = "usb-bus-host", 177 - .parent = &clk_usb_bus, 178 - }, { 179 - .name = "usb-bus-gadget", 180 - .parent = &clk_usb_bus, 181 - }, 122 + static struct clk clk_lcd = { 123 + .name = "lcd", 124 + .parent = &clk_h, 125 + .enable = s3c2410_clkcon_enable, 126 + .ctrlbit = S3C2410_CLKCON_LCDC, 127 + }; 128 + 129 + static struct clk clk_gpio = { 130 + .name = "gpio", 131 + .parent = &clk_p, 132 + .enable = s3c2410_clkcon_enable, 133 + .ctrlbit = S3C2410_CLKCON_GPIO, 134 + }; 135 + 136 + static struct clk clk_usb_host = { 137 + .name = "usb-host", 138 + .parent = &clk_h, 139 + .enable = s3c2410_clkcon_enable, 140 + .ctrlbit = S3C2410_CLKCON_USBH, 141 + }; 142 + 143 + static struct clk clk_usb_device = { 144 + .name = "usb-device", 145 + .parent = &clk_h, 146 + .enable = s3c2410_clkcon_enable, 147 + .ctrlbit = S3C2410_CLKCON_USBD, 148 + }; 149 + 150 + static struct clk clk_timers = { 151 + .name = "timers", 152 + .parent = &clk_p, 153 + .enable = s3c2410_clkcon_enable, 154 + .ctrlbit = S3C2410_CLKCON_PWMT, 155 + }; 156 + 157 + struct clk s3c24xx_clk_uart0 = { 158 + .name = "uart", 159 + .devname = "s3c2410-uart.0", 160 + .parent = &clk_p, 161 + .enable = s3c2410_clkcon_enable, 162 + .ctrlbit = S3C2410_CLKCON_UART0, 163 + }; 164 + 165 + struct clk s3c24xx_clk_uart1 = { 166 + .name = "uart", 167 + .devname = "s3c2410-uart.1", 168 + .parent = &clk_p, 169 + .enable = s3c2410_clkcon_enable, 170 + .ctrlbit = S3C2410_CLKCON_UART1, 171 + }; 172 + 173 + struct clk s3c24xx_clk_uart2 = { 174 + .name = "uart", 175 + .devname = "s3c2410-uart.2", 176 + .parent = &clk_p, 177 + .enable = s3c2410_clkcon_enable, 178 + .ctrlbit = S3C2410_CLKCON_UART2, 179 + }; 180 + 181 + static struct clk clk_rtc = { 182 + .name = "rtc", 183 + .parent = &clk_p, 184 + .enable = s3c2410_clkcon_enable, 185 + .ctrlbit = S3C2410_CLKCON_RTC, 186 + }; 187 + 188 + static struct clk clk_watchdog = { 189 + .name = "watchdog", 190 + .parent = &clk_p, 191 + .ctrlbit = 0, 192 + }; 193 + 194 + static struct clk clk_usb_bus_host = { 195 + .name = "usb-bus-host", 196 + .parent = &clk_usb_bus, 197 + }; 198 + 199 + static struct clk clk_usb_bus_gadget = { 200 + .name = "usb-bus-gadget", 201 + .parent = &clk_usb_bus, 202 + }; 203 + 204 + static struct clk *init_clocks[] = { 205 + &clk_lcd, 206 + &clk_gpio, 207 + &clk_usb_host, 208 + &clk_usb_device, 209 + &clk_timers, 210 + &s3c24xx_clk_uart0, 211 + &s3c24xx_clk_uart1, 212 + &s3c24xx_clk_uart2, 213 + &clk_rtc, 214 + &clk_watchdog, 215 + &clk_usb_bus_host, 216 + &clk_usb_bus_gadget, 182 217 }; 183 218 184 219 /* s3c2410_baseclk_add() ··· 230 195 { 231 196 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); 232 197 unsigned long clkcon = __raw_readl(S3C2410_CLKCON); 233 - struct clk *clkp; 234 198 struct clk *xtal; 235 199 int ret; 236 200 int ptr; ··· 241 207 242 208 /* register clocks from clock array */ 243 209 244 - clkp = init_clocks; 245 - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { 210 + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) { 211 + struct clk *clkp = init_clocks[ptr]; 212 + 246 213 /* ensure that we note the clock state */ 247 214 248 215 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
+3
arch/arm/mach-s3c24xx/clock-s3c2440.c
··· 166 166 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), 167 167 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 168 168 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), 169 + CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0), 170 + CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1), 171 + CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2), 169 172 CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll), 170 173 }; 171 174
+2 -1
arch/arm/mach-sti/Kconfig
··· 11 11 select HAVE_SMP 12 12 select HAVE_ARM_SCU if SMP 13 13 select ARCH_REQUIRE_GPIOLIB 14 - select ARM_ERRATA_720789 15 14 select ARM_ERRATA_754322 15 + select ARM_ERRATA_764369 16 + select ARM_ERRATA_775420 16 17 select PL310_ERRATA_753970 if CACHE_PL310 17 18 select PL310_ERRATA_769419 if CACHE_PL310 18 19 help
+1 -1
arch/arm/mach-zynq/common.c
··· 91 91 zynq_scu_map_io(); 92 92 } 93 93 94 - static void zynq_system_reset(char mode, const char *cmd) 94 + static void zynq_system_reset(enum reboot_mode mode, const char *cmd) 95 95 { 96 96 zynq_slcr_system_reset(); 97 97 }
+7
arch/arm/plat-samsung/Kconfig
··· 29 29 help 30 30 Base platform code for Samsung's S5P series SoC. 31 31 32 + config SAMSUNG_PM 33 + bool 34 + depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM) 35 + default y 36 + help 37 + Base platform power management code for samsung code 38 + 32 39 if PLAT_SAMSUNG 33 40 34 41 # boot configurations
+1 -1
arch/arm/plat-samsung/Makefile
··· 51 51 52 52 # PM support 53 53 54 - obj-$(CONFIG_PM) += pm.o 54 + obj-$(CONFIG_SAMSUNG_PM) += pm.o 55 55 obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o 56 56 obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o 57 57
+5
arch/arm/plat-samsung/include/plat/clock.h
··· 83 83 extern struct clksrc_clk clk_epllref; 84 84 extern struct clksrc_clk clk_esysclk; 85 85 86 + /* S3C24XX UART clocks */ 87 + extern struct clk s3c24xx_clk_uart0; 88 + extern struct clk s3c24xx_clk_uart1; 89 + extern struct clk s3c24xx_clk_uart2; 90 + 86 91 /* S3C64XX specific clocks */ 87 92 extern struct clk clk_h2; 88 93 extern struct clk clk_27m;
+4 -4
arch/arm/plat-samsung/include/plat/pm.h
··· 19 19 20 20 struct device; 21 21 22 - #ifdef CONFIG_PM 22 + #ifdef CONFIG_SAMSUNG_PM 23 23 24 24 extern __init int s3c_pm_init(void); 25 25 extern __init int s3c64xx_pm_init(void); ··· 57 57 extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ 58 58 59 59 /* from sleep.S */ 60 - 61 - extern void s3c_cpu_resume(void); 62 60 63 61 extern int s3c2410_cpu_suspend(unsigned long); 64 62 ··· 104 106 extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); 105 107 extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); 106 108 107 - #ifdef CONFIG_PM 109 + #ifdef CONFIG_SAMSUNG_PM 108 110 extern int s3c_irq_wake(struct irq_data *data, unsigned int state); 109 111 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); 112 + extern void s3c_cpu_resume(void); 110 113 #else 111 114 #define s3c_irq_wake NULL 112 115 #define s3c_irqext_wake NULL 116 + #define s3c_cpu_resume NULL 113 117 #endif 114 118 115 119 /* PM debug functions */
+3 -11
arch/arm/plat-samsung/pm.c
··· 80 80 81 81 #ifdef CONFIG_SAMSUNG_PM_DEBUG 82 82 83 - static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; 83 + static struct pm_uart_save uart_save; 84 84 85 85 static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) 86 86 { ··· 101 101 102 102 static void s3c_pm_save_uarts(void) 103 103 { 104 - struct pm_uart_save *save = uart_save; 105 - unsigned int uart; 106 - 107 - for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) 108 - s3c_pm_save_uart(uart, save); 104 + s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save); 109 105 } 110 106 111 107 static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) ··· 122 126 123 127 static void s3c_pm_restore_uarts(void) 124 128 { 125 - struct pm_uart_save *save = uart_save; 126 - unsigned int uart; 127 - 128 - for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) 129 - s3c_pm_restore_uart(uart, save); 129 + s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save); 130 130 } 131 131 #else 132 132 static void s3c_pm_save_uarts(void) { }
+1 -1
drivers/mmc/host/pxamci.c
··· 128 128 !!on ^ host->pdata->gpio_power_invert); 129 129 } 130 130 if (!host->vcc && host->pdata && host->pdata->setpower) 131 - host->pdata->setpower(mmc_dev(host->mmc), vdd); 131 + return host->pdata->setpower(mmc_dev(host->mmc), vdd); 132 132 133 133 return 0; 134 134 }
+21 -20
drivers/video/backlight/max8925_bl.c
··· 101 101 .get_brightness = max8925_backlight_get_brightness, 102 102 }; 103 103 104 - #ifdef CONFIG_OF 105 - static int max8925_backlight_dt_init(struct platform_device *pdev, 106 - struct max8925_backlight_pdata *pdata) 104 + static void max8925_backlight_dt_init(struct platform_device *pdev) 107 105 { 108 106 struct device_node *nproot = pdev->dev.parent->of_node, *np; 109 - int dual_string; 107 + struct max8925_backlight_pdata *pdata; 108 + u32 val; 110 109 111 - if (!nproot) 112 - return -ENODEV; 110 + if (!nproot || !IS_ENABLED(CONFIG_OF)) 111 + return; 112 + 113 + pdata = devm_kzalloc(&pdev->dev, 114 + sizeof(struct max8925_backlight_pdata), 115 + GFP_KERNEL); 116 + if (!pdata) 117 + return; 118 + 113 119 np = of_find_node_by_name(nproot, "backlight"); 114 120 if (!np) { 115 121 dev_err(&pdev->dev, "failed to find backlight node\n"); 116 - return -ENODEV; 122 + return; 117 123 } 118 124 119 - of_property_read_u32(np, "maxim,max8925-dual-string", &dual_string); 120 - pdata->dual_string = dual_string; 121 - return 0; 125 + if (!of_property_read_u32(np, "maxim,max8925-dual-string", &val)) 126 + pdata->dual_string = val; 127 + 128 + pdev->dev.platform_data = pdata; 122 129 } 123 - #else 124 - #define max8925_backlight_dt_init(x, y) (-1) 125 - #endif 126 130 127 131 static int max8925_backlight_probe(struct platform_device *pdev) 128 132 { 129 133 struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent); 130 - struct max8925_backlight_pdata *pdata = pdev->dev.platform_data; 134 + struct max8925_backlight_pdata *pdata; 131 135 struct max8925_backlight_data *data; 132 136 struct backlight_device *bl; 133 137 struct backlight_properties props; ··· 174 170 platform_set_drvdata(pdev, bl); 175 171 176 172 value = 0; 177 - if (pdev->dev.parent->of_node && !pdata) { 178 - pdata = devm_kzalloc(&pdev->dev, 179 - sizeof(struct max8925_backlight_pdata), 180 - GFP_KERNEL); 181 - max8925_backlight_dt_init(pdev, pdata); 182 - } 173 + if (!pdev->dev.platform_data) 174 + max8925_backlight_dt_init(pdev); 183 175 176 + pdata = pdev->dev.platform_data; 184 177 if (pdata) { 185 178 if (pdata->lxw_scl) 186 179 value |= (1 << 7);
+3 -1
include/dt-bindings/clock/vf610-clock.h
··· 158 158 #define VF610_CLK_GPU_SEL 145 159 159 #define VF610_CLK_GPU_EN 146 160 160 #define VF610_CLK_GPU2D 147 161 - #define VF610_CLK_END 148 161 + #define VF610_CLK_ENET0 148 162 + #define VF610_CLK_ENET1 149 163 + #define VF610_CLK_END 150 162 164 163 165 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
+8 -8
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
··· 103 103 #define IMX6Q_GPR1_EXC_MON_MASK BIT(22) 104 104 #define IMX6Q_GPR1_EXC_MON_OKAY 0x0 105 105 #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) 106 - #define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21) 107 - #define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0 108 - #define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21) 109 - #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20) 110 - #define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0 111 - #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20) 112 - #define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19) 106 + #define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21) 107 + #define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0 108 + #define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21) 109 + #define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20) 113 110 #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0 114 - #define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19) 111 + #define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) 112 + #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19) 113 + #define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0 114 + #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) 115 115 #define IMX6Q_GPR1_PCIE_TEST_PD BIT(18) 116 116 #define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17) 117 117 #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
+1 -1
include/linux/platform_data/mmc-pxamci.h
··· 12 12 unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */ 13 13 int (*init)(struct device *, irq_handler_t , void *); 14 14 int (*get_ro)(struct device *); 15 - void (*setpower)(struct device *, unsigned int); 15 + int (*setpower)(struct device *, unsigned int); 16 16 void (*exit)(struct device *, void *); 17 17 int gpio_card_detect; /* gpio detecting card insertion */ 18 18 int gpio_card_ro; /* gpio detecting read only toggle */
+4
include/linux/shdma-base.h
··· 124 124 int shdma_init(struct device *dev, struct shdma_dev *sdev, 125 125 int chan_num); 126 126 void shdma_cleanup(struct shdma_dev *sdev); 127 + #if IS_ENABLED(CONFIG_SH_DMAE_BASE) 127 128 bool shdma_chan_filter(struct dma_chan *chan, void *arg); 129 + #else 130 + #define shdma_chan_filter NULL 131 + #endif 128 132 129 133 #endif