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net: fec: Refactor: #define magic constants

Add defines for bits of ECR, RCR control registers, TX watermark etc.

Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20240212153717.10023-1-csokas.bence@prolan.hu
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Csókás Bence and committed by
Jakub Kicinski ff049886 65d53afd

+30 -16
+30 -16
drivers/net/ethernet/freescale/fec_main.c
··· 240 240 #define PKT_MINBUF_SIZE 64 241 241 242 242 /* FEC receive acceleration */ 243 - #define FEC_RACC_IPDIS (1 << 1) 244 - #define FEC_RACC_PRODIS (1 << 2) 243 + #define FEC_RACC_IPDIS BIT(1) 244 + #define FEC_RACC_PRODIS BIT(2) 245 245 #define FEC_RACC_SHIFT16 BIT(7) 246 246 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 247 247 ··· 273 273 #define FEC_MMFR_TA (2 << 16) 274 274 #define FEC_MMFR_DATA(v) (v & 0xffff) 275 275 /* FEC ECR bits definition */ 276 - #define FEC_ECR_MAGICEN (1 << 2) 277 - #define FEC_ECR_SLEEP (1 << 3) 276 + #define FEC_ECR_RESET BIT(0) 277 + #define FEC_ECR_ETHEREN BIT(1) 278 + #define FEC_ECR_MAGICEN BIT(2) 279 + #define FEC_ECR_SLEEP BIT(3) 280 + #define FEC_ECR_EN1588 BIT(4) 281 + #define FEC_ECR_BYTESWP BIT(8) 282 + /* FEC RCR bits definition */ 283 + #define FEC_RCR_LOOP BIT(0) 284 + #define FEC_RCR_HALFDPX BIT(1) 285 + #define FEC_RCR_MII BIT(2) 286 + #define FEC_RCR_PROMISC BIT(3) 287 + #define FEC_RCR_BC_REJ BIT(4) 288 + #define FEC_RCR_FLOWCTL BIT(5) 289 + #define FEC_RCR_RMII BIT(8) 290 + #define FEC_RCR_10BASET BIT(9) 291 + /* TX WMARK bits */ 292 + #define FEC_TXWMRK_STRFWD BIT(8) 278 293 279 294 #define FEC_MII_TIMEOUT 30000 /* us */ 280 295 ··· 1077 1062 struct fec_enet_private *fep = netdev_priv(ndev); 1078 1063 u32 temp_mac[2]; 1079 1064 u32 rcntl = OPT_FRAME_SIZE | 0x04; 1080 - u32 ecntl = 0x2; /* ETHEREN */ 1065 + u32 ecntl = FEC_ECR_ETHEREN; 1081 1066 1082 1067 /* Whack a reset. We should wait for this. 1083 1068 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC ··· 1152 1137 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1153 1138 rcntl |= (1 << 6); 1154 1139 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1155 - rcntl |= (1 << 8); 1140 + rcntl |= FEC_RCR_RMII; 1156 1141 else 1157 - rcntl &= ~(1 << 8); 1142 + rcntl &= ~FEC_RCR_RMII; 1158 1143 1159 1144 /* 1G, 100M or 10M */ 1160 1145 if (ndev->phydev) { 1161 1146 if (ndev->phydev->speed == SPEED_1000) 1162 1147 ecntl |= (1 << 5); 1163 1148 else if (ndev->phydev->speed == SPEED_100) 1164 - rcntl &= ~(1 << 9); 1149 + rcntl &= ~FEC_RCR_10BASET; 1165 1150 else 1166 - rcntl |= (1 << 9); 1151 + rcntl |= FEC_RCR_10BASET; 1167 1152 } 1168 1153 } else { 1169 1154 #ifdef FEC_MIIGSK_ENR ··· 1222 1207 1223 1208 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1224 1209 /* enable ENET endian swap */ 1225 - ecntl |= (1 << 8); 1210 + ecntl |= FEC_ECR_BYTESWP; 1226 1211 /* enable ENET store and forward mode */ 1227 - writel(1 << 8, fep->hwp + FEC_X_WMRK); 1212 + writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1228 1213 } 1229 1214 1230 1215 if (fep->bufdesc_ex) 1231 - ecntl |= (1 << 4); 1216 + ecntl |= FEC_ECR_EN1588; 1232 1217 1233 1218 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1234 1219 fep->rgmii_txc_dly) ··· 1327 1312 fec_stop(struct net_device *ndev) 1328 1313 { 1329 1314 struct fec_enet_private *fep = netdev_priv(ndev); 1330 - u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1315 + u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1331 1316 u32 val; 1332 1317 1333 1318 /* We cannot expect a graceful transmit stop without link !!! */ ··· 1346 1331 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 1347 1332 writel(0, fep->hwp + FEC_ECNTRL); 1348 1333 } else { 1349 - writel(1, fep->hwp + FEC_ECNTRL); 1334 + writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1350 1335 udelay(10); 1351 1336 } 1352 1337 } else { ··· 1360 1345 /* We have to keep ENET enabled to have MII interrupt stay working */ 1361 1346 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1362 1347 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1363 - writel(2, fep->hwp + FEC_ECNTRL); 1348 + writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1364 1349 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1365 1350 } 1366 1351 } 1367 - 1368 1352 1369 1353 static void 1370 1354 fec_timeout(struct net_device *ndev, unsigned int txqueue)