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iio: adc: ad7768-1: add support for ADAQ776x-1 ADC Family

Add support for ADAQ7767/68/69-1 series, which includes PGIA and
Anti-aliasing filter (AAF) gains. Unlike the AD7768-1, they do not
provide a VCM regulator interface.

The PGA gain is configured in run-time through the scale attribute,
if supported by the device. PGA is controlled by GPIOs provided in
the device tree.

The AAF gain is defined by hardware connections and should be specified
in the device tree.

Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Jonathan Santos and committed by
Jonathan Cameron ff085189 e7b0312c

+308 -4
+1
drivers/iio/adc/Kconfig
··· 411 411 depends on SPI 412 412 select REGULATOR 413 413 select REGMAP_SPI 414 + select RATIONAL 414 415 select IIO_BUFFER 415 416 select IIO_TRIGGER 416 417 select IIO_TRIGGERED_BUFFER
+307 -4
drivers/iio/adc/ad7768-1.c
··· 6 6 */ 7 7 #include <linux/array_size.h> 8 8 #include <linux/bitfield.h> 9 + #include <linux/cleanup.h> 9 10 #include <linux/clk.h> 10 11 #include <linux/completion.h> 11 12 #include <linux/delay.h> ··· 15 14 #include <linux/gpio/driver.h> 16 15 #include <linux/gpio/consumer.h> 17 16 #include <linux/interrupt.h> 17 + #include <linux/limits.h> 18 + #include <linux/math.h> 18 19 #include <linux/minmax.h> 19 20 #include <linux/module.h> 21 + #include <linux/mutex.h> 22 + #include <linux/rational.h> 20 23 #include <linux/regmap.h> 21 24 #include <linux/regulator/consumer.h> 22 25 #include <linux/regulator/driver.h> ··· 112 107 113 108 #define AD7768_VCM_OFF 0x07 114 109 110 + #define ADAQ776X_GAIN_MAX_NANO (128 * NANO) 111 + #define ADAQ776X_MAX_GAIN_MODES 8 112 + 115 113 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 116 114 117 115 #define AD7768_MAX_CHANNELS 1 116 + 117 + #define ADAQ7768_PGA_PINS 3 118 118 119 119 enum ad7768_conv_mode { 120 120 AD7768_CONTINUOUS, ··· 161 151 enum ad7768_scan_type { 162 152 AD7768_SCAN_TYPE_NORMAL, 163 153 AD7768_SCAN_TYPE_HIGH_SPEED, 154 + }; 155 + 156 + enum { 157 + AD7768_PGA_GAIN_0, 158 + AD7768_PGA_GAIN_1, 159 + AD7768_PGA_GAIN_2, 160 + AD7768_PGA_GAIN_3, 161 + AD7768_PGA_GAIN_4, 162 + AD7768_PGA_GAIN_5, 163 + AD7768_PGA_GAIN_6, 164 + AD7768_PGA_GAIN_7, 165 + }; 166 + 167 + enum { 168 + AD7768_AAF_IN1, 169 + AD7768_AAF_IN2, 170 + AD7768_AAF_IN3, 171 + }; 172 + 173 + /* PGA and AAF gains in V/V */ 174 + static const int adaq7768_gains[] = { 175 + [AD7768_PGA_GAIN_0] = 325, /* 0.325 */ 176 + [AD7768_PGA_GAIN_1] = 650, /* 0.650 */ 177 + [AD7768_PGA_GAIN_2] = 1300, /* 1.300 */ 178 + [AD7768_PGA_GAIN_3] = 2600, /* 2.600 */ 179 + [AD7768_PGA_GAIN_4] = 5200, /* 5.200 */ 180 + [AD7768_PGA_GAIN_5] = 10400, /* 10.400 */ 181 + [AD7768_PGA_GAIN_6] = 20800, /* 20.800 */ 182 + }; 183 + 184 + static const int adaq7769_gains[] = { 185 + [AD7768_PGA_GAIN_0] = 1000, /* 1.000 */ 186 + [AD7768_PGA_GAIN_1] = 2000, /* 2.000 */ 187 + [AD7768_PGA_GAIN_2] = 4000, /* 4.000 */ 188 + [AD7768_PGA_GAIN_3] = 8000, /* 8.000 */ 189 + [AD7768_PGA_GAIN_4] = 16000, /* 16.000 */ 190 + [AD7768_PGA_GAIN_5] = 32000, /* 32.000 */ 191 + [AD7768_PGA_GAIN_6] = 64000, /* 64.000 */ 192 + [AD7768_PGA_GAIN_7] = 128000, /* 128.000 */ 193 + }; 194 + 195 + static const int ad7768_aaf_gains_bp[] = { 196 + [AD7768_AAF_IN1] = 10000, /* 1.000 */ 197 + [AD7768_AAF_IN2] = 3640, /* 0.364 */ 198 + [AD7768_AAF_IN3] = 1430, /* 0.143 */ 164 199 }; 165 200 166 201 /* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */ ··· 272 217 const char *name; 273 218 const struct iio_chan_spec *channel_spec; 274 219 int num_channels; 220 + const int *pga_gains; 221 + int num_pga_modes; 222 + int default_pga_mode; 223 + int pgia_mode2pin_offset; 224 + bool has_pga; 225 + bool has_variable_aaf; 226 + bool has_vcm_regulator; 275 227 }; 276 228 277 229 struct ad7768_state { ··· 296 234 unsigned int samp_freq; 297 235 unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; 298 236 unsigned int samp_freq_avail_len; 237 + unsigned int pga_gain_mode; 238 + unsigned int aaf_gain; 239 + int scale_tbl[ADAQ776X_MAX_GAIN_MODES][2]; 299 240 struct completion completion; 300 241 struct iio_trigger *trig; 242 + struct gpio_descs *pga_gpios; 301 243 struct gpio_desc *gpio_sync_in; 302 244 struct gpio_desc *gpio_reset; 303 245 const char *labels[AD7768_MAX_CHANNELS]; 304 246 struct gpio_chip gpiochip; 305 247 const struct ad7768_chip_info *chip; 306 248 bool en_spi_sync; 249 + struct mutex pga_lock; /* protect device internal state (PGA) */ 307 250 /* 308 251 * DMA (thus cache coherency maintenance) may require the 309 252 * transfer buffers to live in their own cache lines. ··· 531 464 return ret; 532 465 } 533 466 467 + static void ad7768_fill_scale_tbl(struct iio_dev *dev) 468 + { 469 + struct ad7768_state *st = iio_priv(dev); 470 + const struct iio_scan_type *scan_type; 471 + int val, val2, tmp0, tmp1, i; 472 + struct u32_fract fract; 473 + unsigned long n, d; 474 + u64 tmp2; 475 + 476 + scan_type = iio_get_current_scan_type(dev, &dev->channels[0]); 477 + if (scan_type->sign == 's') 478 + val2 = scan_type->realbits - 1; 479 + else 480 + val2 = scan_type->realbits; 481 + 482 + for (i = 0; i < st->chip->num_pga_modes; i++) { 483 + /* Convert gain to a fraction format */ 484 + fract.numerator = st->chip->pga_gains[i]; 485 + fract.denominator = MILLI; 486 + if (st->chip->has_variable_aaf) { 487 + fract.numerator *= ad7768_aaf_gains_bp[st->aaf_gain]; 488 + fract.denominator *= PERMYRIAD; 489 + } 490 + 491 + rational_best_approximation(fract.numerator, fract.denominator, 492 + INT_MAX, INT_MAX, &n, &d); 493 + 494 + val = mult_frac(st->vref_uv, d, n); 495 + /* Would multiply by NANO here, but value is already in milli */ 496 + tmp2 = ((u64)val * MICRO) >> val2; 497 + tmp0 = div_u64_rem(tmp2, NANO, &tmp1); 498 + st->scale_tbl[i][0] = tmp0; /* Integer part */ 499 + st->scale_tbl[i][1] = abs(tmp1); /* Fractional part */ 500 + } 501 + } 502 + 534 503 static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, 535 504 unsigned int dec_rate) 536 505 { ··· 668 565 st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx]; 669 566 } 670 567 568 + /* Update scale table: scale values vary according to the precision */ 569 + ad7768_fill_scale_tbl(dev); 570 + 671 571 ad7768_fill_samp_freq_tbl(st); 672 572 673 573 /* A sync-in pulse is required after every configuration change */ 674 574 return ad7768_send_sync_pulse(st); 575 + } 576 + 577 + static int ad7768_setup_pga(struct device *dev, struct ad7768_state *st) 578 + { 579 + st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); 580 + if (IS_ERR(st->pga_gpios)) 581 + return dev_err_probe(dev, PTR_ERR(st->pga_gpios), 582 + "Failed to get PGA gpios.\n"); 583 + 584 + if (st->pga_gpios->ndescs != ADAQ7768_PGA_PINS) 585 + return dev_err_probe(dev, -EINVAL, 586 + "Expected %d GPIOs for PGA control.\n", 587 + ADAQ7768_PGA_PINS); 588 + return 0; 589 + } 590 + 591 + static int ad7768_calc_pga_gain(struct ad7768_state *st, int gain_int, 592 + int gain_fract, int precision) 593 + { 594 + u64 gain_nano; 595 + u32 tmp; 596 + 597 + gain_nano = gain_int * NANO + gain_fract; 598 + gain_nano = clamp(gain_nano, 0, ADAQ776X_GAIN_MAX_NANO); 599 + tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << precision, NANO); 600 + gain_nano = DIV_ROUND_CLOSEST(st->vref_uv, tmp); 601 + if (st->chip->has_variable_aaf) 602 + gain_nano = DIV_ROUND_CLOSEST_ULL(gain_nano * PERMYRIAD, 603 + ad7768_aaf_gains_bp[st->aaf_gain]); 604 + 605 + return find_closest(gain_nano, st->chip->pga_gains, 606 + (int)st->chip->num_pga_modes); 607 + } 608 + 609 + static int ad7768_set_pga_gain(struct ad7768_state *st, 610 + int gain_mode) 611 + { 612 + int pgia_pins_value = abs(gain_mode - st->chip->pgia_mode2pin_offset); 613 + DECLARE_BITMAP(bitmap, ADAQ7768_PGA_PINS) = { }; 614 + int ret; 615 + 616 + guard(mutex)(&st->pga_lock); 617 + 618 + bitmap_write(bitmap, pgia_pins_value, 0, ADAQ7768_PGA_PINS); 619 + ret = gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); 620 + if (ret) 621 + return ret; 622 + 623 + st->pga_gain_mode = gain_mode; 624 + 625 + return 0; 675 626 } 676 627 677 628 static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) ··· 949 792 AD7768_CHAN(0, 0), 950 793 }; 951 794 795 + static const struct iio_chan_spec adaq776x_channels[] = { 796 + AD7768_CHAN(0, BIT(IIO_CHAN_INFO_SCALE)), 797 + }; 798 + 952 799 static int ad7768_read_raw(struct iio_dev *indio_dev, 953 800 struct iio_chan_spec const *chan, 954 801 int *val, int *val2, long info) ··· 980 819 return IIO_VAL_INT; 981 820 982 821 case IIO_CHAN_INFO_SCALE: 983 - *val = (st->vref_uv * 2) / 1000; 822 + if (st->chip->has_pga) { 823 + guard(mutex)(&st->pga_lock); 824 + 825 + *val = st->scale_tbl[st->pga_gain_mode][0]; 826 + *val2 = st->scale_tbl[st->pga_gain_mode][1]; 827 + return IIO_VAL_INT_PLUS_NANO; 828 + } 829 + 830 + temp = (st->vref_uv * 2) / 1000; 831 + if (st->chip->has_variable_aaf) 832 + temp = (temp * PERMYRIAD) / ad7768_aaf_gains_bp[st->aaf_gain]; 833 + 834 + *val = temp; 984 835 *val2 = scan_type->realbits; 985 836 986 837 return IIO_VAL_FRACTIONAL_LOG2; ··· 1048 875 *length = st->samp_freq_avail_len; 1049 876 *type = IIO_VAL_INT; 1050 877 return IIO_AVAIL_LIST; 878 + case IIO_CHAN_INFO_SCALE: 879 + *vals = (int *)st->scale_tbl; 880 + *length = st->chip->num_pga_modes * 2; 881 + *type = IIO_VAL_INT_PLUS_NANO; 882 + return IIO_AVAIL_LIST; 1051 883 default: 1052 884 return -EINVAL; 885 + } 886 + } 887 + 888 + static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, 889 + struct iio_chan_spec const *chan, long mask) 890 + { 891 + switch (mask) { 892 + case IIO_CHAN_INFO_SCALE: 893 + return IIO_VAL_INT_PLUS_NANO; 894 + default: 895 + return IIO_VAL_INT_PLUS_MICRO; 1053 896 } 1054 897 } 1055 898 ··· 1074 885 int val, int val2, long info) 1075 886 { 1076 887 struct ad7768_state *st = iio_priv(indio_dev); 888 + const struct iio_scan_type *scan_type; 1077 889 int ret; 890 + 891 + scan_type = iio_get_current_scan_type(indio_dev, chan); 892 + if (IS_ERR(scan_type)) 893 + return PTR_ERR(scan_type); 1078 894 1079 895 switch (info) { 1080 896 case IIO_CHAN_INFO_SAMP_FREQ: ··· 1096 902 ret = ad7768_update_dec_rate(indio_dev, val); 1097 903 iio_device_release_direct(indio_dev); 1098 904 return ret; 905 + case IIO_CHAN_INFO_SCALE: { 906 + int gain_mode; 907 + 908 + if (!st->chip->has_pga) 909 + return -EOPNOTSUPP; 910 + 911 + if (scan_type->sign == 's') 912 + gain_mode = ad7768_calc_pga_gain(st, val, val2, 913 + scan_type->realbits - 1); 914 + else 915 + gain_mode = ad7768_calc_pga_gain(st, val, val2, 916 + scan_type->realbits); 917 + 918 + return ad7768_set_pga_gain(st, gain_mode); 919 + } 1099 920 default: 1100 921 return -EINVAL; 1101 922 } ··· 1137 928 .read_raw = &ad7768_read_raw, 1138 929 .read_avail = &ad7768_read_avail, 1139 930 .write_raw = &ad7768_write_raw, 931 + .write_raw_get_fmt = &ad7768_write_raw_get_fmt, 1140 932 .read_label = ad7768_read_label, 1141 933 .get_current_scan_type = &ad7768_get_current_scan_type, 1142 934 .debugfs_reg_access = &ad7768_reg_access, ··· 1521 1311 .owner = THIS_MODULE, 1522 1312 }; 1523 1313 1524 - static int ad7768_register_regulators(struct device *dev, struct ad7768_state *st, 1525 - struct iio_dev *indio_dev) 1314 + static int ad7768_register_vcm_regulator(struct device *dev, 1315 + struct ad7768_state *st, 1316 + struct iio_dev *indio_dev) 1526 1317 { 1527 1318 struct regulator_config config = { 1528 1319 .dev = dev, ··· 1545 1334 return 0; 1546 1335 } 1547 1336 1337 + static int ad7768_parse_aaf_gain(struct device *dev, struct ad7768_state *st) 1338 + { 1339 + u32 val; 1340 + int ret; 1341 + 1342 + ret = device_property_read_u32(dev, "adi,aaf-gain-bp", &val); 1343 + if (ret == -EINVAL) { 1344 + /* If controllable, use default */ 1345 + if (st->chip->has_variable_aaf) 1346 + st->aaf_gain = AD7768_AAF_IN1; 1347 + return 0; 1348 + } 1349 + if (ret) 1350 + return dev_err_probe(dev, ret, "Failed to get AAF gain value\n"); 1351 + 1352 + if (!st->chip->has_variable_aaf) 1353 + return dev_err_probe(dev, -EOPNOTSUPP, 1354 + "AAF gain provided, but not supported for %s\n", st->chip->name); 1355 + 1356 + switch (val) { 1357 + case 10000: 1358 + st->aaf_gain = AD7768_AAF_IN1; 1359 + break; 1360 + case 3640: 1361 + st->aaf_gain = AD7768_AAF_IN2; 1362 + break; 1363 + case 1430: 1364 + st->aaf_gain = AD7768_AAF_IN3; 1365 + break; 1366 + default: 1367 + return dev_err_probe(dev, -EINVAL, "Invalid firmware provided AAF gain\n"); 1368 + } 1369 + 1370 + return 0; 1371 + } 1372 + 1548 1373 static const struct ad7768_chip_info ad7768_chip_info = { 1549 1374 .name = "ad7768-1", 1550 1375 .channel_spec = ad7768_channels, 1551 1376 .num_channels = ARRAY_SIZE(ad7768_channels), 1377 + .has_vcm_regulator = true, 1378 + }; 1379 + 1380 + static const struct ad7768_chip_info adaq7767_chip_info = { 1381 + .name = "adaq7767-1", 1382 + .channel_spec = ad7768_channels, 1383 + .num_channels = ARRAY_SIZE(ad7768_channels), 1384 + .has_variable_aaf = true, 1385 + }; 1386 + 1387 + static const struct ad7768_chip_info adaq7768_chip_info = { 1388 + .name = "adaq7768-1", 1389 + .channel_spec = adaq776x_channels, 1390 + .num_channels = ARRAY_SIZE(adaq776x_channels), 1391 + .pga_gains = adaq7768_gains, 1392 + .default_pga_mode = AD7768_PGA_GAIN_2, 1393 + .num_pga_modes = ARRAY_SIZE(adaq7768_gains), 1394 + .pgia_mode2pin_offset = 6, 1395 + .has_pga = true, 1396 + }; 1397 + 1398 + static const struct ad7768_chip_info adaq7769_chip_info = { 1399 + .name = "adaq7769-1", 1400 + .channel_spec = adaq776x_channels, 1401 + .num_channels = ARRAY_SIZE(adaq776x_channels), 1402 + .pga_gains = adaq7769_gains, 1403 + .default_pga_mode = AD7768_PGA_GAIN_0, 1404 + .num_pga_modes = ARRAY_SIZE(adaq7769_gains), 1405 + .pgia_mode2pin_offset = 0, 1406 + .has_pga = true, 1407 + .has_variable_aaf = true, 1552 1408 }; 1553 1409 1554 1410 static int ad7768_probe(struct spi_device *spi) ··· 1676 1398 indio_dev->modes = INDIO_DIRECT_MODE; 1677 1399 1678 1400 /* Register VCM output regulator */ 1679 - ret = ad7768_register_regulators(&spi->dev, st, indio_dev); 1401 + if (st->chip->has_vcm_regulator) { 1402 + ret = ad7768_register_vcm_regulator(&spi->dev, st, indio_dev); 1403 + if (ret) 1404 + return ret; 1405 + } 1406 + 1407 + ret = ad7768_parse_aaf_gain(&spi->dev, st); 1680 1408 if (ret) 1681 1409 return ret; 1682 1410 ··· 1693 1409 } 1694 1410 1695 1411 init_completion(&st->completion); 1412 + ret = devm_mutex_init(&spi->dev, &st->pga_lock); 1413 + if (ret) 1414 + return ret; 1415 + 1416 + if (st->chip->has_pga) { 1417 + ret = ad7768_setup_pga(&spi->dev, st); 1418 + if (ret) 1419 + return ret; 1420 + 1421 + ret = ad7768_set_pga_gain(st, st->chip->default_pga_mode); 1422 + if (ret) 1423 + return ret; 1424 + } 1696 1425 1697 1426 ret = ad7768_set_channel_label(indio_dev, st->chip->num_channels); 1698 1427 if (ret) ··· 1727 1430 1728 1431 static const struct spi_device_id ad7768_id_table[] = { 1729 1432 { "ad7768-1", (kernel_ulong_t)&ad7768_chip_info }, 1433 + { "adaq7767-1", (kernel_ulong_t)&adaq7767_chip_info }, 1434 + { "adaq7768-1", (kernel_ulong_t)&adaq7768_chip_info }, 1435 + { "adaq7769-1", (kernel_ulong_t)&adaq7769_chip_info }, 1730 1436 { } 1731 1437 }; 1732 1438 MODULE_DEVICE_TABLE(spi, ad7768_id_table); 1733 1439 1734 1440 static const struct of_device_id ad7768_of_match[] = { 1735 1441 { .compatible = "adi,ad7768-1", .data = &ad7768_chip_info }, 1442 + { .compatible = "adi,adaq7767-1", .data = &adaq7767_chip_info }, 1443 + { .compatible = "adi,adaq7768-1", .data = &adaq7768_chip_info }, 1444 + { .compatible = "adi,adaq7769-1", .data = &adaq7769_chip_info }, 1736 1445 { } 1737 1446 }; 1738 1447 MODULE_DEVICE_TABLE(of, ad7768_of_match);