tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'perf_urgent_for_v6.14_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 perf fixes from Borislav Petkov:

- Explicitly clear DEBUGCTL.LBR to prevent LBRs continuing being
enabled after handoff to the OS

- Check CPUID(0x23) leaf and subleafs presence properly

- Remove the PEBS-via-PT feature from being supported on hybrid systems

- Fix perf record/top default commands on systems without a raw PMU
registered

* tag 'perf_urgent_for_v6.14_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/intel: Ensure LBRs are disabled when a CPU is starting
perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF
perf/x86/intel: Clean up PEBS-via-PT on hybrid
perf/x86/rapl: Fix the error checking order

Linus Torvalds ff1848d8 ff3b373e

+54 -32
+14 -19
arch/x86/events/intel/core.c
··· 4905 4905 4906 4906 static void update_pmu_cap(struct x86_hybrid_pmu *pmu) 4907 4907 { 4908 - unsigned int sub_bitmaps, eax, ebx, ecx, edx; 4908 + unsigned int cntr, fixed_cntr, ecx, edx; 4909 + union cpuid35_eax eax; 4910 + union cpuid35_ebx ebx; 4909 4911 4910 - cpuid(ARCH_PERFMON_EXT_LEAF, &sub_bitmaps, &ebx, &ecx, &edx); 4912 + cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx); 4911 4913 4912 - if (ebx & ARCH_PERFMON_EXT_UMASK2) 4914 + if (ebx.split.umask2) 4913 4915 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2; 4914 - if (ebx & ARCH_PERFMON_EXT_EQ) 4916 + if (ebx.split.eq) 4915 4917 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ; 4916 4918 4917 - if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { 4919 + if (eax.split.cntr_subleaf) { 4918 4920 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 4919 - &eax, &ebx, &ecx, &edx); 4920 - pmu->cntr_mask64 = eax; 4921 - pmu->fixed_cntr_mask64 = ebx; 4921 + &cntr, &fixed_cntr, &ecx, &edx); 4922 + pmu->cntr_mask64 = cntr; 4923 + pmu->fixed_cntr_mask64 = fixed_cntr; 4922 4924 } 4923 4925 4924 4926 if (!intel_pmu_broken_perf_cap()) { ··· 4942 4940 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 4943 4941 else 4944 4942 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4945 - 4946 - if (pmu->intel_cap.pebs_output_pt_available) 4947 - pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 4948 - else 4949 - pmu->pmu.capabilities &= ~PERF_PMU_CAP_AUX_OUTPUT; 4950 4943 4951 4944 intel_pmu_check_event_constraints(pmu->event_constraints, 4952 4945 pmu->cntr_mask64, ··· 5020 5023 5021 5024 pr_info("%s PMU driver: ", pmu->name); 5022 5025 5023 - if (pmu->intel_cap.pebs_output_pt_available) 5024 - pr_cont("PEBS-via-PT "); 5025 - 5026 5026 pr_cont("\n"); 5027 5027 5028 5028 x86_pmu_show_pmu_cap(&pmu->pmu); ··· 5042 5048 5043 5049 init_debug_store_on_cpu(cpu); 5044 5050 /* 5045 - * Deal with CPUs that don't clear their LBRs on power-up. 5051 + * Deal with CPUs that don't clear their LBRs on power-up, and that may 5052 + * even boot with LBRs enabled. 5046 5053 */ 5054 + if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr) 5055 + msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT); 5047 5056 intel_pmu_lbr_reset(); 5048 5057 5049 5058 cpuc->lbr_sel = NULL; ··· 6367 6370 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 6368 6371 if (pmu->pmu_type & hybrid_small_tiny) { 6369 6372 pmu->intel_cap.perf_metrics = 0; 6370 - pmu->intel_cap.pebs_output_pt_available = 1; 6371 6373 pmu->mid_ack = true; 6372 6374 } else if (pmu->pmu_type & hybrid_big) { 6373 6375 pmu->intel_cap.perf_metrics = 1; 6374 - pmu->intel_cap.pebs_output_pt_available = 0; 6375 6376 pmu->late_ack = true; 6376 6377 } 6377 6378 }
+9 -1
arch/x86/events/intel/ds.c
··· 2578 2578 } 2579 2579 pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual); 2580 2580 2581 - if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) { 2581 + /* 2582 + * The PEBS-via-PT is not supported on hybrid platforms, 2583 + * because not all CPUs of a hybrid machine support it. 2584 + * The global x86_pmu.intel_cap, which only contains the 2585 + * common capabilities, is used to check the availability 2586 + * of the feature. The per-PMU pebs_output_pt_available 2587 + * in a hybrid machine should be ignored. 2588 + */ 2589 + if (x86_pmu.intel_cap.pebs_output_pt_available) { 2582 2590 pr_cont("PEBS-via-PT, "); 2583 2591 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 2584 2592 }
+4 -8
arch/x86/events/rapl.c
··· 370 370 unsigned int rapl_pmu_idx; 371 371 struct rapl_pmus *rapl_pmus; 372 372 373 + /* only look at RAPL events */ 374 + if (event->attr.type != event->pmu->type) 375 + return -ENOENT; 376 + 373 377 /* unsupported modes and filters */ 374 378 if (event->attr.sample_period) /* no sampling */ 375 379 return -EINVAL; ··· 391 387 rapl_pmus_scope = rapl_pmus->pmu.scope; 392 388 393 389 if (rapl_pmus_scope == PERF_PMU_SCOPE_PKG || rapl_pmus_scope == PERF_PMU_SCOPE_DIE) { 394 - /* only look at RAPL package events */ 395 - if (event->attr.type != rapl_pmus_pkg->pmu.type) 396 - return -ENOENT; 397 - 398 390 cfg = array_index_nospec((long)cfg, NR_RAPL_PKG_DOMAINS + 1); 399 391 if (!cfg || cfg >= NR_RAPL_PKG_DOMAINS + 1) 400 392 return -EINVAL; ··· 398 398 bit = cfg - 1; 399 399 event->hw.event_base = rapl_model->rapl_pkg_msrs[bit].msr; 400 400 } else if (rapl_pmus_scope == PERF_PMU_SCOPE_CORE) { 401 - /* only look at RAPL core events */ 402 - if (event->attr.type != rapl_pmus_core->pmu.type) 403 - return -ENOENT; 404 - 405 401 cfg = array_index_nospec((long)cfg, NR_RAPL_CORE_DOMAINS + 1); 406 402 if (!cfg || cfg >= NR_RAPL_PKG_DOMAINS + 1) 407 403 return -EINVAL;
+2 -1
arch/x86/include/asm/msr-index.h
··· 395 395 #define MSR_IA32_PASID_VALID BIT_ULL(31) 396 396 397 397 /* DEBUGCTLMSR bits (others vary by model): */ 398 - #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 398 + #define DEBUGCTLMSR_LBR_BIT 0 /* last branch recording */ 399 + #define DEBUGCTLMSR_LBR (1UL << DEBUGCTLMSR_LBR_BIT) 399 400 #define DEBUGCTLMSR_BTF_SHIFT 1 400 401 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 401 402 #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
+25 -3
arch/x86/include/asm/perf_event.h
··· 188 188 * detection/enumeration details: 189 189 */ 190 190 #define ARCH_PERFMON_EXT_LEAF 0x00000023 191 - #define ARCH_PERFMON_EXT_UMASK2 0x1 192 - #define ARCH_PERFMON_EXT_EQ 0x2 193 - #define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1 194 191 #define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 192 + 193 + union cpuid35_eax { 194 + struct { 195 + unsigned int leaf0:1; 196 + /* Counters Sub-Leaf */ 197 + unsigned int cntr_subleaf:1; 198 + /* Auto Counter Reload Sub-Leaf */ 199 + unsigned int acr_subleaf:1; 200 + /* Events Sub-Leaf */ 201 + unsigned int events_subleaf:1; 202 + unsigned int reserved:28; 203 + } split; 204 + unsigned int full; 205 + }; 206 + 207 + union cpuid35_ebx { 208 + struct { 209 + /* UnitMask2 Supported */ 210 + unsigned int umask2:1; 211 + /* EQ-bit Supported */ 212 + unsigned int eq:1; 213 + unsigned int reserved:30; 214 + } split; 215 + unsigned int full; 216 + }; 195 217 196 218 /* 197 219 * Intel Architectural LBR CPUID detection/enumeration details: