tjh.dev / kernel
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Merge tag 'drm-fixes-2023-01-20' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Just a pretty regular week for this stage of things, amdgpu and i915,
along with some msm and misc others.

fb-helper:
- switcheroo fix

msm:
- kexec shutdown fix
- fix potential double free

i915:
- Reject display plane with height == 0
- re-disable RC6p on Sandy Bridge
- Fix hugepages' selftest
- DG2 hw workarounds
- switcheroo fix

vc4:
- fix a memory leak

panfrost:
- Kconfig fix

amdgpu:
- Fix display scaling
- Fix RN/CZN power reporting on some firmware versions
- Colorspace fixes
- Fix resource freeing in error case in CS IOCTL
- Fix warning on driver unload
- GC11 fixes
- DCN 3.1.4/5 S/G display workarounds"

* tag 'drm-fixes-2023-01-20' of git://anongit.freedesktop.org/drm/drm: (24 commits)
drm/amd/display: disable S/G display on DCN 3.1.4
drm/amd/display: disable S/G display on DCN 3.1.5
drm/amdgpu: allow multipipe policy on ASICs with one MEC
drm/amdgpu: correct MEC number for gfx11 APUs
drm/amd/display: fix issues with driver unload
drm/amdgpu: fix amdgpu_job_free_resources v2
drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrix
drm/amd/display: Calculate output_color_space after pixel encoding adjustment
drm/amdgpu: fix cleaning up reserved VMID on release
drm/amdgpu: Correct the power calcultion for Renior/Cezanne.
drm/amd/display: Fix set scaling doesn's work
drm/i915: Remove unused variable
drm/i915/dg2: Introduce Wa_18019271663
drm/i915/dg2: Introduce Wa_18018764978
drm/fb-helper: Set framebuffer for vga-switcheroo clients
drm/i915: Allow switching away via vga-switcheroo if uninitialized
drm/i915/selftests: Unwind hugepages to drop wakeref on error
drm/i915: re-disable RC6p on Sandy Bridge
drm/panfrost: fix GENERIC_ATOMIC64 dependency
drm/i915/display: Check source height is > 0
...

Linus Torvalds ff83fec8 35929dae

+92 -42
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
··· 156 156 return amdgpu_compute_multipipe == 1; 157 157 } 158 158 159 + if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)) 160 + return true; 161 + 159 162 /* FIXME: spreading the queues across pipes causes perf regressions 160 163 * on POLARIS11 compute workloads */ 161 164 if (adev->asic_type == CHIP_POLARIS11)
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
··· 497 497 !--id_mgr->reserved_use_count) { 498 498 /* give the reserved ID back to normal round robin */ 499 499 list_add(&id_mgr->reserved->list, &id_mgr->ids_lru); 500 + id_mgr->reserved = NULL; 500 501 } 501 502 vm->reserved_vmid[vmhub] = false; 502 503 mutex_unlock(&id_mgr->lock);
+8 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
··· 161 161 struct dma_fence *f; 162 162 unsigned i; 163 163 164 - /* use sched fence if available */ 165 - f = job->base.s_fence ? &job->base.s_fence->finished : &job->hw_fence; 164 + /* Check if any fences where initialized */ 165 + if (job->base.s_fence && job->base.s_fence->finished.ops) 166 + f = &job->base.s_fence->finished; 167 + else if (job->hw_fence.ops) 168 + f = &job->hw_fence; 169 + else 170 + f = NULL; 171 + 166 172 for (i = 0; i < job->num_ibs; ++i) 167 173 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 168 174 }
+9 -2
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 1287 1287 1288 1288 switch (adev->ip_versions[GC_HWIP][0]) { 1289 1289 case IP_VERSION(11, 0, 0): 1290 - case IP_VERSION(11, 0, 1): 1291 1290 case IP_VERSION(11, 0, 2): 1292 1291 case IP_VERSION(11, 0, 3): 1293 - case IP_VERSION(11, 0, 4): 1294 1292 adev->gfx.me.num_me = 1; 1295 1293 adev->gfx.me.num_pipe_per_me = 1; 1296 1294 adev->gfx.me.num_queue_per_pipe = 1; 1297 1295 adev->gfx.mec.num_mec = 2; 1296 + adev->gfx.mec.num_pipe_per_mec = 4; 1297 + adev->gfx.mec.num_queue_per_pipe = 4; 1298 + break; 1299 + case IP_VERSION(11, 0, 1): 1300 + case IP_VERSION(11, 0, 4): 1301 + adev->gfx.me.num_me = 1; 1302 + adev->gfx.me.num_pipe_per_me = 1; 1303 + adev->gfx.me.num_queue_per_pipe = 1; 1304 + adev->gfx.mec.num_mec = 1; 1298 1305 adev->gfx.mec.num_pipe_per_mec = 4; 1299 1306 adev->gfx.mec.num_queue_per_pipe = 4; 1300 1307 break;
+4 -10
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 1503 1503 case IP_VERSION(3, 0, 1): 1504 1504 case IP_VERSION(3, 1, 2): 1505 1505 case IP_VERSION(3, 1, 3): 1506 - case IP_VERSION(3, 1, 4): 1507 - case IP_VERSION(3, 1, 5): 1508 1506 case IP_VERSION(3, 1, 6): 1509 1507 init_data.flags.gpu_vm_support = true; 1510 1508 break; ··· 1726 1728 if (adev->dm.vblank_control_workqueue) { 1727 1729 destroy_workqueue(adev->dm.vblank_control_workqueue); 1728 1730 adev->dm.vblank_control_workqueue = NULL; 1729 - } 1730 - 1731 - for (i = 0; i < adev->dm.display_indexes_num; i++) { 1732 - drm_encoder_cleanup(&adev->dm.mst_encoders[i].base); 1733 1731 } 1734 1732 1735 1733 amdgpu_dm_destroy_drm_device(&adev->dm); ··· 5305 5311 5306 5312 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5307 5313 5308 - stream->output_color_space = get_output_color_space(timing_out); 5309 - 5310 5314 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 5311 5315 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 5312 5316 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { ··· 5315 5323 adjust_colour_depth_from_display_info(timing_out, info); 5316 5324 } 5317 5325 } 5326 + 5327 + stream->output_color_space = get_output_color_space(timing_out); 5318 5328 } 5319 5329 5320 5330 static void fill_audio_info(struct audio_info *audio_info, ··· 9524 9530 goto fail; 9525 9531 } 9526 9532 9527 - if (dm_old_con_state->abm_level != 9528 - dm_new_con_state->abm_level) 9533 + if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 9534 + dm_old_con_state->scaling != dm_new_con_state->scaling) 9529 9535 new_crtc_state->connectors_changed = true; 9530 9536 } 9531 9537
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 468 468 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 469 469 { 470 470 drm_encoder_cleanup(encoder); 471 - kfree(encoder); 472 471 } 473 472 474 473 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
+2 -2
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
··· 90 90 { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, 91 91 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, 92 92 { COLOR_SPACE_YCBCR2020_TYPE, 93 - { 0x1000, 0xF149, 0xFEB7, 0x0000, 0x0868, 0x15B2, 94 - 0x01E6, 0x0000, 0xFB88, 0xF478, 0x1000, 0x0000} }, 93 + { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868, 0x15B2, 94 + 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} }, 95 95 { COLOR_SPACE_YCBCR709_BLACK_TYPE, 96 96 { 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 97 97 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, 0x1000} },
+6 -1
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
··· 1171 1171 int ret = 0; 1172 1172 uint32_t apu_percent = 0; 1173 1173 uint32_t dgpu_percent = 0; 1174 + struct amdgpu_device *adev = smu->adev; 1174 1175 1175 1176 1176 1177 ret = smu_cmn_get_metrics_table(smu, ··· 1197 1196 *value = metrics->AverageUvdActivity / 100; 1198 1197 break; 1199 1198 case METRICS_AVERAGE_SOCKETPOWER: 1200 - *value = (metrics->CurrentSocketPower << 8) / 1000; 1199 + if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) && (adev->pm.fw_version >= 0x40000f)) || 1200 + ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0)) && (adev->pm.fw_version >= 0x373200))) 1201 + *value = metrics->CurrentSocketPower << 8; 1202 + else 1203 + *value = (metrics->CurrentSocketPower << 8) / 1000; 1201 1204 break; 1202 1205 case METRICS_TEMPERATURE_EDGE: 1203 1206 *value = (metrics->GfxTemperature / 100) *
+7
drivers/gpu/drm/drm_fb_helper.c
··· 30 30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 31 31 32 32 #include <linux/console.h> 33 + #include <linux/pci.h> 33 34 #include <linux/sysrq.h> 35 + #include <linux/vga_switcheroo.h> 34 36 35 37 #include <drm/drm_atomic.h> 36 38 #include <drm/drm_drv.h> ··· 1911 1909 return ret; 1912 1910 1913 1911 strcpy(fb_helper->fb->comm, "[fbcon]"); 1912 + 1913 + /* Set the fb info for vgaswitcheroo clients. Does nothing otherwise. */ 1914 + if (dev_is_pci(dev->dev)) 1915 + vga_switcheroo_client_fb_set(to_pci_dev(dev->dev), fb_helper->info); 1916 + 1914 1917 return 0; 1915 1918 } 1916 1919
+1 -1
drivers/gpu/drm/i915/display/skl_universal_plane.c
··· 1627 1627 u32 offset; 1628 1628 int ret; 1629 1629 1630 - if (w > max_width || w < min_width || h > max_height) { 1630 + if (w > max_width || w < min_width || h > max_height || h < 1) { 1631 1631 drm_dbg_kms(&dev_priv->drm, 1632 1632 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", 1633 1633 w, h, min_width, max_width, max_height);
+4 -4
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
··· 1847 1847 I915_SHRINK_ACTIVE); 1848 1848 i915_vma_unpin(vma); 1849 1849 if (err) 1850 - goto out_put; 1850 + goto out_wf; 1851 1851 1852 1852 /* 1853 1853 * Now that the pages are *unpinned* shrinking should invoke ··· 1863 1863 pr_err("unexpected pages mismatch, should_swap=%s\n", 1864 1864 str_yes_no(should_swap)); 1865 1865 err = -EINVAL; 1866 - goto out_put; 1866 + goto out_wf; 1867 1867 } 1868 1868 1869 1869 if (should_swap == (obj->mm.page_sizes.sg || obj->mm.page_sizes.phys)) { 1870 1870 pr_err("unexpected residual page-size bits, should_swap=%s\n", 1871 1871 str_yes_no(should_swap)); 1872 1872 err = -EINVAL; 1873 - goto out_put; 1873 + goto out_wf; 1874 1874 } 1875 1875 1876 1876 err = i915_vma_pin(vma, 0, 0, flags); 1877 1877 if (err) 1878 - goto out_put; 1878 + goto out_wf; 1879 1879 1880 1880 while (n--) { 1881 1881 err = cpu_check(obj, n, 0xdeadbeaf);
+7 -3
drivers/gpu/drm/i915/gt/intel_gt_regs.h
··· 429 429 #define RC_OP_FLUSH_ENABLE (1 << 0) 430 430 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) 431 431 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 432 - #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) 433 - #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) 434 - #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) 432 + #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 433 + #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) 434 + #define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) 435 + #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) 435 436 436 437 #define GEN7_GT_MODE _MMIO(0x7008) 437 438 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) ··· 457 456 458 457 #define GEN8_L3CNTLREG _MMIO(0x7034) 459 458 #define GEN8_ERRDETBCTRL (1 << 9) 459 + 460 + #define PSS_MODE2 _MMIO(0x703c) 461 + #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 460 462 461 463 #define GEN7_SC_INSTDONE _MMIO(0x7100) 462 464 #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
+9 -1
drivers/gpu/drm/i915/gt/intel_workarounds.c
··· 771 771 772 772 /* Wa_14014947963:dg2 */ 773 773 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 774 - IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 774 + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 775 775 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 776 + 777 + /* Wa_18018764978:dg2 */ 778 + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || 779 + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 780 + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 776 781 777 782 /* Wa_15010599737:dg2 */ 778 783 wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 784 + 785 + /* Wa_18019271663:dg2 */ 786 + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 779 787 } 780 788 781 789 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
+1 -4
drivers/gpu/drm/i915/i915_driver.c
··· 1069 1069 */ 1070 1070 static void i915_driver_lastclose(struct drm_device *dev) 1071 1071 { 1072 - struct drm_i915_private *i915 = to_i915(dev); 1073 - 1074 1072 intel_fbdev_restore_mode(dev); 1075 1073 1076 - if (HAS_DISPLAY(i915)) 1077 - vga_switcheroo_process_delayed_switch(); 1074 + vga_switcheroo_process_delayed_switch(); 1078 1075 } 1079 1076 1080 1077 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
+2 -1
drivers/gpu/drm/i915/i915_pci.c
··· 423 423 .has_coherent_ggtt = true, \ 424 424 .has_llc = 1, \ 425 425 .has_rc6 = 1, \ 426 - .has_rc6p = 1, \ 426 + /* snb does support rc6p, but enabling it causes various issues */ \ 427 + .has_rc6p = 0, \ 427 428 .has_rps = true, \ 428 429 .dma_mask_size = 40, \ 429 430 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
+5 -1
drivers/gpu/drm/i915/i915_switcheroo.c
··· 19 19 dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n"); 20 20 return; 21 21 } 22 + if (!HAS_DISPLAY(i915)) { 23 + dev_err(&pdev->dev, "Device state not initialized, aborting switch.\n"); 24 + return; 25 + } 22 26 23 27 if (state == VGA_SWITCHEROO_ON) { 24 28 drm_info(&i915->drm, "switched on\n"); ··· 48 44 * locking inversion with the driver load path. And the access here is 49 45 * completely racy anyway. So don't bother with locking for now. 50 46 */ 51 - return i915 && atomic_read(&i915->drm.open_count) == 0; 47 + return i915 && HAS_DISPLAY(i915) && atomic_read(&i915->drm.open_count) == 0; 52 48 } 53 49 54 50 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
+3 -2
drivers/gpu/drm/msm/adreno/adreno_device.c
··· 551 551 return 0; 552 552 } 553 553 554 + static int adreno_system_suspend(struct device *dev); 554 555 static void adreno_unbind(struct device *dev, struct device *master, 555 556 void *data) 556 557 { 557 558 struct msm_drm_private *priv = dev_get_drvdata(master); 558 559 struct msm_gpu *gpu = dev_to_gpu(dev); 559 560 560 - pm_runtime_force_suspend(dev); 561 + WARN_ON_ONCE(adreno_system_suspend(dev)); 561 562 gpu->funcs->destroy(gpu); 562 563 563 564 priv->gpu_pdev = NULL; ··· 610 609 611 610 static void adreno_shutdown(struct platform_device *pdev) 612 611 { 613 - pm_runtime_force_suspend(&pdev->dev); 612 + WARN_ON_ONCE(adreno_system_suspend(&pdev->dev)); 614 613 } 615 614 616 615 static const struct of_device_id dt_match[] = {
+4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
··· 352 352 /* Ensure string is null terminated: */ 353 353 str[len] = '\0'; 354 354 355 + mutex_lock(&gpu->lock); 356 + 355 357 if (param == MSM_PARAM_COMM) { 356 358 paramp = &ctx->comm; 357 359 } else { ··· 362 360 363 361 kfree(*paramp); 364 362 *paramp = str; 363 + 364 + mutex_unlock(&gpu->lock); 365 365 366 366 return 0; 367 367 }
+2
drivers/gpu/drm/msm/msm_gpu.c
··· 335 335 struct msm_file_private *ctx = submit->queue->ctx; 336 336 struct task_struct *task; 337 337 338 + WARN_ON(!mutex_is_locked(&submit->gpu->lock)); 339 + 338 340 /* Note that kstrdup will return NULL if argument is NULL: */ 339 341 *comm = kstrdup(ctx->comm, GFP_KERNEL); 340 342 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL);
+10 -2
drivers/gpu/drm/msm/msm_gpu.h
··· 376 376 */ 377 377 int sysprof; 378 378 379 - /** comm: Overridden task comm, see MSM_PARAM_COMM */ 379 + /** 380 + * comm: Overridden task comm, see MSM_PARAM_COMM 381 + * 382 + * Accessed under msm_gpu::lock 383 + */ 380 384 char *comm; 381 385 382 - /** cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE */ 386 + /** 387 + * cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE 388 + * 389 + * Accessed under msm_gpu::lock 390 + */ 383 391 char *cmdline; 384 392 385 393 /**
+2 -1
drivers/gpu/drm/panfrost/Kconfig
··· 3 3 config DRM_PANFROST 4 4 tristate "Panfrost (DRM support for ARM Mali Midgard/Bifrost GPUs)" 5 5 depends on DRM 6 - depends on ARM || ARM64 || (COMPILE_TEST && !GENERIC_ATOMIC64) 6 + depends on ARM || ARM64 || COMPILE_TEST 7 + depends on !GENERIC_ATOMIC64 # for IOMMU_IO_PGTABLE_LPAE 7 8 depends on MMU 8 9 select DRM_SCHED 9 10 select IOMMU_SUPPORT
+2 -4
drivers/gpu/drm/vc4/vc4_bo.c
··· 179 179 bo->validated_shader = NULL; 180 180 } 181 181 182 + mutex_destroy(&bo->madv_lock); 182 183 drm_gem_dma_free(&bo->base); 183 184 } 184 185 ··· 395 394 { 396 395 struct vc4_dev *vc4 = to_vc4_dev(dev); 397 396 struct vc4_bo *bo; 398 - int ret; 399 397 400 398 if (WARN_ON_ONCE(vc4->is_vc5)) 401 399 return ERR_PTR(-ENODEV); ··· 406 406 bo->madv = VC4_MADV_WILLNEED; 407 407 refcount_set(&bo->usecnt, 0); 408 408 409 - ret = drmm_mutex_init(dev, &bo->madv_lock); 410 - if (ret) 411 - return ERR_PTR(ret); 409 + mutex_init(&bo->madv_lock); 412 410 413 411 mutex_lock(&vc4->bo_lock); 414 412 bo->label = VC4_BO_TYPE_KERNEL;