drm/amd/display: Revert regression · tjh.dev/kernel@ffe0fcb

-10

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 2300 2300 enum surface_update_type update_type, 2301 2301 struct dc_state *context) 2302 2302 { 2303 - bool mpcc_disconnected = false; 2304 2303 int i, j; 2305 2304 struct pipe_ctx *top_pipe_to_program = NULL; 2306 2305 ··· 2328 2329 dc->hwss.prepare_bandwidth(dc, context); 2329 2330 2330 2331 context_clock_trace(dc, context); 2331 - } 2332 - 2333 - if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock && 2334 - dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){ 2335 - dc->hwss.interdependent_update_lock(dc, context, true); 2336 - mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context); 2337 - dc->hwss.interdependent_update_lock(dc, context, false); 2338 - if (mpcc_disconnected) 2339 - dc->hwss.wait_for_pending_cleared(dc, context); 2340 2332 } 2341 2333 2342 2334 for (j = 0; j < dc->res_pool->pipe_count; j++) {

-114

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

··· 1624 1624 } 1625 1625 } 1626 1626 1627 - bool dcn20_disconnect_pipes( 1628 - struct dc *dc, 1629 - struct dc_state *context) 1630 - { 1631 - int i; 1632 - struct dce_hwseq *hws = dc->hwseq; 1633 - bool mpcc_disconnected = false; 1634 - DC_LOGGER_INIT(dc->ctx->logger); 1635 - 1636 - /* Set pipe update flags and lock pipes */ 1637 - for (i = 0; i < dc->res_pool->pipe_count; i++) 1638 - dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1639 - &context->res_ctx.pipe_ctx[i]); 1640 - 1641 - if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1642 - /* OTG blank before disabling all front ends */ 1643 - for (i = 0; i < dc->res_pool->pipe_count; i++) { 1644 - if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1645 - && !context->res_ctx.pipe_ctx[i].top_pipe 1646 - && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1647 - && context->res_ctx.pipe_ctx[i].stream) { 1648 - hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1649 - } 1650 - } 1651 - 1652 - /* Disconnect mpcc */ 1653 - for (i = 0; i < dc->res_pool->pipe_count; i++) { 1654 - if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) { 1655 - hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1656 - DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1657 - mpcc_disconnected = true; 1658 - } 1659 - } 1660 - } 1661 - 1662 - if (mpcc_disconnected) { 1663 - for (i = 0; i < dc->res_pool->pipe_count; i++) { 1664 - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1665 - struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1666 - struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1667 - struct hubp *hubp = pipe_ctx->plane_res.hubp; 1668 - 1669 - if (!pipe_ctx || !plane_state || !pipe_ctx->stream) 1670 - continue; 1671 - 1672 - // Only update scaler and viewport here if we lose a pipe split. 1673 - // This is to prevent half the screen from being black when we 1674 - // unlock after disconnecting MPCC. 1675 - if (!(old_pipe && !pipe_ctx->top_pipe && 1676 - !pipe_ctx->bottom_pipe && old_pipe->bottom_pipe)) 1677 - continue; 1678 - 1679 - if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) { 1680 - if (pipe_ctx->update_flags.bits.scaler || 1681 - plane_state->update_flags.bits.scaling_change || 1682 - plane_state->update_flags.bits.position_change || 1683 - plane_state->update_flags.bits.per_pixel_alpha_change || 1684 - pipe_ctx->stream->update_flags.bits.scaling) { 1685 - 1686 - pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1687 - ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP); 1688 - /* scaler configuration */ 1689 - pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1690 - pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1691 - } 1692 - 1693 - if (pipe_ctx->update_flags.bits.viewport || 1694 - (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1695 - (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1696 - (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1697 - 1698 - hubp->funcs->mem_program_viewport( 1699 - hubp, 1700 - &pipe_ctx->plane_res.scl_data.viewport, 1701 - &pipe_ctx->plane_res.scl_data.viewport_c); 1702 - } 1703 - } 1704 - } 1705 - } 1706 - return mpcc_disconnected; 1707 - } 1708 - 1709 - void dcn20_wait_for_pending_cleared(struct dc *dc, 1710 - struct dc_state *context) 1711 - { 1712 - struct pipe_ctx *pipe_ctx; 1713 - struct timing_generator *tg; 1714 - int i; 1715 - 1716 - for (i = 0; i < dc->res_pool->pipe_count; i++) { 1717 - pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1718 - tg = pipe_ctx->stream_res.tg; 1719 - 1720 - /* 1721 - * Only wait for top pipe's tg penindg bit 1722 - * Also skip if pipe is disabled. 1723 - */ 1724 - if (pipe_ctx->top_pipe || 1725 - !pipe_ctx->stream || !pipe_ctx->plane_state || 1726 - !tg->funcs->is_tg_enabled(tg)) 1727 - continue; 1728 - 1729 - /* 1730 - * Wait for VBLANK then VACTIVE to ensure we get VUPDATE. 1731 - * For some reason waiting for OTG_UPDATE_PENDING cleared 1732 - * seems to not trigger the update right away, and if we 1733 - * lock again before VUPDATE then we don't get a separated 1734 - * operation. 1735 - */ 1736 - pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1737 - pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1738 - } 1739 - } 1740 - 1741 1627 void dcn20_program_front_end_for_ctx( 1742 1628 struct dc *dc, 1743 1629 struct dc_state *context)

-7

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

··· 131 131 int dcn20_init_sys_ctx(struct dce_hwseq *hws, 132 132 struct dc *dc, 133 133 struct dc_phy_addr_space_config *pa_config); 134 - bool dcn20_disconnect_pipes( 135 - struct dc *dc, 136 - struct dc_state *context); 137 - 138 - void dcn20_wait_for_pending_cleared(struct dc *dc, 139 - struct dc_state *context); 140 - 141 134 142 135 #ifndef TRIM_FSFT 143 136 bool dcn20_optimize_timing_for_fsft(struct dc *dc,

-2

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c

··· 34 34 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 35 35 .apply_ctx_for_surface = NULL, 36 36 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, 37 - .disconnect_pipes = dcn20_disconnect_pipes, 38 - .wait_for_pending_cleared = dcn20_wait_for_pending_cleared, 39 37 .post_unlock_program_front_end = dcn20_post_unlock_program_front_end, 40 38 .update_plane_addr = dcn20_update_plane_addr, 41 39 .update_dchub = dcn10_update_dchub,

-2

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c

··· 35 35 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 36 36 .apply_ctx_for_surface = NULL, 37 37 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, 38 - .disconnect_pipes = dcn20_disconnect_pipes, 39 - .wait_for_pending_cleared = dcn20_wait_for_pending_cleared, 40 38 .post_unlock_program_front_end = dcn20_post_unlock_program_front_end, 41 39 .update_plane_addr = dcn20_update_plane_addr, 42 40 .update_dchub = dcn10_update_dchub,

-2

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c

··· 35 35 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 36 36 .apply_ctx_for_surface = NULL, 37 37 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, 38 - .disconnect_pipes = dcn20_disconnect_pipes, 39 - .wait_for_pending_cleared = dcn20_wait_for_pending_cleared, 40 38 .post_unlock_program_front_end = dcn20_post_unlock_program_front_end, 41 39 .update_plane_addr = dcn20_update_plane_addr, 42 40 .update_dchub = dcn10_update_dchub,

-4

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

··· 67 67 int num_planes, struct dc_state *context); 68 68 void (*program_front_end_for_ctx)(struct dc *dc, 69 69 struct dc_state *context); 70 - bool (*disconnect_pipes)(struct dc *dc, 71 - struct dc_state *context); 72 - void (*wait_for_pending_cleared)(struct dc *dc, 73 - struct dc_state *context); 74 70 void (*post_unlock_program_front_end)(struct dc *dc, 75 71 struct dc_state *context); 76 72 void (*update_plane_addr)(const struct dc *dc,

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