Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-next-2025-08-08' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"This is the fixes that built up in the merge window, mostly amdgpu and
xe with one i915 display fix, seems like things are pretty good for
rc1.
i915:
- DP LPFS fixes
xe:
- SRIOV: PF fixes and removal of need of module param
- Fix driver unbind around Devcoredump
- Mark xe driver as BROKEN if kernel page size is not 4kB
amdgpu:
- GC 9.5.0 fixes
- SMU fix
- DCE 6 DC fixes
- mmhub client ID fixes
- VRR fix
- Backlight fix
- UserQ fix
- Legacy reset fix
- Misc fixes
amdkfd:
- CRIU fix
- Debugfs fix"
* tag 'drm-next-2025-08-08' of https://gitlab.freedesktop.org/drm/kernel: (28 commits)
drm/amdgpu: add missing vram lost check for LEGACY RESET
drm/amdgpu/discovery: fix fw based ip discovery
drm/amdkfd: Destroy KFD debugfs after destroy KFD wq
amdgpu/amdgpu_discovery: increase timeout limit for IFWI init
drm/amdgpu: Update SDMA firmware version check for user queue support
drm/amdgpu: Add NULL check for asic_funcs
drm/amd/display: Revert "drm/amd/display: Fix AMDGPU_MAX_BL_LEVEL value"
drm/amd/display: fix a Null pointer dereference vulnerability
drm/amd/display: Add primary plane to commits for correct VRR handling
drm/amdgpu: update mmhub 3.3 client id mappings
drm/amdgpu: update mmhub 3.0.1 client id mappings
drm/amdgpu: Retain job->vm in amdgpu_job_prepare_job
drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming.
drm/amd/display: Don't overwrite dce60_clk_mgr
drm/amdkfd: Fix checkpoint-restore on multi-xcc
drm/amd: Restore cached manual clock settings during resume
drm/amd: Restore cached power limit during resume
drm/amdgpu: Update external revid for GC v9.5.0
drm/amdgpu: Update supported modes for GC v9.5.0
Mark xe driver as BROKEN if kernel page size is not 4kB
...
+456
-141
+3
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+3
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
2570
2570
2571
2571
adev->firmware.gpu_info_fw = NULL;
2572
2572
2573
-
if (adev->mman.discovery_bin)
2574
-
return 0;
2575
-
2576
2573
switch (adev->asic_type) {
2577
2574
default:
2578
2575
return 0;
···
2591
2594
chip_name = "arcturus";
2592
2595
break;
2593
2596
case CHIP_NAVI12:
2597
+
if (adev->mman.discovery_bin)
2598
+
return 0;
2594
2599
chip_name = "navi12";
2595
2600
break;
2596
2601
}
···
3270
3271
* always assumed to be lost.
3271
3272
*/
3272
3273
switch (amdgpu_asic_reset_method(adev)) {
3274
+
case AMD_RESET_METHOD_LEGACY:
3273
3275
case AMD_RESET_METHOD_LINK:
3274
3276
case AMD_RESET_METHOD_BACO:
3275
3277
case AMD_RESET_METHOD_MODE1:
+41
-35
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+41
-35
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
···
276
276
u32 msg;
277
277
278
278
if (!amdgpu_sriov_vf(adev)) {
279
-
/* It can take up to a second for IFWI init to complete on some dGPUs,
279
+
/* It can take up to two second for IFWI init to complete on some dGPUs,
280
280
* but generally it should be in the 60-100ms range. Normally this starts
281
281
* as soon as the device gets power so by the time the OS loads this has long
282
282
* completed. However, when a card is hotplugged via e.g., USB4, we need to
···
284
284
* continue.
285
285
*/
286
286
287
-
for (i = 0; i < 1000; i++) {
287
+
for (i = 0; i < 2000; i++) {
288
288
msg = RREG32(mmMP0_SMN_C2PMSG_33);
289
289
if (msg & 0x80000000)
290
290
break;
···
2555
2555
2556
2556
switch (adev->asic_type) {
2557
2557
case CHIP_VEGA10:
2558
-
case CHIP_VEGA12:
2559
-
case CHIP_RAVEN:
2560
-
case CHIP_VEGA20:
2561
-
case CHIP_ARCTURUS:
2562
-
case CHIP_ALDEBARAN:
2563
-
/* this is not fatal. We have a fallback below
2564
-
* if the new firmwares are not present. some of
2565
-
* this will be overridden below to keep things
2566
-
* consistent with the current behavior.
2558
+
/* This is not fatal. We only need the discovery
2559
+
* binary for sysfs. We don't need it for a
2560
+
* functional system.
2567
2561
*/
2568
-
r = amdgpu_discovery_reg_base_init(adev);
2569
-
if (!r) {
2570
-
amdgpu_discovery_harvest_ip(adev);
2571
-
amdgpu_discovery_get_gfx_info(adev);
2572
-
amdgpu_discovery_get_mall_info(adev);
2573
-
amdgpu_discovery_get_vcn_info(adev);
2574
-
}
2575
-
break;
2576
-
default:
2577
-
r = amdgpu_discovery_reg_base_init(adev);
2578
-
if (r) {
2579
-
drm_err(&adev->ddev, "discovery failed: %d\n", r);
2580
-
return r;
2581
-
}
2582
-
2583
-
amdgpu_discovery_harvest_ip(adev);
2584
-
amdgpu_discovery_get_gfx_info(adev);
2585
-
amdgpu_discovery_get_mall_info(adev);
2586
-
amdgpu_discovery_get_vcn_info(adev);
2587
-
break;
2588
-
}
2589
-
2590
-
switch (adev->asic_type) {
2591
-
case CHIP_VEGA10:
2562
+
amdgpu_discovery_init(adev);
2592
2563
vega10_reg_base_init(adev);
2593
2564
adev->sdma.num_instances = 2;
2594
2565
adev->gmc.num_umc = 4;
···
2582
2611
adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
2583
2612
break;
2584
2613
case CHIP_VEGA12:
2614
+
/* This is not fatal. We only need the discovery
2615
+
* binary for sysfs. We don't need it for a
2616
+
* functional system.
2617
+
*/
2618
+
amdgpu_discovery_init(adev);
2585
2619
vega10_reg_base_init(adev);
2586
2620
adev->sdma.num_instances = 2;
2587
2621
adev->gmc.num_umc = 4;
···
2609
2633
adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
2610
2634
break;
2611
2635
case CHIP_RAVEN:
2636
+
/* This is not fatal. We only need the discovery
2637
+
* binary for sysfs. We don't need it for a
2638
+
* functional system.
2639
+
*/
2640
+
amdgpu_discovery_init(adev);
2612
2641
vega10_reg_base_init(adev);
2613
2642
adev->sdma.num_instances = 1;
2614
2643
adev->vcn.num_vcn_inst = 1;
···
2655
2674
}
2656
2675
break;
2657
2676
case CHIP_VEGA20:
2677
+
/* This is not fatal. We only need the discovery
2678
+
* binary for sysfs. We don't need it for a
2679
+
* functional system.
2680
+
*/
2681
+
amdgpu_discovery_init(adev);
2658
2682
vega20_reg_base_init(adev);
2659
2683
adev->sdma.num_instances = 2;
2660
2684
adev->gmc.num_umc = 8;
···
2683
2697
adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2684
2698
break;
2685
2699
case CHIP_ARCTURUS:
2700
+
/* This is not fatal. We only need the discovery
2701
+
* binary for sysfs. We don't need it for a
2702
+
* functional system.
2703
+
*/
2704
+
amdgpu_discovery_init(adev);
2686
2705
arct_reg_base_init(adev);
2687
2706
adev->sdma.num_instances = 8;
2688
2707
adev->vcn.num_vcn_inst = 2;
···
2716
2725
adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
2717
2726
break;
2718
2727
case CHIP_ALDEBARAN:
2728
+
/* This is not fatal. We only need the discovery
2729
+
* binary for sysfs. We don't need it for a
2730
+
* functional system.
2731
+
*/
2732
+
amdgpu_discovery_init(adev);
2719
2733
aldebaran_reg_base_init(adev);
2720
2734
adev->sdma.num_instances = 5;
2721
2735
adev->vcn.num_vcn_inst = 2;
···
2747
2751
adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
2748
2752
break;
2749
2753
default:
2754
+
r = amdgpu_discovery_reg_base_init(adev);
2755
+
if (r) {
2756
+
drm_err(&adev->ddev, "discovery failed: %d\n", r);
2757
+
return r;
2758
+
}
2759
+
2760
+
amdgpu_discovery_harvest_ip(adev);
2761
+
amdgpu_discovery_get_gfx_info(adev);
2762
+
amdgpu_discovery_get_mall_info(adev);
2763
+
amdgpu_discovery_get_vcn_info(adev);
2750
2764
break;
2751
2765
}
2752
2766
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
···
365
365
dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r);
366
366
goto error;
367
367
}
368
-
/*
369
-
* The VM structure might be released after the VMID is
370
-
* assigned, we had multiple problems with people trying to use
371
-
* the VM pointer so better set it to NULL.
372
-
*/
373
-
if (!fence)
374
-
job->vm = NULL;
375
368
return fence;
376
369
}
377
370
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
···
55
55
56
56
bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev)
57
57
{
58
-
if (amdgpu_sriov_vf(adev) || !adev->asic_funcs->get_pcie_replay_count ||
58
+
if (amdgpu_sriov_vf(adev) || !adev->asic_funcs ||
59
+
!adev->asic_funcs->get_pcie_replay_count ||
59
60
(!adev->nbio.funcs || !adev->nbio.funcs->get_pcie_replay_count))
60
61
return false;
61
62
+4
-1
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+4
-1
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
···
227
227
uint16_t *nps_modes)
228
228
{
229
229
struct amdgpu_device *adev = xcp_mgr->adev;
230
+
uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
230
231
231
232
if (!num_xcp || !nps_modes || !(xcp_mgr->supp_xcp_modes & BIT(px_mode)))
232
233
return -EINVAL;
···
251
250
*num_xcp = 4;
252
251
*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
253
252
BIT(AMDGPU_NPS4_PARTITION_MODE);
253
+
if (gc_ver == IP_VERSION(9, 5, 0))
254
+
*nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE);
254
255
break;
255
256
case AMDGPU_CPX_PARTITION_MODE:
256
257
*num_xcp = NUM_XCC(adev->gfx.xcc_mask);
257
258
*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
258
259
BIT(AMDGPU_NPS4_PARTITION_MODE);
259
-
if (amdgpu_sriov_vf(adev))
260
+
if (gc_ver == IP_VERSION(9, 5, 0))
260
261
*nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE);
261
262
break;
262
263
default:
+32
-25
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+32
-25
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
···
36
36
37
37
static const char *mmhub_client_ids_v3_0_1[][2] = {
38
38
[0][0] = "VMC",
39
+
[1][0] = "ISPXT",
40
+
[2][0] = "ISPIXT",
39
41
[4][0] = "DCEDMC",
40
42
[5][0] = "DCEVGA",
41
43
[6][0] = "MP0",
42
44
[7][0] = "MP1",
43
-
[8][0] = "MPIO",
44
-
[16][0] = "HDP",
45
-
[17][0] = "LSDMA",
46
-
[18][0] = "JPEG",
47
-
[19][0] = "VCNU0",
48
-
[21][0] = "VSCH",
49
-
[22][0] = "VCNU1",
50
-
[23][0] = "VCN1",
51
-
[32+20][0] = "VCN0",
52
-
[2][1] = "DBGUNBIO",
45
+
[8][0] = "MPM",
46
+
[12][0] = "ISPTNR",
47
+
[14][0] = "ISPCRD0",
48
+
[15][0] = "ISPCRD1",
49
+
[16][0] = "ISPCRD2",
50
+
[22][0] = "HDP",
51
+
[23][0] = "LSDMA",
52
+
[24][0] = "JPEG",
53
+
[27][0] = "VSCH",
54
+
[28][0] = "VCNU",
55
+
[29][0] = "VCN",
56
+
[1][1] = "ISPXT",
57
+
[2][1] = "ISPIXT",
53
58
[3][1] = "DCEDWB",
54
59
[4][1] = "DCEDMC",
55
60
[5][1] = "DCEVGA",
56
61
[6][1] = "MP0",
57
62
[7][1] = "MP1",
58
-
[8][1] = "MPIO",
59
-
[10][1] = "DBGU0",
60
-
[11][1] = "DBGU1",
61
-
[12][1] = "DBGU2",
62
-
[13][1] = "DBGU3",
63
-
[14][1] = "XDP",
64
-
[15][1] = "OSSSYS",
65
-
[16][1] = "HDP",
66
-
[17][1] = "LSDMA",
67
-
[18][1] = "JPEG",
68
-
[19][1] = "VCNU0",
69
-
[20][1] = "VCN0",
70
-
[21][1] = "VSCH",
71
-
[22][1] = "VCNU1",
72
-
[23][1] = "VCN1",
63
+
[8][1] = "MPM",
64
+
[10][1] = "ISPMWR0",
65
+
[11][1] = "ISPMWR1",
66
+
[12][1] = "ISPTNR",
67
+
[13][1] = "ISPSWR",
68
+
[14][1] = "ISPCWR0",
69
+
[15][1] = "ISPCWR1",
70
+
[16][1] = "ISPCWR2",
71
+
[17][1] = "ISPCWR3",
72
+
[18][1] = "XDP",
73
+
[21][1] = "OSSSYS",
74
+
[22][1] = "HDP",
75
+
[23][1] = "LSDMA",
76
+
[24][1] = "JPEG",
77
+
[27][1] = "VSCH",
78
+
[28][1] = "VCNU",
79
+
[29][1] = "VCN",
73
80
};
74
81
75
82
static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
+112
-9
drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c
+112
-9
drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c
···
40
40
41
41
static const char *mmhub_client_ids_v3_3[][2] = {
42
42
[0][0] = "VMC",
43
+
[1][0] = "ISPXT",
44
+
[2][0] = "ISPIXT",
45
+
[4][0] = "DCEDMC",
46
+
[6][0] = "MP0",
47
+
[7][0] = "MP1",
48
+
[8][0] = "MPM",
49
+
[9][0] = "ISPPDPRD",
50
+
[10][0] = "ISPCSTATRD",
51
+
[11][0] = "ISPBYRPRD",
52
+
[12][0] = "ISPRGBPRD",
53
+
[13][0] = "ISPMCFPRD",
54
+
[14][0] = "ISPMCFPRD1",
55
+
[15][0] = "ISPYUVPRD",
56
+
[16][0] = "ISPMCSCRD",
57
+
[17][0] = "ISPGDCRD",
58
+
[18][0] = "ISPLMERD",
59
+
[22][0] = "ISPXT1",
60
+
[23][0] = "ISPIXT1",
61
+
[24][0] = "HDP",
62
+
[25][0] = "LSDMA",
63
+
[26][0] = "JPEG",
64
+
[27][0] = "VPE",
65
+
[28][0] = "VSCH",
66
+
[29][0] = "VCNU",
67
+
[30][0] = "VCN",
68
+
[1][1] = "ISPXT",
69
+
[2][1] = "ISPIXT",
70
+
[3][1] = "DCEDWB",
71
+
[4][1] = "DCEDMC",
72
+
[5][1] = "ISPCSISWR",
73
+
[6][1] = "MP0",
74
+
[7][1] = "MP1",
75
+
[8][1] = "MPM",
76
+
[9][1] = "ISPPDPWR",
77
+
[10][1] = "ISPCSTATWR",
78
+
[11][1] = "ISPBYRPWR",
79
+
[12][1] = "ISPRGBPWR",
80
+
[13][1] = "ISPMCFPWR",
81
+
[14][1] = "ISPMWR0",
82
+
[15][1] = "ISPYUVPWR",
83
+
[16][1] = "ISPMCSCWR",
84
+
[17][1] = "ISPGDCWR",
85
+
[18][1] = "ISPLMEWR",
86
+
[20][1] = "ISPMWR2",
87
+
[21][1] = "OSSSYS",
88
+
[22][1] = "ISPXT1",
89
+
[23][1] = "ISPIXT1",
90
+
[24][1] = "HDP",
91
+
[25][1] = "LSDMA",
92
+
[26][1] = "JPEG",
93
+
[27][1] = "VPE",
94
+
[28][1] = "VSCH",
95
+
[29][1] = "VCNU",
96
+
[30][1] = "VCN",
97
+
};
98
+
99
+
static const char *mmhub_client_ids_v3_3_1[][2] = {
100
+
[0][0] = "VMC",
43
101
[4][0] = "DCEDMC",
44
102
[6][0] = "MP0",
45
103
[7][0] = "MP1",
46
104
[8][0] = "MPM",
47
105
[24][0] = "HDP",
48
106
[25][0] = "LSDMA",
49
-
[26][0] = "JPEG",
50
-
[27][0] = "VPE",
51
-
[29][0] = "VCNU",
52
-
[30][0] = "VCN",
107
+
[26][0] = "JPEG0",
108
+
[27][0] = "VPE0",
109
+
[28][0] = "VSCH",
110
+
[29][0] = "VCNU0",
111
+
[30][0] = "VCN0",
112
+
[32+1][0] = "ISPXT",
113
+
[32+2][0] = "ISPIXT",
114
+
[32+9][0] = "ISPPDPRD",
115
+
[32+10][0] = "ISPCSTATRD",
116
+
[32+11][0] = "ISPBYRPRD",
117
+
[32+12][0] = "ISPRGBPRD",
118
+
[32+13][0] = "ISPMCFPRD",
119
+
[32+14][0] = "ISPMCFPRD1",
120
+
[32+15][0] = "ISPYUVPRD",
121
+
[32+16][0] = "ISPMCSCRD",
122
+
[32+17][0] = "ISPGDCRD",
123
+
[32+18][0] = "ISPLMERD",
124
+
[32+22][0] = "ISPXT1",
125
+
[32+23][0] = "ISPIXT1",
126
+
[32+26][0] = "JPEG1",
127
+
[32+27][0] = "VPE1",
128
+
[32+29][0] = "VCNU1",
129
+
[32+30][0] = "VCN1",
53
130
[3][1] = "DCEDWB",
54
131
[4][1] = "DCEDMC",
55
132
[6][1] = "MP0",
···
135
58
[21][1] = "OSSSYS",
136
59
[24][1] = "HDP",
137
60
[25][1] = "LSDMA",
138
-
[26][1] = "JPEG",
139
-
[27][1] = "VPE",
140
-
[29][1] = "VCNU",
141
-
[30][1] = "VCN",
61
+
[26][1] = "JPEG0",
62
+
[27][1] = "VPE0",
63
+
[28][1] = "VSCH",
64
+
[29][1] = "VCNU0",
65
+
[30][1] = "VCN0",
66
+
[32+1][1] = "ISPXT",
67
+
[32+2][1] = "ISPIXT",
68
+
[32+5][1] = "ISPCSISWR",
69
+
[32+9][1] = "ISPPDPWR",
70
+
[32+10][1] = "ISPCSTATWR",
71
+
[32+11][1] = "ISPBYRPWR",
72
+
[32+12][1] = "ISPRGBPWR",
73
+
[32+13][1] = "ISPMCFPWR",
74
+
[32+14][1] = "ISPMWR0",
75
+
[32+15][1] = "ISPYUVPWR",
76
+
[32+16][1] = "ISPMCSCWR",
77
+
[32+17][1] = "ISPGDCWR",
78
+
[32+18][1] = "ISPLMEWR",
79
+
[32+19][1] = "ISPMWR1",
80
+
[32+20][1] = "ISPMWR2",
81
+
[32+22][1] = "ISPXT1",
82
+
[32+23][1] = "ISPIXT1",
83
+
[32+26][1] = "JPEG1",
84
+
[32+27][1] = "VPE1",
85
+
[32+29][1] = "VCNU1",
86
+
[32+30][1] = "VCN1",
142
87
};
143
88
144
89
static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid,
···
201
102
202
103
switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
203
104
case IP_VERSION(3, 3, 0):
204
-
case IP_VERSION(3, 3, 1):
205
105
case IP_VERSION(3, 3, 2):
206
106
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ?
207
107
mmhub_client_ids_v3_3[cid][rw] :
108
+
cid == 0x140 ? "UMSCH" : NULL;
109
+
break;
110
+
case IP_VERSION(3, 3, 1):
111
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3_1) ?
112
+
mmhub_client_ids_v3_3_1[cid][rw] :
208
113
cid == 0x140 ? "UMSCH" : NULL;
209
114
break;
210
115
default:
+1
-1
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
···
1353
1353
switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1354
1354
case IP_VERSION(7, 0, 0):
1355
1355
case IP_VERSION(7, 0, 1):
1356
-
if ((adev->sdma.instance[0].fw_version >= 7836028) && !adev->sdma.disable_uq)
1356
+
if ((adev->sdma.instance[0].fw_version >= 7966358) && !adev->sdma.disable_uq)
1357
1357
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
1358
1358
break;
1359
1359
default:
+2
drivers/gpu/drm/amd/amdgpu/soc15.c
+2
drivers/gpu/drm/amd/amdgpu/soc15.c
···
1218
1218
AMD_PG_SUPPORT_JPEG;
1219
1219
/*TODO: need a new external_rev_id for GC 9.4.4? */
1220
1220
adev->external_rev_id = adev->rev_id + 0x46;
1221
+
if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
1222
+
adev->external_rev_id = adev->rev_id + 0x50;
1221
1223
break;
1222
1224
default:
1223
1225
/* FIXME: not supported yet */
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
···
2725
2725
2726
2726
dqm_lock(dqm);
2727
2727
mqd_mgr = dqm->mqd_mgrs[mqd_type];
2728
-
*mqd_size = mqd_mgr->mqd_size;
2728
+
*mqd_size = mqd_mgr->mqd_size * NUM_XCC(mqd_mgr->dev->xcc_mask);
2729
2729
*ctl_stack_size = 0;
2730
2730
2731
2731
if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info)
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_module.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_module.c
+51
-10
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+51
-10
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
···
373
373
{
374
374
struct v9_mqd *m = get_mqd(mqd);
375
375
376
-
*ctl_stack_size = m->cp_hqd_cntl_stack_size;
376
+
*ctl_stack_size = m->cp_hqd_cntl_stack_size * NUM_XCC(mm->dev->xcc_mask);
377
377
}
378
378
379
379
static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
···
386
386
387
387
memcpy(mqd_dst, m, sizeof(struct v9_mqd));
388
388
memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size);
389
+
}
390
+
391
+
static void checkpoint_mqd_v9_4_3(struct mqd_manager *mm,
392
+
void *mqd,
393
+
void *mqd_dst,
394
+
void *ctl_stack_dst)
395
+
{
396
+
struct v9_mqd *m;
397
+
int xcc;
398
+
uint64_t size = get_mqd(mqd)->cp_mqd_stride_size;
399
+
400
+
for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {
401
+
m = get_mqd(mqd + size * xcc);
402
+
403
+
checkpoint_mqd(mm, m,
404
+
(uint8_t *)mqd_dst + sizeof(*m) * xcc,
405
+
(uint8_t *)ctl_stack_dst + m->cp_hqd_cntl_stack_size * xcc);
406
+
}
389
407
}
390
408
391
409
static void restore_mqd(struct mqd_manager *mm, void **mqd,
···
782
764
const void *mqd_src,
783
765
const void *ctl_stack_src, u32 ctl_stack_size)
784
766
{
785
-
restore_mqd(mm, mqd, mqd_mem_obj, gart_addr, qp, mqd_src, ctl_stack_src, ctl_stack_size);
786
-
if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) {
787
-
struct v9_mqd *m;
767
+
struct kfd_mem_obj xcc_mqd_mem_obj;
768
+
u32 mqd_ctl_stack_size;
769
+
struct v9_mqd *m;
770
+
u32 num_xcc;
771
+
int xcc;
788
772
789
-
m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr;
790
-
m->cp_hqd_pq_doorbell_control |= 1 <<
791
-
CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT;
773
+
uint64_t offset = mm->mqd_stride(mm, qp);
774
+
775
+
mm->dev->dqm->current_logical_xcc_start++;
776
+
777
+
num_xcc = NUM_XCC(mm->dev->xcc_mask);
778
+
mqd_ctl_stack_size = ctl_stack_size / num_xcc;
779
+
780
+
memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj));
781
+
782
+
/* Set the MQD pointer and gart address to XCC0 MQD */
783
+
*mqd = mqd_mem_obj->cpu_ptr;
784
+
if (gart_addr)
785
+
*gart_addr = mqd_mem_obj->gpu_addr;
786
+
787
+
for (xcc = 0; xcc < num_xcc; xcc++) {
788
+
get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset * xcc);
789
+
restore_mqd(mm, (void **)&m,
790
+
&xcc_mqd_mem_obj,
791
+
NULL,
792
+
qp,
793
+
(uint8_t *)mqd_src + xcc * sizeof(*m),
794
+
(uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size,
795
+
mqd_ctl_stack_size);
792
796
}
793
797
}
794
798
static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
···
946
906
mqd->free_mqd = kfd_free_mqd_cp;
947
907
mqd->is_occupied = kfd_is_occupied_cp;
948
908
mqd->get_checkpoint_info = get_checkpoint_info;
949
-
mqd->checkpoint_mqd = checkpoint_mqd;
950
909
mqd->mqd_size = sizeof(struct v9_mqd);
951
910
mqd->mqd_stride = mqd_stride_v9;
952
911
#if defined(CONFIG_DEBUG_FS)
···
957
918
mqd->init_mqd = init_mqd_v9_4_3;
958
919
mqd->load_mqd = load_mqd_v9_4_3;
959
920
mqd->update_mqd = update_mqd_v9_4_3;
960
-
mqd->restore_mqd = restore_mqd_v9_4_3;
961
921
mqd->destroy_mqd = destroy_mqd_v9_4_3;
962
922
mqd->get_wave_state = get_wave_state_v9_4_3;
923
+
mqd->checkpoint_mqd = checkpoint_mqd_v9_4_3;
924
+
mqd->restore_mqd = restore_mqd_v9_4_3;
963
925
} else {
964
926
mqd->init_mqd = init_mqd;
965
927
mqd->load_mqd = load_mqd;
966
928
mqd->update_mqd = update_mqd;
967
-
mqd->restore_mqd = restore_mqd;
968
929
mqd->destroy_mqd = kfd_destroy_mqd_cp;
969
930
mqd->get_wave_state = get_wave_state;
931
+
mqd->checkpoint_mqd = checkpoint_mqd;
932
+
mqd->restore_mqd = restore_mqd;
970
933
}
971
934
break;
972
935
case KFD_MQD_TYPE_HIQ:
+15
-5
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+15
-5
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
···
914
914
915
915
q_data = (struct kfd_criu_queue_priv_data *)q_private_data;
916
916
917
-
/* data stored in this order: priv_data, mqd, ctl_stack */
917
+
/*
918
+
* data stored in this order:
919
+
* priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...
920
+
*/
918
921
q_data->mqd_size = mqd_size;
919
922
q_data->ctl_stack_size = ctl_stack_size;
920
923
···
966
963
}
967
964
968
965
static void set_queue_properties_from_criu(struct queue_properties *qp,
969
-
struct kfd_criu_queue_priv_data *q_data)
966
+
struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc)
970
967
{
971
968
qp->is_interop = false;
972
969
qp->queue_percent = q_data->q_percent;
···
979
976
qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size;
980
977
qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address;
981
978
qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size;
982
-
qp->ctl_stack_size = q_data->ctl_stack_size;
979
+
if (q_data->type == KFD_QUEUE_TYPE_COMPUTE)
980
+
qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc;
981
+
else
982
+
qp->ctl_stack_size = q_data->ctl_stack_size;
983
+
983
984
qp->type = q_data->type;
984
985
qp->format = q_data->format;
985
986
}
···
1043
1036
goto exit;
1044
1037
}
1045
1038
1046
-
/* data stored in this order: mqd, ctl_stack */
1039
+
/*
1040
+
* data stored in this order:
1041
+
* mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...
1042
+
*/
1047
1043
mqd = q_extra_data;
1048
1044
ctl_stack = mqd + q_data->mqd_size;
1049
1045
1050
1046
memset(&qp, 0, sizeof(qp));
1051
-
set_queue_properties_from_criu(&qp, q_data);
1047
+
set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask));
1052
1048
1053
1049
print_queue_properties(&qp);
1054
1050
+4
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+4
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
4756
4756
return 1;
4757
4757
}
4758
4758
4759
-
/* Rescale from [min..max] to [0..MAX_BACKLIGHT_LEVEL] */
4759
+
/* Rescale from [min..max] to [0..AMDGPU_MAX_BL_LEVEL] */
4760
4760
static inline u32 scale_input_to_fw(int min, int max, u64 input)
4761
4761
{
4762
-
return DIV_ROUND_CLOSEST_ULL(input * MAX_BACKLIGHT_LEVEL, max - min);
4762
+
return DIV_ROUND_CLOSEST_ULL(input * AMDGPU_MAX_BL_LEVEL, max - min);
4763
4763
}
4764
4764
4765
-
/* Rescale from [0..MAX_BACKLIGHT_LEVEL] to [min..max] */
4765
+
/* Rescale from [0..AMDGPU_MAX_BL_LEVEL] to [min..max] */
4766
4766
static inline u32 scale_fw_to_input(int min, int max, u64 input)
4767
4767
{
4768
-
return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), MAX_BACKLIGHT_LEVEL);
4768
+
return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), AMDGPU_MAX_BL_LEVEL);
4769
4769
}
4770
4770
4771
4771
static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,
+9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
···
661
661
return -EINVAL;
662
662
}
663
663
664
+
if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) {
665
+
struct drm_plane_state *primary_state;
666
+
667
+
/* Pull in primary plane for correct VRR handling */
668
+
primary_state = drm_atomic_get_plane_state(state, crtc->primary);
669
+
if (IS_ERR(primary_state))
670
+
return PTR_ERR(primary_state);
671
+
}
672
+
664
673
/* In some use cases, like reset, no stream is attached */
665
674
if (!dm_crtc_state->stream)
666
675
return 0;
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+5
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+5
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
···
245
245
pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
246
246
pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
247
247
248
+
/* DCE 6.0, DCE 6.4: engine clock is the same as PLL0 */
249
+
if (clk_mgr_base->ctx->dce_version == DCE_VERSION_6_0 ||
250
+
clk_mgr_base->ctx->dce_version == DCE_VERSION_6_4)
251
+
pxl_clk_params.pll_id = CLOCK_SOURCE_ID_PLL0;
252
+
248
253
if (clk_mgr_dce->dfs_bypass_active)
249
254
pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
250
255
+10
-9
drivers/gpu/drm/amd/display/dc/core/dc.c
+10
-9
drivers/gpu/drm/amd/display/dc/core/dc.c
···
938
938
if (dc->link_srv)
939
939
link_destroy_link_service(&dc->link_srv);
940
940
941
-
if (dc->ctx->gpio_service)
942
-
dal_gpio_service_destroy(&dc->ctx->gpio_service);
941
+
if (dc->ctx) {
942
+
if (dc->ctx->gpio_service)
943
+
dal_gpio_service_destroy(&dc->ctx->gpio_service);
943
944
944
-
if (dc->ctx->created_bios)
945
-
dal_bios_parser_destroy(&dc->ctx->dc_bios);
945
+
if (dc->ctx->created_bios)
946
+
dal_bios_parser_destroy(&dc->ctx->dc_bios);
947
+
kfree(dc->ctx->logger);
948
+
dc_perf_trace_destroy(&dc->ctx->perf_trace);
946
949
947
-
kfree(dc->ctx->logger);
948
-
dc_perf_trace_destroy(&dc->ctx->perf_trace);
949
-
950
-
kfree(dc->ctx);
951
-
dc->ctx = NULL;
950
+
kfree(dc->ctx);
951
+
dc->ctx = NULL;
952
+
}
952
953
953
954
kfree(dc->bw_vbios);
954
955
dc->bw_vbios = NULL;
+20
-14
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+20
-14
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
···
373
373
.num_timing_generator = 6,
374
374
.num_audio = 6,
375
375
.num_stream_encoder = 6,
376
-
.num_pll = 2,
376
+
.num_pll = 3,
377
377
.num_ddc = 6,
378
378
};
379
379
···
389
389
.num_timing_generator = 2,
390
390
.num_audio = 2,
391
391
.num_stream_encoder = 2,
392
-
.num_pll = 2,
392
+
.num_pll = 3,
393
393
.num_ddc = 2,
394
394
};
395
395
···
973
973
974
974
if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
975
975
pool->base.dp_clock_source =
976
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
976
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
977
977
978
+
/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
978
979
pool->base.clock_sources[0] =
979
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
980
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
980
981
pool->base.clock_sources[1] =
981
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
982
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
982
983
pool->base.clk_src_count = 2;
983
984
984
985
} else {
985
986
pool->base.dp_clock_source =
986
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
987
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
987
988
988
989
pool->base.clock_sources[0] =
989
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
990
-
pool->base.clk_src_count = 1;
990
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
991
+
pool->base.clock_sources[1] =
992
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
993
+
pool->base.clk_src_count = 2;
991
994
}
992
995
993
996
if (pool->base.dp_clock_source == NULL) {
···
1368
1365
1369
1366
if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1370
1367
pool->base.dp_clock_source =
1371
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1368
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1372
1369
1370
+
/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
1373
1371
pool->base.clock_sources[0] =
1374
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1372
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1375
1373
pool->base.clock_sources[1] =
1376
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1374
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1377
1375
pool->base.clk_src_count = 2;
1378
1376
1379
1377
} else {
1380
1378
pool->base.dp_clock_source =
1381
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1379
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1382
1380
1383
1381
pool->base.clock_sources[0] =
1384
-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1385
-
pool->base.clk_src_count = 1;
1382
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1383
+
pool->base.clock_sources[1] =
1384
+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1385
+
pool->base.clk_src_count = 2;
1386
1386
}
1387
1387
1388
1388
if (pool->base.dp_clock_source == NULL) {
+16
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+16
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
77
77
static void smu_power_profile_mode_put(struct smu_context *smu,
78
78
enum PP_SMC_POWER_PROFILE profile_mode);
79
79
static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type);
80
+
static int smu_od_edit_dpm_table(void *handle,
81
+
enum PP_OD_DPM_TABLE_COMMAND type,
82
+
long *input, uint32_t size);
80
83
81
84
static int smu_sys_get_pp_feature_mask(void *handle,
82
85
char *buf)
···
2198
2195
int ret;
2199
2196
struct amdgpu_device *adev = ip_block->adev;
2200
2197
struct smu_context *smu = adev->powerplay.pp_handle;
2198
+
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2201
2199
2202
2200
if (amdgpu_sriov_multi_vf_mode(adev))
2203
2201
return 0;
···
2229
2225
smu->disable_uclk_switch = 0;
2230
2226
2231
2227
adev->pm.dpm_enabled = true;
2228
+
2229
+
if (smu->current_power_limit) {
2230
+
ret = smu_set_power_limit(smu, smu->current_power_limit);
2231
+
if (ret && ret != -EOPNOTSUPP)
2232
+
return ret;
2233
+
}
2234
+
2235
+
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
2236
+
ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0);
2237
+
if (ret)
2238
+
return ret;
2239
+
}
2232
2240
2233
2241
dev_info(adev->dev, "SMU is resumed successfully!\n");
2234
2242
+15
-6
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+15
-6
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
3239
3239
const struct intel_crtc_state *crtc_state)
3240
3240
{
3241
3241
struct intel_display *display = to_intel_display(encoder);
3242
-
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
3243
-
bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
3244
-
crtc_state);
3242
+
intel_wakeref_t wakeref;
3245
3243
int i;
3244
+
u8 owned_lane_mask;
3246
3245
3247
-
if (DISPLAY_VER(display) < 20)
3246
+
if (DISPLAY_VER(display) < 20 ||
3247
+
!intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
3248
3248
return;
3249
+
3250
+
owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
3251
+
3252
+
wakeref = intel_cx0_phy_transaction_begin(encoder);
3253
+
3254
+
if (intel_encoder_is_c10phy(encoder))
3255
+
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0,
3256
+
C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
3249
3257
3250
3258
for (i = 0; i < 4; i++) {
3251
3259
int tx = i % 2 + 1;
···
3264
3256
3265
3257
intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
3266
3258
CONTROL0_MAC_TRANSMIT_LFPS,
3267
-
enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
3268
-
MB_WRITE_COMMITTED);
3259
+
CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);
3269
3260
}
3261
+
3262
+
intel_cx0_phy_transaction_end(encoder, wakeref);
3270
3263
}
3271
3264
3272
3265
static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
+1
drivers/gpu/drm/xe/Kconfig
+1
drivers/gpu/drm/xe/Kconfig
···
5
5
depends on KUNIT || !KUNIT
6
6
depends on INTEL_VSEC || !INTEL_VSEC
7
7
depends on X86_PLATFORM_DEVICES || !(X86 && ACPI)
8
+
depends on PAGE_SIZE_4KB || COMPILE_TEST || BROKEN
8
9
select INTERVAL_TREE
9
10
# we need shmfs for the swappable backing store, and in particular
10
11
# the shmem_readpage() which depends upon tmpfs
+4
-4
drivers/gpu/drm/xe/xe_device.c
+4
-4
drivers/gpu/drm/xe/xe_device.c
···
802
802
return err;
803
803
}
804
804
805
-
err = xe_devcoredump_init(xe);
806
-
if (err)
807
-
return err;
808
-
809
805
/*
810
806
* From here on, if a step fails, make sure a Driver-FLR is triggereed
811
807
*/
···
865
869
if (xe->tiles->media_gt &&
866
870
XE_WA(xe->tiles->media_gt, 15015404425_disable))
867
871
XE_DEVICE_WA_DISABLE(xe, 15015404425);
872
+
873
+
err = xe_devcoredump_init(xe);
874
+
if (err)
875
+
return err;
868
876
869
877
xe_nvm_init(xe);
870
878
+56
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf.c
+56
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf.c
···
16
16
#include "xe_gt_sriov_pf_migration.h"
17
17
#include "xe_gt_sriov_pf_service.h"
18
18
#include "xe_gt_sriov_printk.h"
19
+
#include "xe_guc_submit.h"
19
20
#include "xe_mmio.h"
20
21
#include "xe_pm.h"
21
22
···
48
47
49
48
static void pf_init_workers(struct xe_gt *gt)
50
49
{
50
+
xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
51
51
INIT_WORK(>->sriov.pf.workers.restart, pf_worker_restart_func);
52
+
}
53
+
54
+
static void pf_fini_workers(struct xe_gt *gt)
55
+
{
56
+
xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
57
+
disable_work_sync(>->sriov.pf.workers.restart);
52
58
}
53
59
54
60
/**
···
87
79
return 0;
88
80
}
89
81
82
+
static void pf_fini_action(void *arg)
83
+
{
84
+
struct xe_gt *gt = arg;
85
+
86
+
pf_fini_workers(gt);
87
+
}
88
+
89
+
static int pf_init_late(struct xe_gt *gt)
90
+
{
91
+
struct xe_device *xe = gt_to_xe(gt);
92
+
93
+
xe_gt_assert(gt, IS_SRIOV_PF(xe));
94
+
return devm_add_action_or_reset(xe->drm.dev, pf_fini_action, gt);
95
+
}
96
+
90
97
/**
91
98
* xe_gt_sriov_pf_init - Prepare SR-IOV PF data structures on PF.
92
99
* @gt: the &xe_gt to initialize
···
118
95
if (err)
119
96
return err;
120
97
121
-
return xe_gt_sriov_pf_migration_init(gt);
98
+
err = xe_gt_sriov_pf_migration_init(gt);
99
+
if (err)
100
+
return err;
101
+
102
+
err = pf_init_late(gt);
103
+
if (err)
104
+
return err;
105
+
106
+
return 0;
122
107
}
123
108
124
109
static bool pf_needs_enable_ggtt_guest_update(struct xe_device *xe)
···
260
229
void xe_gt_sriov_pf_restart(struct xe_gt *gt)
261
230
{
262
231
pf_queue_restart(gt);
232
+
}
233
+
234
+
static void pf_flush_restart(struct xe_gt *gt)
235
+
{
236
+
xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
237
+
flush_work(>->sriov.pf.workers.restart);
238
+
}
239
+
240
+
/**
241
+
* xe_gt_sriov_pf_wait_ready() - Wait until per-GT PF SR-IOV support is ready.
242
+
* @gt: the &xe_gt
243
+
*
244
+
* This function can only be called on PF.
245
+
*
246
+
* Return: 0 on success or a negative error code on failure.
247
+
*/
248
+
int xe_gt_sriov_pf_wait_ready(struct xe_gt *gt)
249
+
{
250
+
/* don't wait if there is another ongoing reset */
251
+
if (xe_guc_read_stopped(>->uc.guc))
252
+
return -EBUSY;
253
+
254
+
pf_flush_restart(gt);
255
+
return 0;
263
256
}
+1
drivers/gpu/drm/xe/xe_gt_sriov_pf.h
+1
drivers/gpu/drm/xe/xe_gt_sriov_pf.h
···
11
11
#ifdef CONFIG_PCI_IOV
12
12
int xe_gt_sriov_pf_init_early(struct xe_gt *gt);
13
13
int xe_gt_sriov_pf_init(struct xe_gt *gt);
14
+
int xe_gt_sriov_pf_wait_ready(struct xe_gt *gt);
14
15
void xe_gt_sriov_pf_init_hw(struct xe_gt *gt);
15
16
void xe_gt_sriov_pf_sanitize_hw(struct xe_gt *gt, unsigned int vfid);
16
17
void xe_gt_sriov_pf_stop_prepare(struct xe_gt *gt);
+3
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
+3
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
···
22
22
#include "xe_gt_sriov_pf_policy.h"
23
23
#include "xe_gt_sriov_pf_service.h"
24
24
#include "xe_pm.h"
25
+
#include "xe_sriov_pf.h"
25
26
26
27
/*
27
28
* /sys/kernel/debug/dri/0/
···
206
205
return -EOVERFLOW; \
207
206
\
208
207
xe_pm_runtime_get(xe); \
209
-
err = xe_gt_sriov_pf_config_set_##CONFIG(gt, vfid, val); \
208
+
err = xe_sriov_pf_wait_ready(xe) ?: \
209
+
xe_gt_sriov_pf_config_set_##CONFIG(gt, vfid, val); \
210
210
xe_pm_runtime_put(xe); \
211
211
\
212
212
return err; \
+6
drivers/gpu/drm/xe/xe_guc_capture.c
+6
drivers/gpu/drm/xe/xe_guc_capture.c
···
1817
1817
str_yes_no(snapshot->kernel_reserved));
1818
1818
1819
1819
for (type = GUC_STATE_CAPTURE_TYPE_GLOBAL; type < GUC_STATE_CAPTURE_TYPE_MAX; type++) {
1820
+
/*
1821
+
* FIXME: During devcoredump print we should avoid accessing the
1822
+
* driver pointers for gt or engine. Printing should be done only
1823
+
* using the snapshot captured. Here we are accessing the gt
1824
+
* pointer. It should be fixed.
1825
+
*/
1820
1826
list = xe_guc_capture_get_reg_desc_list(gt, GUC_CAPTURE_LIST_INDEX_PF, type,
1821
1827
capture_class, false);
1822
1828
snapshot_print_by_list_order(snapshot, p, type, list);
+7
-1
drivers/gpu/drm/xe/xe_module.c
+7
-1
drivers/gpu/drm/xe/xe_module.c
···
27
27
#define DEFAULT_PROBE_DISPLAY true
28
28
#define DEFAULT_VRAM_BAR_SIZE 0
29
29
#define DEFAULT_FORCE_PROBE CONFIG_DRM_XE_FORCE_PROBE
30
+
#define DEFAULT_MAX_VFS ~0
31
+
#define DEFAULT_MAX_VFS_STR "unlimited"
30
32
#define DEFAULT_WEDGED_MODE 1
31
33
#define DEFAULT_SVM_NOTIFIER_SIZE 512
32
34
···
36
34
.probe_display = DEFAULT_PROBE_DISPLAY,
37
35
.guc_log_level = DEFAULT_GUC_LOG_LEVEL,
38
36
.force_probe = DEFAULT_FORCE_PROBE,
37
+
#ifdef CONFIG_PCI_IOV
38
+
.max_vfs = DEFAULT_MAX_VFS,
39
+
#endif
39
40
.wedged_mode = DEFAULT_WEDGED_MODE,
40
41
.svm_notifier_size = DEFAULT_SVM_NOTIFIER_SIZE,
41
42
/* the rest are 0 by default */
···
84
79
module_param_named(max_vfs, xe_modparam.max_vfs, uint, 0400);
85
80
MODULE_PARM_DESC(max_vfs,
86
81
"Limit number of Virtual Functions (VFs) that could be managed. "
87
-
"(0 = no VFs [default]; N = allow up to N VFs)");
82
+
"(0=no VFs; N=allow up to N VFs "
83
+
"[default=" DEFAULT_MAX_VFS_STR "])");
88
84
#endif
89
85
90
86
module_param_named_unsafe(wedged_mode, xe_modparam.wedged_mode, int, 0600);
+6
-1
drivers/gpu/drm/xe/xe_pci_sriov.c
+6
-1
drivers/gpu/drm/xe/xe_pci_sriov.c
···
12
12
#include "xe_pci_sriov.h"
13
13
#include "xe_pm.h"
14
14
#include "xe_sriov.h"
15
+
#include "xe_sriov_pf.h"
15
16
#include "xe_sriov_pf_helpers.h"
16
17
#include "xe_sriov_printk.h"
17
18
···
139
138
xe_assert(xe, num_vfs <= total_vfs);
140
139
xe_sriov_dbg(xe, "enabling %u VF%s\n", num_vfs, str_plural(num_vfs));
141
140
141
+
err = xe_sriov_pf_wait_ready(xe);
142
+
if (err)
143
+
goto out;
144
+
142
145
/*
143
146
* We must hold additional reference to the runtime PM to keep PF in D0
144
147
* during VFs lifetime, as our VFs do not implement the PM capability.
···
174
169
failed:
175
170
pf_unprovision_vfs(xe, num_vfs);
176
171
xe_pm_runtime_put(xe);
177
-
172
+
out:
178
173
xe_sriov_notice(xe, "Failed to enable %u VF%s (%pe)\n",
179
174
num_vfs, str_plural(num_vfs), ERR_PTR(err));
180
175
return err;
+27
drivers/gpu/drm/xe/xe_sriov_pf.c
+27
drivers/gpu/drm/xe/xe_sriov_pf.c
···
9
9
10
10
#include "xe_assert.h"
11
11
#include "xe_device.h"
12
+
#include "xe_gt_sriov_pf.h"
12
13
#include "xe_module.h"
13
14
#include "xe_sriov.h"
14
15
#include "xe_sriov_pf.h"
···
99
98
return err;
100
99
101
100
xe_sriov_pf_service_init(xe);
101
+
102
+
return 0;
103
+
}
104
+
105
+
/**
106
+
* xe_sriov_pf_wait_ready() - Wait until PF is ready to operate.
107
+
* @xe: the &xe_device to test
108
+
*
109
+
* This function can only be called on PF.
110
+
*
111
+
* Return: 0 on success or a negative error code on failure.
112
+
*/
113
+
int xe_sriov_pf_wait_ready(struct xe_device *xe)
114
+
{
115
+
struct xe_gt *gt;
116
+
unsigned int id;
117
+
int err;
118
+
119
+
if (xe_device_wedged(xe))
120
+
return -ECANCELED;
121
+
122
+
for_each_gt(gt, xe, id) {
123
+
err = xe_gt_sriov_pf_wait_ready(gt);
124
+
if (err)
125
+
return err;
126
+
}
102
127
103
128
return 0;
104
129
}
+1
drivers/gpu/drm/xe/xe_sriov_pf.h
+1
drivers/gpu/drm/xe/xe_sriov_pf.h
···
15
15
#ifdef CONFIG_PCI_IOV
16
16
bool xe_sriov_pf_readiness(struct xe_device *xe);
17
17
int xe_sriov_pf_init_early(struct xe_device *xe);
18
+
int xe_sriov_pf_wait_ready(struct xe_device *xe);
18
19
void xe_sriov_pf_debugfs_register(struct xe_device *xe, struct dentry *root);
19
20
void xe_sriov_pf_print_vfs_summary(struct xe_device *xe, struct drm_printer *p);
20
21
#else