Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
imx233: make sure dma descriptors are cache friendly
Because DMA descriptors needs to be committed and discarded from
the cache, if they are not cache aligned and/or if their size
is not a multiple of cache ligne, nasty side effects could occur
with adjacents data. The same applies to DMA buffers which are
still potentially broken. Add a macro to ensure that these
constraints will not break by error in the future.
Change-Id: I1dd69a5a9c29796c156d953eaa57c0d281e79846
+34
-7
+6
firmware/export/imx233.h
+6
firmware/export/imx233.h
···
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/* 32 bytes per cache line */
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#define CACHEALIGN_BITS 5
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+
#define ___ENSURE_ZERO(line, x) static uint8_t __ensure_zero_##line[-(x)] __attribute__((unused));
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#define __ENSURE_ZERO(x) ___ENSURE_ZERO(__LINE__, x)
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#define __ENSURE_MULTIPLE(x, y) __ENSURE_ZERO((x) % (y))
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#define __ENSURE_CACHELINE_MULTIPLE(x) __ENSURE_MULTIPLE(x, 1 << CACHEALIGN_BITS)
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#define __ENSURE_STRUCT_CACHE_FRIENDLY(name) __ENSURE_CACHELINE_MULTIPLE(sizeof(name))
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+
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#define __XTRACT(reg, field) ((reg & reg##__##field##_BM) >> reg##__##field##_BP)
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#define __XTRACT_EX(val, field) (((val) & field##_BM) >> field##_BP)
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#define __FIELD_SET(reg, field, val) reg = (reg & ~reg##__##field##_BM) | (val << reg##__##field##_BP)
+4
firmware/target/arm/imx233/dma-imx233.h
+4
firmware/target/arm/imx233/dma-imx233.h
···
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* COMMON *
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**********/
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/* DMA structures should be cache aligned and be padded so that their size
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* is a multiple of a cache line size. Otherwise some nasty side effects
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* could occur with adjacents data fields.
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* The same apply to DMA buffers for the same reasons */
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struct apb_dma_command_t
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{
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struct apb_dma_command_t *next;
+5
-1
firmware/target/arm/imx233/i2c-imx233.c
+5
-1
firmware/target/arm/imx233/i2c-imx233.c
···
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struct apb_dma_command_t dma;
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/* PIO words */
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uint32_t ctrl0;
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-
};
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+
/* padded to next multiple of cache line size (32 bytes) */
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uint32_t pad[4];
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} __attribute__((packed)) CACHEALIGN_ATTR;
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+
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__ENSURE_STRUCT_CACHE_FRIENDLY(struct i2c_dma_command_t)
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#define I2C_NR_STAGES 4
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/* Current transfer */
+14
-5
firmware/target/arm/imx233/pcm-imx233.c
+14
-5
firmware/target/arm/imx233/pcm-imx233.c
···
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#include "pcm-internal.h"
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#include "audioout-imx233.h"
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struct pcm_dma_command_t
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{
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struct apb_dma_command_t dma;
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/* padded to next multiple of cache line size (32 bytes) */
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uint32_t pad[5];
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} __attribute__((packed)) CACHEALIGN_ATTR;
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+
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__ENSURE_STRUCT_CACHE_FRIENDLY(struct pcm_dma_command_t)
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+
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static int locked = 0;
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-
static struct apb_dma_command_t dac_dma;
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static struct pcm_dma_command_t dac_dma;
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static bool pcm_freezed = false;
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/**
···
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static void play(const void *addr, size_t size)
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{
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-
dac_dma.next = NULL;
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-
dac_dma.buffer = (void *)addr;
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-
dac_dma.cmd = HW_APB_CHx_CMD__COMMAND__READ |
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dac_dma.dma.next = NULL;
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dac_dma.dma.buffer = (void *)addr;
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dac_dma.dma.cmd = HW_APB_CHx_CMD__COMMAND__READ |
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HW_APB_CHx_CMD__IRQONCMPLT |
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HW_APB_CHx_CMD__SEMAPHORE |
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size << HW_APB_CHx_CMD__XFER_COUNT_BP;
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/* dma subsystem will make sure cached stuff is written to memory */
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-
imx233_dma_start_command(APB_AUDIO_DAC, &dac_dma);
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+
imx233_dma_start_command(APB_AUDIO_DAC, &dac_dma.dma);
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}
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void INT_DAC_DMA(void)
+5
-1
firmware/target/arm/imx233/ssp-imx233.c
+5
-1
firmware/target/arm/imx233/ssp-imx233.c
···
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uint32_t ctrl0;
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uint32_t cmd0;
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uint32_t cmd1;
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-
};
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+
/* padded to next multiple of cache line size (32 bytes) */
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+
uint32_t pad[2];
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+
} __attribute__((packed)) CACHEALIGN_ATTR;
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+
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__ENSURE_STRUCT_CACHE_FRIENDLY(struct ssp_dma_command_t)
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static bool ssp_in_use[2];
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static int ssp_nr_in_use = 0;