Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
stm32h7: refactor clock init to target-specific callback
Given the myriad of clocking options the STM32H7 family
provides, it is easiest to let targets simply implement
what they need.
Change-Id: I9cceed40a2d638998e8b583651f73557d2ffbd46
authored by
Aidan MacDonald
and committed by
Solomon Peachy
23448a13
37b90baa
+180
-121
+1
firmware/SOURCES
+1
firmware/SOURCES
···
2034
2034
target/arm/stm32/echoplayer/audiohw-echoplayer.c
2035
2035
target/arm/stm32/echoplayer/backlight-echoplayer.c
2036
2036
target/arm/stm32/echoplayer/button-echoplayer.c
2037
+
target/arm/stm32/echoplayer/clock-echoplayer.c
2037
2038
target/arm/stm32/echoplayer/lcd-echoplayer.c
2038
2039
target/arm/stm32/echoplayer/power-echoplayer.c
2039
2040
target/arm/stm32/echoplayer/system-echoplayer.c
+33
firmware/target/arm/stm32/clock-stm32h7.h
+33
firmware/target/arm/stm32/clock-stm32h7.h
···
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __CLOCK_STM32H7_H__
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#define __CLOCK_STM32H7_H__
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#include "system.h"
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+
26
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/*
27
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* Implemented by the target to initialize all oscillators,
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* system, CPU, and bus clocks that need to be enabled from
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* early boot.
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*/
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void stm_target_clock_init(void) INIT_ATTR;
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#endif /* __CLOCK_STM32H7_H__ */
+143
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
+143
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
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* \/ \/ \/ \/ \/
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+
* $Id$
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+
*
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+
* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
13
+
* modify it under the terms of the GNU General Public License
14
+
* as published by the Free Software Foundation; either version 2
15
+
* of the License, or (at your option) any later version.
16
+
*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "clock-stm32h7.h"
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#include "panic.h"
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#include "regs/stm32h743/flash.h"
24
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#include "regs/stm32h743/fmc.h"
25
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#include "regs/stm32h743/pwr.h"
26
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/syscfg.h"
28
+
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/* Flag to use VOS0 */
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#define STM32H743_USE_VOS0 (CPU_FREQ > 400000000)
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+
32
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static void init_hse(void)
33
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{
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reg_writef(RCC_CR, HSEON(1));
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+
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while (!reg_readf(RCC_CR, HSERDY));
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}
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+
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static void init_pll(void)
40
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{
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/* Select HSE/4 input for PLL1 (6 MHz) */
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reg_writef(RCC_PLLCKSELR,
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PLLSRC_V(HSE),
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DIVM1(4),
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DIVM2(0),
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DIVM3(0));
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+
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/* Enable PLL1P and PLL1Q */
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reg_writef(RCC_PLLCFGR,
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DIVP1EN(1),
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DIVQ1EN(1),
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DIVR1EN(0),
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DIVP2EN(0),
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DIVQ2EN(0),
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DIVR2EN(0),
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DIVP3EN(0),
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DIVQ3EN(0),
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DIVR3EN(0),
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PLL1RGE_V(4_8MHZ),
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PLL1VCOSEL_V(WIDE));
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+
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reg_writef(RCC_PLL1DIVR,
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DIVN(80 - 1), /* 6 * 80 = 480 MHz */
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DIVP(1 - 1), /* 480 / 1 = 480 MHz */
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DIVQ(8 - 1), /* 480 / 8 = 60 MHz */
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DIVR(1 - 1));
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+
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reg_writef(RCC_CR, PLL1ON(1));
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while (!reg_readf(RCC_CR, PLL1RDY));
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}
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+
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static void init_vos(void)
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{
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reg_writef(PWR_D3CR, VOS_V(VOS1));
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while (!reg_readf(PWR_D3CR, VOSRDY));
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+
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if (STM32H743_USE_VOS0)
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{
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reg_writef(RCC_APB4ENR, SYSCFGEN(1));
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/* Set ODEN bit to enter VOS0 */
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reg_writef(SYSCFG_PWRCFG, ODEN(1));
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while (!reg_readf(PWR_D3CR, VOSRDY));
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reg_writef(RCC_APB4ENR, SYSCFGEN(0));
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}
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}
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static void init_system_clock(void)
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{
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/* Enable HCLK /2 divider (CPU is at 480 MHz, HCLK limit is 240 MHz) */
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reg_writef(RCC_D1CFGR, HPRE(8));
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while (reg_readf(RCC_D1CFGR, HPRE) != 8);
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+
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/* Enable ABP /2 dividers (HCLK/2, APB limit is 120 MHz) */
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reg_writef(RCC_D1CFGR, D1PPRE(4));
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reg_writef(RCC_D2CFGR, D2PPRE1(4), D2PPRE2(4));
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reg_writef(RCC_D3CFGR, D3PPRE(4));
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/* Switch to PLL1P system clock source */
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reg_writef(RCC_CFGR, SW_V(PLL1P));
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while (reg_readf(RCC_CFGR, SWS) != BV_RCC_CFGR_SWS_PLL1P);
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+
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/* Reduce flash access latency */
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reg_writef(FLASH_ACR, LATENCY(4), WRHIGHFREQ(2));
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while (reg_readf(FLASH_ACR, LATENCY) != 4);
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}
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static void init_lse(void)
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{
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/*
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* Skip if LSE and RTC are already enabled.
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*/
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if (reg_readf(RCC_BDCR, LSERDY) &&
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reg_readf(RCC_BDCR, RTCEN))
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return;
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/*
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* Enable LSE and set it as RTC clock source,
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* then re-enable backup domain write protection.
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*/
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reg_writef(PWR_CR1, DBP(1));
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/* Reset backup domain */
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reg_writef(RCC_BDCR, BDRST(1));
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reg_writef(RCC_BDCR, BDRST(0));
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reg_writef(RCC_BDCR, LSEON(1), LSEDRV(3));
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while (!reg_readf(RCC_BDCR, LSERDY));
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reg_writef(RCC_BDCR, RTCEN(1), RTCSEL_V(LSE));
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reg_writef(PWR_CR1, DBP(0));
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}
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void stm_target_clock_init(void)
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{
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init_hse();
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init_pll();
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init_vos();
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init_system_clock();
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init_lse();
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}
+3
-121
firmware/target/arm/stm32/system-stm32h7.c
+3
-121
firmware/target/arm/stm32/system-stm32h7.c
···
20
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****************************************************************************/
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#include "system.h"
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#include "tick.h"
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#include "clock-stm32h7.h"
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#include "gpio-stm32h7.h"
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#include "regs/cortex-m/cm_scb.h"
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#include "regs/cortex-m/cm_systick.h"
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/pwr.h"
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#include "regs/stm32h743/syscfg.h"
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#include "regs/stm32h743/flash.h"
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#include "regs/stm32h743/dbgmcu.h"
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/* EXT timer is 1/8th of CPU clock */
···
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/* Max delay is limited by kernel tick interval + safety margin */
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#define SYSTICK_DELAY_MAX_US (1000000 / HZ / 2)
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#define SYSTICK_DELAY_MAX_MS (SYSTICK_DELAY_MAX_US / 1000)
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/* Flag to use VOS0 */
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#define STM32H743_USE_VOS0 (CPU_FREQ > 400000000)
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/* Base address of vector table */
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extern char __vectors_arm[];
···
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arm_isb();
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}
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static void stm_init_hse(void)
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{
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reg_writef(RCC_CR, HSEON(1));
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while (!reg_readf(RCC_CR, HSERDY));
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}
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static void stm_init_pll(void)
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{
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/* TODO - this should be determined by the target in some way. */
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-
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/* Select HSE/4 input for PLL1 (6 MHz) */
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reg_writef(RCC_PLLCKSELR,
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PLLSRC_V(HSE),
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DIVM1(4),
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DIVM2(0),
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DIVM3(0));
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-
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/* Enable PLL1P and PLL1Q */
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reg_writef(RCC_PLLCFGR,
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DIVP1EN(1),
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DIVQ1EN(1),
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DIVR1EN(0),
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DIVP2EN(0),
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DIVQ2EN(0),
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DIVR2EN(0),
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DIVP3EN(0),
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DIVQ3EN(0),
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DIVR3EN(0),
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PLL1RGE_V(4_8MHZ),
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PLL1VCOSEL_V(WIDE));
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-
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reg_writef(RCC_PLL1DIVR,
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DIVN(80 - 1), /* 6 * 80 = 480 MHz */
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DIVP(1 - 1), /* 480 / 1 = 480 MHz */
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DIVQ(8 - 1), /* 480 / 8 = 60 MHz */
100
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DIVR(1 - 1));
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-
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reg_writef(RCC_CR, PLL1ON(1));
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while (!reg_readf(RCC_CR, PLL1RDY));
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}
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-
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static void stm_init_vos(void)
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{
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reg_writef(PWR_D3CR, VOS_V(VOS1));
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while (!reg_readf(PWR_D3CR, VOSRDY));
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-
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if (STM32H743_USE_VOS0)
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{
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reg_writef(RCC_APB4ENR, SYSCFGEN(1));
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-
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/* Set ODEN bit to enter VOS0 */
116
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reg_writef(SYSCFG_PWRCFG, ODEN(1));
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while (!reg_readf(PWR_D3CR, VOSRDY));
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-
119
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reg_writef(RCC_APB4ENR, SYSCFGEN(0));
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}
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}
122
-
123
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static void stm_init_system_clock(void)
124
-
{
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/* Enable HCLK /2 divider (CPU is at 480 MHz, HCLK limit is 240 MHz) */
126
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reg_writef(RCC_D1CFGR, HPRE(8));
127
-
while (reg_readf(RCC_D1CFGR, HPRE) != 8);
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-
129
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/* Enable ABP /2 dividers (HCLK/2, APB limit is 120 MHz) */
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reg_writef(RCC_D1CFGR, D1PPRE(4));
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reg_writef(RCC_D2CFGR, D2PPRE1(4), D2PPRE2(4));
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reg_writef(RCC_D3CFGR, D3PPRE(4));
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-
134
-
/* Switch to PLL1P system clock source */
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reg_writef(RCC_CFGR, SW_V(PLL1P));
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while (reg_readf(RCC_CFGR, SWS) != BV_RCC_CFGR_SWS_PLL1P);
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-
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/* Reduce flash access latency */
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reg_writef(FLASH_ACR, LATENCY(4), WRHIGHFREQ(2));
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while (reg_readf(FLASH_ACR, LATENCY) != 4);
141
-
}
142
-
143
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static void stm_init_lse(void)
144
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{
145
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/*
146
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* Skip if LSE and RTC are already enabled.
147
-
*/
148
-
if (reg_readf(RCC_BDCR, LSERDY) &&
149
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reg_readf(RCC_BDCR, RTCEN))
150
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return;
151
-
152
-
/*
153
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* Enable LSE and set it as RTC clock source,
154
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* then re-enable backup domain write protection.
155
-
*/
156
-
157
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reg_writef(PWR_CR1, DBP(1));
158
-
159
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/* Reset backup domain */
160
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reg_writef(RCC_BDCR, BDRST(1));
161
-
reg_writef(RCC_BDCR, BDRST(0));
162
-
163
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reg_writef(RCC_BDCR, LSEON(1), LSEDRV(3));
164
-
while (!reg_readf(RCC_BDCR, LSERDY));
165
-
166
-
reg_writef(RCC_BDCR, RTCEN(1), RTCSEL_V(LSE));
167
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reg_writef(PWR_CR1, DBP(0));
168
-
}
169
-
170
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void system_init(void)
171
59
{
172
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#if defined(DEBUG)
···
180
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/* Enable CPU caches */
181
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stm_enable_caches();
182
70
183
-
/* Start up clocks and get running at max CPU frequency */
184
-
stm_init_hse();
185
-
stm_init_pll();
186
-
stm_init_vos();
187
-
stm_init_system_clock();
188
-
189
-
/* Start up LSE and RTC if necessary so backup domain works */
190
-
stm_init_lse();
71
+
/* Initialize system clocks */
72
+
stm_target_clock_init();
191
73
192
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/* TODO: move this */
193
75
systick_init(1000/HZ);