+854 -871

firmware/export/s5l87xx.h

reviewed

··· 19 19 * 20 20 ****************************************************************************/ 21 21 22 22 - #ifndef __S5L8700_H__ 23 23 - #define __S5L8700_H__ 22 22 + #ifndef __S5L87XX_H__ 23 23 + #define __S5L87XX_H__ 24 24 25 25 #ifndef ASM 26 26 #include <stdint.h> 27 27 #endif 28 28 29 29 - #define REG16_PTR_T volatile uint16_t * 30 30 - #define REG32_PTR_T volatile uint32_t * 29 29 + #define REG16_PTR_T volatile uint16_t * 30 30 + #define REG32_PTR_T volatile uint32_t * 31 31 + #define VOID_PTR_PTR_T void* volatile* 32 32 + #define CONST_VOID_PTR_PTR_T const void* volatile* 31 33 32 34 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 33 35 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ ··· 54 56 /* 04. CALMADM2E */ 55 57 56 58 /* Following registers are mapped on IO Area in data memory area of Calm. */ 57 57 - #define CONFIG0 (*(REG16_PTR_T)(0x3F000000)) /* configuration/control register 0 */ 58 58 - #define CONFIG1 (*(REG16_PTR_T)(0x3F000002)) /* configuration/control register 1*/ 59 59 - #define COMMUN (*(REG16_PTR_T)(0x3F000004)) /* Communication Control Register */ 60 60 - #define DDATA0 (*(REG16_PTR_T)(0x3F000006)) /* Communication data from host to ADM */ 61 61 - #define DDATA1 (*(REG16_PTR_T)(0x3F000008)) /* Communication data from host to ADM */ 62 62 - #define DDATA2 (*(REG16_PTR_T)(0x3F00000A)) /* Communication data from host to ADM */ 63 63 - #define DDATA3 (*(REG16_PTR_T)(0x3F00000C)) /* Communication data from host to ADM */ 64 64 - #define DDATA4 (*(REG16_PTR_T)(0x3F00000E)) /* Communication data from host to ADM */ 65 65 - #define DDATA5 (*(REG16_PTR_T)(0x3F000010)) /* Communication data from host to ADM */ 66 66 - #define DDATA6 (*(REG16_PTR_T)(0x3F000012)) /* Communication data from host to ADM */ 67 67 - #define DDATA7 (*(REG16_PTR_T)(0x3F000014)) /* Communication data from host to ADM */ 68 68 - #define UDATA0 (*(REG16_PTR_T)(0x3F000016)) /* Communication data from ADM to host */ 69 69 - #define UDATA1 (*(REG16_PTR_T)(0x3F000018)) /* Communication data from ADM to host */ 70 70 - #define UDATA2 (*(REG16_PTR_T)(0x3F00001A)) /* Communication data from ADM to host */ 71 71 - #define UDATA3 (*(REG16_PTR_T)(0x3F00001C)) /* Communication data from ADM to host */ 72 72 - #define UDATA4 (*(REG16_PTR_T)(0x3F00001E)) /* Communication data from ADM to host */ 73 73 - #define UDATA5 (*(REG16_PTR_T)(0x3F000020)) /* Communication data from ADM to host */ 74 74 - #define UDATA6 (*(REG16_PTR_T)(0x3F000022)) /* Communication data from ADM to host */ 75 75 - #define UDATA7 (*(REG16_PTR_T)(0x3F000024)) /* Communication data from ADM to host */ 76 76 - #define IBASE_H (*(REG16_PTR_T)(0x3F000026)) /* Higher half of start address for ADM instruction area */ 77 77 - #define IBASE_L (*(REG16_PTR_T)(0x3F000028)) /* Lower half of start address for ADM instruction area */ 78 78 - #define DBASE_H (*(REG16_PTR_T)(0x3F00002A)) /* Higher half of start address for CalmRISC data area */ 79 79 - #define DBASE_L (*(REG16_PTR_T)(0x3F00002C)) /* Lower half of start address for CalmRISC data area */ 80 80 - #define XBASE_H (*(REG16_PTR_T)(0x3F00002E)) /* Higher half of start address for Mac X area */ 81 81 - #define XBASE_L (*(REG16_PTR_T)(0x3F000030)) /* Lower half of start address for Mac X area */ 82 82 - #define YBASE_H (*(REG16_PTR_T)(0x3F000032)) /* Higher half of start address for Mac Y area */ 83 83 - #define YBASE_L (*(REG16_PTR_T)(0x3F000034)) /* Lower half of start address for Mac Y area */ 84 84 - #define S0BASE_H (*(REG16_PTR_T)(0x3F000036)) /* Higher half of start address for sequential buffer 0 area */ 85 85 - #define S0BASE_L (*(REG16_PTR_T)(0x3F000038)) /* Lower half of start address for sequential buffer 0 area */ 86 86 - #define S1BASE_H (*(REG16_PTR_T)(0x3F00003A)) /* Higher half of start address for sequential buffer 1 area */ 87 87 - #define S1BASE_L (*(REG16_PTR_T)(0x3F00003C)) /* Lower half of start address for sequential buffer 1 area */ 88 88 - #define CACHECON (*(REG16_PTR_T)(0x3F00003E)) /* Cache Control Register */ 89 89 - #define CACHESTAT (*(REG16_PTR_T)(0x3F000040)) /* Cache status register */ 90 90 - #define SBFCON (*(REG16_PTR_T)(0x3F000042)) /* Sequential Buffer Control Register */ 91 91 - #define SBFSTAT (*(REG16_PTR_T)(0x3F000044)) /* Sequential Buffer Status Register */ 92 92 - #define SBL0OFF_H (*(REG16_PTR_T)(0x3F000046)) /* Higher bits of Offset register of sequential block 0 area */ 93 93 - #define SBL0OFF_L (*(REG16_PTR_T)(0x3F000048)) /* Lower bits of Offset register of sequential block 0 area */ 94 94 - #define SBL1OFF_H (*(REG16_PTR_T)(0x3F00004A)) /* Higher bits of Offset register of sequential block 1 area */ 95 95 - #define SBL1OFF_L (*(REG16_PTR_T)(0x3F00004C)) /* Lower bits of Offset register of sequential block 1 area */ 96 96 - #define SBL0BEGIN_H (*(REG16_PTR_T)(0x3F00004E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */ 97 97 - #define SBL0BEGIN_L (*(REG16_PTR_T)(0x3F000050)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */ 98 98 - #define SBL1BEGIN_H (*(REG16_PTR_T)(0x3F000052)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */ 99 99 - #define SBL1BEGIN_L (*(REG16_PTR_T)(0x3F000054)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */ 100 100 - #define SBL0END_H (*(REG16_PTR_T)(0x3F000056)) /* Lower bits of End Offset of sequential block 0 area in ring mode */ 101 101 - #define SBL0END_L (*(REG16_PTR_T)(0x3F000058)) /* Higher bits of End Offset of sequential block 0 area in ring mode */ 102 102 - #define SBL1END_H (*(REG16_PTR_T)(0x3F00005A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */ 103 103 - #define SBL1END_L (*(REG16_PTR_T)(0x3F00005C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */ 59 59 + #define ADM_BASE 0x3F000000 60 60 + 61 61 + #define CONFIG0 (*(REG16_PTR_T)(ADM_BASE)) /* configuration/control register 0 */ 62 62 + #define CONFIG1 (*(REG16_PTR_T)(ADM_BASE + 0x02)) /* configuration/control register 1*/ 63 63 + #define COMMUN (*(REG16_PTR_T)(ADM_BASE + 0x04)) /* Communication Control Register */ 64 64 + #define DDATA0 (*(REG16_PTR_T)(ADM_BASE + 0x06)) /* Communication data from host to ADM */ 65 65 + #define DDATA1 (*(REG16_PTR_T)(ADM_BASE + 0x08)) /* Communication data from host to ADM */ 66 66 + #define DDATA2 (*(REG16_PTR_T)(ADM_BASE + 0x0A)) /* Communication data from host to ADM */ 67 67 + #define DDATA3 (*(REG16_PTR_T)(ADM_BASE + 0x0C)) /* Communication data from host to ADM */ 68 68 + #define DDATA4 (*(REG16_PTR_T)(ADM_BASE + 0x0E)) /* Communication data from host to ADM */ 69 69 + #define DDATA5 (*(REG16_PTR_T)(ADM_BASE + 0x10)) /* Communication data from host to ADM */ 70 70 + #define DDATA6 (*(REG16_PTR_T)(ADM_BASE + 0x12)) /* Communication data from host to ADM */ 71 71 + #define DDATA7 (*(REG16_PTR_T)(ADM_BASE + 0x14)) /* Communication data from host to ADM */ 72 72 + #define UDATA0 (*(REG16_PTR_T)(ADM_BASE + 0x16)) /* Communication data from ADM to host */ 73 73 + #define UDATA1 (*(REG16_PTR_T)(ADM_BASE + 0x18)) /* Communication data from ADM to host */ 74 74 + #define UDATA2 (*(REG16_PTR_T)(ADM_BASE + 0x1A)) /* Communication data from ADM to host */ 75 75 + #define UDATA3 (*(REG16_PTR_T)(ADM_BASE + 0x1C)) /* Communication data from ADM to host */ 76 76 + #define UDATA4 (*(REG16_PTR_T)(ADM_BASE + 0x1E)) /* Communication data from ADM to host */ 77 77 + #define UDATA5 (*(REG16_PTR_T)(ADM_BASE + 0x20)) /* Communication data from ADM to host */ 78 78 + #define UDATA6 (*(REG16_PTR_T)(ADM_BASE + 0x22)) /* Communication data from ADM to host */ 79 79 + #define UDATA7 (*(REG16_PTR_T)(ADM_BASE + 0x24)) /* Communication data from ADM to host */ 80 80 + #define IBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x26)) /* Higher half of start address for ADM instruction area */ 81 81 + #define IBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x28)) /* Lower half of start address for ADM instruction area */ 82 82 + #define DBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x2A)) /* Higher half of start address for CalmRISC data area */ 83 83 + #define DBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x2C)) /* Lower half of start address for CalmRISC data area */ 84 84 + #define XBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x2E)) /* Higher half of start address for Mac X area */ 85 85 + #define XBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x30)) /* Lower half of start address for Mac X area */ 86 86 + #define YBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x32)) /* Higher half of start address for Mac Y area */ 87 87 + #define YBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x34)) /* Lower half of start address for Mac Y area */ 88 88 + #define S0BASE_H (*(REG16_PTR_T)(ADM_BASE + 0x36)) /* Higher half of start address for sequential buffer 0 area */ 89 89 + #define S0BASE_L (*(REG16_PTR_T)(ADM_BASE + 0x38)) /* Lower half of start address for sequential buffer 0 area */ 90 90 + #define S1BASE_H (*(REG16_PTR_T)(ADM_BASE + 0x3A)) /* Higher half of start address for sequential buffer 1 area */ 91 91 + #define S1BASE_L (*(REG16_PTR_T)(ADM_BASE + 0x3C)) /* Lower half of start address for sequential buffer 1 area */ 92 92 + #define CACHECON (*(REG16_PTR_T)(ADM_BASE + 0x3E)) /* Cache Control Register */ 93 93 + #define CACHESTAT (*(REG16_PTR_T)(ADM_BASE + 0x40)) /* Cache status register */ 94 94 + #define SBFCON (*(REG16_PTR_T)(ADM_BASE + 0x42)) /* Sequential Buffer Control Register */ 95 95 + #define SBFSTAT (*(REG16_PTR_T)(ADM_BASE + 0x44)) /* Sequential Buffer Status Register */ 96 96 + #define SBL0OFF_H (*(REG16_PTR_T)(ADM_BASE + 0x46)) /* Higher bits of Offset register of sequential block 0 area */ 97 97 + #define SBL0OFF_L (*(REG16_PTR_T)(ADM_BASE + 0x48)) /* Lower bits of Offset register of sequential block 0 area */ 98 98 + #define SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE + 0x4A)) /* Higher bits of Offset register of sequential block 1 area */ 99 99 + #define SBL1OFF_L (*(REG16_PTR_T)(ADM_BASE + 0x4C)) /* Lower bits of Offset register of sequential block 1 area */ 100 100 + #define SBL0BEGIN_H (*(REG16_PTR_T)(ADM_BASE + 0x4E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */ 101 101 + #define SBL0BEGIN_L (*(REG16_PTR_T)(ADM_BASE + 0x50)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */ 102 102 + #define SBL1BEGIN_H (*(REG16_PTR_T)(ADM_BASE + 0x52)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */ 103 103 + #define SBL1BEGIN_L (*(REG16_PTR_T)(ADM_BASE + 0x54)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */ 104 104 + #define SBL0END_H (*(REG16_PTR_T)(ADM_BASE + 0x56)) /* Lower bits of End Offset of sequential block 0 area in ring mode */ 105 105 + #define SBL0END_L (*(REG16_PTR_T)(ADM_BASE + 0x58)) /* Higher bits of End Offset of sequential block 0 area in ring mode */ 106 106 + #define SBL1END_H (*(REG16_PTR_T)(ADM_BASE + 0x5A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */ 107 107 + #define SBL1END_L (*(REG16_PTR_T)(ADM_BASE + 0x5C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */ 104 108 105 109 /* Following registers are components of SFRS of the target system */ 106 106 - #define ADM_CONFIG (*(REG32_PTR_T)(0x39000000)) /* Configuration/Control Register */ 107 107 - #define ADM_COMMUN (*(REG32_PTR_T)(0x39000004)) /* Communication Control Register */ 108 108 - #define ADM_DDATA0 (*(REG32_PTR_T)(0x39000010)) /* Communication data from host to ADM */ 109 109 - #define ADM_DDATA1 (*(REG32_PTR_T)(0x39000014)) /* Communication data from host to ADM */ 110 110 - #define ADM_DDATA2 (*(REG32_PTR_T)(0x39000018)) /* Communication data from host to ADM */ 111 111 - #define ADM_DDATA3 (*(REG32_PTR_T)(0x3900001C)) /* Communication data from host to ADM */ 112 112 - #define ADM_DDATA4 (*(REG32_PTR_T)(0x39000020)) /* Communication data from host to ADM */ 113 113 - #define ADM_DDATA5 (*(REG32_PTR_T)(0x39000024)) /* Communication data from host to ADM */ 114 114 - #define ADM_DDATA6 (*(REG32_PTR_T)(0x39000028)) /* Communication data from host to ADM */ 115 115 - #define ADM_DDATA7 (*(REG32_PTR_T)(0x3900002C)) /* Communication data from host to ADM */ 116 116 - #define ADM_UDATA0 (*(REG32_PTR_T)(0x39000030)) /* Communication data from ADM to host */ 117 117 - #define ADM_UDATA1 (*(REG32_PTR_T)(0x39000034)) /* Communication data from ADM to host */ 118 118 - #define ADM_UDATA2 (*(REG32_PTR_T)(0x39000038)) /* Communication data from ADM to host */ 119 119 - #define ADM_UDATA3 (*(REG32_PTR_T)(0x3900003C)) /* Communication data from ADM to host */ 120 120 - #define ADM_UDATA4 (*(REG32_PTR_T)(0x39000040)) /* Communication data from ADM to host */ 121 121 - #define ADM_UDATA5 (*(REG32_PTR_T)(0x39000044)) /* Communication data from ADM to host */ 122 122 - #define ADM_UDATA6 (*(REG32_PTR_T)(0x39000048)) /* Communication data from ADM to host */ 123 123 - #define ADM_UDATA7 (*(REG32_PTR_T)(0x3900004C)) /* Communication data from ADM to host */ 124 124 - #define ADM_IBASE (*(REG32_PTR_T)(0x39000050)) /* Start Address for ADM Instruction Area */ 125 125 - #define ADM_DBASE (*(REG32_PTR_T)(0x39000054)) /* Start Address for CalmRISC Data Area */ 126 126 - #define ADM_XBASE (*(REG32_PTR_T)(0x39000058)) /* Start Address for Mac X Area */ 127 127 - #define ADM_YBASE (*(REG32_PTR_T)(0x3900005C)) /* Start Address for Mac Y Area */ 128 128 - #define ADM_S0BASE (*(REG32_PTR_T)(0x39000060)) /* Start Address for Sequential Block 0 Area */ 129 129 - #define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */ 110 110 + #define ADM_SFR_BASE 0x39000000 111 111 + 112 112 + #define ADM_CONFIG (*(REG32_PTR_T)(ADM_SFR_BASE)) /* Configuration/Control Register */ 113 113 + #define ADM_COMMUN (*(REG32_PTR_T)(ADM_SFR_BASE + 0x04)) /* Communication Control Register */ 114 114 + #define ADM_DDATA0 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x10)) /* Communication data from host to ADM */ 115 115 + #define ADM_DDATA1 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x14)) /* Communication data from host to ADM */ 116 116 + #define ADM_DDATA2 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x18)) /* Communication data from host to ADM */ 117 117 + #define ADM_DDATA3 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x1C)) /* Communication data from host to ADM */ 118 118 + #define ADM_DDATA4 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x20)) /* Communication data from host to ADM */ 119 119 + #define ADM_DDATA5 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x24)) /* Communication data from host to ADM */ 120 120 + #define ADM_DDATA6 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x28)) /* Communication data from host to ADM */ 121 121 + #define ADM_DDATA7 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x2C)) /* Communication data from host to ADM */ 122 122 + #define ADM_UDATA0 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x30)) /* Communication data from ADM to host */ 123 123 + #define ADM_UDATA1 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x34)) /* Communication data from ADM to host */ 124 124 + #define ADM_UDATA2 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x38)) /* Communication data from ADM to host */ 125 125 + #define ADM_UDATA3 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x3C)) /* Communication data from ADM to host */ 126 126 + #define ADM_UDATA4 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x40)) /* Communication data from ADM to host */ 127 127 + #define ADM_UDATA5 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x44)) /* Communication data from ADM to host */ 128 128 + #define ADM_UDATA6 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x48)) /* Communication data from ADM to host */ 129 129 + #define ADM_UDATA7 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x4C)) /* Communication data from ADM to host */ 130 130 + #define ADM_IBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x50)) /* Start Address for ADM Instruction Area */ 131 131 + #define ADM_DBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x54)) /* Start Address for CalmRISC Data Area */ 132 132 + #define ADM_XBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x58)) /* Start Address for Mac X Area */ 133 133 + #define ADM_YBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x5C)) /* Start Address for Mac Y Area */ 134 134 + #define ADM_S0BASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x60)) /* Start Address for Sequential Block 0 Area */ 135 135 + #define ADM_S1BASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x64)) /* Start Address for Sequential Block 1 Area */ 130 136 131 137 /* 05. CLOCK & POWER MANAGEMENT */ 138 138 + #define CLK_BASE 0x3C500000 139 139 + 132 140 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 133 133 - #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control register */ 134 134 - #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value register */ 135 135 - #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value register */ 136 136 - #define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value register - S5L8701 only? */ 137 137 - #define CLKCON3 (*(REG32_PTR_T)(0x3C500010)) /* Clock control register 3 */ 138 138 - #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ 139 139 - #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ 140 140 - #define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */ 141 141 - #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ 142 142 - #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ 143 143 - #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ 144 144 - #define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */ 145 145 - #define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ 146 146 - #define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ 147 147 - #define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */ 148 148 - #define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* Clock control register 2 */ 149 149 - #define PWRCONEXT (*(REG32_PTR_T)(0x3C500040)) /* Clock power control register 2 */ 141 141 + #define CLKCON (*(REG32_PTR_T)(CLK_BASE)) /* Clock control register */ 142 142 + #define PLL0PMS (*(REG32_PTR_T)(CLK_BASE + 0x04)) /* PLL PMS value register */ 143 143 + #define PLL1PMS (*(REG32_PTR_T)(CLK_BASE + 0x08)) /* PLL PMS value register */ 144 144 + #define PLL2PMS (*(REG32_PTR_T)(CLK_BASE + 0x0C)) /* PLL PMS value register - S5L8701 only? */ 145 145 + #define CLKCON3 (*(REG32_PTR_T)(CLK_BASE + 0x10)) /* Clock control register 3 */ 146 146 + #define PLL0LCNT (*(REG32_PTR_T)(CLK_BASE + 0x14)) /* PLL0 lock count register */ 147 147 + #define PLL1LCNT (*(REG32_PTR_T)(CLK_BASE + 0x18)) /* PLL1 lock count register */ 148 148 + #define PLL2LCNT (*(REG32_PTR_T)(CLK_BASE + 0x1C)) /* PLL2 lock count register - S5L8701 only? */ 149 149 + #define PLLLOCK (*(REG32_PTR_T)(CLK_BASE + 0x20)) /* PLL lock status register */ 150 150 + #define PLLCON (*(REG32_PTR_T)(CLK_BASE + 0x24)) /* PLL control register */ 151 151 + #define PWRCON (*(REG32_PTR_T)(CLK_BASE + 0x28)) /* Clock power control register */ 152 152 + #define PWRMODE (*(REG32_PTR_T)(CLK_BASE + 0x2C)) /* Power mode control register */ 153 153 + #define SWRCON (*(REG32_PTR_T)(CLK_BASE + 0x30)) /* Software reset control register */ 154 154 + #define RSTSR (*(REG32_PTR_T)(CLK_BASE + 0x34)) /* Reset status register */ 155 155 + #define DSPCLKMD (*(REG32_PTR_T)(CLK_BASE + 0x38)) /* DSP clock mode register */ 156 156 + #define CLKCON2 (*(REG32_PTR_T)(CLK_BASE + 0x3C)) /* Clock control register 2 */ 157 157 + #define PWRCONEXT (*(REG32_PTR_T)(CLK_BASE + 0x40)) /* Clock power control register 2 */ 150 158 #elif CONFIG_CPU==S5L8702 151 151 - #define CLKCON0 (*((REG32_PTR_T)(0x3C500000))) 152 152 - #define CLKCON1 (*((REG32_PTR_T)(0x3C500004))) 153 153 - #define CLKCON2 (*((REG32_PTR_T)(0x3C500008))) 154 154 - #define CLKCON3 (*((REG32_PTR_T)(0x3C50000C))) 155 155 - #define CLKCON4 (*((REG32_PTR_T)(0x3C500010))) 156 156 - #define CLKCON5 (*((REG32_PTR_T)(0x3C500014))) 157 157 - #define PLL0PMS (*((REG32_PTR_T)(0x3C500020))) 158 158 - #define PLL1PMS (*((REG32_PTR_T)(0x3C500024))) 159 159 - #define PLL2PMS (*((REG32_PTR_T)(0x3C500028))) 160 160 - #define PLL0LCNT (*((REG32_PTR_T)(0x3C500030))) 161 161 - #define PLL1LCNT (*((REG32_PTR_T)(0x3C500034))) 162 162 - #define PLL2LCNT (*((REG32_PTR_T)(0x3C500038))) 163 163 - #define PLLLOCK (*((REG32_PTR_T)(0x3C500040))) 164 164 - #define PLLMODE (*((REG32_PTR_T)(0x3C500044))) 165 165 - #define PWRCON(i) (*((REG32_PTR_T)(0x3C500000 \ 159 159 + #define CLKCON0 (*((REG32_PTR_T)(CLK_BASE))) 160 160 + #define CLKCON1 (*((REG32_PTR_T)(CLK_BASE + 0x04))) 161 161 + #define CLKCON2 (*((REG32_PTR_T)(CLK_BASE + 0x08))) 162 162 + #define CLKCON3 (*((REG32_PTR_T)(CLK_BASE + 0x0C))) 163 163 + #define CLKCON4 (*((REG32_PTR_T)(CLK_BASE + 0x10))) 164 164 + #define CLKCON5 (*((REG32_PTR_T)(CLK_BASE + 0x14))) 165 165 + #define PLL0PMS (*((REG32_PTR_T)(CLK_BASE + 0x20))) 166 166 + #define PLL1PMS (*((REG32_PTR_T)(CLK_BASE + 0x24))) 167 167 + #define PLL2PMS (*((REG32_PTR_T)(CLK_BASE + 0x28))) 168 168 + #define PLL0LCNT (*((REG32_PTR_T)(CLK_BASE + 0x30))) 169 169 + #define PLL1LCNT (*((REG32_PTR_T)(CLK_BASE + 0x34))) 170 170 + #define PLL2LCNT (*((REG32_PTR_T)(CLK_BASE + 0x38))) 171 171 + #define PLLLOCK (*((REG32_PTR_T)(CLK_BASE + 0x40))) 172 172 + #define PLLMODE (*((REG32_PTR_T)(CLK_BASE + 0x44))) 173 173 + #define PWRCON(i) (*((REG32_PTR_T)(CLK_BASE \ 166 174 + ((i) == 4 ? 0x6C : \ 167 175 ((i) == 3 ? 0x68 : \ 168 176 ((i) == 2 ? 0x58 : \ 169 177 ((i) == 1 ? 0x4C : \ 170 178 0x48))))))) 171 179 /* SW Reset Control Register */ 172 172 - #define SWRCON (*((REG32_PTR_T)(0x3C500050))) 180 180 + #define SWRCON (*((REG32_PTR_T)(CLK_BASE + 0x50))) 173 181 /* Reset Status Register */ 174 174 - #define RSTSR (*((REG32_PTR_T)(0x3C500054))) 182 182 + #define RSTSR (*((REG32_PTR_T)(CLK_BASE + 0x54))) 175 183 #define RSTSR_WDR_BIT (1 << 2) 176 184 #define RSTSR_SWR_BIT (1 << 1) 177 185 #define RSTSR_HWR_BIT (1 << 0) ··· 214 222 #endif 215 223 216 224 /* 06. INTERRUPT CONTROLLER UNIT */ 217 217 - #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ 218 218 - #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ 219 219 - #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ 225 225 + #define INT_BASE 0x39C00000 226 226 + 227 227 + #define SRCPND (*(REG32_PTR_T)(INT_BASE)) /* Indicates the interrupt request status. */ 228 228 + #define INTMOD (*(REG32_PTR_T)(INT_BASE + 0x04)) /* Interrupt mode register. */ 229 229 + #define INTMSK (*(REG32_PTR_T)(INT_BASE + 0x08)) /* Determines which interrupt source is masked. 230 230 + The masked interrupt source will not be serviced. */ 220 231 221 232 #if CONFIG_CPU==S5L8700 222 233 #define INTMSK_TIMERA (1<<5) ··· 241 252 #define INTMSK_UART2 (1<<7) 242 253 #endif 243 254 244 244 - #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ 245 245 - #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ 246 246 - #define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ 255 255 + #define PRIORITY (*(REG32_PTR_T)(INT_BASE + 0x0C)) /* IRQ priority control register */ 256 256 + #define INTPND (*(REG32_PTR_T)(INT_BASE + 0x10)) /* Indicates the interrupt request status. */ 257 257 + #define INTOFFSET (*(REG32_PTR_T)(INT_BASE + 0x14)) /* Indicates the IRQ interrupt request source */ 247 258 248 259 #if CONFIG_CPU==S5L8700 249 249 - #define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */ 250 250 - #define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */ 251 251 - #define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */ 260 260 + #define EINTPOL (*(REG32_PTR_T)(INT_BASE + 0x18)) /* Indicates external interrupt polarity */ 261 261 + #define EINTPEND (*(REG32_PTR_T)(INT_BASE + 0x1C)) /* Indicates whether external interrupts are pending. */ 262 262 + #define EINTMSK (*(REG32_PTR_T)(INT_BASE + 0x20)) /* Indicates whether external interrupts are masked */ 252 263 #elif CONFIG_CPU==S5L8701 253 264 /* 254 265 * s5l8701 GPIO (External) Interrupt Controller. ··· 264 275 * Group2[31:0] PDAT11:PDAT10:PDAT7:PDAT6 265 276 * Group3[31:0] PDAT15:PDAT14:PDAT13:PDAT12 266 277 */ 267 267 - #define GPIOIC_INTLEVEL(g) (*(REG32_PTR_T)(0x39C00018 + 4*(g))) 268 268 - #define GPIOIC_INTSTAT(g) (*(REG32_PTR_T)(0x39C00028 + 4*(g))) 269 269 - #define GPIOIC_INTEN(g) (*(REG32_PTR_T)(0x39C00038 + 4*(g))) 270 270 - #define GPIOIC_INTTYPE(g) (*(REG32_PTR_T)(0x39C00048 + 4*(g))) 278 278 + #define GPIOIC_INTLEVEL(g) (*(REG32_PTR_T)(INT_BASE + 0x18 + 4*(g))) 279 279 + #define GPIOIC_INTSTAT(g) (*(REG32_PTR_T)(INT_BASE + 0x28 + 4*(g))) 280 280 + #define GPIOIC_INTEN(g) (*(REG32_PTR_T)(INT_BASE + 0x38 + 4*(g))) 281 281 + #define GPIOIC_INTTYPE(g) (*(REG32_PTR_T)(INT_BASE + 0x48 + 4*(g))) 271 282 #endif 272 283 273 284 /* 07. MEMORY INTERFACE UNIT (MIU) */ 274 285 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 286 286 + #define MIU_BASE 0x38200000 287 287 + #elif CONFIG_CPU==S5L8702 288 288 + #define MIU_BASE 0x38100000 289 289 + #endif 290 290 + 291 291 + #define MIU_REG(off) (*((REG32_PTR_T)(MIU_BASE + (off)))) 292 292 + 275 293 /* SDRAM */ 276 276 - #define MIUCON (*(REG32_PTR_T)(0x38200000)) /* External Memory configuration register */ 277 277 - #define MIUCOM (*(REG32_PTR_T)(0x38200004)) /* Command and status register */ 278 278 - #define MIUAREF (*(REG32_PTR_T)(0x38200008)) /* Auto-refresh control register */ 279 279 - #define MIUMRS (*(REG32_PTR_T)(0x3820000C)) /* SDRAM Mode Register Set Value Register */ 280 280 - #define MIUSDPARA (*(REG32_PTR_T)(0x38200010)) /* SDRAM parameter register */ 294 294 + #define MIUCON (*(REG32_PTR_T)(MIU_BASE)) /* External Memory configuration register */ 295 295 + #define MIUCOM (*(REG32_PTR_T)(MIU_BASE + 0x04)) /* Command and status register */ 296 296 + #define MIUAREF (*(REG32_PTR_T)(MIU_BASE + 0x08)) /* Auto-refresh control register */ 297 297 + #define MIUMRS (*(REG32_PTR_T)(MIU_BASE + 0x0C)) /* SDRAM Mode Register Set Value Register */ 298 298 + #define MIUSDPARA (*(REG32_PTR_T)(MIU_BASE + 0x10)) /* SDRAM parameter register */ 281 299 282 300 /* DDR */ 283 283 - #define MEMCONF (*(REG32_PTR_T)(0x38200020)) /* External Memory configuration register */ 284 284 - #define USRCMD (*(REG32_PTR_T)(0x38200024)) /* Command and Status register */ 285 285 - #define AREF (*(REG32_PTR_T)(0x38200028)) /* Auto-refresh control register */ 286 286 - #define MRS (*(REG32_PTR_T)(0x3820002C)) /* DRAM mode register set value register */ 287 287 - #define DPARAM (*(REG32_PTR_T)(0x38200030)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */ 288 288 - #define SMEMCONF (*(REG32_PTR_T)(0x38200034)) /* Static memory mode register set value register */ 289 289 - #define MIUS01PARA (*(REG32_PTR_T)(0x38200038)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */ 290 290 - #define MIUS23PARA (*(REG32_PTR_T)(0x3820003C)) /* SRAM2 and SRAM3 static memory parameter register */ 301 301 + #define MEMCONF (*(REG32_PTR_T)(MIU_BASE + 0x20)) /* External Memory configuration register */ 302 302 + #define USRCMD (*(REG32_PTR_T)(MIU_BASE + 0x24)) /* Command and Status register */ 303 303 + #define AREF (*(REG32_PTR_T)(MIU_BASE + 0x28)) /* Auto-refresh control register */ 304 304 + #define MRS (*(REG32_PTR_T)(MIU_BASE + 0x2C)) /* DRAM mode register set value register */ 305 305 + #define DPARAM (*(REG32_PTR_T)(MIU_BASE + 0x30)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */ 306 306 + #define SMEMCONF (*(REG32_PTR_T)(MIU_BASE + 0x34)) /* Static memory mode register set value register */ 307 307 + #define MIUS01PARA (*(REG32_PTR_T)(MIU_BASE + 0x38)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */ 308 308 + #define MIUS23PARA (*(REG32_PTR_T)(MIU_BASE + 0x3C)) /* SRAM2 and SRAM3 static memory parameter register */ 291 309 292 292 - #define MIUORG (*(REG32_PTR_T)(0x38200040)) /* SDR/DDR selection */ 293 293 - #define MIUDLYDQS (*(REG32_PTR_T)(0x38200044)) /* DQS/DQS-rst delay parameter */ 294 294 - #define MIUDLYCLK (*(REG32_PTR_T)(0x38200048)) /* SDR/DDR Clock delay parameter */ 295 295 - #define MIU_DSS_SEL_B (*(REG32_PTR_T)(0x3820004C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */ 296 296 - #define MIU_DSS_SEL_O (*(REG32_PTR_T)(0x38200050)) /* SSTL2 Drive Strength parameter for Output signal */ 297 297 - #define MIU_DSS_SEL_C (*(REG32_PTR_T)(0x38200054)) /* SSTL2 Drive Strength parameter for Clock signal */ 298 298 - #define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(0x38200058)) /* Wide range I/O Drive Strength parameter for NOR interface */ 299 299 - #define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(0x3820005C)) /* Wide range I/O Drive Strength parameter for ATA interface */ 300 300 - #define SSTL2_PAD_ON (*(REG32_PTR_T)(0x38200060)) /* SSTL2 pad ON/OFF select */ 301 301 - #elif CONFIG_CPU==S5L8702 302 302 - #define MIU_BASE (0x38100000) 303 303 - #define MIU_REG(off) (*((REG32_PTR_T)(MIU_BASE + (off)))) 304 304 - /* following registers are similar to s5l8700x */ 305 305 - #define MIUCON (*((REG32_PTR_T)(0x38100000))) 306 306 - #define MIUCOM (*((REG32_PTR_T)(0x38100004))) 307 307 - #define MIUAREF (*((REG32_PTR_T)(0x38100008))) 308 308 - #define MIUMRS (*((REG32_PTR_T)(0x3810000C))) 309 309 - #define MIUSDPARA (*((REG32_PTR_T)(0x38100010))) 310 310 - #endif 310 310 + #define MIUORG (*(REG32_PTR_T)(MIU_BASE + 0x40)) /* SDR/DDR selection */ 311 311 + #define MIUDLYDQS (*(REG32_PTR_T)(MIU_BASE + 0x44)) /* DQS/DQS-rst delay parameter */ 312 312 + #define MIUDLYCLK (*(REG32_PTR_T)(MIU_BASE + 0x48)) /* SDR/DDR Clock delay parameter */ 313 313 + #define MIU_DSS_SEL_B (*(REG32_PTR_T)(MIU_BASE + 0x4C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */ 314 314 + #define MIU_DSS_SEL_O (*(REG32_PTR_T)(MIU_BASE + 0x50)) /* SSTL2 Drive Strength parameter for Output signal */ 315 315 + #define MIU_DSS_SEL_C (*(REG32_PTR_T)(MIU_BASE + 0x54)) /* SSTL2 Drive Strength parameter for Clock signal */ 316 316 + #define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(MIU_BASE + 0x58)) /* Wide range I/O Drive Strength parameter for NOR interface */ 317 317 + #define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(MIU_BASE + 0x5C)) /* Wide range I/O Drive Strength parameter for ATA interface */ 318 318 + #define SSTL2_PAD_ON (*(REG32_PTR_T)(MIU_BASE + 0x60)) /* SSTL2 pad ON/OFF select */ 311 319 312 320 /* 08. IODMA CONTROLLER */ 313 313 - #define DMABASE0 (*(REG32_PTR_T)(0x38400000)) /* Base address register for channel 0 */ 314 314 - #define DMACON0 (*(REG32_PTR_T)(0x38400004)) /* Configuration register for channel 0 */ 315 315 - #define DMATCNT0 (*(REG32_PTR_T)(0x38400008)) /* Transfer count register for channel 0 */ 316 316 - #define DMACADDR0 (*(REG32_PTR_T)(0x3840000C)) /* Current memory address register for channel 0 */ 317 317 - #define DMACTCNT0 (*(REG32_PTR_T)(0x38400010)) /* Current transfer count register for channel 0 */ 318 318 - #define DMACOM0 (*(REG32_PTR_T)(0x38400014)) /* Channel 0 command register */ 319 319 - #define DMANOFF0 (*(REG32_PTR_T)(0x38400018)) /* Channel 0 offset2 register */ 320 320 - #define DMABASE1 (*(REG32_PTR_T)(0x38400020)) /* Base address register for channel 1 */ 321 321 - #define DMACON1 (*(REG32_PTR_T)(0x38400024)) /* Configuration register for channel 1 */ 322 322 - #define DMATCNT1 (*(REG32_PTR_T)(0x38400028)) /* Transfer count register for channel 1 */ 323 323 - #define DMACADDR1 (*(REG32_PTR_T)(0x3840002C)) /* Current memory address register for channel 1 */ 324 324 - #define DMACTCNT1 (*(REG32_PTR_T)(0x38400030)) /* Current transfer count register for channel 1 */ 325 325 - #define DMACOM1 (*(REG32_PTR_T)(0x38400034)) /* Channel 1 command register */ 326 326 - #define DMABASE2 (*(REG32_PTR_T)(0x38400040)) /* Base address register for channel 2 */ 327 327 - #define DMACON2 (*(REG32_PTR_T)(0x38400044)) /* Configuration register for channel 2 */ 328 328 - #define DMATCNT2 (*(REG32_PTR_T)(0x38400048)) /* Transfer count register for channel 2 */ 329 329 - #define DMACADDR2 (*(REG32_PTR_T)(0x3840004C)) /* Current memory address register for channel 2 */ 330 330 - #define DMACTCNT2 (*(REG32_PTR_T)(0x38400050)) /* Current transfer count register for channel 2 */ 331 331 - #define DMACOM2 (*(REG32_PTR_T)(0x38400054)) /* Channel 2 command register */ 332 332 - #define DMABASE3 (*(REG32_PTR_T)(0x38400060)) /* Base address register for channel 3 */ 333 333 - #define DMACON3 (*(REG32_PTR_T)(0x38400064)) /* Configuration register for channel 3 */ 334 334 - #define DMATCNT3 (*(REG32_PTR_T)(0x38400068)) /* Transfer count register for channel 3 */ 335 335 - #define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */ 336 336 - #define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */ 337 337 - #define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */ 321 321 + #define DMA_BASE 0x38400000 322 322 + 323 323 + #define DMABASE0 (*(REG32_PTR_T)(DMA_BASE)) /* Base address register for channel 0 */ 324 324 + #define DMACON0 (*(REG32_PTR_T)(DMA_BASE + 0x04)) /* Configuration register for channel 0 */ 325 325 + #define DMATCNT0 (*(REG32_PTR_T)(DMA_BASE + 0x08)) /* Transfer count register for channel 0 */ 326 326 + #define DMACADDR0 (*(REG32_PTR_T)(DMA_BASE + 0x0C)) /* Current memory address register for channel 0 */ 327 327 + #define DMACTCNT0 (*(REG32_PTR_T)(DMA_BASE + 0x10)) /* Current transfer count register for channel 0 */ 328 328 + #define DMACOM0 (*(REG32_PTR_T)(DMA_BASE + 0x14)) /* Channel 0 command register */ 329 329 + #define DMANOFF0 (*(REG32_PTR_T)(DMA_BASE + 0x18)) /* Channel 0 offset2 register */ 330 330 + #define DMABASE1 (*(REG32_PTR_T)(DMA_BASE + 0x20)) /* Base address register for channel 1 */ 331 331 + #define DMACON1 (*(REG32_PTR_T)(DMA_BASE + 0x24)) /* Configuration register for channel 1 */ 332 332 + #define DMATCNT1 (*(REG32_PTR_T)(DMA_BASE + 0x28)) /* Transfer count register for channel 1 */ 333 333 + #define DMACADDR1 (*(REG32_PTR_T)(DMA_BASE + 0x2C)) /* Current memory address register for channel 1 */ 334 334 + #define DMACTCNT1 (*(REG32_PTR_T)(DMA_BASE + 0x30)) /* Current transfer count register for channel 1 */ 335 335 + #define DMACOM1 (*(REG32_PTR_T)(DMA_BASE + 0x34)) /* Channel 1 command register */ 336 336 + #define DMABASE2 (*(REG32_PTR_T)(DMA_BASE + 0x40)) /* Base address register for channel 2 */ 337 337 + #define DMACON2 (*(REG32_PTR_T)(DMA_BASE + 0x44)) /* Configuration register for channel 2 */ 338 338 + #define DMATCNT2 (*(REG32_PTR_T)(DMA_BASE + 0x48)) /* Transfer count register for channel 2 */ 339 339 + #define DMACADDR2 (*(REG32_PTR_T)(DMA_BASE + 0x4C)) /* Current memory address register for channel 2 */ 340 340 + #define DMACTCNT2 (*(REG32_PTR_T)(DMA_BASE + 0x50)) /* Current transfer count register for channel 2 */ 341 341 + #define DMACOM2 (*(REG32_PTR_T)(DMA_BASE + 0x54)) /* Channel 2 command register */ 342 342 + #define DMABASE3 (*(REG32_PTR_T)(DMA_BASE + 0x60)) /* Base address register for channel 3 */ 343 343 + #define DMACON3 (*(REG32_PTR_T)(DMA_BASE + 0x64)) /* Configuration register for channel 3 */ 344 344 + #define DMATCNT3 (*(REG32_PTR_T)(DMA_BASE + 0x68)) /* Transfer count register for channel 3 */ 345 345 + #define DMACADDR3 (*(REG32_PTR_T)(DMA_BASE + 0x6C)) /* Current memory address register for channel 3 */ 346 346 + #define DMACTCNT3 (*(REG32_PTR_T)(DMA_BASE + 0x70)) /* Current transfer count register for channel 3 */ 347 347 + #define DMACOM3 (*(REG32_PTR_T)(DMA_BASE + 0x74)) /* Channel 3 command register */ 338 348 339 349 #if CONFIG_CPU==S5L8700 340 340 - #define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */ 350 350 + #define DMAALLST (*(REG32_PTR_T)(DMA_BASE + 0x100)) /* All channel status register */ 341 351 #elif CONFIG_CPU==S5L8701 342 342 - #define DMABASE4 (*(REG32_PTR_T)(0x38400080)) /* Base address register for channel 4 */ 343 343 - #define DMACON4 (*(REG32_PTR_T)(0x38400084)) /* Configuration register for channel 4 */ 344 344 - #define DMATCNT4 (*(REG32_PTR_T)(0x38400088)) /* Transfer count register for channel 4 */ 345 345 - #define DMACADDR4 (*(REG32_PTR_T)(0x3840008C)) /* Current memory address register for channel 4 */ 346 346 - #define DMACTCNT4 (*(REG32_PTR_T)(0x38400090)) /* Current transfer count register for channel 4 */ 347 347 - #define DMACOM4 (*(REG32_PTR_T)(0x38400094)) /* Channel 4 command register */ 348 348 - #define DMABASE5 (*(REG32_PTR_T)(0x384000A0)) /* Base address register for channel 5 */ 349 349 - #define DMACON5 (*(REG32_PTR_T)(0x384000A4)) /* Configuration register for channel 5 */ 350 350 - #define DMATCNT5 (*(REG32_PTR_T)(0x384000A8)) /* Transfer count register for channel 5 */ 351 351 - #define DMACADDR5 (*(REG32_PTR_T)(0x384000AC)) /* Current memory address register for channel 5 */ 352 352 - #define DMACTCNT5 (*(REG32_PTR_T)(0x384000B0)) /* Current transfer count register for channel 5 */ 353 353 - #define DMACOM5 (*(REG32_PTR_T)(0x384000B4)) /* Channel 5 command register */ 354 354 - #define DMABASE6 (*(REG32_PTR_T)(0x384000C0)) /* Base address register for channel 6 */ 355 355 - #define DMACON6 (*(REG32_PTR_T)(0x384000C4)) /* Configuration register for channel 6 */ 356 356 - #define DMATCNT6 (*(REG32_PTR_T)(0x384000C8)) /* Transfer count register for channel 6 */ 357 357 - #define DMACADDR6 (*(REG32_PTR_T)(0x384000CC)) /* Current memory address register for channel 6 */ 358 358 - #define DMACTCNT6 (*(REG32_PTR_T)(0x384000D0)) /* Current transfer count register for channel 6 */ 359 359 - #define DMACOM6 (*(REG32_PTR_T)(0x384000D4)) /* Channel 6 command register */ 360 360 - #define DMABASE7 (*(REG32_PTR_T)(0x384000E0)) /* Base address register for channel 7 */ 361 361 - #define DMACON7 (*(REG32_PTR_T)(0x384000E4)) /* Configuration register for channel 7 */ 362 362 - #define DMATCNT7 (*(REG32_PTR_T)(0x384000E8)) /* Transfer count register for channel 7 */ 363 363 - #define DMACADDR7 (*(REG32_PTR_T)(0x384000EC)) /* Current memory address register for channel 7 */ 364 364 - #define DMACTCNT7 (*(REG32_PTR_T)(0x384000F0)) /* Current transfer count register for channel 7 */ 365 365 - #define DMACOM7 (*(REG32_PTR_T)(0x384000F4)) /* Channel 7 command register */ 366 366 - #define DMABASE8 (*(REG32_PTR_T)(0x38400100)) /* Base address register for channel 8 */ 367 367 - #define DMACON8 (*(REG32_PTR_T)(0x38400104)) /* Configuration register for channel 8 */ 368 368 - #define DMATCNT8 (*(REG32_PTR_T)(0x38400108)) /* Transfer count register for channel 8 */ 369 369 - #define DMACADDR8 (*(REG32_PTR_T)(0x3840010C)) /* Current memory address register for channel 8 */ 370 370 - #define DMACTCNT8 (*(REG32_PTR_T)(0x38400110)) /* Current transfer count register for channel 8 */ 371 371 - #define DMACOM8 (*(REG32_PTR_T)(0x38400114)) /* Channel 8 command register */ 372 372 - #define DMAALLST (*(REG32_PTR_T)(0x38400180)) /* All channel status register */ 352 352 + #define DMABASE4 (*(REG32_PTR_T)(DMA_BASE + 0x80)) /* Base address register for channel 4 */ 353 353 + #define DMACON4 (*(REG32_PTR_T)(DMA_BASE + 0x84)) /* Configuration register for channel 4 */ 354 354 + #define DMATCNT4 (*(REG32_PTR_T)(DMA_BASE + 0x88)) /* Transfer count register for channel 4 */ 355 355 + #define DMACADDR4 (*(REG32_PTR_T)(DMA_BASE + 0x8C)) /* Current memory address register for channel 4 */ 356 356 + #define DMACTCNT4 (*(REG32_PTR_T)(DMA_BASE + 0x90)) /* Current transfer count register for channel 4 */ 357 357 + #define DMACOM4 (*(REG32_PTR_T)(DMA_BASE + 0x94)) /* Channel 4 command register */ 358 358 + #define DMABASE5 (*(REG32_PTR_T)(DMA_BASE + 0xA0)) /* Base address register for channel 5 */ 359 359 + #define DMACON5 (*(REG32_PTR_T)(DMA_BASE + 0xA4)) /* Configuration register for channel 5 */ 360 360 + #define DMATCNT5 (*(REG32_PTR_T)(DMA_BASE + 0xA8)) /* Transfer count register for channel 5 */ 361 361 + #define DMACADDR5 (*(REG32_PTR_T)(DMA_BASE + 0xAC)) /* Current memory address register for channel 5 */ 362 362 + #define DMACTCNT5 (*(REG32_PTR_T)(DMA_BASE + 0xB0)) /* Current transfer count register for channel 5 */ 363 363 + #define DMACOM5 (*(REG32_PTR_T)(DMA_BASE + 0xB4)) /* Channel 5 command register */ 364 364 + #define DMABASE6 (*(REG32_PTR_T)(DMA_BASE + 0xC0)) /* Base address register for channel 6 */ 365 365 + #define DMACON6 (*(REG32_PTR_T)(DMA_BASE + 0xC4)) /* Configuration register for channel 6 */ 366 366 + #define DMATCNT6 (*(REG32_PTR_T)(DMA_BASE + 0xC8)) /* Transfer count register for channel 6 */ 367 367 + #define DMACADDR6 (*(REG32_PTR_T)(DMA_BASE + 0xCC)) /* Current memory address register for channel 6 */ 368 368 + #define DMACTCNT6 (*(REG32_PTR_T)(DMA_BASE + 0xD0)) /* Current transfer count register for channel 6 */ 369 369 + #define DMACOM6 (*(REG32_PTR_T)(DMA_BASE + 0xD4)) /* Channel 6 command register */ 370 370 + #define DMABASE7 (*(REG32_PTR_T)(DMA_BASE + 0xE0)) /* Base address register for channel 7 */ 371 371 + #define DMACON7 (*(REG32_PTR_T)(DMA_BASE + 0xE4)) /* Configuration register for channel 7 */ 372 372 + #define DMATCNT7 (*(REG32_PTR_T)(DMA_BASE + 0xE8)) /* Transfer count register for channel 7 */ 373 373 + #define DMACADDR7 (*(REG32_PTR_T)(DMA_BASE + 0xEC)) /* Current memory address register for channel 7 */ 374 374 + #define DMACTCNT7 (*(REG32_PTR_T)(DMA_BASE + 0xF0)) /* Current transfer count register for channel 7 */ 375 375 + #define DMACOM7 (*(REG32_PTR_T)(DMA_BASE + 0xF4)) /* Channel 7 command register */ 376 376 + #define DMABASE8 (*(REG32_PTR_T)(DMA_BASE + 0x100)) /* Base address register for channel 8 */ 377 377 + #define DMACON8 (*(REG32_PTR_T)(DMA_BASE + 0x104)) /* Configuration register for channel 8 */ 378 378 + #define DMATCNT8 (*(REG32_PTR_T)(DMA_BASE + 0x108)) /* Transfer count register for channel 8 */ 379 379 + #define DMACADDR8 (*(REG32_PTR_T)(DMA_BASE + 0x10C)) /* Current memory address register for channel 8 */ 380 380 + #define DMACTCNT8 (*(REG32_PTR_T)(DMA_BASE + 0x110)) /* Current transfer count register for channel 8 */ 381 381 + #define DMACOM8 (*(REG32_PTR_T)(DMA_BASE + 0x114)) /* Channel 8 command register */ 382 382 + #define DMAALLST (*(REG32_PTR_T)(DMA_BASE + 0x180)) /* All channel status register */ 373 383 #endif 374 384 375 385 #define DMACON_DEVICE_SHIFT 30 ··· 397 407 #define DMAALLST_CHAN3_MASK (0xF << 12) 398 408 399 409 /* 10. REAL TIMER CLOCK (RTC) */ 400 400 - #define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */ 401 401 - #define RTCRST (*(REG32_PTR_T)(0x3D200004)) /* RTC Round Reset Register */ 402 402 - #define RTCALM (*(REG32_PTR_T)(0x3D200008)) /* RTC Alarm Control Register */ 403 403 - #define ALMSEC (*(REG32_PTR_T)(0x3D20000C)) /* Alarm Second Data Register */ 404 404 - #define ALMMIN (*(REG32_PTR_T)(0x3D200010)) /* Alarm Minute Data Register */ 405 405 - #define ALMHOUR (*(REG32_PTR_T)(0x3D200014)) /* Alarm Hour Data Register */ 406 406 - #define ALMDATE (*(REG32_PTR_T)(0x3D200018)) /* Alarm Date Data Register */ 407 407 - #define ALMDAY (*(REG32_PTR_T)(0x3D20001C)) /* Alarm Day of Week Data Register */ 408 408 - #define ALMMON (*(REG32_PTR_T)(0x3D200020)) /* Alarm Month Data Register */ 409 409 - #define ALMYEAR (*(REG32_PTR_T)(0x3D200024)) /* Alarm Year Data Register */ 410 410 - #define BCDSEC (*(REG32_PTR_T)(0x3D200028)) /* BCD Second Register */ 411 411 - #define BCDMIN (*(REG32_PTR_T)(0x3D20002C)) /* BCD Minute Register */ 412 412 - #define BCDHOUR (*(REG32_PTR_T)(0x3D200030)) /* BCD Hour Register */ 413 413 - #define BCDDATE (*(REG32_PTR_T)(0x3D200034)) /* BCD Date Register */ 414 414 - #define BCDDAY (*(REG32_PTR_T)(0x3D200038)) /* BCD Day of Week Register */ 415 415 - #define BCDMON (*(REG32_PTR_T)(0x3D20003C)) /* BCD Month Register */ 416 416 - #define BCDYEAR (*(REG32_PTR_T)(0x3D200040)) /* BCD Year Register */ 417 417 - #define RTCIM (*(REG32_PTR_T)(0x3D200044)) /* RTC Interrupt Mode Register */ 418 418 - #define RTCPEND (*(REG32_PTR_T)(0x3D200048)) /* RTC Interrupt Pending Register */ 410 410 + #define RTC_BASE 0x3D200000 411 411 + 412 412 + #define RTCCON (*(REG32_PTR_T)(RTC_BASE)) /* RTC Control Register */ 413 413 + #define RTCRST (*(REG32_PTR_T)(RTC_BASE + 0x04)) /* RTC Round Reset Register */ 414 414 + #define RTCALM (*(REG32_PTR_T)(RTC_BASE + 0x08)) /* RTC Alarm Control Register */ 415 415 + #define ALMSEC (*(REG32_PTR_T)(RTC_BASE + 0x0C)) /* Alarm Second Data Register */ 416 416 + #define ALMMIN (*(REG32_PTR_T)(RTC_BASE + 0x10)) /* Alarm Minute Data Register */ 417 417 + #define ALMHOUR (*(REG32_PTR_T)(RTC_BASE + 0x14)) /* Alarm Hour Data Register */ 418 418 + #define ALMDATE (*(REG32_PTR_T)(RTC_BASE + 0x18)) /* Alarm Date Data Register */ 419 419 + #define ALMDAY (*(REG32_PTR_T)(RTC_BASE + 0x1C)) /* Alarm Day of Week Data Register */ 420 420 + #define ALMMON (*(REG32_PTR_T)(RTC_BASE + 0x20)) /* Alarm Month Data Register */ 421 421 + #define ALMYEAR (*(REG32_PTR_T)(RTC_BASE + 0x24)) /* Alarm Year Data Register */ 422 422 + #define BCDSEC (*(REG32_PTR_T)(RTC_BASE + 0x28)) /* BCD Second Register */ 423 423 + #define BCDMIN (*(REG32_PTR_T)(RTC_BASE + 0x2C)) /* BCD Minute Register */ 424 424 + #define BCDHOUR (*(REG32_PTR_T)(RTC_BASE + 0x30)) /* BCD Hour Register */ 425 425 + #define BCDDATE (*(REG32_PTR_T)(RTC_BASE + 0x34)) /* BCD Date Register */ 426 426 + #define BCDDAY (*(REG32_PTR_T)(RTC_BASE + 0x38)) /* BCD Day of Week Register */ 427 427 + #define BCDMON (*(REG32_PTR_T)(RTC_BASE + 0x3C)) /* BCD Month Register */ 428 428 + #define BCDYEAR (*(REG32_PTR_T)(RTC_BASE + 0x40)) /* BCD Year Register */ 429 429 + #define RTCIM (*(REG32_PTR_T)(RTC_BASE + 0x44)) /* RTC Interrupt Mode Register */ 430 430 + #define RTCPEND (*(REG32_PTR_T)(RTC_BASE + 0x48)) /* RTC Interrupt Pending Register */ 419 431 420 432 /* 09. WATCHDOG TIMER*/ 421 421 - #define WDTCON (*(REG32_PTR_T)(0x3C800000)) /* Control Register */ 422 422 - #define WDTCNT (*(REG32_PTR_T)(0x3C800004)) /* 11-bits internal counter */ 433 433 + #define WDT_BASE 0x3C800000 434 434 + 435 435 + #define WDTCON (*(REG32_PTR_T)(WDT_BASE)) /* Control Register */ 436 436 + #define WDTCNT (*(REG32_PTR_T)(WDT_BASE + 0x04)) /* 11-bits internal counter */ 423 437 424 438 /* 11. 16 BIT TIMER */ 425 425 - #define TACON (*(REG32_PTR_T)(0x3C700000)) /* Control Register for timer A */ 426 426 - #define TACMD (*(REG32_PTR_T)(0x3C700004)) /* Command Register for timer A */ 427 427 - #define TADATA0 (*(REG32_PTR_T)(0x3C700008)) /* Data0 Register */ 428 428 - #define TADATA1 (*(REG32_PTR_T)(0x3C70000C)) /* Data1 Register */ 429 429 - #define TAPRE (*(REG32_PTR_T)(0x3C700010)) /* Pre-scale register */ 430 430 - #define TACNT (*(REG32_PTR_T)(0x3C700014)) /* Counter register */ 431 431 - #define TBCON (*(REG32_PTR_T)(0x3C700020)) /* Control Register for timer B */ 432 432 - #define TBCMD (*(REG32_PTR_T)(0x3C700024)) /* Command Register for timer B */ 433 433 - #define TBDATA0 (*(REG32_PTR_T)(0x3C700028)) /* Data0 Register */ 434 434 - #define TBDATA1 (*(REG32_PTR_T)(0x3C70002C)) /* Data1 Register */ 435 435 - #define TBPRE (*(REG32_PTR_T)(0x3C700030)) /* Pre-scale register */ 436 436 - #define TBCNT (*(REG32_PTR_T)(0x3C700034)) /* Counter register */ 437 437 - #define TCCON (*(REG32_PTR_T)(0x3C700040)) /* Control Register for timer C */ 438 438 - #define TCCMD (*(REG32_PTR_T)(0x3C700044)) /* Command Register for timer C */ 439 439 - #define TCDATA0 (*(REG32_PTR_T)(0x3C700048)) /* Data0 Register */ 440 440 - #define TCDATA1 (*(REG32_PTR_T)(0x3C70004C)) /* Data1 Register */ 441 441 - #define TCPRE (*(REG32_PTR_T)(0x3C700050)) /* Pre-scale register */ 442 442 - #define TCCNT (*(REG32_PTR_T)(0x3C700054)) /* Counter register */ 443 443 - #define TDCON (*(REG32_PTR_T)(0x3C700060)) /* Control Register for timer D */ 444 444 - #define TDCMD (*(REG32_PTR_T)(0x3C700064)) /* Command Register for timer D */ 445 445 - #define TDDATA0 (*(REG32_PTR_T)(0x3C700068)) /* Data0 Register */ 446 446 - #define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */ 447 447 - #define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */ 448 448 - #define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */ 439 439 + #define TIMER_BASE 0x3C700000 440 440 + 441 441 + #define TACON (*(REG32_PTR_T)(TIMER_BASE)) /* Control Register for timer A */ 442 442 + #define TACMD (*(REG32_PTR_T)(TIMER_BASE + 0x04)) /* Command Register for timer A */ 443 443 + #define TADATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x08)) /* Data0 Register */ 444 444 + #define TADATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x0C)) /* Data1 Register */ 445 445 + #define TAPRE (*(REG32_PTR_T)(TIMER_BASE + 0x10)) /* Pre-scale register */ 446 446 + #define TACNT (*(REG32_PTR_T)(TIMER_BASE + 0x14)) /* Counter register */ 447 447 + #define TBCON (*(REG32_PTR_T)(TIMER_BASE + 0x20)) /* Control Register for timer B */ 448 448 + #define TBCMD (*(REG32_PTR_T)(TIMER_BASE + 0x24)) /* Command Register for timer B */ 449 449 + #define TBDATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x28)) /* Data0 Register */ 450 450 + #define TBDATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x2C)) /* Data1 Register */ 451 451 + #define TBPRE (*(REG32_PTR_T)(TIMER_BASE + 0x30)) /* Pre-scale register */ 452 452 + #define TBCNT (*(REG32_PTR_T)(TIMER_BASE + 0x34)) /* Counter register */ 453 453 + #define TCCON (*(REG32_PTR_T)(TIMER_BASE + 0x40)) /* Control Register for timer C */ 454 454 + #define TCCMD (*(REG32_PTR_T)(TIMER_BASE + 0x44)) /* Command Register for timer C */ 455 455 + #define TCDATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x48)) /* Data0 Register */ 456 456 + #define TCDATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x4C)) /* Data1 Register */ 457 457 + #define TCPRE (*(REG32_PTR_T)(TIMER_BASE + 0x50)) /* Pre-scale register */ 458 458 + #define TCCNT (*(REG32_PTR_T)(TIMER_BASE + 0x54)) /* Counter register */ 459 459 + #define TDCON (*(REG32_PTR_T)(TIMER_BASE + 0x60)) /* Control Register for timer D */ 460 460 + #define TDCMD (*(REG32_PTR_T)(TIMER_BASE + 0x64)) /* Command Register for timer D */ 461 461 + #define TDDATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x68)) /* Data0 Register */ 462 462 + #define TDDATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x6C)) /* Data1 Register */ 463 463 + #define TDPRE (*(REG32_PTR_T)(TIMER_BASE + 0x70)) /* Pre-scale register */ 464 464 + #define TDCNT (*(REG32_PTR_T)(TIMER_BASE + 0x74)) /* Counter register */ 449 465 450 466 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 451 467 #define TIMER_FREQ (1843200 * 4 * 26 / 1 / 4) /* 47923200 Hz */ 452 468 453 453 - #define FIVE_USEC_TIMER (((uint64_t)(*(REG32_PTR_T)(0x3C700080)) << 32) \ 454 454 - | (*(REG32_PTR_T)(0x3C700084))) /* 64bit 5usec timer */ 469 469 + #define TREG_80 (*(REG32_PTR_T)(TIMER_BASE + 0x80)) 470 470 + #define TREG_84 (*(REG32_PTR_T)(TIMER_BASE + 0x84)) 471 471 + #define FIVE_USEC_TIMER (((uint64_t)TREG_80 << 32) | TREG_84) /* 64bit 5usec timer */ 455 472 #define USEC_TIMER (FIVE_USEC_TIMER * 5) /* usecs */ 456 473 #elif CONFIG_CPU==S5L8702 457 474 /* 16/32-bit timers: ··· 482 499 */ 483 500 #define TIMER_FREQ 12000000 /* ECLK */ 484 501 485 485 - #define TECON (*((REG32_PTR_T)(0x3C7000A0))) 486 486 - #define TECMD (*((REG32_PTR_T)(0x3C7000A4))) 487 487 - #define TEDATA0 (*((REG32_PTR_T)(0x3C7000A8))) 488 488 - #define TEDATA1 (*((REG32_PTR_T)(0x3C7000AC))) 489 489 - #define TEPRE (*((REG32_PTR_T)(0x3C7000B0))) 490 490 - #define TECNT (*((REG32_PTR_T)(0x3C7000B4))) 491 491 - #define TFCON (*((REG32_PTR_T)(0x3C7000C0))) 492 492 - #define TFCMD (*((REG32_PTR_T)(0x3C7000C4))) 493 493 - #define TFDATA0 (*((REG32_PTR_T)(0x3C7000C8))) 494 494 - #define TFDATA1 (*((REG32_PTR_T)(0x3C7000CC))) 495 495 - #define TFPRE (*((REG32_PTR_T)(0x3C7000D0))) 496 496 - #define TFCNT (*((REG32_PTR_T)(0x3C7000D4))) 497 497 - #define TGCON (*((REG32_PTR_T)(0x3C7000E0))) 498 498 - #define TGCMD (*((REG32_PTR_T)(0x3C7000E4))) 499 499 - #define TGDATA0 (*((REG32_PTR_T)(0x3C7000E8))) 500 500 - #define TGDATA1 (*((REG32_PTR_T)(0x3C7000EC))) 501 501 - #define TGPRE (*((REG32_PTR_T)(0x3C7000F0))) 502 502 - #define TGCNT (*((REG32_PTR_T)(0x3C7000F4))) 503 503 - #define THCON (*((REG32_PTR_T)(0x3C700100))) 504 504 - #define THCMD (*((REG32_PTR_T)(0x3C700104))) 505 505 - #define THDATA0 (*((REG32_PTR_T)(0x3C700108))) 506 506 - #define THDATA1 (*((REG32_PTR_T)(0x3C70010C))) 507 507 - #define THPRE (*((REG32_PTR_T)(0x3C700110))) 508 508 - #define THCNT (*((REG32_PTR_T)(0x3C700114))) 509 509 - #define TSTAT (*((REG32_PTR_T)(0x3C700118))) 502 502 + #define TECON (*((REG32_PTR_T)(TIMER_BASE + 0xA0))) 503 503 + #define TECMD (*((REG32_PTR_T)(TIMER_BASE + 0xA4))) 504 504 + #define TEDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0xA8))) 505 505 + #define TEDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0xAC))) 506 506 + #define TEPRE (*((REG32_PTR_T)(TIMER_BASE + 0xB0))) 507 507 + #define TECNT (*((REG32_PTR_T)(TIMER_BASE + 0xB4))) 508 508 + #define TFCON (*((REG32_PTR_T)(TIMER_BASE + 0xC0))) 509 509 + #define TFCMD (*((REG32_PTR_T)(TIMER_BASE + 0xC4))) 510 510 + #define TFDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0xC8))) 511 511 + #define TFDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0xCC))) 512 512 + #define TFPRE (*((REG32_PTR_T)(TIMER_BASE + 0xD0))) 513 513 + #define TFCNT (*((REG32_PTR_T)(TIMER_BASE + 0xD4))) 514 514 + #define TGCON (*((REG32_PTR_T)(TIMER_BASE + 0xE0))) 515 515 + #define TGCMD (*((REG32_PTR_T)(TIMER_BASE + 0xE4))) 516 516 + #define TGDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0xE8))) 517 517 + #define TGDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0xEC))) 518 518 + #define TGPRE (*((REG32_PTR_T)(TIMER_BASE + 0xF0))) 519 519 + #define TGCNT (*((REG32_PTR_T)(TIMER_BASE + 0xF4))) 520 520 + #define THCON (*((REG32_PTR_T)(TIMER_BASE + 0x100))) 521 521 + #define THCMD (*((REG32_PTR_T)(TIMER_BASE + 0x104))) 522 522 + #define THDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0x108))) 523 523 + #define THDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0x10C))) 524 524 + #define THPRE (*((REG32_PTR_T)(TIMER_BASE + 0x110))) 525 525 + #define THCNT (*((REG32_PTR_T)(TIMER_BASE + 0x114))) 526 526 + #define TSTAT (*((REG32_PTR_T)(TIMER_BASE + 0x118))) 527 527 + 510 528 #define USEC_TIMER TECNT 511 529 #endif 512 530 ··· 588 606 589 607 /* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */ 590 608 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 591 591 - #define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */ 592 592 - #define SDCI_DCTRL (*(REG32_PTR_T)(0x3C300004)) /* Data Control Register */ 593 593 - #define SDCI_CMD (*(REG32_PTR_T)(0x3C300008)) /* Command Register */ 594 594 - #define SDCI_ARGU (*(REG32_PTR_T)(0x3C30000C)) /* Argument Register */ 595 595 - #define SDCI_STATE (*(REG32_PTR_T)(0x3C300010)) /* State Register */ 596 596 - #define SDCI_STAC (*(REG32_PTR_T)(0x3C300014)) /* Status Clear Register */ 597 597 - #define SDCI_DSTA (*(REG32_PTR_T)(0x3C300018)) /* Data Status Register */ 598 598 - #define SDCI_FSTA (*(REG32_PTR_T)(0x3C30001C)) /* FIFO Status Register */ 599 599 - #define SDCI_RESP0 (*(REG32_PTR_T)(0x3C300020)) /* Response0 Register */ 600 600 - #define SDCI_RESP1 (*(REG32_PTR_T)(0x3C300024)) /* Response1 Register */ 601 601 - #define SDCI_RESP2 (*(REG32_PTR_T)(0x3C300028)) /* Response2 Register */ 602 602 - #define SDCI_RESP3 (*(REG32_PTR_T)(0x3C30002C)) /* Response3 Register */ 603 603 - #define SDCI_CLKDIV (*(REG32_PTR_T)(0x3C300030)) /* Clock Divider Register */ 604 604 - #define SDIO_CSR (*(REG32_PTR_T)(0x3C300034)) /* SDIO Control & Status Register */ 605 605 - #define SDIO_IRQ (*(REG32_PTR_T)(0x3C300038)) /* Interrupt Source Register */ 609 609 + #define SDCI_BASE 0x3C300000 606 610 #elif CONFIG_CPU==S5L8702 607 607 - #define SDCI_CTRL (*((REG32_PTR_T)(0x38b00000))) 608 608 - #define SDCI_DCTRL (*((REG32_PTR_T)(0x38b00004))) 609 609 - #define SDCI_CMD (*((REG32_PTR_T)(0x38b00008))) 610 610 - #define SDCI_ARGU (*((REG32_PTR_T)(0x38b0000c))) 611 611 - #define SDCI_STATE (*((REG32_PTR_T)(0x38b00010))) 612 612 - #define SDCI_STAC (*((REG32_PTR_T)(0x38b00014))) 613 613 - #define SDCI_DSTA (*((REG32_PTR_T)(0x38b00018))) 614 614 - #define SDCI_FSTA (*((REG32_PTR_T)(0x38b0001c))) 615 615 - #define SDCI_RESP0 (*((REG32_PTR_T)(0x38b00020))) 616 616 - #define SDCI_RESP1 (*((REG32_PTR_T)(0x38b00024))) 617 617 - #define SDCI_RESP2 (*((REG32_PTR_T)(0x38b00028))) 618 618 - #define SDCI_RESP3 (*((REG32_PTR_T)(0x38b0002c))) 619 619 - #define SDCI_CDIV (*((REG32_PTR_T)(0x38b00030))) 620 620 - #define SDCI_SDIO_CSR (*((REG32_PTR_T)(0x38b00034))) 621 621 - #define SDCI_IRQ (*((REG32_PTR_T)(0x38b00038))) 622 622 - #define SDCI_IRQ_MASK (*((REG32_PTR_T)(0x38b0003c))) 623 623 - #define SDCI_DATA (*((REG32_PTR_T)(0x38b00040))) 624 624 - #define SDCI_DMAADDR (*((void* volatile*)(0x38b00044))) 625 625 - #define SDCI_DMASIZE (*((REG32_PTR_T)(0x38b00048))) 626 626 - #define SDCI_DMACOUNT (*((REG32_PTR_T)(0x38b0004c))) 627 627 - #define SDCI_RESET (*((REG32_PTR_T)(0x38b0006c))) 611 611 + #define SDCI_BASE 0x38b00000 612 612 + #endif 613 613 + 614 614 + #define SDCI_CTRL (*(REG32_PTR_T)(SDCI_BASE)) /* Control Register */ 615 615 + #define SDCI_DCTRL (*(REG32_PTR_T)(SDCI_BASE + 0x04)) /* Data Control Register */ 616 616 + #define SDCI_CMD (*(REG32_PTR_T)(SDCI_BASE + 0x08)) /* Command Register */ 617 617 + #define SDCI_ARGU (*(REG32_PTR_T)(SDCI_BASE + 0x0C)) /* Argument Register */ 618 618 + #define SDCI_STATE (*(REG32_PTR_T)(SDCI_BASE + 0x10)) /* State Register */ 619 619 + #define SDCI_STAC (*(REG32_PTR_T)(SDCI_BASE + 0x14)) /* Status Clear Register */ 620 620 + #define SDCI_DSTA (*(REG32_PTR_T)(SDCI_BASE + 0x18)) /* Data Status Register */ 621 621 + #define SDCI_FSTA (*(REG32_PTR_T)(SDCI_BASE + 0x1C)) /* FIFO Status Register */ 622 622 + #define SDCI_RESP0 (*(REG32_PTR_T)(SDCI_BASE + 0x20)) /* Response0 Register */ 623 623 + #define SDCI_RESP1 (*(REG32_PTR_T)(SDCI_BASE + 0x24)) /* Response1 Register */ 624 624 + #define SDCI_RESP2 (*(REG32_PTR_T)(SDCI_BASE + 0x28)) /* Response2 Register */ 625 625 + #define SDCI_RESP3 (*(REG32_PTR_T)(SDCI_BASE + 0x2C)) /* Response3 Register */ 626 626 + #define SDCI_CLKDIV (*(REG32_PTR_T)(SDCI_BASE + 0x30)) /* Clock Divider Register */ 627 627 + #define SDIO_CSR (*(REG32_PTR_T)(SDCI_BASE + 0x34)) /* SDIO Control & Status Register */ 628 628 + #define SDCI_IRQ (*(REG32_PTR_T)(SDCI_BASE + 0x38)) /* Interrupt Source Register */ 629 629 + #define SDCI_IRQ_MASK (*(REG32_PTR_T)(SDCI_BASE + 0x3c)) 630 630 + 631 631 + #if CONFIG_CPU==S5L8702 632 632 + #define SDCI_DATA (*(REG32_PTR_T)(SDCI_BASE + 0x40)) 633 633 + #define SDCI_DMAADDR (*(VOID_PTR_PTR_T)(SDCI_BASE + 0x44)) 634 634 + #define SDCI_DMASIZE (*(REG32_PTR_T)(SDCI_BASE + 0x48)) 635 635 + #define SDCI_DMACOUNT (*(REG32_PTR_T)(SDCI_BASE + 0x4c)) 636 636 + #define SDCI_RESET (*(REG32_PTR_T)(SDCI_BASE + 0x6c)) 637 637 + #endif 628 638 629 639 #define SDCI_CTRL_SDCIEN BIT(0) 630 640 #define SDCI_CTRL_CARD_TYPE_MASK BIT(1) ··· 785 795 #define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0) 786 796 #define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1) 787 797 #define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2) 788 788 - #endif 789 798 790 799 /* 14. MEMORY STICK HOST CONTROLLER */ 791 791 - #define MSPRE (*(REG32_PTR_T)(0x3C600000)) /* Prescaler Register */ 792 792 - #define MSINTEN (*(REG32_PTR_T)(0x3C600004)) /* Interrupt Enable Register */ 793 793 - #define MSCMD (*(REG32_PTR_T)(0x3C601000)) /* Command Register */ 794 794 - #define MSFIFO (*(REG32_PTR_T)(0x3C601008)) /* Receive/Transmit Register */ 795 795 - #define MSPP (*(REG32_PTR_T)(0x3C601010)) /* Parallel Port Control/Data Register */ 796 796 - #define MSCTRL2 (*(REG32_PTR_T)(0x3C601014)) /* Control Register 2 */ 797 797 - #define MSACD (*(REG32_PTR_T)(0x3C601018)) /* ACD Command Register */ 800 800 + #define MS_BASE 0x3C600000 801 801 + #define MS_CMD_BASE (MS_BASE + 0x1000) 802 802 + 803 803 + #define MSPRE (*(REG32_PTR_T)(MS_BASE)) /* Prescaler Register */ 804 804 + #define MSINTEN (*(REG32_PTR_T)(MS_BASE + 0x04)) /* Interrupt Enable Register */ 805 805 + #define MSCMD (*(REG32_PTR_T)(MS_CMD_BASE)) /* Command Register */ 806 806 + #define MSFIFO (*(REG32_PTR_T)(MS_CMD_BASE + 0x08)) /* Receive/Transmit Register */ 807 807 + #define MSPP (*(REG32_PTR_T)(MS_CMD_BASE + 0x10)) /* Parallel Port Control/Data Register */ 808 808 + #define MSCTRL2 (*(REG32_PTR_T)(MS_CMD_BASE + 0x14)) /* Control Register 2 */ 809 809 + #define MSACD (*(REG32_PTR_T)(MS_CMD_BASE + 0x18)) /* ACD Command Register */ 798 810 799 811 /* 15. SPDIF TRANSMITTER (SPDIFOUT) */ 800 800 - #define SPDCLKCON (*(REG32_PTR_T)(0x3CB00000)) /* Clock Control Register */ 801 801 - #define SPDCON (*(REG32_PTR_T)(0x3CB00004)) /* Control Register 0020 */ 802 802 - #define SPDBSTAS (*(REG32_PTR_T)(0x3CB00008)) /* Burst Status Register */ 803 803 - #define SPDCSTAS (*(REG32_PTR_T)(0x3CB0000C)) /* Channel Status Register 0x2000 8000 */ 804 804 - #define SPDDAT (*(REG32_PTR_T)(0x3CB00010)) /* SPDIFOUT Data Buffer */ 805 805 - #define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */ 812 812 + #define SPD_BASE 0x3CB00000 813 813 + 814 814 + #define SPDCLKCON (*(REG32_PTR_T)(SPD_BASE)) /* Clock Control Register */ 815 815 + #define SPDCON (*(REG32_PTR_T)(SPD_BASE + 0x04)) /* Control Register 0020 */ 816 816 + #define SPDBSTAS (*(REG32_PTR_T)(SPD_BASE + 0x08)) /* Burst Status Register */ 817 817 + #define SPDCSTAS (*(REG32_PTR_T)(SPD_BASE + 0x0C)) /* Channel Status Register 0x2000 8000 */ 818 818 + #define SPDDAT (*(REG32_PTR_T)(SPD_BASE + 0x10)) /* SPDIFOUT Data Buffer */ 819 819 + #define SPDCNT (*(REG32_PTR_T)(SPD_BASE + 0x14)) /* Repetition Count Register */ 806 820 807 821 /* 16. REED-SOLOMON ECC CODEC */ 808 808 - #define ECC_DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */ 809 809 - #define ECC_SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */ 810 810 - #define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */ 811 811 - #define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */ 812 812 - #define ECC_UNK1 (*(REG32_PTR_T)(0x39E00014)) /* No idea what this is, but the OFW uses it on S5L8701 */ 813 813 - #define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */ 814 814 - #define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */ 815 815 - #define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */ 816 816 - #define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */ 817 817 - #define ECC_PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */ 818 818 - #define ECC_PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */ 819 819 - #define ECC_PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */ 820 820 - #define ECC_INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */ 821 821 - #define ECC_SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */ 822 822 - #define ECC_SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */ 823 823 - #define ECC_SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */ 822 822 + #define ECC_BASE 0x39E00000 823 823 + 824 824 + #define ECC_DATA_PTR (*(REG32_PTR_T)(ECC_BASE + 0x04)) /* Data Area Start Pointer */ 825 825 + #define ECC_SPARE_PTR (*(REG32_PTR_T)(ECC_BASE + 0x08)) /* Spare Area Start Pointer */ 826 826 + #define ECC_CTRL (*(REG32_PTR_T)(ECC_BASE + 0x0C)) /* ECC Control Register */ 827 827 + #define ECC_RESULT (*(REG32_PTR_T)(ECC_BASE + 0x10)) /* ECC Result */ 828 828 + #define ECC_UNK1 (*(REG32_PTR_T)(ECC_BASE + 0x14)) /* No idea what this is, but the OFW uses it on S5L8701 */ 829 829 + #define ECC_EVAL0 (*(REG32_PTR_T)(ECC_BASE + 0x20)) /* Error Eval0 Poly */ 830 830 + #define ECC_EVAL1 (*(REG32_PTR_T)(ECC_BASE + 0x24)) /* Error Eval1 Poly */ 831 831 + #define ECC_LOC0 (*(REG32_PTR_T)(ECC_BASE + 0x28)) /* Error Loc0 Poly */ 832 832 + #define ECC_LOC1 (*(REG32_PTR_T)(ECC_BASE + 0x2C)) /* Error Loc1 Poly */ 833 833 + #define ECC_PARITY0 (*(REG32_PTR_T)(ECC_BASE + 0x30)) /* Encode Parity0 Poly */ 834 834 + #define ECC_PARITY1 (*(REG32_PTR_T)(ECC_BASE + 0x34)) /* Encode Pariyt1 Poly */ 835 835 + #define ECC_PARITY2 (*(REG32_PTR_T)(ECC_BASE + 0x38)) /* Encode Parity2 Poly */ 836 836 + #define ECC_INT_CLR (*(REG32_PTR_T)(ECC_BASE + 0x40)) /* Interrupt Clear Register */ 837 837 + #define ECC_SYND0 (*(REG32_PTR_T)(ECC_BASE + 0x44)) /* Syndrom0 Poly */ 838 838 + #define ECC_SYND1 (*(REG32_PTR_T)(ECC_BASE + 0x48)) /* Syndrom1 Poly */ 839 839 + #define ECC_SYND2 (*(REG32_PTR_T)(ECC_BASE + 0x4C)) /* Syndrom2 Poly */ 824 840 #define ECCCTRL_STARTDECODING (1 << 0) 825 841 #define ECCCTRL_STARTENCODING (1 << 1) 826 842 #define ECCCTRL_STARTDECNOSYND (1 << 2) 827 843 828 844 /* 17. IIS Tx/Rx INTERFACE */ 829 829 - #define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */ 830 830 - #define I2STXCON (*(REG32_PTR_T)(0x3CA00004)) /* Tx configuration Register */ 831 831 - #define I2STXCOM (*(REG32_PTR_T)(0x3CA00008)) /* Tx command Register */ 832 832 - #define I2STXDB0 (*(REG32_PTR_T)(0x3CA00010)) /* Tx data buffer */ 833 833 - #define I2SRXCON (*(REG32_PTR_T)(0x3CA00030)) /* Rx configuration Register */ 834 834 - #define I2SRXCOM (*(REG32_PTR_T)(0x3CA00034)) /* Rx command Register */ 835 835 - #define I2SRXDB (*(REG32_PTR_T)(0x3CA00038)) /* Rx data buffer */ 836 836 - #define I2SSTATUS (*(REG32_PTR_T)(0x3CA0003C)) /* status register */ 845 845 + #define I2S_BASE 0x3CA00000 846 846 + 847 847 + #define I2SCLKCON (*(REG32_PTR_T)(I2S_BASE)) /* Clock Control Register */ 848 848 + #define I2STXCON (*(REG32_PTR_T)(I2S_BASE + 0x04)) /* Tx configuration Register */ 849 849 + #define I2STXCOM (*(REG32_PTR_T)(I2S_BASE + 0x08)) /* Tx command Register */ 850 850 + #define I2STXDB0 (*(REG32_PTR_T)(I2S_BASE + 0x10)) /* Tx data buffer */ 851 851 + #define I2SRXCON (*(REG32_PTR_T)(I2S_BASE + 0x30)) /* Rx configuration Register */ 852 852 + #define I2SRXCOM (*(REG32_PTR_T)(I2S_BASE + 0x34)) /* Rx command Register */ 853 853 + #define I2SRXDB (*(REG32_PTR_T)(I2S_BASE + 0x38)) /* Rx data buffer */ 854 854 + #define I2SSTATUS (*(REG32_PTR_T)(I2S_BASE + 0x3C)) /* status register */ 837 855 838 856 #if CONFIG_CPU==S5L8702 839 839 - #define I2SCLKDIV (*(REG32_PTR_T)(0x3CA00040)) 857 857 + #define I2SCLKDIV (*(REG32_PTR_T)(I2S_BASE + 0x40)) 840 858 841 859 #define I2SCLKGATE(i) ((i) == 2 ? CLOCKGATE_I2S2 : \ 842 860 (i) == 1 ? CLOCKGATE_I2S1 : \ ··· 845 863 846 864 /* 18. IIC BUS INTERFACE */ 847 865 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 848 848 - #define IICCON (*(REG32_PTR_T)(0x3C900000)) /* Control Register */ 849 849 - #define IICSTAT (*(REG32_PTR_T)(0x3C900004)) /* Control/Status Register */ 850 850 - #define IICADD (*(REG32_PTR_T)(0x3C900008)) /* Bus Address Register */ 851 851 - #define IICDS (*(REG32_PTR_T)(0x3C90000C)) 866 866 + #define IIC_BASE 0x3C900000 867 867 + 868 868 + #define IICCON (*(REG32_PTR_T)(IIC_BASE)) /* Control Register */ 869 869 + #define IICSTAT (*(REG32_PTR_T)(IIC_BASE + 0x04)) /* Control/Status Register */ 870 870 + #define IICADD (*(REG32_PTR_T)(IIC_BASE + 0x08)) /* Bus Address Register */ 871 871 + #define IICDS (*(REG32_PTR_T)(IIC_BASE + 0x0C)) 852 872 #elif CONFIG_CPU==S5L8702 853 853 - #define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \ 854 854 - CLOCKGATE_I2C0) 855 855 - 856 873 /* s5l8702 I2C controller is similar to s5l8700, known differences are: 857 874 858 875 * IICCON[5] is not used in s5l8702. ··· 866 883 transmited or received, in Master mode the tx/rx of the next byte 867 884 starts when it is written as "1". 868 885 */ 886 886 + #define IIC_BASE 0x3C600000 869 887 870 870 - #define IICCON(bus) (*((REG32_PTR_T)(0x3C600000 + 0x300000 * (bus)))) 871 871 - #define IICSTAT(bus) (*((REG32_PTR_T)(0x3C600004 + 0x300000 * (bus)))) 872 872 - #define IICADD(bus) (*((REG32_PTR_T)(0x3C600008 + 0x300000 * (bus)))) 873 873 - #define IICDS(bus) (*((REG32_PTR_T)(0x3C60000C + 0x300000 * (bus)))) 874 874 - #define IICUNK10(bus) (*((REG32_PTR_T)(0x3C600010 + 0x300000 * (bus)))) 875 875 - #define IICUNK14(bus) (*((REG32_PTR_T)(0x3C600014 + 0x300000 * (bus)))) 876 876 - #define IICUNK18(bus) (*((REG32_PTR_T)(0x3C600018 + 0x300000 * (bus)))) 877 877 - #define IICSTA2(bus) (*((REG32_PTR_T)(0x3C600020 + 0x300000 * (bus)))) 888 888 + #define IICCON(bus) (*((REG32_PTR_T)(IIC_BASE + 0x300000 * (bus)))) 889 889 + #define IICSTAT(bus) (*((REG32_PTR_T)(IIC_BASE + 0x04 + 0x300000 * (bus)))) 890 890 + #define IICADD(bus) (*((REG32_PTR_T)(IIC_BASE + 0x08 + 0x300000 * (bus)))) 891 891 + #define IICDS(bus) (*((REG32_PTR_T)(IIC_BASE + 0x0C + 0x300000 * (bus)))) 892 892 + #define IICUNK10(bus) (*((REG32_PTR_T)(IIC_BASE + 0x10 + 0x300000 * (bus)))) 893 893 + #define IICUNK14(bus) (*((REG32_PTR_T)(IIC_BASE + 0x14 + 0x300000 * (bus)))) 894 894 + #define IICUNK18(bus) (*((REG32_PTR_T)(IIC_BASE + 0x18 + 0x300000 * (bus)))) 895 895 + #define IICSTA2(bus) (*((REG32_PTR_T)(IIC_BASE + 0x20 + 0x300000 * (bus)))) 896 896 + 897 897 + #define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \ 898 898 + CLOCKGATE_I2C0) 878 899 #endif 879 900 880 901 /* 19. SPI (SERIAL PERHIPERAL INTERFACE) */ 881 902 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 882 882 - #define SPCLKCON (*(REG32_PTR_T)(0x3CD00000)) /* Clock Control Register */ 883 883 - #define SPCON (*(REG32_PTR_T)(0x3CD00004)) /* Control Register */ 884 884 - #define SPSTA (*(REG32_PTR_T)(0x3CD00008)) /* Status Register */ 885 885 - #define SPPIN (*(REG32_PTR_T)(0x3CD0000C)) /* Pin Control Register */ 886 886 - #define SPTDAT (*(REG32_PTR_T)(0x3CD00010)) /* Tx Data Register */ 887 887 - #define SPRDAT (*(REG32_PTR_T)(0x3CD00014)) /* Rx Data Register */ 888 888 - #define SPPRE (*(REG32_PTR_T)(0x3CD00018)) /* Baud Rate Prescaler Register */ 903 903 + #define SPI_BASE 0x3CD00000 904 904 + 905 905 + #define SPCLKCON (*(REG32_PTR_T)(SPI_BASE)) /* Clock Control Register */ 906 906 + #define SPCON (*(REG32_PTR_T)(SPI_BASE + 0x04)) /* Control Register */ 907 907 + #define SPSTA (*(REG32_PTR_T)(SPI_BASE + 0x08)) /* Status Register */ 908 908 + #define SPPIN (*(REG32_PTR_T)(SPI_BASE + 0x0C)) /* Pin Control Register */ 909 909 + #define SPTDAT (*(REG32_PTR_T)(SPI_BASE + 0x10)) /* Tx Data Register */ 910 910 + #define SPRDAT (*(REG32_PTR_T)(SPI_BASE + 0x14)) /* Rx Data Register */ 911 911 + #define SPPRE (*(REG32_PTR_T)(SPI_BASE + 0x18)) /* Baud Rate Prescaler Register */ 889 912 #elif CONFIG_CPU==S5L8702 890 913 #define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \ 891 914 (i) == 1 ? 0x3ce00000 : \ ··· 908 931 #endif 909 932 910 933 /* 20. ADC CONTROLLER */ 911 911 - #define ADCCON (*(REG32_PTR_T)(0x3CE00000)) /* ADC Control Register */ 912 912 - #define ADCTSC (*(REG32_PTR_T)(0x3CE00004)) /* ADC Touch Screen Control Register */ 913 913 - #define ADCDLY (*(REG32_PTR_T)(0x3CE00008)) /* ADC Start or Interval Delay Register */ 914 914 - #define ADCDAT0 (*(REG32_PTR_T)(0x3CE0000C)) /* ADC Conversion Data Register */ 915 915 - #define ADCDAT1 (*(REG32_PTR_T)(0x3CE00010)) /* ADC Conversion Data Register */ 916 916 - #define ADCUPDN (*(REG32_PTR_T)(0x3CE00014)) /* Stylus Up or Down Interrpt Register */ 934 934 + #define ADC_BASE 0x3CE00000 935 935 + 936 936 + #define ADCCON (*(REG32_PTR_T)(ADC_BASE)) /* ADC Control Register */ 937 937 + #define ADCTSC (*(REG32_PTR_T)(ADC_BASE + 0x04)) /* ADC Touch Screen Control Register */ 938 938 + #define ADCDLY (*(REG32_PTR_T)(ADC_BASE + 0x08)) /* ADC Start or Interval Delay Register */ 939 939 + #define ADCDAT0 (*(REG32_PTR_T)(ADC_BASE + 0x0C)) /* ADC Conversion Data Register */ 940 940 + #define ADCDAT1 (*(REG32_PTR_T)(ADC_BASE + 0x10)) /* ADC Conversion Data Register */ 941 941 + #define ADCUPDN (*(REG32_PTR_T)(ADC_BASE + 0x14)) /* Stylus Up or Down Interrpt Register */ 917 942 918 943 /* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */ 919 919 - #define USB_IR (*(REG32_PTR_T)(0x38800000)) /* Index Register */ 920 920 - #define USB_EIR (*(REG32_PTR_T)(0x38800004)) /* Endpoint Interrupt Register */ 921 921 - #define USB_EIER (*(REG32_PTR_T)(0x38800008)) /* Endpoint Interrupt Enable Register */ 922 922 - #define USB_FAR (*(REG32_PTR_T)(0x3880000C)) /* Function Address Register */ 923 923 - #define USB_FNR (*(REG32_PTR_T)(0x38800010)) /* Frame Number Register */ 924 924 - #define USB_EDR (*(REG32_PTR_T)(0x38800014)) /* Endpoint Direction Register */ 925 925 - #define USB_TR (*(REG32_PTR_T)(0x38800018)) /* Test Register */ 926 926 - #define USB_SSR (*(REG32_PTR_T)(0x3880001C)) /* System Status Register */ 927 927 - #define USB_SCR (*(REG32_PTR_T)(0x38800020)) /* System Control Register */ 928 928 - #define USB_EP0SR (*(REG32_PTR_T)(0x38800024)) /* EP0 Status Register */ 929 929 - #define USB_EP0CR (*(REG32_PTR_T)(0x38800028)) /* EP0 Control Register */ 930 930 - #define USB_ESR (*(REG32_PTR_T)(0x3880002C)) /* Endpoints Status Register */ 931 931 - #define USB_ECR (*(REG32_PTR_T)(0x38800030)) /* Endpoints Control Register */ 932 932 - #define USB_BRCR (*(REG32_PTR_T)(0x38800034)) /* Byte Read Count Register */ 933 933 - #define USB_BWCR (*(REG32_PTR_T)(0x38800038)) /* Byte Write Count Register */ 934 934 - #define USB_MPR (*(REG32_PTR_T)(0x3880003C)) /* Max Packet Register */ 935 935 - #define USB_MCR (*(REG32_PTR_T)(0x38800040)) /* Master Control Register */ 936 936 - #define USB_MTCR (*(REG32_PTR_T)(0x38800044)) /* Master Transfer Counter Register */ 937 937 - #define USB_MFCR (*(REG32_PTR_T)(0x38800048)) /* Master FIFO Counter Register */ 938 938 - #define USB_MTTCR1 (*(REG32_PTR_T)(0x3880004C)) /* Master Total Transfer Counter1 Register */ 939 939 - #define USB_MTTCR2 (*(REG32_PTR_T)(0x38800050)) /* Master Total Transfer Counter2 Register */ 940 940 - #define USB_EP0BR (*(REG32_PTR_T)(0x38800060)) /* EP0 Buffer Register */ 941 941 - #define USB_EP1BR (*(REG32_PTR_T)(0x38800064)) /* EP1 Buffer Register */ 942 942 - #define USB_EP2BR (*(REG32_PTR_T)(0x38800068)) /* EP2 Buffer Register */ 943 943 - #define USB_EP3BR (*(REG32_PTR_T)(0x3880006C)) /* EP3 Buffer Register */ 944 944 - #define USB_EP4BR (*(REG32_PTR_T)(0x38800070)) /* EP4 Buffer Register */ 945 945 - #define USB_EP5BR (*(REG32_PTR_T)(0x38800074)) /* EP5 Buffer Register */ 946 946 - #define USB_EP6BR (*(REG32_PTR_T)(0x38800078)) /* EP6 Buffer Register */ 947 947 - #define USB_MICR (*(REG32_PTR_T)(0x38800084)) /* Master Interface Counter Register */ 948 948 - #define USB_MBAR1 (*(REG32_PTR_T)(0x38800088)) /* Memory Base Address Register1 */ 949 949 - #define USB_MBAR2 (*(REG32_PTR_T)(0x3880008C)) /* Memory Base Address Register2 */ 950 950 - #define USB_MCAR1 (*(REG32_PTR_T)(0x38800094)) /* Memory Current Address Register1 */ 951 951 - #define USB_MCAR2 (*(REG32_PTR_T)(0x38800098)) /* Memory Current Address Register2 */ 944 944 + #define USB_FC_BASE 0x38800000 945 945 + 946 946 + #define USB_IR (*(REG32_PTR_T)(USB_FC_BASE)) /* Index Register */ 947 947 + #define USB_EIR (*(REG32_PTR_T)(USB_FC_BASE + 0x04)) /* Endpoint Interrupt Register */ 948 948 + #define USB_EIER (*(REG32_PTR_T)(USB_FC_BASE + 0x08)) /* Endpoint Interrupt Enable Register */ 949 949 + #define USB_FAR (*(REG32_PTR_T)(USB_FC_BASE + 0x0C)) /* Function Address Register */ 950 950 + #define USB_FNR (*(REG32_PTR_T)(USB_FC_BASE + 0x10)) /* Frame Number Register */ 951 951 + #define USB_EDR (*(REG32_PTR_T)(USB_FC_BASE + 0x14)) /* Endpoint Direction Register */ 952 952 + #define USB_TR (*(REG32_PTR_T)(USB_FC_BASE + 0x18)) /* Test Register */ 953 953 + #define USB_SSR (*(REG32_PTR_T)(USB_FC_BASE + 0x1C)) /* System Status Register */ 954 954 + #define USB_SCR (*(REG32_PTR_T)(USB_FC_BASE + 0x20)) /* System Control Register */ 955 955 + #define USB_EP0SR (*(REG32_PTR_T)(USB_FC_BASE + 0x24)) /* EP0 Status Register */ 956 956 + #define USB_EP0CR (*(REG32_PTR_T)(USB_FC_BASE + 0x28)) /* EP0 Control Register */ 957 957 + #define USB_ESR (*(REG32_PTR_T)(USB_FC_BASE + 0x2C)) /* Endpoints Status Register */ 958 958 + #define USB_ECR (*(REG32_PTR_T)(USB_FC_BASE + 0x30)) /* Endpoints Control Register */ 959 959 + #define USB_BRCR (*(REG32_PTR_T)(USB_FC_BASE + 0x34)) /* Byte Read Count Register */ 960 960 + #define USB_BWCR (*(REG32_PTR_T)(USB_FC_BASE + 0x38)) /* Byte Write Count Register */ 961 961 + #define USB_MPR (*(REG32_PTR_T)(USB_FC_BASE + 0x3C)) /* Max Packet Register */ 962 962 + #define USB_MCR (*(REG32_PTR_T)(USB_FC_BASE + 0x40)) /* Master Control Register */ 963 963 + #define USB_MTCR (*(REG32_PTR_T)(USB_FC_BASE + 0x44)) /* Master Transfer Counter Register */ 964 964 + #define USB_MFCR (*(REG32_PTR_T)(USB_FC_BASE + 0x48)) /* Master FIFO Counter Register */ 965 965 + #define USB_MTTCR1 (*(REG32_PTR_T)(USB_FC_BASE + 0x4C)) /* Master Total Transfer Counter1 Register */ 966 966 + #define USB_MTTCR2 (*(REG32_PTR_T)(USB_FC_BASE + 0x50)) /* Master Total Transfer Counter2 Register */ 967 967 + #define USB_EP0BR (*(REG32_PTR_T)(USB_FC_BASE + 0x60)) /* EP0 Buffer Register */ 968 968 + #define USB_EP1BR (*(REG32_PTR_T)(USB_FC_BASE + 0x64)) /* EP1 Buffer Register */ 969 969 + #define USB_EP2BR (*(REG32_PTR_T)(USB_FC_BASE + 0x68)) /* EP2 Buffer Register */ 970 970 + #define USB_EP3BR (*(REG32_PTR_T)(USB_FC_BASE + 0x6C)) /* EP3 Buffer Register */ 971 971 + #define USB_EP4BR (*(REG32_PTR_T)(USB_FC_BASE + 0x70)) /* EP4 Buffer Register */ 972 972 + #define USB_EP5BR (*(REG32_PTR_T)(USB_FC_BASE + 0x74)) /* EP5 Buffer Register */ 973 973 + #define USB_EP6BR (*(REG32_PTR_T)(USB_FC_BASE + 0x78)) /* EP6 Buffer Register */ 974 974 + #define USB_MICR (*(REG32_PTR_T)(USB_FC_BASE + 0x84)) /* Master Interface Counter Register */ 975 975 + #define USB_MBAR1 (*(REG32_PTR_T)(USB_FC_BASE + 0x88)) /* Memory Base Address Register1 */ 976 976 + #define USB_MBAR2 (*(REG32_PTR_T)(USB_FC_BASE + 0x8C)) /* Memory Base Address Register2 */ 977 977 + #define USB_MCAR1 (*(REG32_PTR_T)(USB_FC_BASE + 0x94)) /* Memory Current Address Register1 */ 978 978 + #define USB_MCAR2 (*(REG32_PTR_T)(USB_FC_BASE + 0x98)) /* Memory Current Address Register2 */ 952 979 953 980 /* 22. USB 1.1 HOST CONTROLLER SPECIAL REGISTER */ 954 954 - #define HcRevision (*(REG32_PTR_T)(0x38600000)) 955 955 - #define HcControl (*(REG32_PTR_T)(0x38600004)) 956 956 - #define HcCommandStatus (*(REG32_PTR_T)(0x38600008)) 957 957 - #define HcInterruptStatus (*(REG32_PTR_T)(0x3860000C)) 958 958 - #define HcInterruptEnable (*(REG32_PTR_T)(0x38600010)) 959 959 - #define HcInterruptDisable (*(REG32_PTR_T)(0x38600014)) 960 960 - #define HcHCCA (*(REG32_PTR_T)(0x38600018)) 961 961 - #define HcPeriodCurrentED (*(REG32_PTR_T)(0x3860001C)) 962 962 - #define HcControlHeadED (*(REG32_PTR_T)(0x38600020)) 963 963 - #define HcControlCurrentED (*(REG32_PTR_T)(0x38600024)) 964 964 - #define HcBulkHeadED (*(REG32_PTR_T)(0x38600028)) 965 965 - #define HcBulkCurrentED (*(REG32_PTR_T)(0x3860002C)) 966 966 - #define HcDoneHead (*(REG32_PTR_T)(0x38600030)) 967 967 - #define HcFmInterval (*(REG32_PTR_T)(0x38600034)) 968 968 - #define HcFmRemaining (*(REG32_PTR_T)(0x38600038)) 969 969 - #define HcFmNumber (*(REG32_PTR_T)(0x3860003C)) 970 970 - #define HcPeriodicStart (*(REG32_PTR_T)(0x38600040)) 971 971 - #define HcLSThreshold (*(REG32_PTR_T)(0x38600044)) 972 972 - #define HcRhDescriptorA (*(REG32_PTR_T)(0x38600048)) 973 973 - #define HcRhDescriptorB (*(REG32_PTR_T)(0x3860004C)) 974 974 - #define HcRhStatus (*(REG32_PTR_T)(0x38600050)) 975 975 - #define HcRhPortStatus (*(REG32_PTR_T)(0x38600054)) 981 981 + #define USB_HC_BASE 0x38600000 982 982 + 983 983 + #define HcRevision (*(REG32_PTR_T)(USB_HC_BASE)) 984 984 + #define HcControl (*(REG32_PTR_T)(USB_HC_BASE + 0x04)) 985 985 + #define HcCommandStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x08)) 986 986 + #define HcInterruptStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x0C)) 987 987 + #define HcInterruptEnable (*(REG32_PTR_T)(USB_HC_BASE + 0x10)) 988 988 + #define HcInterruptDisable (*(REG32_PTR_T)(USB_HC_BASE + 0x14)) 989 989 + #define HcHCCA (*(REG32_PTR_T)(USB_HC_BASE + 0x18)) 990 990 + #define HcPeriodCurrentED (*(REG32_PTR_T)(USB_HC_BASE + 0x1C)) 991 991 + #define HcControlHeadED (*(REG32_PTR_T)(USB_HC_BASE + 0x20)) 992 992 + #define HcControlCurrentED (*(REG32_PTR_T)(USB_HC_BASE + 0x24)) 993 993 + #define HcBulkHeadED (*(REG32_PTR_T)(USB_HC_BASE + 0x28)) 994 994 + #define HcBulkCurrentED (*(REG32_PTR_T)(USB_HC_BASE + 0x2C)) 995 995 + #define HcDoneHead (*(REG32_PTR_T)(USB_HC_BASE + 0x30)) 996 996 + #define HcFmInterval (*(REG32_PTR_T)(USB_HC_BASE + 0x34)) 997 997 + #define HcFmRemaining (*(REG32_PTR_T)(USB_HC_BASE + 0x38)) 998 998 + #define HcFmNumber (*(REG32_PTR_T)(USB_HC_BASE + 0x3C)) 999 999 + #define HcPeriodicStart (*(REG32_PTR_T)(USB_HC_BASE + 0x40)) 1000 1000 + #define HcLSThreshold (*(REG32_PTR_T)(USB_HC_BASE + 0x44)) 1001 1001 + #define HcRhDescriptorA (*(REG32_PTR_T)(USB_HC_BASE + 0x48)) 1002 1002 + #define HcRhDescriptorB (*(REG32_PTR_T)(USB_HC_BASE + 0x4C)) 1003 1003 + #define HcRhStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x50)) 1004 1004 + #define HcRhPortStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x54)) 976 1005 977 1006 /* 23. USB 2.0 PHY CONTROL */ 978 978 - #define PHYCTRL (*(REG32_PTR_T)(0x3C400000)) /* USB2.0 PHY Control Register */ 979 979 - #define PHYPWR (*(REG32_PTR_T)(0x3C400004)) /* USB2.0 PHY Power Control Register */ 980 980 - #define URSTCON (*(REG32_PTR_T)(0x3C400008)) /* USB Reset Control Register */ 981 981 - #define UCLKCON (*(REG32_PTR_T)(0x3C400010)) /* USB Clock Control Register */ 1007 1007 + #define USB_PHY_BASE 0x3C400000 1008 1008 + 1009 1009 + #define PHYCTRL (*(REG32_PTR_T)(USB_PHY_BASE)) /* USB2.0 PHY Control Register */ 1010 1010 + #define PHYPWR (*(REG32_PTR_T)(USB_PHY_BASE + 0x04)) /* USB2.0 PHY Power Control Register */ 1011 1011 + #define URSTCON (*(REG32_PTR_T)(USB_PHY_BASE + 0x08)) /* USB Reset Control Register */ 1012 1012 + #define UCLKCON (*(REG32_PTR_T)(USB_PHY_BASE + 0x10)) /* USB Clock Control Register */ 982 1013 983 1014 /* 24. GPIO PORT CONTROL */ 1015 1015 + #define GPIO_BASE 0x3CF00000 1016 1016 + 984 1017 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 985 985 - #define PCON0 (*(REG32_PTR_T)(0x3CF00000)) /* Configures the pins of port 0 */ 986 986 - #define PDAT0 (*(REG32_PTR_T)(0x3CF00004)) /* The data register for port 0 */ 987 987 - #define PCON1 (*(REG32_PTR_T)(0x3CF00010)) /* Configures the pins of port 1 */ 988 988 - #define PDAT1 (*(REG32_PTR_T)(0x3CF00014)) /* The data register for port 1 */ 989 989 - #define PCON2 (*(REG32_PTR_T)(0x3CF00020)) /* Configures the pins of port 2 */ 990 990 - #define PDAT2 (*(REG32_PTR_T)(0x3CF00024)) /* The data register for port 2 */ 991 991 - #define PCON3 (*(REG32_PTR_T)(0x3CF00030)) /* Configures the pins of port 3 */ 992 992 - #define PDAT3 (*(REG32_PTR_T)(0x3CF00034)) /* The data register for port 3 */ 993 993 - #define PCON4 (*(REG32_PTR_T)(0x3CF00040)) /* Configures the pins of port 4 */ 994 994 - #define PDAT4 (*(REG32_PTR_T)(0x3CF00044)) /* The data register for port 4 */ 995 995 - #define PCON5 (*(REG32_PTR_T)(0x3CF00050)) /* Configures the pins of port 5 */ 996 996 - #define PDAT5 (*(REG32_PTR_T)(0x3CF00054)) /* The data register for port 5 */ 997 997 - #define PUNK5 (*(REG32_PTR_T)(0x3CF0005C)) /* Unknown thing for port 5 */ 998 998 - #define PCON6 (*(REG32_PTR_T)(0x3CF00060)) /* Configures the pins of port 6 */ 999 999 - #define PDAT6 (*(REG32_PTR_T)(0x3CF00064)) /* The data register for port 6 */ 1000 1000 - #define PCON7 (*(REG32_PTR_T)(0x3CF00070)) /* Configures the pins of port 7 */ 1001 1001 - #define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 7 */ 1002 1002 - #define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 10 */ 1003 1003 - #define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 10 */ 1004 1004 - #define PCON11 (*(REG32_PTR_T)(0x3CF000B0)) /* Configures the pins of port 11 */ 1005 1005 - #define PDAT11 (*(REG32_PTR_T)(0x3CF000B4)) /* The data register for port 11 */ 1006 1006 - #define PCON13 (*(REG32_PTR_T)(0x3CF000D0)) /* Configures the pins of port 13 */ 1007 1007 - #define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */ 1008 1008 - #define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */ 1009 1009 - #define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */ 1010 1010 - #define PCON15 (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port 15 */ 1011 1011 - #define PUNK15 (*(REG32_PTR_T)(0x3CF000FC)) /* Unknown thing for port 15 */ 1012 1012 - #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ 1013 1013 - #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ 1018 1018 + #define GPIO_OFFSET_BITS 4 1014 1019 #elif CONFIG_CPU==S5L8702 1015 1015 - #define PCON(i) (*((REG32_PTR_T)(0x3cf00000 + ((i) << 5)))) 1016 1016 - #define PDAT(i) (*((REG32_PTR_T)(0x3cf00004 + ((i) << 5)))) 1017 1017 - #define PUNA(i) (*((REG32_PTR_T)(0x3cf00008 + ((i) << 5)))) 1018 1018 - #define PUNB(i) (*((REG32_PTR_T)(0x3cf0000c + ((i) << 5)))) 1019 1019 - #define PUNC(i) (*((REG32_PTR_T)(0x3cf00010 + ((i) << 5)))) 1020 1020 - #define PCON0 (*((REG32_PTR_T)(0x3cf00000))) 1021 1021 - #define PDAT0 (*((REG32_PTR_T)(0x3cf00004))) 1022 1022 - #define PCON1 (*((REG32_PTR_T)(0x3cf00020))) 1023 1023 - #define PDAT1 (*((REG32_PTR_T)(0x3cf00024))) 1024 1024 - #define PCON2 (*((REG32_PTR_T)(0x3cf00040))) 1025 1025 - #define PDAT2 (*((REG32_PTR_T)(0x3cf00044))) 1026 1026 - #define PCON3 (*((REG32_PTR_T)(0x3cf00060))) 1027 1027 - #define PDAT3 (*((REG32_PTR_T)(0x3cf00064))) 1028 1028 - #define PCON4 (*((REG32_PTR_T)(0x3cf00080))) 1029 1029 - #define PDAT4 (*((REG32_PTR_T)(0x3cf00084))) 1030 1030 - #define PCON5 (*((REG32_PTR_T)(0x3cf000a0))) 1031 1031 - #define PDAT5 (*((REG32_PTR_T)(0x3cf000a4))) 1032 1032 - #define PCON6 (*((REG32_PTR_T)(0x3cf000c0))) 1033 1033 - #define PDAT6 (*((REG32_PTR_T)(0x3cf000c4))) 1034 1034 - #define PCON7 (*((REG32_PTR_T)(0x3cf000e0))) 1035 1035 - #define PDAT7 (*((REG32_PTR_T)(0x3cf000e4))) 1036 1036 - #define PCON8 (*((REG32_PTR_T)(0x3cf00100))) 1037 1037 - #define PDAT8 (*((REG32_PTR_T)(0x3cf00104))) 1038 1038 - #define PCON9 (*((REG32_PTR_T)(0x3cf00120))) 1039 1039 - #define PDAT9 (*((REG32_PTR_T)(0x3cf00124))) 1040 1040 - #define PCONA (*((REG32_PTR_T)(0x3cf00140))) 1041 1041 - #define PDATA (*((REG32_PTR_T)(0x3cf00144))) 1042 1042 - #define PCONB (*((REG32_PTR_T)(0x3cf00160))) 1043 1043 - #define PDATB (*((REG32_PTR_T)(0x3cf00164))) 1044 1044 - #define PCONC (*((REG32_PTR_T)(0x3cf00180))) 1045 1045 - #define PDATC (*((REG32_PTR_T)(0x3cf00184))) 1046 1046 - #define PCOND (*((REG32_PTR_T)(0x3cf001a0))) 1047 1047 - #define PDATD (*((REG32_PTR_T)(0x3cf001a4))) 1048 1048 - #define PCONE (*((REG32_PTR_T)(0x3cf001c0))) 1049 1049 - #define PDATE (*((REG32_PTR_T)(0x3cf001c4))) 1050 1050 - #define PCONF (*((REG32_PTR_T)(0x3cf001e0))) 1051 1051 - #define PDATF (*((REG32_PTR_T)(0x3cf001e4))) 1052 1052 - #define GPIOCMD (*((REG32_PTR_T)(0x3cf00200))) 1020 1020 + #define GPIO_OFFSET_BITS 5 1021 1021 + #endif 1022 1022 + 1023 1023 + #define PCON(i) (*((REG32_PTR_T)(GPIO_BASE + ((i) << GPIO_OFFSET_BITS)))) 1024 1024 + #define PDAT(i) (*((REG32_PTR_T)(GPIO_BASE + 0x04 + ((i) << GPIO_OFFSET_BITS)))) 1025 1025 + #define PUNA(i) (*((REG32_PTR_T)(GPIO_BASE + 0x08 + ((i) << GPIO_OFFSET_BITS)))) 1026 1026 + #define PUNB(i) (*((REG32_PTR_T)(GPIO_BASE + 0x0c + ((i) << GPIO_OFFSET_BITS)))) 1027 1027 + 1028 1028 + #if CONFIG_CPU==S5L8702 1029 1029 + #define PUNC(i) (*((REG32_PTR_T)(GPIO_BASE + 0x10 + ((i) << GPIO_OFFSET_BITS)))) 1030 1030 + #endif 1031 1031 + 1032 1032 + #define PCON0 PCON(0) /* Configures the pins of port 0 */ 1033 1033 + #define PDAT0 PDAT(0) /* The data register for port 0 */ 1034 1034 + #define PCON1 PCON(1) /* Configures the pins of port 1 */ 1035 1035 + #define PDAT1 PDAT(1) /* The data register for port 1 */ 1036 1036 + #define PCON2 PCON(2) /* Configures the pins of port 2 */ 1037 1037 + #define PDAT2 PDAT(2) /* The data register for port 2 */ 1038 1038 + #define PCON3 PCON(3) /* Configures the pins of port 3 */ 1039 1039 + #define PDAT3 PDAT(3) /* The data register for port 3 */ 1040 1040 + #define PCON4 PCON(4) /* Configures the pins of port 4 */ 1041 1041 + #define PDAT4 PDAT(4) /* The data register for port 4 */ 1042 1042 + #define PCON5 PCON(5) /* Configures the pins of port 5 */ 1043 1043 + #define PDAT5 PDAT(5) /* The data register for port 5 */ 1044 1044 + #define PUNK5 PUNB(5) /* Unknown thing for port 5 */ 1045 1045 + #define PCON6 PCON(6) /* Configures the pins of port 6 */ 1046 1046 + #define PDAT6 PDAT(6) /* The data register for port 6 */ 1047 1047 + #define PCON7 PCON(7) /* Configures the pins of port 7 */ 1048 1048 + #define PDAT7 PDAT(7) /* The data register for port 7 */ 1049 1049 + #define PCON10 PCON(10) /* Configures the pins of port 10 */ 1050 1050 + #define PDAT10 PDAT(10) /* The data register for port 10 */ 1051 1051 + #define PCON11 PCON(11) /* Configures the pins of port 11 */ 1052 1052 + #define PDAT11 PDAT(11) /* The data register for port 11 */ 1053 1053 + #define PCON12 PCON(12) /* Configures the pins of port 12 */ 1054 1054 + #define PDAT12 PDAT(12) /* The data register for port 12 */ 1055 1055 + #define PCON13 PCON(13) /* Configures the pins of port 13 */ 1056 1056 + #define PDAT13 PDAT(13) /* The data register for port 13 */ 1057 1057 + #define PCON14 PCON(14) /* Configures the pins of port 14 */ 1058 1058 + #define PDAT14 PDAT(14) /* The data register for port 14 */ 1059 1059 + #define PCON15 PCON(15) /* Configures the pins of port 15 */ 1060 1060 + #define PUNK15 PUNB(15) /* Unknown thing for port 15 */ 1061 1061 + 1062 1062 + #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 1063 1063 + #define PCON_ASRAM PCON15 /* Configures the pins of port nor flash */ 1064 1064 + #define PCON_SDRAM PDAT15 /* Configures the pins of port sdram */ 1065 1065 + #elif CONFIG_CPU==S5L8702 1066 1066 + #define GPIOCMD (*((REG32_PTR_T)(GPIO_BASE + 0x200))) 1053 1067 #endif 1054 1068 1055 1069 /* 25. UART */ 1056 1070 #if CONFIG_CPU==S5L8700 1057 1071 /* s5l8700 UC87XX HW: 1 UARTC, 2 ports */ 1058 1058 - #define S5L8700_N_UARTC 1 1059 1072 #define S5L8700_N_PORTS 2 1060 1073 1061 1074 #define UARTC_BASE_ADDR 0x3CC00000 1062 1075 #define UARTC_N_PORTS 2 1063 1076 #define UARTC_PORT_OFFSET 0x8000 1064 1064 - 1065 1065 - /* UART 0 */ 1066 1066 - #define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */ 1067 1067 - #define UCON0 (*(REG32_PTR_T)(0x3CC00004)) /* Control Register */ 1068 1068 - #define UFCON0 (*(REG32_PTR_T)(0x3CC00008)) /* FIFO Control Register */ 1069 1069 - #define UMCON0 (*(REG32_PTR_T)(0x3CC0000C)) /* Modem Control Register */ 1070 1070 - #define UTRSTAT0 (*(REG32_PTR_T)(0x3CC00010)) /* Tx/Rx Status Register */ 1071 1071 - #define UERSTAT0 (*(REG32_PTR_T)(0x3CC00014)) /* Rx Error Status Register */ 1072 1072 - #define UFSTAT0 (*(REG32_PTR_T)(0x3CC00018)) /* FIFO Status Register */ 1073 1073 - #define UMSTAT0 (*(REG32_PTR_T)(0x3CC0001C)) /* Modem Status Register */ 1074 1074 - #define UTXH0 (*(REG32_PTR_T)(0x3CC00020)) /* Transmit Buffer Register */ 1075 1075 - #define URXH0 (*(REG32_PTR_T)(0x3CC00024)) /* Receive Buffer Register */ 1076 1076 - #define UBRDIV0 (*(REG32_PTR_T)(0x3CC00028)) /* Baud Rate Divisor Register */ 1077 1077 - 1078 1078 - /* UART 1*/ 1079 1079 - #define ULCON1 (*(REG32_PTR_T)(0x3CC08000)) /* Line Control Register */ 1080 1080 - #define UCON1 (*(REG32_PTR_T)(0x3CC08004)) /* Control Register */ 1081 1081 - #define UFCON1 (*(REG32_PTR_T)(0x3CC08008)) /* FIFO Control Register */ 1082 1082 - #define UMCON1 (*(REG32_PTR_T)(0x3CC0800C)) /* Modem Control Register */ 1083 1083 - #define UTRSTAT1 (*(REG32_PTR_T)(0x3CC08010)) /* Tx/Rx Status Register */ 1084 1084 - #define UERSTAT1 (*(REG32_PTR_T)(0x3CC08014)) /* Rx Error Status Register */ 1085 1085 - #define UFSTAT1 (*(REG32_PTR_T)(0x3CC08018)) /* FIFO Status Register */ 1086 1086 - #define UMSTAT1 (*(REG32_PTR_T)(0x3CC0801C)) /* Modem Status Register */ 1087 1087 - #define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */ 1088 1088 - #define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */ 1089 1089 - #define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ 1090 1077 #elif CONFIG_CPU==S5L8701 1091 1078 /* s5l8701 UC87XX HW: 3 UARTC, 1 port per UARTC */ 1092 1079 #define S5L8701_N_UARTC 3 1093 1093 - #define S5L8701_N_PORTS 3 1094 1080 1095 1081 #define UARTC0_BASE_ADDR 0x3CC00000 1096 1082 #define UARTC0_N_PORTS 1 ··· 1117 1103 #define LCD_BASE 0x38300000 1118 1104 #endif 1119 1105 1120 1120 - #define LCD_CON (*(REG32_PTR_T)(LCD_BASE+0x00)) /* Control register. */ 1121 1121 - #define LCD_WCMD (*(REG32_PTR_T)(LCD_BASE+0x04)) /* Write command register. */ 1122 1122 - #define LCD_RCMD (*(REG32_PTR_T)(LCD_BASE+0x0C)) /* Read command register. */ 1123 1123 - #define LCD_RDATA (*(REG32_PTR_T)(LCD_BASE+0x10)) /* Read data register. */ 1124 1124 - #define LCD_DBUFF (*(REG32_PTR_T)(LCD_BASE+0x14)) /* Read Data buffer */ 1125 1125 - #define LCD_INTCON (*(REG32_PTR_T)(LCD_BASE+0x18)) /* Interrupt control register */ 1126 1126 - #define LCD_STATUS (*(REG32_PTR_T)(LCD_BASE+0x1C)) /* LCD Interface status 0106 */ 1127 1127 - #define LCD_PHTIME (*(REG32_PTR_T)(LCD_BASE+0x20)) /* Phase time register 0060 */ 1128 1128 - #define LCD_RST_TIME (*(REG32_PTR_T)(LCD_BASE+0x24)) /* Reset active period 07FF */ 1129 1129 - #define LCD_DRV_RST (*(REG32_PTR_T)(LCD_BASE+0x28)) /* Reset drive signal */ 1130 1130 - #define LCD_WDATA (*(REG32_PTR_T)(LCD_BASE+0x40)) /* Write data register (0x40...0x5C) FIXME */ 1106 1106 + #define LCD_CON (*(REG32_PTR_T)(LCD_BASE)) /* Control register. */ 1107 1107 + #define LCD_WCMD (*(REG32_PTR_T)(LCD_BASE + 0x04)) /* Write command register. */ 1108 1108 + #define LCD_RCMD (*(REG32_PTR_T)(LCD_BASE + 0x0C)) /* Read command register. */ 1109 1109 + #define LCD_RDATA (*(REG32_PTR_T)(LCD_BASE + 0x10)) /* Read data register. */ 1110 1110 + #define LCD_DBUFF (*(REG32_PTR_T)(LCD_BASE + 0x14)) /* Read Data buffer */ 1111 1111 + #define LCD_INTCON (*(REG32_PTR_T)(LCD_BASE + 0x18)) /* Interrupt control register */ 1112 1112 + #define LCD_STATUS (*(REG32_PTR_T)(LCD_BASE + 0x1C)) /* LCD Interface status 0106 */ 1113 1113 + #define LCD_PHTIME (*(REG32_PTR_T)(LCD_BASE + 0x20)) /* Phase time register 0060 */ 1114 1114 + #define LCD_RST_TIME (*(REG32_PTR_T)(LCD_BASE + 0x24)) /* Reset active period 07FF */ 1115 1115 + #define LCD_DRV_RST (*(REG32_PTR_T)(LCD_BASE + 0x28)) /* Reset drive signal */ 1116 1116 + #define LCD_WDATA (*(REG32_PTR_T)(LCD_BASE + 0x40)) /* Write data register (0x40...0x5C) FIXME */ 1131 1117 1132 1118 /* 27. CLCD CONTROLLER */ 1133 1133 - #define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */ 1134 1134 - #define LCDCON2 (*(REG32_PTR_T)(0x39200004)) /* LCD control 2 register */ 1135 1135 - #define LCDTCON1 (*(REG32_PTR_T)(0x39200008)) /* LCD time control 1 register */ 1136 1136 - #define LCDTCON2 (*(REG32_PTR_T)(0x3920000C)) /* LCD time control 2 register */ 1137 1137 - #define LCDTCON3 (*(REG32_PTR_T)(0x39200010)) /* LCD time control 3 register */ 1138 1138 - #define LCDOSD1 (*(REG32_PTR_T)(0x39200014)) /* LCD OSD control 1 register */ 1139 1139 - #define LCDOSD2 (*(REG32_PTR_T)(0x39200018)) /* LCD OSD control 2 register */ 1140 1140 - #define LCDOSD3 (*(REG32_PTR_T)(0x3920001C)) /* LCD OSD control 3 register */ 1141 1141 - #define LCDB1SADDR1 (*(REG32_PTR_T)(0x39200020)) /* Frame buffer start address register for Back-Ground buffer 1 */ 1142 1142 - #define LCDB2SADDR1 (*(REG32_PTR_T)(0x39200024)) /* Frame buffer start address register for Back-Ground buffer 2 */ 1143 1143 - #define LCDF1SADDR1 (*(REG32_PTR_T)(0x39200028)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */ 1144 1144 - #define LCDF2SADDR1 (*(REG32_PTR_T)(0x3920002C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */ 1145 1145 - #define LCDB1SADDR2 (*(REG32_PTR_T)(0x39200030)) /* Frame buffer end address register for Back-Ground buffer 1 */ 1146 1146 - #define LCDB2SADDR2 (*(REG32_PTR_T)(0x39200034)) /* Frame buffer end address register for Back-Ground buffer 2 */ 1147 1147 - #define LCDF1SADDR2 (*(REG32_PTR_T)(0x39200038)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */ 1148 1148 - #define LCDF2SADDR2 (*(REG32_PTR_T)(0x3920003C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */ 1149 1149 - #define LCDB1SADDR3 (*(REG32_PTR_T)(0x39200040)) /* Virtual screen address set for Back-Ground buffer 1 */ 1150 1150 - #define LCDB2SADDR3 (*(REG32_PTR_T)(0x39200044)) /* Virtual screen address set for Back-Ground buffer 2 */ 1151 1151 - #define LCDF1SADDR3 (*(REG32_PTR_T)(0x39200048)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */ 1152 1152 - #define LCDF2SADDR3 (*(REG32_PTR_T)(0x3920004C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */ 1153 1153 - #define LCDINTCON (*(REG32_PTR_T)(0x39200050)) /* Indicate the LCD interrupt control register */ 1154 1154 - #define LCDKEYCON (*(REG32_PTR_T)(0x39200054)) /* Color key control register */ 1155 1155 - #define LCDCOLVAL (*(REG32_PTR_T)(0x39200058)) /* Color key value ( transparent value) register */ 1156 1156 - #define LCDBGCON (*(REG32_PTR_T)(0x3920005C)) /* Back-Ground color control */ 1157 1157 - #define LCDFGCON (*(REG32_PTR_T)(0x39200060)) /* Fore-Ground color control */ 1158 1158 - #define LCDDITHMODE (*(REG32_PTR_T)(0x39200064)) /* Dithering mode register. */ 1119 1119 + #define LCDBASE 0x39200000 1120 1120 + 1121 1121 + #define LCDCON1 (*(REG32_PTR_T)(LCDBASE)) /* LCD control 1 register */ 1122 1122 + #define LCDCON2 (*(REG32_PTR_T)(LCDBASE + 0x04)) /* LCD control 2 register */ 1123 1123 + #define LCDTCON1 (*(REG32_PTR_T)(LCDBASE + 0x08)) /* LCD time control 1 register */ 1124 1124 + #define LCDTCON2 (*(REG32_PTR_T)(LCDBASE + 0x0C)) /* LCD time control 2 register */ 1125 1125 + #define LCDTCON3 (*(REG32_PTR_T)(LCDBASE + 0x10)) /* LCD time control 3 register */ 1126 1126 + #define LCDOSD1 (*(REG32_PTR_T)(LCDBASE + 0x14)) /* LCD OSD control 1 register */ 1127 1127 + #define LCDOSD2 (*(REG32_PTR_T)(LCDBASE + 0x18)) /* LCD OSD control 2 register */ 1128 1128 + #define LCDOSD3 (*(REG32_PTR_T)(LCDBASE + 0x1C)) /* LCD OSD control 3 register */ 1129 1129 + #define LCDB1SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x20)) /* Frame buffer start address register for Back-Ground buffer 1 */ 1130 1130 + #define LCDB2SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x24)) /* Frame buffer start address register for Back-Ground buffer 2 */ 1131 1131 + #define LCDF1SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x28)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */ 1132 1132 + #define LCDF2SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x2C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */ 1133 1133 + #define LCDB1SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x30)) /* Frame buffer end address register for Back-Ground buffer 1 */ 1134 1134 + #define LCDB2SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x34)) /* Frame buffer end address register for Back-Ground buffer 2 */ 1135 1135 + #define LCDF1SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x38)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */ 1136 1136 + #define LCDF2SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x3C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */ 1137 1137 + #define LCDB1SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x40)) /* Virtual screen address set for Back-Ground buffer 1 */ 1138 1138 + #define LCDB2SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x44)) /* Virtual screen address set for Back-Ground buffer 2 */ 1139 1139 + #define LCDF1SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x48)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */ 1140 1140 + #define LCDF2SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x4C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */ 1141 1141 + #define LCDINTCON (*(REG32_PTR_T)(LCDBASE + 0x50)) /* Indicate the LCD interrupt control register */ 1142 1142 + #define LCDKEYCON (*(REG32_PTR_T)(LCDBASE + 0x54)) /* Color key control register */ 1143 1143 + #define LCDCOLVAL (*(REG32_PTR_T)(LCDBASE + 0x58)) /* Color key value ( transparent value) register */ 1144 1144 + #define LCDBGCON (*(REG32_PTR_T)(LCDBASE + 0x5C)) /* Back-Ground color control */ 1145 1145 + #define LCDFGCON (*(REG32_PTR_T)(LCDBASE + 0x60)) /* Fore-Ground color control */ 1146 1146 + #define LCDDITHMODE (*(REG32_PTR_T)(LCDBASE + 0x64)) /* Dithering mode register. */ 1159 1147 1160 1148 /* 28. ATA CONTROLLER */ 1161 1149 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 1162 1162 - #define ATA_CONTROL (*(REG32_PTR_T)(0x38E00000)) /* Enable and clock down status */ 1163 1163 - #define ATA_STATUS (*(REG32_PTR_T)(0x38E00004)) /* Status */ 1164 1164 - #define ATA_COMMAND (*(REG32_PTR_T)(0x38E00008)) /* Command */ 1165 1165 - #define ATA_SWRST (*(REG32_PTR_T)(0x38E0000C)) /* Software reset */ 1166 1166 - #define ATA_IRQ (*(REG32_PTR_T)(0x38E00010)) /* Interrupt sources */ 1167 1167 - #define ATA_IRQ_MASK (*(REG32_PTR_T)(0x38E00014)) /* Interrupt mask */ 1168 1168 - #define ATA_CFG (*(REG32_PTR_T)(0x38E00018)) /* Configuration for ATA interface */ 1169 1169 - #define ATA_PIO_TIME (*(REG32_PTR_T)(0x38E0002C)) /* PIO timing */ 1170 1170 - #define ATA_UDMA_TIME (*(REG32_PTR_T)(0x38E00030)) /* UDMA timing */ 1171 1171 - #define ATA_XFR_NUM (*(REG32_PTR_T)(0x38E00034)) /* Transfer number */ 1172 1172 - #define ATA_XFR_CNT (*(REG32_PTR_T)(0x38E00038)) /* Current transfer count */ 1173 1173 - #define ATA_TBUF_START (*(REG32_PTR_T)(0x38E0003C)) /* Start address of track buffer */ 1174 1174 - #define ATA_TBUF_SIZE (*(REG32_PTR_T)(0x38E00040)) /* Size of track buffer */ 1175 1175 - #define ATA_SBUF_START (*(REG32_PTR_T)(0x38E00044)) /* Start address of Source buffer1 */ 1176 1176 - #define ATA_SBUF_SIZE (*(REG32_PTR_T)(0x38E00048)) /* Size of source buffer1 */ 1177 1177 - #define ATA_CADR_TBUF (*(REG32_PTR_T)(0x38E0004C)) /* Current write address of track buffer */ 1178 1178 - #define ATA_CADR_SBUF (*(REG32_PTR_T)(0x38E00050)) /* Current read address of source buffer */ 1179 1179 - #define ATA_PIO_DTR (*(REG32_PTR_T)(0x38E00054)) /* PIO device data register */ 1180 1180 - #define ATA_PIO_FED (*(REG32_PTR_T)(0x38E00058)) /* PIO device Feature/Error register */ 1181 1181 - #define ATA_PIO_SCR (*(REG32_PTR_T)(0x38E0005C)) /* PIO sector count register */ 1182 1182 - #define ATA_PIO_LLR (*(REG32_PTR_T)(0x38E00060)) /* PIO device LBA low register */ 1183 1183 - #define ATA_PIO_LMR (*(REG32_PTR_T)(0x38E00064)) /* PIO device LBA middle register */ 1184 1184 - #define ATA_PIO_LHR (*(REG32_PTR_T)(0x38E00068)) /* PIO device LBA high register */ 1185 1185 - #define ATA_PIO_DVR (*(REG32_PTR_T)(0x38E0006C)) /* PIO device register */ 1186 1186 - #define ATA_PIO_CSD (*(REG32_PTR_T)(0x38E00070)) /* PIO device command/status register */ 1187 1187 - #define ATA_PIO_DAD (*(REG32_PTR_T)(0x38E00074)) /* PIO control/alternate status register */ 1188 1188 - #define ATA_PIO_READY (*(REG32_PTR_T)(0x38E00078)) /* PIO data read/write ready */ 1189 1189 - #define ATA_PIO_RDATA (*(REG32_PTR_T)(0x38E0007C)) /* PIO read data from device register */ 1190 1190 - #define BUS_FIFO_STATUS (*(REG32_PTR_T)(0x38E00080)) /* Reserved */ 1191 1191 - #define ATA_FIFO_STATUS (*(REG32_PTR_T)(0x38E00084)) /* Reserved */ 1150 1150 + #define ATA_BASE 0x38E00000 1192 1151 #elif CONFIG_CPU==S5L8702 1193 1193 - #define ATA_CONTROL (*((REG32_PTR_T)(0x38700000))) 1194 1194 - #define ATA_STATUS (*((REG32_PTR_T)(0x38700004))) 1195 1195 - #define ATA_COMMAND (*((REG32_PTR_T)(0x38700008))) 1196 1196 - #define ATA_SWRST (*((REG32_PTR_T)(0x3870000c))) 1197 1197 - #define ATA_IRQ (*((REG32_PTR_T)(0x38700010))) 1198 1198 - #define ATA_IRQ_MASK (*((REG32_PTR_T)(0x38700014))) 1199 1199 - #define ATA_CFG (*((REG32_PTR_T)(0x38700018))) 1200 1200 - #define ATA_MDMA_TIME (*((REG32_PTR_T)(0x38700028))) 1201 1201 - #define ATA_PIO_TIME (*((REG32_PTR_T)(0x3870002c))) 1202 1202 - #define ATA_UDMA_TIME (*((REG32_PTR_T)(0x38700030))) 1203 1203 - #define ATA_XFR_NUM (*((REG32_PTR_T)(0x38700034))) 1204 1204 - #define ATA_XFR_CNT (*((REG32_PTR_T)(0x38700038))) 1205 1205 - #define ATA_TBUF_START (*((void* volatile*)(0x3870003c))) 1206 1206 - #define ATA_TBUF_SIZE (*((REG32_PTR_T)(0x38700040))) 1207 1207 - #define ATA_SBUF_START (*((void* volatile*)(0x38700044))) 1208 1208 - #define ATA_SBUF_SIZE (*((REG32_PTR_T)(0x38700048))) 1209 1209 - #define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c))) 1210 1210 - #define ATA_CADR_SBUF (*((void* volatile*)(0x38700050))) 1211 1211 - #define ATA_PIO_DTR (*((REG32_PTR_T)(0x38700054))) 1212 1212 - #define ATA_PIO_FED (*((REG32_PTR_T)(0x38700058))) 1213 1213 - #define ATA_PIO_SCR (*((REG32_PTR_T)(0x3870005c))) 1214 1214 - #define ATA_PIO_LLR (*((REG32_PTR_T)(0x38700060))) 1215 1215 - #define ATA_PIO_LMR (*((REG32_PTR_T)(0x38700064))) 1216 1216 - #define ATA_PIO_LHR (*((REG32_PTR_T)(0x38700068))) 1217 1217 - #define ATA_PIO_DVR (*((REG32_PTR_T)(0x3870006c))) 1218 1218 - #define ATA_PIO_CSD (*((REG32_PTR_T)(0x38700070))) 1219 1219 - #define ATA_PIO_DAD (*((REG32_PTR_T)(0x38700074))) 1220 1220 - #define ATA_PIO_READY (*((REG32_PTR_T)(0x38700078))) 1221 1221 - #define ATA_PIO_RDATA (*((REG32_PTR_T)(0x3870007c))) 1222 1222 - #define ATA_BUS_FIFO_STATUS (*((REG32_PTR_T)(0x38700080))) 1223 1223 - #define ATA_FIFO_STATUS (*((REG32_PTR_T)(0x38700084))) 1224 1224 - #define ATA_DMA_ADDR (*((void* volatile*)(0x38700088))) 1152 1152 + #define ATA_BASE 0x38700000 1225 1153 #endif 1226 1154 1155 1155 + #define ATA_CONTROL (*(REG32_PTR_T)(ATA_BASE)) /* Enable and clock down status */ 1156 1156 + #define ATA_STATUS (*(REG32_PTR_T)(ATA_BASE + 0x04)) /* Status */ 1157 1157 + #define ATA_COMMAND (*(REG32_PTR_T)(ATA_BASE + 0x08)) /* Command */ 1158 1158 + #define ATA_SWRST (*(REG32_PTR_T)(ATA_BASE + 0x0C)) /* Software reset */ 1159 1159 + #define ATA_IRQ (*(REG32_PTR_T)(ATA_BASE + 0x10)) /* Interrupt sources */ 1160 1160 + #define ATA_IRQ_MASK (*(REG32_PTR_T)(ATA_BASE + 0x14)) /* Interrupt mask */ 1161 1161 + #define ATA_CFG (*(REG32_PTR_T)(ATA_BASE + 0x18)) /* Configuration for ATA interface */ 1162 1162 + #define ATA_MDMA_TIME (*(REG32_PTR_T)(ATA_BASE + 0x28)) 1163 1163 + #define ATA_PIO_TIME (*(REG32_PTR_T)(ATA_BASE + 0x2C)) /* PIO timing */ 1164 1164 + #define ATA_UDMA_TIME (*(REG32_PTR_T)(ATA_BASE + 0x30)) /* UDMA timing */ 1165 1165 + #define ATA_XFR_NUM (*(REG32_PTR_T)(ATA_BASE + 0x34)) /* Transfer number */ 1166 1166 + #define ATA_XFR_CNT (*(REG32_PTR_T)(ATA_BASE + 0x38)) /* Current transfer count */ 1167 1167 + #define ATA_TBUF_START (*(VOID_PTR_PTR_T)(ATA_BASE + 0x3C)) /* Start address of track buffer */ 1168 1168 + #define ATA_TBUF_SIZE (*(REG32_PTR_T)(ATA_BASE + 0x40)) /* Size of track buffer */ 1169 1169 + #define ATA_SBUF_START (*(VOID_PTR_PTR_T)(ATA_BASE + 0x44)) /* Start address of Source buffer1 */ 1170 1170 + #define ATA_SBUF_SIZE (*(REG32_PTR_T)(ATA_BASE + 0x48)) /* Size of source buffer1 */ 1171 1171 + #define ATA_CADR_TBUF (*(VOID_PTR_PTR_T)(ATA_BASE + 0x4C)) /* Current write address of track buffer */ 1172 1172 + #define ATA_CADR_SBUF (*(VOID_PTR_PTR_T)(ATA_BASE + 0x50)) /* Current read address of source buffer */ 1173 1173 + #define ATA_PIO_DTR (*(REG32_PTR_T)(ATA_BASE + 0x54)) /* PIO device data register */ 1174 1174 + #define ATA_PIO_FED (*(REG32_PTR_T)(ATA_BASE + 0x58)) /* PIO device Feature/Error register */ 1175 1175 + #define ATA_PIO_SCR (*(REG32_PTR_T)(ATA_BASE + 0x5C)) /* PIO sector count register */ 1176 1176 + #define ATA_PIO_LLR (*(REG32_PTR_T)(ATA_BASE + 0x60)) /* PIO device LBA low register */ 1177 1177 + #define ATA_PIO_LMR (*(REG32_PTR_T)(ATA_BASE + 0x64)) /* PIO device LBA middle register */ 1178 1178 + #define ATA_PIO_LHR (*(REG32_PTR_T)(ATA_BASE + 0x68)) /* PIO device LBA high register */ 1179 1179 + #define ATA_PIO_DVR (*(REG32_PTR_T)(ATA_BASE + 0x6C)) /* PIO device register */ 1180 1180 + #define ATA_PIO_CSD (*(REG32_PTR_T)(ATA_BASE + 0x70)) /* PIO device command/status register */ 1181 1181 + #define ATA_PIO_DAD (*(REG32_PTR_T)(ATA_BASE + 0x74)) /* PIO control/alternate status register */ 1182 1182 + #define ATA_PIO_READY (*(REG32_PTR_T)(ATA_BASE + 0x78)) /* PIO data read/write ready */ 1183 1183 + #define ATA_PIO_RDATA (*(REG32_PTR_T)(ATA_BASE + 0x7C)) /* PIO read data from device register */ 1184 1184 + #define ATA_BUS_FIFO_STATUS (*(REG32_PTR_T)(ATA_BASE + 0x80)) /* Reserved */ 1185 1185 + #define ATA_FIFO_STATUS (*(REG32_PTR_T)(ATA_BASE + 0x84)) /* Reserved */ 1186 1186 + #define ATA_DMA_ADDR (*(VOID_PTR_PTR_T)(ATA_BASE + 0x88)) 1187 1187 + 1227 1188 /* 29. CHIP ID */ 1228 1228 - #define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */ 1229 1229 - #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ 1189 1189 + #define CHIP_ID_BASE 0x3D100000 1190 1190 + #define REG_ONE (*(REG32_PTR_T)(CHIP_ID_BASE)) /* Receive the first 32 bits from a fuse box */ 1191 1191 + #define REG_TWO (*(REG32_PTR_T)(CHIP_ID_BASE + 0x04)) /* Receive the other 8 bits from a fuse box */ 1230 1192 1193 1193 + /* 1194 1194 + The following peripherals are not present in the Samsung S5L8700 datasheet. 1195 1195 + Information for them was gathered solely by reverse-engineering Apple's firmware. 1196 1196 + */ 1231 1197 1232 1198 /* Hardware AES crypto unit - S5L8701+ */ 1233 1199 #if CONFIG_CPU==S5L8701 1234 1234 - #define AESCONTROL (*(REG32_PTR_T)(0x39800000)) 1235 1235 - #define AESGO (*(REG32_PTR_T)(0x39800004)) 1236 1236 - #define AESUNKREG0 (*(REG32_PTR_T)(0x39800008)) 1237 1237 - #define AESSTATUS (*(REG32_PTR_T)(0x3980000C)) 1238 1238 - #define AESUNKREG1 (*(REG32_PTR_T)(0x39800010)) 1239 1239 - #define AESKEYLEN (*(REG32_PTR_T)(0x39800014)) 1240 1240 - #define AESOUTSIZE (*(REG32_PTR_T)(0x39800018)) 1241 1241 - #define AESOUTADDR (*(REG32_PTR_T)(0x39800020)) 1242 1242 - #define AESINSIZE (*(REG32_PTR_T)(0x39800024)) 1243 1243 - #define AESINADDR (*(REG32_PTR_T)(0x39800028)) 1244 1244 - #define AESAUXSIZE (*(REG32_PTR_T)(0x3980002C)) 1245 1245 - #define AESAUXADDR (*(REG32_PTR_T)(0x39800030)) 1246 1246 - #define AESSIZE3 (*(REG32_PTR_T)(0x39800034)) 1247 1247 - #define AESTYPE (*(REG32_PTR_T)(0x3980006C)) 1200 1200 + #define AES_BASE 0x39800000 1248 1201 #elif CONFIG_CPU==S5L8702 1249 1249 - #define AESCONTROL (*((REG32_PTR_T)(0x38c00000))) 1250 1250 - #define AESGO (*((REG32_PTR_T)(0x38c00004))) 1251 1251 - #define AESUNKREG0 (*((REG32_PTR_T)(0x38c00008))) 1252 1252 - #define AESSTATUS (*((REG32_PTR_T)(0x38c0000c))) 1253 1253 - #define AESUNKREG1 (*((REG32_PTR_T)(0x38c00010))) 1254 1254 - #define AESKEYLEN (*((REG32_PTR_T)(0x38c00014))) 1255 1255 - #define AESOUTSIZE (*((REG32_PTR_T)(0x38c00018))) 1256 1256 - #define AESOUTADDR (*((void* volatile*)(0x38c00020))) 1257 1257 - #define AESINSIZE (*((REG32_PTR_T)(0x38c00024))) 1258 1258 - #define AESINADDR (*((const void* volatile*)(0x38c00028))) 1259 1259 - #define AESAUXSIZE (*((REG32_PTR_T)(0x38c0002c))) 1260 1260 - #define AESAUXADDR (*((void* volatile*)(0x38c00030))) 1261 1261 - #define AESSIZE3 (*((REG32_PTR_T)(0x38c00034))) 1262 1262 - #define AESKEY ((REG32_PTR_T)(0x38c0004c)) 1263 1263 - #define AESTYPE (*((REG32_PTR_T)(0x38c0006c))) 1264 1264 - #define AESIV ((REG32_PTR_T)(0x38c00074)) 1265 1265 - #define AESTYPE2 (*((REG32_PTR_T)(0x38c00088))) 1266 1266 - #define AESUNKREG2 (*((REG32_PTR_T)(0x38c0008c))) 1202 1202 + #define AES_BASE 0x38c00000 1203 1203 + #endif 1204 1204 + 1205 1205 + #if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 1206 1206 + #define AESCONTROL (*((REG32_PTR_T)(AES_BASE))) 1207 1207 + #define AESGO (*((REG32_PTR_T)(AES_BASE + 0x04))) 1208 1208 + #define AESUNKREG0 (*((REG32_PTR_T)(AES_BASE + 0x08))) 1209 1209 + #define AESSTATUS (*((REG32_PTR_T)(AES_BASE + 0x0c))) 1210 1210 + #define AESUNKREG1 (*((REG32_PTR_T)(AES_BASE + 0x10))) 1211 1211 + #define AESKEYLEN (*((REG32_PTR_T)(AES_BASE + 0x14))) 1212 1212 + #define AESOUTSIZE (*((REG32_PTR_T)(AES_BASE + 0x18))) 1213 1213 + #define AESINSIZE (*((REG32_PTR_T)(AES_BASE + 0x24))) 1214 1214 + #define AESAUXSIZE (*((REG32_PTR_T)(AES_BASE + 0x2c))) 1215 1215 + #define AESSIZE3 (*((REG32_PTR_T)(AES_BASE + 0x34))) 1216 1216 + #define AESTYPE (*((REG32_PTR_T)(AES_BASE + 0x6c))) 1217 1217 + #endif 1218 1218 + 1219 1219 + #if CONFIG_CPU==S5L8701 1220 1220 + #define AESOUTADDR (*((REG32_PTR_T)(AES_BASE + 0x20))) 1221 1221 + #define AESINADDR (*((REG32_PTR_T)(AES_BASE + 0x28))) 1222 1222 + #define AESAUXADDR (*((REG32_PTR_T)(AES_BASE + 0x30))) 1223 1223 + #elif CONFIG_CPU==S5L8702 1224 1224 + #define AESOUTADDR (*((VOID_PTR_PTR_T)(AES_BASE + 0x20))) 1225 1225 + #define AESINADDR (*((CONST_VOID_PTR_PTR_T)(AES_BASE + 0x28))) 1226 1226 + #define AESAUXADDR (*((VOID_PTR_PTR_T)(AES_BASE + 0x30))) 1227 1227 + #define AESKEY ((REG32_PTR_T)(AES_BASE + 0x4c)) 1228 1228 + #define AESIV ((REG32_PTR_T)(AES_BASE + 0x74)) 1229 1229 + #define AESTYPE2 (*((REG32_PTR_T)(AES_BASE + 0x88))) 1230 1230 + #define AESUNKREG2 (*((REG32_PTR_T)(AES_BASE + 0x8c))) 1267 1231 #endif 1268 1232 1269 1233 /* SHA-1 unit - S5L8701+ */ 1270 1234 #if CONFIG_CPU==S5L8701 1271 1271 - #define HASHCTRL (*(REG32_PTR_T)(0x3C600000)) 1272 1272 - #define HASHRESULT ((REG32_PTR_T)(0x3C600020)) 1273 1273 - #define HASHDATAIN ((REG32_PTR_T)(0x3C600040)) 1235 1235 + #define HASH_BASE 0x3C600000 1236 1236 + 1237 1237 + #define HASHCTRL (*(REG32_PTR_T)(HASH_BASE)) 1238 1238 + #define HASHRESULT ((REG32_PTR_T)(HASH_BASE + 0x20)) 1239 1239 + #define HASHDATAIN ((REG32_PTR_T)(HASH_BASE + 0x40)) 1274 1240 #elif CONFIG_CPU==S5L8702 1275 1275 - #define SHA1CONFIG (*((REG32_PTR_T)(0x38000000))) 1276 1276 - #define SHA1RESET (*((REG32_PTR_T)(0x38000004))) 1277 1277 - #define SHA1RESULT ((REG32_PTR_T)(0x38000020)) 1278 1278 - #define SHA1DATAIN ((REG32_PTR_T)(0x38000040)) 1241 1241 + #define SHA1_BASE 0x38000000 1242 1242 + 1243 1243 + #define SHA1CONFIG (*((REG32_PTR_T)(SHA1_BASE))) 1244 1244 + #define SHA1RESET (*((REG32_PTR_T)(SHA1_BASE + 0x04))) 1245 1245 + #define SHA1RESULT ((REG32_PTR_T)(SHA1_BASE + 0x20)) 1246 1246 + #define SHA1DATAIN ((REG32_PTR_T)(SHA1_BASE + 0x40)) 1279 1247 #endif 1280 1248 1281 1249 /* Clickwheel controller - S5L8701+ */ 1282 1250 #if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 1283 1283 - #define WHEEL00 (*((REG32_PTR_T)(0x3C200000))) 1284 1284 - #define WHEEL04 (*((REG32_PTR_T)(0x3C200004))) 1285 1285 - #define WHEEL08 (*((REG32_PTR_T)(0x3C200008))) 1286 1286 - #define WHEEL0C (*((REG32_PTR_T)(0x3C20000C))) 1287 1287 - #define WHEEL10 (*((REG32_PTR_T)(0x3C200010))) 1288 1288 - #define WHEELINT (*((REG32_PTR_T)(0x3C200014))) 1289 1289 - #define WHEELRX (*((REG32_PTR_T)(0x3C200018))) 1290 1290 - #define WHEELTX (*((REG32_PTR_T)(0x3C20001C))) 1251 1251 + #define WHEEL_BASE 0x3C200000 1252 1252 + 1253 1253 + #define WHEEL00 (*((REG32_PTR_T)(WHEEL_BASE))) 1254 1254 + #define WHEEL04 (*((REG32_PTR_T)(WHEEL_BASE + 0x04))) 1255 1255 + #define WHEEL08 (*((REG32_PTR_T)(WHEEL_BASE + 0x08))) 1256 1256 + #define WHEEL0C (*((REG32_PTR_T)(WHEEL_BASE + 0x0C))) 1257 1257 + #define WHEEL10 (*((REG32_PTR_T)(WHEEL_BASE + 0x10))) 1258 1258 + #define WHEELINT (*((REG32_PTR_T)(WHEEL_BASE + 0x14))) 1259 1259 + #define WHEELRX (*((REG32_PTR_T)(WHEEL_BASE + 0x18))) 1260 1260 + #define WHEELTX (*((REG32_PTR_T)(WHEEL_BASE + 0x1C))) 1291 1261 #endif 1292 1262 1293 1263 /* Synopsys OTG - S5L8701 only */ ··· 1331 1301 1332 1302 #if CONFIG_CPU==S5L8702 1333 1303 /////INTERRUPT CONTROLLERS///// 1334 1334 - #define VICIRQSTATUS(v) (*((REG32_PTR_T)(0x38E00000 + 0x1000 * (v)))) 1335 1335 - #define VICFIQSTATUS(v) (*((REG32_PTR_T)(0x38E00004 + 0x1000 * (v)))) 1336 1336 - #define VICRAWINTR(v) (*((REG32_PTR_T)(0x38E00008 + 0x1000 * (v)))) 1337 1337 - #define VICINTSELECT(v) (*((REG32_PTR_T)(0x38E0000C + 0x1000 * (v)))) 1338 1338 - #define VICINTENABLE(v) (*((REG32_PTR_T)(0x38E00010 + 0x1000 * (v)))) 1339 1339 - #define VICINTENCLEAR(v) (*((REG32_PTR_T)(0x38E00014 + 0x1000 * (v)))) 1340 1340 - #define VICSOFTINT(v) (*((REG32_PTR_T)(0x38E00018 + 0x1000 * (v)))) 1341 1341 - #define VICSOFTINTCLEAR(v) (*((REG32_PTR_T)(0x38E0001C + 0x1000 * (v)))) 1342 1342 - #define VICPROTECTION(v) (*((REG32_PTR_T)(0x38E00020 + 0x1000 * (v)))) 1343 1343 - #define VICSWPRIORITYMASK(v) (*((REG32_PTR_T)(0x38E00024 + 0x1000 * (v)))) 1344 1344 - #define VICPRIORITYDAISY(v) (*((REG32_PTR_T)(0x38E00028 + 0x1000 * (v)))) 1345 1345 - #define VICVECTADDR(v, i) (*((REG32_PTR_T)(0x38E00100 + 0x1000 * (v) + 4 * (i)))) 1346 1346 - #define VICVECTPRIORITY(v, i) (*((REG32_PTR_T)(0x38E00200 + 0x1000 * (v) + 4 * (i)))) 1347 1347 - #define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v)))) 1348 1348 - #define VIC0IRQSTATUS (*((REG32_PTR_T)(0x38E00000))) 1349 1349 - #define VIC0FIQSTATUS (*((REG32_PTR_T)(0x38E00004))) 1350 1350 - #define VIC0RAWINTR (*((REG32_PTR_T)(0x38E00008))) 1351 1351 - #define VIC0INTSELECT (*((REG32_PTR_T)(0x38E0000C))) 1352 1352 - #define VIC0INTENABLE (*((REG32_PTR_T)(0x38E00010))) 1353 1353 - #define VIC0INTENCLEAR (*((REG32_PTR_T)(0x38E00014))) 1354 1354 - #define VIC0SOFTINT (*((REG32_PTR_T)(0x38E00018))) 1355 1355 - #define VIC0SOFTINTCLEAR (*((REG32_PTR_T)(0x38E0001C))) 1356 1356 - #define VIC0PROTECTION (*((REG32_PTR_T)(0x38E00020))) 1357 1357 - #define VIC0SWPRIORITYMASK (*((REG32_PTR_T)(0x38E00024))) 1358 1358 - #define VIC0PRIORITYDAISY (*((REG32_PTR_T)(0x38E00028))) 1359 1359 - #define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i)))) 1360 1360 - #define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100))) 1361 1361 - #define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104))) 1362 1362 - #define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108))) 1363 1363 - #define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C))) 1364 1364 - #define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110))) 1365 1365 - #define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114))) 1366 1366 - #define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118))) 1367 1367 - #define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C))) 1368 1368 - #define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120))) 1369 1369 - #define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124))) 1370 1370 - #define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128))) 1371 1371 - #define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C))) 1372 1372 - #define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130))) 1373 1373 - #define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134))) 1374 1374 - #define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138))) 1375 1375 - #define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C))) 1376 1376 - #define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140))) 1377 1377 - #define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144))) 1378 1378 - #define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148))) 1379 1379 - #define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C))) 1380 1380 - #define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150))) 1381 1381 - #define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154))) 1382 1382 - #define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158))) 1383 1383 - #define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C))) 1384 1384 - #define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160))) 1385 1385 - #define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164))) 1386 1386 - #define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168))) 1387 1387 - #define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C))) 1388 1388 - #define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170))) 1389 1389 - #define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174))) 1390 1390 - #define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178))) 1391 1391 - #define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C))) 1392 1392 - #define VIC0VECTPRIORITY(i) (*((REG32_PTR_T)(0x38E00200 + 4 * (i)))) 1393 1393 - #define VIC0VECTPRIORITY0 (*((REG32_PTR_T)(0x38E00200))) 1394 1394 - #define VIC0VECTPRIORITY1 (*((REG32_PTR_T)(0x38E00204))) 1395 1395 - #define VIC0VECTPRIORITY2 (*((REG32_PTR_T)(0x38E00208))) 1396 1396 - #define VIC0VECTPRIORITY3 (*((REG32_PTR_T)(0x38E0020C))) 1397 1397 - #define VIC0VECTPRIORITY4 (*((REG32_PTR_T)(0x38E00210))) 1398 1398 - #define VIC0VECTPRIORITY5 (*((REG32_PTR_T)(0x38E00214))) 1399 1399 - #define VIC0VECTPRIORITY6 (*((REG32_PTR_T)(0x38E00218))) 1400 1400 - #define VIC0VECTPRIORITY7 (*((REG32_PTR_T)(0x38E0021C))) 1401 1401 - #define VIC0VECTPRIORITY8 (*((REG32_PTR_T)(0x38E00220))) 1402 1402 - #define VIC0VECTPRIORITY9 (*((REG32_PTR_T)(0x38E00224))) 1403 1403 - #define VIC0VECTPRIORITY10 (*((REG32_PTR_T)(0x38E00228))) 1404 1404 - #define VIC0VECTPRIORITY11 (*((REG32_PTR_T)(0x38E0022C))) 1405 1405 - #define VIC0VECTPRIORITY12 (*((REG32_PTR_T)(0x38E00230))) 1406 1406 - #define VIC0VECTPRIORITY13 (*((REG32_PTR_T)(0x38E00234))) 1407 1407 - #define VIC0VECTPRIORITY14 (*((REG32_PTR_T)(0x38E00238))) 1408 1408 - #define VIC0VECTPRIORITY15 (*((REG32_PTR_T)(0x38E0023C))) 1409 1409 - #define VIC0VECTPRIORITY16 (*((REG32_PTR_T)(0x38E00240))) 1410 1410 - #define VIC0VECTPRIORITY17 (*((REG32_PTR_T)(0x38E00244))) 1411 1411 - #define VIC0VECTPRIORITY18 (*((REG32_PTR_T)(0x38E00248))) 1412 1412 - #define VIC0VECTPRIORITY19 (*((REG32_PTR_T)(0x38E0024C))) 1413 1413 - #define VIC0VECTPRIORITY20 (*((REG32_PTR_T)(0x38E00250))) 1414 1414 - #define VIC0VECTPRIORITY21 (*((REG32_PTR_T)(0x38E00254))) 1415 1415 - #define VIC0VECTPRIORITY22 (*((REG32_PTR_T)(0x38E00258))) 1416 1416 - #define VIC0VECTPRIORITY23 (*((REG32_PTR_T)(0x38E0025C))) 1417 1417 - #define VIC0VECTPRIORITY24 (*((REG32_PTR_T)(0x38E00260))) 1418 1418 - #define VIC0VECTPRIORITY25 (*((REG32_PTR_T)(0x38E00264))) 1419 1419 - #define VIC0VECTPRIORITY26 (*((REG32_PTR_T)(0x38E00268))) 1420 1420 - #define VIC0VECTPRIORITY27 (*((REG32_PTR_T)(0x38E0026C))) 1421 1421 - #define VIC0VECTPRIORITY28 (*((REG32_PTR_T)(0x38E00270))) 1422 1422 - #define VIC0VECTPRIORITY29 (*((REG32_PTR_T)(0x38E00274))) 1423 1423 - #define VIC0VECTPRIORITY30 (*((REG32_PTR_T)(0x38E00278))) 1424 1424 - #define VIC0VECTPRIORITY31 (*((REG32_PTR_T)(0x38E0027C))) 1425 1425 - #define VIC0ADDRESS (*((void* volatile*)(0x38E00F00))) 1426 1426 - #define VIC1IRQSTATUS (*((REG32_PTR_T)(0x38E01000))) 1427 1427 - #define VIC1FIQSTATUS (*((REG32_PTR_T)(0x38E01004))) 1428 1428 - #define VIC1RAWINTR (*((REG32_PTR_T)(0x38E01008))) 1429 1429 - #define VIC1INTSELECT (*((REG32_PTR_T)(0x38E0100C))) 1430 1430 - #define VIC1INTENABLE (*((REG32_PTR_T)(0x38E01010))) 1431 1431 - #define VIC1INTENCLEAR (*((REG32_PTR_T)(0x38E01014))) 1432 1432 - #define VIC1SOFTINT (*((REG32_PTR_T)(0x38E01018))) 1433 1433 - #define VIC1SOFTINTCLEAR (*((REG32_PTR_T)(0x38E0101C))) 1434 1434 - #define VIC1PROTECTION (*((REG32_PTR_T)(0x38E01020))) 1435 1435 - #define VIC1SWPRIORITYMASK (*((REG32_PTR_T)(0x38E01024))) 1436 1436 - #define VIC1PRIORITYDAISY (*((REG32_PTR_T)(0x38E01028))) 1437 1437 - #define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i)))) 1438 1438 - #define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100))) 1439 1439 - #define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104))) 1440 1440 - #define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108))) 1441 1441 - #define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C))) 1442 1442 - #define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110))) 1443 1443 - #define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114))) 1444 1444 - #define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118))) 1445 1445 - #define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C))) 1446 1446 - #define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120))) 1447 1447 - #define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124))) 1448 1448 - #define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128))) 1449 1449 - #define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C))) 1450 1450 - #define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130))) 1451 1451 - #define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134))) 1452 1452 - #define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138))) 1453 1453 - #define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C))) 1454 1454 - #define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140))) 1455 1455 - #define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144))) 1456 1456 - #define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148))) 1457 1457 - #define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C))) 1458 1458 - #define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150))) 1459 1459 - #define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154))) 1460 1460 - #define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158))) 1461 1461 - #define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C))) 1462 1462 - #define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160))) 1463 1463 - #define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164))) 1464 1464 - #define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168))) 1465 1465 - #define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C))) 1466 1466 - #define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170))) 1467 1467 - #define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174))) 1468 1468 - #define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178))) 1469 1469 - #define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C))) 1470 1470 - #define VIC1VECTPRIORITY(i) (*((REG32_PTR_T)(0x38E01200 + 4 * (i)))) 1471 1471 - #define VIC1VECTPRIORITY0 (*((REG32_PTR_T)(0x38E01200))) 1472 1472 - #define VIC1VECTPRIORITY1 (*((REG32_PTR_T)(0x38E01204))) 1473 1473 - #define VIC1VECTPRIORITY2 (*((REG32_PTR_T)(0x38E01208))) 1474 1474 - #define VIC1VECTPRIORITY3 (*((REG32_PTR_T)(0x38E0120C))) 1475 1475 - #define VIC1VECTPRIORITY4 (*((REG32_PTR_T)(0x38E01210))) 1476 1476 - #define VIC1VECTPRIORITY5 (*((REG32_PTR_T)(0x38E01214))) 1477 1477 - #define VIC1VECTPRIORITY6 (*((REG32_PTR_T)(0x38E01218))) 1478 1478 - #define VIC1VECTPRIORITY7 (*((REG32_PTR_T)(0x38E0121C))) 1479 1479 - #define VIC1VECTPRIORITY8 (*((REG32_PTR_T)(0x38E01220))) 1480 1480 - #define VIC1VECTPRIORITY9 (*((REG32_PTR_T)(0x38E01224))) 1481 1481 - #define VIC1VECTPRIORITY10 (*((REG32_PTR_T)(0x38E01228))) 1482 1482 - #define VIC1VECTPRIORITY11 (*((REG32_PTR_T)(0x38E0122C))) 1483 1483 - #define VIC1VECTPRIORITY12 (*((REG32_PTR_T)(0x38E01230))) 1484 1484 - #define VIC1VECTPRIORITY13 (*((REG32_PTR_T)(0x38E01234))) 1485 1485 - #define VIC1VECTPRIORITY14 (*((REG32_PTR_T)(0x38E01238))) 1486 1486 - #define VIC1VECTPRIORITY15 (*((REG32_PTR_T)(0x38E0123C))) 1487 1487 - #define VIC1VECTPRIORITY16 (*((REG32_PTR_T)(0x38E01240))) 1488 1488 - #define VIC1VECTPRIORITY17 (*((REG32_PTR_T)(0x38E01244))) 1489 1489 - #define VIC1VECTPRIORITY18 (*((REG32_PTR_T)(0x38E01248))) 1490 1490 - #define VIC1VECTPRIORITY19 (*((REG32_PTR_T)(0x38E0124C))) 1491 1491 - #define VIC1VECTPRIORITY20 (*((REG32_PTR_T)(0x38E01250))) 1492 1492 - #define VIC1VECTPRIORITY21 (*((REG32_PTR_T)(0x38E01254))) 1493 1493 - #define VIC1VECTPRIORITY22 (*((REG32_PTR_T)(0x38E01258))) 1494 1494 - #define VIC1VECTPRIORITY23 (*((REG32_PTR_T)(0x38E0125C))) 1495 1495 - #define VIC1VECTPRIORITY24 (*((REG32_PTR_T)(0x38E01260))) 1496 1496 - #define VIC1VECTPRIORITY25 (*((REG32_PTR_T)(0x38E01264))) 1497 1497 - #define VIC1VECTPRIORITY26 (*((REG32_PTR_T)(0x38E01268))) 1498 1498 - #define VIC1VECTPRIORITY27 (*((REG32_PTR_T)(0x38E0126C))) 1499 1499 - #define VIC1VECTPRIORITY28 (*((REG32_PTR_T)(0x38E01270))) 1500 1500 - #define VIC1VECTPRIORITY29 (*((REG32_PTR_T)(0x38E01274))) 1501 1501 - #define VIC1VECTPRIORITY30 (*((REG32_PTR_T)(0x38E01278))) 1502 1502 - #define VIC1VECTPRIORITY31 (*((REG32_PTR_T)(0x38E0127C))) 1503 1503 - #define VIC1ADDRESS (*((void* volatile*)(0x38E01F00))) 1304 1304 + #define VIC_BASE 0x38E00000 1305 1305 + #define VIC_OFFSET 0x1000 1306 1306 + 1307 1307 + #define VICBASE(v) (VIC_BASE + VIC_OFFSET * (v)) 1308 1308 + 1309 1309 + #define VICIRQSTATUS(v) (*((REG32_PTR_T)(VICBASE(v)))) 1310 1310 + #define VICFIQSTATUS(v) (*((REG32_PTR_T)(VICBASE(v) + 0x04))) 1311 1311 + #define VICRAWINTR(v) (*((REG32_PTR_T)(VICBASE(v) + 0x08))) 1312 1312 + #define VICINTSELECT(v) (*((REG32_PTR_T)(VICBASE(v) + 0x0C))) 1313 1313 + #define VICINTENABLE(v) (*((REG32_PTR_T)(VICBASE(v) + 0x10))) 1314 1314 + #define VICINTENCLEAR(v) (*((REG32_PTR_T)(VICBASE(v) + 0x14))) 1315 1315 + #define VICSOFTINT(v) (*((REG32_PTR_T)(VICBASE(v) + 0x18))) 1316 1316 + #define VICSOFTINTCLEAR(v) (*((REG32_PTR_T)(VICBASE(v) + 0x1C))) 1317 1317 + #define VICPROTECTION(v) (*((REG32_PTR_T)(VICBASE(v) + 0x20))) 1318 1318 + #define VICSWPRIORITYMASK(v) (*((REG32_PTR_T)(VICBASE(v) + 0x24))) 1319 1319 + #define VICPRIORITYDAISY(v) (*((REG32_PTR_T)(VICBASE(v) + 0x28))) 1320 1320 + #define VICVECTADDR(v, i) (*((REG32_PTR_T)(VICBASE(v) + 0x100 + 4 * (i)))) 1321 1321 + #define VICVECTPRIORITY(v, i) (*((REG32_PTR_T)(VICBASE(v) + 0x200 + 4 * (i)))) 1322 1322 + #define VICADDRESS(v) (*((CONST_VOID_PTR_PTR_T)(VICBASE(v) + 0xF00))) 1323 1323 + 1324 1324 + #define VIC0IRQSTATUS VICIRQSTATUS(0) 1325 1325 + #define VIC0FIQSTATUS VICFIQSTATUS(0) 1326 1326 + #define VIC0RAWINTR VICRAWINTR(0) 1327 1327 + #define VIC0INTSELECT VICINTSELECT(0) 1328 1328 + #define VIC0INTENABLE VICINTENABLE(0) 1329 1329 + #define VIC0INTENCLEAR VICINTENCLEAR(0) 1330 1330 + #define VIC0SOFTINT VICSOFTINT(0) 1331 1331 + #define VIC0SOFTINTCLEAR VICSOFTINTCLEAR(0) 1332 1332 + #define VIC0PROTECTION VICPROTECTION(0) 1333 1333 + #define VIC0SWPRIORITYMASK VICSWPRIORITYMASK(0) 1334 1334 + #define VIC0PRIORITYDAISY VICPRIORITYDAISY(0) 1335 1335 + 1336 1336 + #define VIC0VECTADDR(i) VICVECTADDR(0, i) 1337 1337 + #define VIC0VECTADDR0 VIC0VECTADDR(0) 1338 1338 + #define VIC0VECTADDR1 VIC0VECTADDR(1) 1339 1339 + #define VIC0VECTADDR2 VIC0VECTADDR(2) 1340 1340 + #define VIC0VECTADDR3 VIC0VECTADDR(3) 1341 1341 + #define VIC0VECTADDR4 VIC0VECTADDR(4) 1342 1342 + #define VIC0VECTADDR5 VIC0VECTADDR(5) 1343 1343 + #define VIC0VECTADDR6 VIC0VECTADDR(6) 1344 1344 + #define VIC0VECTADDR7 VIC0VECTADDR(7) 1345 1345 + #define VIC0VECTADDR8 VIC0VECTADDR(8) 1346 1346 + #define VIC0VECTADDR9 VIC0VECTADDR(9) 1347 1347 + #define VIC0VECTADDR10 VIC0VECTADDR(10) 1348 1348 + #define VIC0VECTADDR11 VIC0VECTADDR(11) 1349 1349 + #define VIC0VECTADDR12 VIC0VECTADDR(12) 1350 1350 + #define VIC0VECTADDR13 VIC0VECTADDR(13) 1351 1351 + #define VIC0VECTADDR14 VIC0VECTADDR(14) 1352 1352 + #define VIC0VECTADDR15 VIC0VECTADDR(15) 1353 1353 + #define VIC0VECTADDR16 VIC0VECTADDR(16) 1354 1354 + #define VIC0VECTADDR17 VIC0VECTADDR(17) 1355 1355 + #define VIC0VECTADDR18 VIC0VECTADDR(18) 1356 1356 + #define VIC0VECTADDR19 VIC0VECTADDR(19) 1357 1357 + #define VIC0VECTADDR20 VIC0VECTADDR(20) 1358 1358 + #define VIC0VECTADDR21 VIC0VECTADDR(21) 1359 1359 + #define VIC0VECTADDR22 VIC0VECTADDR(22) 1360 1360 + #define VIC0VECTADDR23 VIC0VECTADDR(23) 1361 1361 + #define VIC0VECTADDR24 VIC0VECTADDR(24) 1362 1362 + #define VIC0VECTADDR25 VIC0VECTADDR(25) 1363 1363 + #define VIC0VECTADDR26 VIC0VECTADDR(26) 1364 1364 + #define VIC0VECTADDR27 VIC0VECTADDR(27) 1365 1365 + #define VIC0VECTADDR28 VIC0VECTADDR(28) 1366 1366 + #define VIC0VECTADDR29 VIC0VECTADDR(29) 1367 1367 + #define VIC0VECTADDR30 VIC0VECTADDR(30) 1368 1368 + #define VIC0VECTADDR31 VIC0VECTADDR(31) 1369 1369 + 1370 1370 + #define VIC0VECTPRIORITY(i) VICVECTPRIORITY(0, i) 1371 1371 + #define VIC0VECTPRIORITY0 VIC0VECTPRIORITY(0) 1372 1372 + #define VIC0VECTPRIORITY1 VIC0VECTPRIORITY(1) 1373 1373 + #define VIC0VECTPRIORITY2 VIC0VECTPRIORITY(2) 1374 1374 + #define VIC0VECTPRIORITY3 VIC0VECTPRIORITY(3) 1375 1375 + #define VIC0VECTPRIORITY4 VIC0VECTPRIORITY(4) 1376 1376 + #define VIC0VECTPRIORITY5 VIC0VECTPRIORITY(5) 1377 1377 + #define VIC0VECTPRIORITY6 VIC0VECTPRIORITY(6) 1378 1378 + #define VIC0VECTPRIORITY7 VIC0VECTPRIORITY(7) 1379 1379 + #define VIC0VECTPRIORITY8 VIC0VECTPRIORITY(8) 1380 1380 + #define VIC0VECTPRIORITY9 VIC0VECTPRIORITY(9) 1381 1381 + #define VIC0VECTPRIORITY10 VIC0VECTPRIORITY(10) 1382 1382 + #define VIC0VECTPRIORITY11 VIC0VECTPRIORITY(11) 1383 1383 + #define VIC0VECTPRIORITY12 VIC0VECTPRIORITY(12) 1384 1384 + #define VIC0VECTPRIORITY13 VIC0VECTPRIORITY(13) 1385 1385 + #define VIC0VECTPRIORITY14 VIC0VECTPRIORITY(14) 1386 1386 + #define VIC0VECTPRIORITY15 VIC0VECTPRIORITY(15) 1387 1387 + #define VIC0VECTPRIORITY16 VIC0VECTPRIORITY(16) 1388 1388 + #define VIC0VECTPRIORITY17 VIC0VECTPRIORITY(17) 1389 1389 + #define VIC0VECTPRIORITY18 VIC0VECTPRIORITY(18) 1390 1390 + #define VIC0VECTPRIORITY19 VIC0VECTPRIORITY(19) 1391 1391 + #define VIC0VECTPRIORITY20 VIC0VECTPRIORITY(20) 1392 1392 + #define VIC0VECTPRIORITY21 VIC0VECTPRIORITY(21) 1393 1393 + #define VIC0VECTPRIORITY22 VIC0VECTPRIORITY(22) 1394 1394 + #define VIC0VECTPRIORITY23 VIC0VECTPRIORITY(23) 1395 1395 + #define VIC0VECTPRIORITY24 VIC0VECTPRIORITY(24) 1396 1396 + #define VIC0VECTPRIORITY25 VIC0VECTPRIORITY(25) 1397 1397 + #define VIC0VECTPRIORITY26 VIC0VECTPRIORITY(26) 1398 1398 + #define VIC0VECTPRIORITY27 VIC0VECTPRIORITY(27) 1399 1399 + #define VIC0VECTPRIORITY28 VIC0VECTPRIORITY(28) 1400 1400 + #define VIC0VECTPRIORITY29 VIC0VECTPRIORITY(29) 1401 1401 + #define VIC0VECTPRIORITY30 VIC0VECTPRIORITY(30) 1402 1402 + #define VIC0VECTPRIORITY31 VIC0VECTPRIORITY(31) 1403 1403 + 1404 1404 + #define VIC0ADDRESS VICADDRESS(0) 1405 1405 + 1406 1406 + #define VIC1IRQSTATUS VICIRQSTATUS(1) 1407 1407 + #define VIC1FIQSTATUS VICFIQSTATUS(1) 1408 1408 + #define VIC1RAWINTR VICRAWINTR(1) 1409 1409 + #define VIC1INTSELECT VICINTSELECT(1) 1410 1410 + #define VIC1INTENABLE VICINTENABLE(1) 1411 1411 + #define VIC1INTENCLEAR VICINTENCLEAR(1) 1412 1412 + #define VIC1SOFTINT VICSOFTINT(1) 1413 1413 + #define VIC1SOFTINTCLEAR VICSOFTINTCLEAR(1) 1414 1414 + #define VIC1PROTECTION VICPROTECTION(1) 1415 1415 + #define VIC1SWPRIORITYMASK VICSWPRIORITYMASK(1) 1416 1416 + #define VIC1PRIORITYDAISY VICPRIORITYDAISY(1) 1417 1417 + 1418 1418 + #define VIC1VECTADDR(i) VICVECTADDR(1, i) 1419 1419 + #define VIC1VECTADDR0 VIC1VECTADDR(0) 1420 1420 + #define VIC1VECTADDR1 VIC1VECTADDR(1) 1421 1421 + #define VIC1VECTADDR2 VIC1VECTADDR(2) 1422 1422 + #define VIC1VECTADDR3 VIC1VECTADDR(3) 1423 1423 + #define VIC1VECTADDR4 VIC1VECTADDR(4) 1424 1424 + #define VIC1VECTADDR5 VIC1VECTADDR(5) 1425 1425 + #define VIC1VECTADDR6 VIC1VECTADDR(6) 1426 1426 + #define VIC1VECTADDR7 VIC1VECTADDR(7) 1427 1427 + #define VIC1VECTADDR8 VIC1VECTADDR(8) 1428 1428 + #define VIC1VECTADDR9 VIC1VECTADDR(9) 1429 1429 + #define VIC1VECTADDR10 VIC1VECTADDR(10) 1430 1430 + #define VIC1VECTADDR11 VIC1VECTADDR(11) 1431 1431 + #define VIC1VECTADDR12 VIC1VECTADDR(12) 1432 1432 + #define VIC1VECTADDR13 VIC1VECTADDR(13) 1433 1433 + #define VIC1VECTADDR14 VIC1VECTADDR(14) 1434 1434 + #define VIC1VECTADDR15 VIC1VECTADDR(15) 1435 1435 + #define VIC1VECTADDR16 VIC1VECTADDR(16) 1436 1436 + #define VIC1VECTADDR17 VIC1VECTADDR(17) 1437 1437 + #define VIC1VECTADDR18 VIC1VECTADDR(18) 1438 1438 + #define VIC1VECTADDR19 VIC1VECTADDR(19) 1439 1439 + #define VIC1VECTADDR20 VIC1VECTADDR(20) 1440 1440 + #define VIC1VECTADDR21 VIC1VECTADDR(21) 1441 1441 + #define VIC1VECTADDR22 VIC1VECTADDR(22) 1442 1442 + #define VIC1VECTADDR23 VIC1VECTADDR(23) 1443 1443 + #define VIC1VECTADDR24 VIC1VECTADDR(24) 1444 1444 + #define VIC1VECTADDR25 VIC1VECTADDR(25) 1445 1445 + #define VIC1VECTADDR26 VIC1VECTADDR(26) 1446 1446 + #define VIC1VECTADDR27 VIC1VECTADDR(27) 1447 1447 + #define VIC1VECTADDR28 VIC1VECTADDR(28) 1448 1448 + #define VIC1VECTADDR29 VIC1VECTADDR(29) 1449 1449 + #define VIC1VECTADDR30 VIC1VECTADDR(30) 1450 1450 + #define VIC1VECTADDR31 VIC1VECTADDR(31) 1451 1451 + 1452 1452 + #define VIC1VECTPRIORITY(i) VICVECTPRIORITY(1, i) 1453 1453 + #define VIC1VECTPRIORITY0 VIC1VECTPRIORITY(0) 1454 1454 + #define VIC1VECTPRIORITY1 VIC1VECTPRIORITY(1) 1455 1455 + #define VIC1VECTPRIORITY2 VIC1VECTPRIORITY(2) 1456 1456 + #define VIC1VECTPRIORITY3 VIC1VECTPRIORITY(3) 1457 1457 + #define VIC1VECTPRIORITY4 VIC1VECTPRIORITY(4) 1458 1458 + #define VIC1VECTPRIORITY5 VIC1VECTPRIORITY(5) 1459 1459 + #define VIC1VECTPRIORITY6 VIC1VECTPRIORITY(6) 1460 1460 + #define VIC1VECTPRIORITY7 VIC1VECTPRIORITY(7) 1461 1461 + #define VIC1VECTPRIORITY8 VIC1VECTPRIORITY(8) 1462 1462 + #define VIC1VECTPRIORITY9 VIC1VECTPRIORITY(9) 1463 1463 + #define VIC1VECTPRIORITY10 VIC1VECTPRIORITY(10) 1464 1464 + #define VIC1VECTPRIORITY11 VIC1VECTPRIORITY(11) 1465 1465 + #define VIC1VECTPRIORITY12 VIC1VECTPRIORITY(12) 1466 1466 + #define VIC1VECTPRIORITY13 VIC1VECTPRIORITY(13) 1467 1467 + #define VIC1VECTPRIORITY14 VIC1VECTPRIORITY(14) 1468 1468 + #define VIC1VECTPRIORITY15 VIC1VECTPRIORITY(15) 1469 1469 + #define VIC1VECTPRIORITY16 VIC1VECTPRIORITY(16) 1470 1470 + #define VIC1VECTPRIORITY17 VIC1VECTPRIORITY(17) 1471 1471 + #define VIC1VECTPRIORITY18 VIC1VECTPRIORITY(18) 1472 1472 + #define VIC1VECTPRIORITY19 VIC1VECTPRIORITY(19) 1473 1473 + #define VIC1VECTPRIORITY20 VIC1VECTPRIORITY(20) 1474 1474 + #define VIC1VECTPRIORITY21 VIC1VECTPRIORITY(21) 1475 1475 + #define VIC1VECTPRIORITY22 VIC1VECTPRIORITY(22) 1476 1476 + #define VIC1VECTPRIORITY23 VIC1VECTPRIORITY(23) 1477 1477 + #define VIC1VECTPRIORITY24 VIC1VECTPRIORITY(24) 1478 1478 + #define VIC1VECTPRIORITY25 VIC1VECTPRIORITY(25) 1479 1479 + #define VIC1VECTPRIORITY26 VIC1VECTPRIORITY(26) 1480 1480 + #define VIC1VECTPRIORITY27 VIC1VECTPRIORITY(27) 1481 1481 + #define VIC1VECTPRIORITY28 VIC1VECTPRIORITY(28) 1482 1482 + #define VIC1VECTPRIORITY29 VIC1VECTPRIORITY(29) 1483 1483 + #define VIC1VECTPRIORITY30 VIC1VECTPRIORITY(30) 1484 1484 + #define VIC1VECTPRIORITY31 VIC1VECTPRIORITY(31) 1485 1485 + 1486 1486 + #define VIC1ADDRESS VICADDRESS(1) 1504 1487 1505 1488 /////INTERRUPTS///// 1506 1489 #define IRQ_TIMER32 7 1507 1490 #define IRQ_TIMER 8 1508 1491 #define IRQ_SPI(i) (9+(i)) /* TBC */ 1509 1509 - #define IRQ_SPI0 9 1510 1510 - #define IRQ_SPI1 10 1511 1511 - #define IRQ_SPI2 11 1492 1492 + #define IRQ_SPI0 IRQ_SPI(0) 1493 1493 + #define IRQ_SPI1 IRQ_SPI(1) 1494 1494 + #define IRQ_SPI2 IRQ_SPI(2) 1512 1495 #define IRQ_LCD 14 1513 1496 #define IRQ_DMAC(d) (16+(d)) 1514 1514 - #define IRQ_DMAC0 16 1515 1515 - #define IRQ_DMAC1 17 1497 1497 + #define IRQ_DMAC0 IRQ_DMAC(0) 1498 1498 + #define IRQ_DMAC1 IRQ_DMAC(1) 1516 1499 #define IRQ_USB_FUNC 19 1517 1500 #define IRQ_I2C(i) (21+(i)) 1518 1518 - #define IRQ_I2C0 21 1519 1519 - #define IRQ_I2C1 22 1501 1501 + #define IRQ_I2C0 IRQ_I2C(0) 1502 1502 + #define IRQ_I2C1 IRQ_I2C(1) 1520 1503 #define IRQ_WHEEL 23 1521 1504 #define IRQ_UART(i) (24+(i)) 1522 1522 - #define IRQ_UART0 24 1523 1523 - #define IRQ_UART1 25 1524 1524 - #define IRQ_UART2 26 1525 1525 - #define IRQ_UART3 27 1526 1526 - #define IRQ_UART4 28 /* obsolete/not implemented on s5l8702 ??? */ 1505 1505 + #define IRQ_UART0 IRQ_UART(0) 1506 1506 + #define IRQ_UART1 IRQ_UART(1) 1507 1507 + #define IRQ_UART2 IRQ_UART(2) 1508 1508 + #define IRQ_UART3 IRQ_UART(3) 1509 1509 + #define IRQ_UART4 IRQ_UART(4) /* obsolete/not implemented on s5l8702 ??? */ 1527 1510 #define IRQ_ATA 29 1528 1511 #define IRQ_SBOOT 36 1529 1512 #define IRQ_AES 39 ··· 1539 1522 #define IRQ_EXT6 33 1540 1523 #endif 1541 1524 1542 1542 - #endif /* __S5L8700_H__ */ 1525 1525 + #endif /* __S5L87XX_H__ */

+3 -3

firmware/target/arm/ipod/button-clickwheel.c

reviewed

··· 381 381 PDAT10 &= ~2; 382 382 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 383 383 clockgate_enable(CLOCKGATE_CWHEEL, true); 384 384 - PCONE = (PCONE & ~0x00ffff00) | 0x00222200; 384 384 + PCON14 = (PCON14 & ~0x00ffff00) | 0x00222200; 385 385 WHEEL00 = 0; /* stop s5l8702 controller */ 386 386 WHEELINT = 7; 387 387 WHEEL10 = 1; ··· 420 420 #if CONFIG_CPU==S5L8701 421 421 return ((PDAT14 & (1 << 5)) != 0); 422 422 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 423 423 - return ((PDATA & (1 << 6)) != 0); 423 423 + return ((PDAT10 & (1 << 6)) != 0); 424 424 #endif 425 425 } 426 426 #endif ··· 455 455 PWRCONEXT |= 1; 456 456 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 457 457 WHEEL00 = 0; 458 458 - PCONE = (PCONE & ~0x00ffff00) | 0x000e0e00; 458 458 + PCON14 = (PCON14 & ~0x00ffff00) | 0x000e0e00; 459 459 clockgate_enable(CLOCKGATE_CWHEEL, false); 460 460 #endif 461 461 }

+2 -2

firmware/target/arm/s5l8702/ipod6g/power-6g.c

reviewed

··· 72 72 * is not present or it is insufficient or limited, 73 73 * additional required power is drained from battery. 74 74 */ 75 75 - PCONB = (PCONB & 0x000000ff) 75 75 + PCON11 = (PCON11 & 0x000000ff) 76 76 | (0xe << 8) /* route D+ to ADC2: off */ 77 77 | (0xe << 12) /* route D- to ADC2: off */ 78 78 | (0x0 << 16) /* USB related input, POL pin ??? */ ··· 80 80 | (0xe << 24) /* HPWR: 100mA */ 81 81 | (0xe << 28); /* USB suspend: off */ 82 82 83 83 - PCONC = (PCONC & 0xffff0000) 83 83 + PCON12 = (PCON12 & 0xffff0000) 84 84 | (0xe << 0) /* double HPWR limit: off */ 85 85 | (0xe << 4) /* disable battery charge: off */ 86 86 | (0xe << 8) /* disable battery charge: off */

+2 -2

firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c

reviewed

··· 678 678 *((uint32_t volatile*)0x3cf0010c) = 0xff; 679 679 SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK 680 680 | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14; 681 681 - SDCI_CDIV = SDCI_CDIV_CLKDIV(260); 681 681 + SDCI_CLKDIV = SDCI_CDIV_CLKDIV(260); 682 682 *((uint32_t volatile*)0x3cf00200) = 0xb000f; 683 683 SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT; 684 684 PASS_RC(mmc_init(), 3, 0); 685 685 - SDCI_CDIV = SDCI_CDIV_CLKDIV(4); 685 685 + SDCI_CLKDIV = SDCI_CDIV_CLKDIV(4); 686 686 sleep(HZ / 100); 687 687 PASS_RC(ceata_init(8), 3, 1); 688 688 PASS_RC(ata_identify(identify_info), 3, 2);

+2 -2

firmware/target/arm/s5l8702/spi-s5l8702.c

reviewed

··· 51 51 PCON6 = (PCON6 & ~0xffff0000) | (val << 16); 52 52 break; 53 53 case 2: 54 54 - PCONE = (PCONE & ~0xff000000) | (val << 24); 55 55 - PCONF = (PCONF & ~0xff) | (val >> 8); 54 54 + PCON14 = (PCON14 & ~0xff000000) | (val << 24); 55 55 + PCON15 = (PCON15 & ~0xff) | (val >> 8); 56 56 break; 57 57 } 58 58 }

+4 -3

firmware/target/arm/s5l8702/system-s5l8702.c

reviewed

··· 157 157 asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */ 158 158 "sub sp, sp, #8 \n"); /* Reserve stack */ 159 159 160 160 - void* dummy = VIC0ADDRESS; 161 161 - dummy = VIC1ADDRESS; 162 162 - (void)dummy; 160 160 + const void* dummy0 = VIC0ADDRESS; 161 161 + (void)dummy0; 162 162 + const void* dummy1 = VIC1ADDRESS; 163 163 + (void)dummy1; 163 164 uint32_t irqs0 = VIC0IRQSTATUS; 164 165 uint32_t irqs1 = VIC1IRQSTATUS; 165 166 for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1)

+2 -2

firmware/target/arm/s5l8702/uart-s5l8702.c

reviewed

··· 55 55 break; 56 56 case 1: 57 57 /* configure UART1 GPIO ports, including RTS/CTS signals */ 58 58 - PCOND = (PCOND & 0xff0000ff) | 0x00222200; 58 58 + PCON13 = (PCON13 & 0xff0000ff) | 0x00222200; 59 59 break; 60 60 case 2: 61 61 case 3: ··· 74 74 PCON0 = (PCON0 & 0xff00ffff) | 0x00ee0000; 75 75 break; 76 76 case 1: 77 77 - PCOND = (PCOND & 0xff0000ff) | 0x00eeee00; 77 77 + PCON13 = (PCON13 & 0xff0000ff) | 0x00eeee00; 78 78 break; 79 79 case 2: 80 80 case 3: