Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
Fix build errors+warnings introduced in 350a2250b1
Change-Id: Ia5f2079ccc99da30e0058b0d9ce5bb8369201804
+111
-106
+3
firmware/drivers/isp1583.c
+3
firmware/drivers/isp1583.c
···
629
629
int usb_drv_init_endpoint(int endpoint, int type, int max_packet_size)
630
630
{
631
631
(void)max_packet_size; /* FIXME: support max packet size override */
632
+
(void)type;
633
+
(void)endpoint;
632
634
return 0;
633
635
}
634
636
635
637
int usb_drv_deinit_endpoint(int endpoint)
636
638
{
639
+
(void)endpoint;
637
640
return 0;
638
641
}
639
642
+96
-97
firmware/drivers/m66591.c
+96
-97
firmware/drivers/m66591.c
···
47
47
#define HISPEED
48
48
49
49
/* Right now sending blocks till the full transfer has completed. The driver
50
-
* will work without USB_TRAN_BLOCK set, but it is more than 50% slower.
50
+
* will work without USB_TRAN_BLOCK set, but it is more than 50% slower.
51
51
* The driver is more "Proper" without USB_TRAN_BLOCK defined so if you start
52
52
* having freezeups or trouble using USB undefine this option.
53
53
*/
···
72
72
static void control_received(void);
73
73
static void transfer_complete(int endpoint);
74
74
static int mxx_transmit_receive(int endpoint);
75
-
static int mxx_queue(int endpoint, void * ptr, int length, bool send,
75
+
static int mxx_queue(int endpoint, void * ptr, int length, bool send,
76
76
bool wait);
77
77
78
78
struct M66591_epstat {
···
97
97
static void pipe_init(int pipe) {
98
98
volatile unsigned short *pipe_cfg;
99
99
pipe_cfg = pipe_ctrl_addr(pipe);
100
-
100
+
101
101
*pipe_cfg |= 1<<9; /* ACLR */
102
102
*pipe_cfg &= ~(1<<9); /* Force de-assertion */
103
103
*pipe_cfg |= 1<<8; /* SQCLR */
···
106
106
/* This function sets the pipe/endpoint handshake */
107
107
static void pipe_handshake(int pipe, int handshake) {
108
108
handshake&=0x03;
109
-
109
+
110
110
if(handshake == PIPE_SHAKE_STALL) {
111
111
if( *(pipe_ctrl_addr(pipe)) & 0x03 ) {
112
112
*(pipe_ctrl_addr(pipe)) = 0x03;
···
122
122
* warites/reads are valid */
123
123
static void pipe_c_select (int pipe, bool dir) {
124
124
M66591_CPORT_CTRL0 = pipe | (1<<10) | (dir<<5);
125
-
125
+
126
126
// Wait for the Pipe to be valid;
127
-
udelay(2);
127
+
udelay(2);
128
128
}
129
129
130
130
#if !defined(USB_TRAN_BLOCK)
···
199
199
static void control_received(void) {
200
200
/* copy setup data from packet */
201
201
static struct usb_ctrlrequest temp;
202
-
202
+
203
203
memcpy(&temp, (unsigned char*)&M66591_USB_REQ0, 8);
204
-
204
+
205
205
logf("mxx: bReqType=0x%02x bReq=0x%02x wVal=0x%04x"
206
-
" wIdx=0x%04x wLen=0x%04x",
206
+
" wIdx=0x%04x wLen=0x%04x",
207
207
temp.bRequestType, temp.bRequest, temp.wValue,
208
208
temp.wIndex, temp.wLength);
209
209
···
220
220
M66591_INTCFG_EMP &= ~(1 << endpoint);
221
221
logf("mxx: ep %d transfer complete", endpoint);
222
222
int temp=M66591_eps[endpoint].dir ? USB_DIR_IN : USB_DIR_OUT;
223
-
usb_core_transfer_complete(endpoint, temp, 0,
223
+
usb_core_transfer_complete(endpoint, temp, 0,
224
224
M66591_eps[endpoint].count);
225
225
}
226
226
···
229
229
*/
230
230
static int mxx_transmit_receive(int endpoint) {
231
231
logf("mxx: do start");
232
-
232
+
233
233
/* Only the lower 15 bits of the endpoint correlate to the pipe number.
234
234
* For example pipe 2 will corelate to endpoint 0x82, so the upper bits
235
235
* need to be masked out.
···
238
238
239
239
int i; /* Used as a loop counter */
240
240
int length; /* Used in transfers to determine the amount to send/receive */
241
-
241
+
242
242
bool send=M66591_eps[endpoint].dir;
243
-
243
+
244
244
/* This is used as the internal buffer pointer */
245
245
unsigned short *ptrs;
246
246
···
265
265
length = M66591_eps[endpoint].length;
266
266
#else
267
267
int bufsize=pipe_buffer_size(endpoint);
268
-
length=MIN(M66591_eps[endpoint].length - M66591_eps[endpoint].count,
268
+
length=MIN(M66591_eps[endpoint].length - M66591_eps[endpoint].count,
269
269
bufsize);
270
270
#endif
271
271
···
274
274
*/
275
275
ptrs = (unsigned short *)(M66591_eps[endpoint].buf
276
276
+ M66591_eps[endpoint].count);
277
-
277
+
278
278
/* Check if the buffer is alligned */
279
279
if( LIKELY(((int)ptrs) & 0x01) == 0 )
280
280
{
281
281
/* Start sending data in 16-bit words (fast) */
282
-
for (i = 0; i < (length>>1); i++) {
282
+
for (i = 0; i < (length>>1); i++) {
283
283
#if defined(USB_TRAN_BLOCK)
284
-
/* This wait is dangerous in the event that something happens
285
-
* to the PHY pipe where it never becomes ready again, should
284
+
/* This wait is dangerous in the event that something happens
285
+
* to the PHY pipe where it never becomes ready again, should
286
286
* probably add a timeout, and ideally completely remove.
287
287
*/
288
288
while(!(M66591_CPORT_CTRL1&(1<<13))){};
···
291
291
M66591_CPORT = *ptrs++;
292
292
M66591_eps[endpoint].count+=2;
293
293
}
294
-
295
-
/* If the length is odd, send the last byte after setting the byte
294
+
295
+
/* If the length is odd, send the last byte after setting the byte
296
296
* width of the FIFO.
297
297
*/
298
298
if(length & 0x01) {
···
304
304
}
305
305
else
306
306
{
307
-
/* The buffer is mis-aligned - data needs to be organized first.
307
+
/* The buffer is mis-aligned - data needs to be organized first.
308
308
* This is slower than the above method.
309
309
*/
310
310
unsigned short sbuf;
311
311
unsigned char *ptrc = (unsigned char*)ptrs;
312
-
312
+
313
313
/* Start sending data in 16-bit words */
314
-
for (i = 0; i < (length>>1); i++) {
314
+
for (i = 0; i < (length>>1); i++) {
315
315
#if defined(USB_TRAN_BLOCK)
316
-
/* This wait is dangerous in the event that something happens
317
-
* to the PHY pipe where it never becomes ready again, should
316
+
/* This wait is dangerous in the event that something happens
317
+
* to the PHY pipe where it never becomes ready again, should
318
318
* probably add a timeout, and ideally completely remove.
319
319
*/
320
320
while(!(M66591_CPORT_CTRL1&(1<<13))){};
···
329
329
M66591_CPORT = sbuf;
330
330
M66591_eps[endpoint].count+=2;
331
331
}
332
-
333
-
/* If the length is odd, send the last byte after setting the byte
332
+
333
+
/* If the length is odd, send the last byte after setting the byte
334
334
* width of the FIFO.
335
335
*/
336
336
if(length & 0x01) {
···
340
340
M66591_eps[endpoint].count++;
341
341
}
342
342
}
343
-
343
+
344
344
/* If the transfer is complete set up interrupts to notify when FIFO is
345
345
* EMPTY, disable READY and let the handler know that there is nothing
346
346
* left to transfer on this pipe.
···
356
356
/* There is still data to transfer, make sure READY is enabled */
357
357
M66591_INTCFG_RDY |= 1 << endpoint;
358
358
}
359
-
359
+
360
360
/* Set BVAL if length is not a multiple of the maximum packet size */
361
361
if( (length == 0) || (length % maxpack != 0) ) {
362
362
logf("mxx: do set BVAL");
···
364
364
}
365
365
} else {
366
366
/* Read data from FIFO */
367
-
367
+
368
368
/* Read the number of bytes that the PHY received */
369
369
int receive_length=M66591_CPORT_CTRL1 & 0x03FF;
370
-
370
+
371
371
/* The number of bytes to actually read is either what's left of the
372
372
* amount requested, or the amount that the PHY received. Choose the
373
373
* smaller of the two.
374
374
*/
375
-
length = MIN(M66591_eps[endpoint].length - M66591_eps[endpoint].count,
375
+
length = MIN(M66591_eps[endpoint].length - M66591_eps[endpoint].count,
376
376
receive_length);
377
377
378
378
/* If the length is zero, just clear the buffer as specified in the
379
379
* datasheet. Otherwise read in the data (in 16-bit pieces */
380
380
if(length==0) {
381
381
/* Set the BCLR bit */
382
-
M66591_CPORT_CTRL1 |= 1<<14;
382
+
M66591_CPORT_CTRL1 |= 1<<14;
383
383
} else {
384
384
/* Set the position in the buffer */
385
-
ptrs = (unsigned short *)(M66591_eps[endpoint].buf
385
+
ptrs = (unsigned short *)(M66591_eps[endpoint].buf
386
386
+ M66591_eps[endpoint].count);
387
-
387
+
388
388
/* Read in the data (buffer size should be even). The PHY cannot
389
389
* switch from 16-bit mode to 8-bit mode on an OUT buffer.
390
390
*/
···
393
393
M66591_eps[endpoint].count+=2;
394
394
}
395
395
}
396
-
396
+
397
397
/* If the length was odd subtract 1 from the count */
398
398
M66591_eps[endpoint].count -= (length&0x01);
399
-
399
+
400
400
/* If the requested size of data was received, or the data received was
401
401
* less than the maximum packet size end the transfer.
402
402
*/
403
-
if( (M66591_eps[endpoint].count == M66591_eps[endpoint].length)
403
+
if( (M66591_eps[endpoint].count == M66591_eps[endpoint].length)
404
404
|| (length % pipe_maxpack_size(endpoint)) ) {
405
-
405
+
406
406
/* If the host tries to send anything else the FIFO is not ready/
407
407
* enabled yet (NAK).
408
408
*/
···
411
411
M66591_eps[endpoint].waiting=false;
412
412
/* Disable ready */
413
413
M66591_INTCFG_RDY &= ~(1 << endpoint);
414
-
414
+
415
415
/* Let the stack know that the transfer is complete */
416
416
if(endpoint!=0)
417
417
transfer_complete(endpoint);
418
418
}
419
419
}
420
-
421
-
logf("mxx: do done ep %d %s len: %d cnt: %d", endpoint,
420
+
421
+
logf("mxx: do done ep %d %s len: %d cnt: %d", endpoint,
422
422
send ? "out" : "in", length, M66591_eps[endpoint].count);
423
423
424
424
return 0;
425
425
}
426
426
427
-
/* This function is used to start transfers. It is a helper function for the
427
+
/* This function is used to start transfers. It is a helper function for the
428
428
* usb_drv_send_nonblocking, usb_drv_send, and usb_drv_receive functions.
429
429
*
430
-
* The functionality for wait needs to be added. Currently the driver is
430
+
* The functionality for wait needs to be added. Currently the driver is
431
431
* always used in a blocking mode(USB_TRAN_BLOCK) so it is not required.
432
432
*/
433
-
static int mxx_queue(int endpoint, void * ptr, int length, bool send,
434
-
bool wait)
433
+
static int mxx_queue(int endpoint, void * ptr, int length, bool send,
434
+
bool wait)
435
435
{
436
436
#if defined(USB_TRAN_BLOCK) && !defined(LOGF_ENABLE)
437
437
(void) wait;
···
445
445
* need to be masked out.
446
446
*/
447
447
endpoint &= 0x7F;
448
-
448
+
449
449
/* Initialize the enpoint status registers used for the transfer */
450
450
M66591_eps[endpoint].buf=ptr;
451
451
M66591_eps[endpoint].length=length;
···
453
453
M66591_eps[endpoint].dir=send;
454
454
M66591_eps[endpoint].waiting=true;
455
455
456
-
logf("mxx: queue ep %d %s, len: %d, wait: %d",
456
+
logf("mxx: queue ep %d %s, len: %d, wait: %d",
457
457
endpoint, send ? "out" : "in", length, wait);
458
-
458
+
459
459
/* Pick the pipe that communications are happening on */
460
460
pipe_c_select(endpoint, send);
461
461
462
462
/* All transfers start with a BUF handshake */
463
463
pipe_handshake(endpoint, PIPE_SHAKE_BUF);
464
-
464
+
465
465
/* This USB PHY takes care of control completion packets by setting the
466
466
* CCPL bit in EP0 (endpoint 0, or DCP). If the control state is "write no
467
-
* data tranfer" then we just need to set the CCPL bit (hopefully)
467
+
* data tranfer" then we just need to set the CCPL bit (hopefully)
468
468
* regardless of what the stack said to send.
469
469
*/
470
470
int control_state = (M66591_INTSTAT_MAIN & 0x07);
471
471
if(endpoint==0 && control_state==CTRL_WTND) {
472
472
logf("mxx: queue ep 0 ctls: 5, set ccpl");
473
-
473
+
474
474
/* Set CCPL */
475
-
M66591_DCPCTRL |= 1<<2;
475
+
M66591_DCPCTRL |= 1<<2;
476
476
} else {
477
477
/* This is the standard case for transmitting data */
478
478
if(send) {
479
-
/* If the pipe is not ready don't try and send right away; instead
479
+
/* If the pipe is not ready don't try and send right away; instead
480
480
* just set the READY interrupt so that the handler can initiate
481
481
* the transfer.
482
482
*/
···
485
485
} else {
486
486
M66591_INTCFG_RDY |= 1 << endpoint;
487
487
}
488
-
488
+
489
489
if(length==0) {
490
490
transfer_complete(endpoint);
491
491
}
···
510
510
void USB_DEVICE(void) {
511
511
int pipe_restore=M66591_CPORT_CTRL0;
512
512
logf("\nmxx: INT BEGIN tick: %d", (int) current_tick);
513
-
514
-
logf("mxx: sMAIN0: 0x%04x, sRDY: 0x%04x",
513
+
514
+
logf("mxx: sMAIN0: 0x%04x, sRDY: 0x%04x",
515
515
M66591_INTSTAT_MAIN, M66591_INTSTAT_RDY);
516
-
logf("mxx: sNRDY: 0x%04x, sEMP: 0x%04x",
516
+
logf("mxx: sNRDY: 0x%04x, sEMP: 0x%04x",
517
517
M66591_INTSTAT_NRDY, M66591_INTSTAT_EMP);
518
518
519
519
/* VBUS (connected) interrupt */
···
537
537
/* Device state transition interrupt: Not used, but useful for debugging */
538
538
if(M66591_INTSTAT_MAIN & (1<<12)) {
539
539
M66591_INTSTAT_MAIN &= ~(1<<12);
540
-
logf("mxx: DEV state CHANGE=%d",
540
+
logf("mxx: DEV state CHANGE=%d",
541
541
((M66591_INTSTAT_MAIN & (0x07<<4)) >> 4) );
542
542
}
543
543
···
545
545
if(M66591_INTSTAT_MAIN & (1<<11)) {
546
546
M66591_INTSTAT_MAIN &= ~(1<<11);
547
547
int control_state = (M66591_INTSTAT_MAIN & 0x07);
548
-
548
+
549
549
logf("mxx: CTRT with CTSQ=%d", control_state);
550
-
550
+
551
551
switch ( control_state ) {
552
552
case CTRL_IDLE:
553
553
transfer_complete(0);
554
554
break;
555
-
case CTRL_RTDS:
555
+
case CTRL_RTDS:
556
556
case CTRL_WTDS:
557
557
case CTRL_WTND:
558
558
/* If data is not valid stop */
···
572
572
break;
573
573
}
574
574
}
575
-
575
+
576
576
/* FIFO EMPTY interrupt: when this happens the transfer should be complete.
577
577
* When the interrupt occurs notify the stack.
578
578
*/
579
579
if(M66591_INTSTAT_MAIN & (1<<10)) {
580
580
int i;
581
581
logf("mxx: INT EMPTY: 0x%04x", M66591_INTSTAT_EMP);
582
-
582
+
583
583
for(i=0; i<USB_NUM_ENDPOINTS; i++) {
584
584
if(M66591_INTSTAT_EMP&(1<<i)) {
585
585
/* Clear the empty flag */
···
589
589
}
590
590
}
591
591
}
592
-
592
+
593
593
/* FIFO NOT READY interrupt: This is not used, but included incase the
594
594
* interrupt is endabled.
595
595
*/
···
602
602
if(M66591_INTSTAT_MAIN & (1<<8)) {
603
603
int i;
604
604
logf("mxx: INT READY: 0x%04x", M66591_INTSTAT_RDY);
605
-
605
+
606
606
for(i=0; i<USB_NUM_ENDPOINTS; i++) {
607
607
/* Was this endpoint ready and waiting */
608
608
if(M66591_INTSTAT_RDY&(1<<i) && M66591_eps[i].waiting) {
···
613
613
}
614
614
}
615
615
}
616
-
616
+
617
617
/* Make sure that the INTStatus register is completely cleared. */
618
618
M66591_INTSTAT_MAIN = 0;
619
-
619
+
620
620
/* Restore the pipe state before the interrupt occured */
621
621
M66591_CPORT_CTRL0=pipe_restore;
622
622
logf("mxx: INT END\n");
···
643
643
int usb_drv_init_endpoint(int endpoint, int type, int max_packet_size) {
644
644
(void)max_packet_size; /* FIXME: support max packet size override */
645
645
646
-
int pipecfg;
646
+
int pipecfg = 0;
647
647
648
648
if(type == USB_ENDPOINT_XFER_BULK) {
649
649
/* Enable double buffer mode (only used for ep 1 and 2) */
650
-
pipecfg |= 1<<9 | 1<<8;
650
+
pipecfg |= 1<<9 | 1<<8;
651
651
} else if(type == USB_ENDPOINT_XFER_BULK) {
652
652
pipecfg |= 1<<13;
653
653
} else {
···
662
662
}
663
663
664
664
M66591_eps[num].dir = dir;
665
-
665
+
666
666
M66591_PIPE_CFGSEL=num;
667
667
668
668
/* Enable pipe (15) */
669
-
pipecfg |= 1<<15;
670
-
669
+
pipecfg |= 1<<15;
670
+
671
671
pipe_handshake(num, PIPE_SHAKE_NAK);
672
672
673
673
/* Setup the flags */
674
674
M66591_PIPE_CFGWND=pipecfg;
675
-
675
+
676
676
pipe_init(num);
677
-
677
+
678
678
logf("mxx: ep req ep#: %d config: 0x%04x", num, M66591_PIPE_CFGWND);
679
679
680
680
return 0;
···
689
689
}
690
690
691
691
int flags = disable_irq_save();
692
-
692
+
693
693
logf("mxx: ep %d release", num);
694
694
695
695
M66591_eps[num].dir = -1;
···
719
719
/* This is where the driver stuff starts */
720
720
void usb_drv_init(void) {
721
721
logf("mxx: Device Init");
722
-
722
+
723
723
M66591_PIN_CFG1 = 0x8000; /* Drive Current: 3.3V setting */
724
724
M66591_PIN_CFG2 = 0x0000;
725
-
725
+
726
726
M66591_TRN_CTRL = 0x8000; /* External 48 MHz clock */
727
727
M66591_TRN_CTRL |=0x0001;
728
728
···
744
744
/* fully enable driver */
745
745
void usb_attach(void) {
746
746
int i;
747
-
747
+
748
748
/* Reset Endpoint states */
749
749
for(i=0; i<USB_NUM_ENDPOINTS; i++) {
750
750
M66591_eps[i].dir = -1;
···
757
757
/* Issue a h/w reset */
758
758
usb_init_device();
759
759
usb_core_init();
760
-
761
-
/* USB Attach Process: This follows the flow diagram in the M66591GP
760
+
761
+
/* USB Attach Process: This follows the flow diagram in the M66591GP
762
762
* Reference Manual Rev 1.00, p. 77 */
763
763
764
764
#if defined(HISPEED)
···
784
784
785
785
/* Disable PIPE ready interrupts */
786
786
M66591_INTCFG_RDY = 0;
787
-
787
+
788
788
/* Disable PIPE not-ready interrupts */
789
789
M66591_INTCFG_NRDY = 0;
790
-
790
+
791
791
/* Disable PIPE empyt/size error interrupts */
792
792
M66591_INTCFG_EMP = 0;
793
793
···
795
795
M66591_INTCFG_MAIN = 0x1DFF;
796
796
797
797
pipe_c_select(0, false);
798
-
798
+
799
799
/* Enable continuous transfer mode on the DCP */
800
800
M66591_DCP_CNTMD |= (1<<8);
801
-
801
+
802
802
/* Set the threshold that the PHY will automatically transmit from EP0 */
803
803
M66591_DCP_CTRLEN = 256;
804
-
804
+
805
805
pipe_handshake(0, PIPE_SHAKE_NAK);
806
-
806
+
807
807
/* Set the Max packet size to 64 */
808
808
M66591_DCP_MXPKSZ = 64;
809
809
···
814
814
}
815
815
816
816
void usb_drv_exit(void) {
817
-
/* USB Detach Process: This follows the flow diagram in the M66591GP
817
+
/* USB Detach Process: This follows the flow diagram in the M66591GP
818
818
* Reference Manual Rev 1.00, p. 78.
819
819
*/
820
820
···
868
868
return mxx_queue(endpoint, ptr, length, false, false);
869
869
}
870
870
871
-
/* This function checks the reset handshake speed status
871
+
/* This function checks the reset handshake speed status
872
872
* (Fullspeed or Highspeed)
873
873
*/
874
874
int usb_drv_port_speed(void)
875
875
{
876
876
int handshake = (M66591_HSFS & 0xFF);
877
-
877
+
878
878
if( handshake == 0x02) {
879
879
return 0; /* Handshook at Full-Speed */
880
880
} else if( handshake == 0x03) {
···
890
890
bool usb_drv_stalled(int endpoint,bool in)
891
891
{
892
892
(void) in;
893
-
893
+
894
894
bool stalled = (*(pipe_ctrl_addr(endpoint)) & (0x02)) ? true : false;
895
-
895
+
896
896
logf("mxx: stall?: %s ep: %d", stalled ? "true" : "false", endpoint);
897
-
897
+
898
898
if(stalled) {
899
899
return true;
900
900
} else {
···
909
909
void usb_drv_stall(int endpoint, bool stall,bool in)
910
910
{
911
911
(void) in;
912
-
912
+
913
913
logf("mxx: stall - ep: %d", endpoint);
914
-
914
+
915
915
if(stall) {
916
916
/* Stall the pipe (host needs to intervene/error) */
917
917
pipe_handshake(endpoint, PIPE_SHAKE_STALL);
···
935
935
M66591_eps[endpoint].buf = NULL;
936
936
}
937
937
}
938
-
938
+
939
939
restore_irq(flags);
940
940
}
941
-
+4
-4
firmware/target/arm/as3525/usb-drv-as3525.c
+4
-4
firmware/target/arm/as3525/usb-drv-as3525.c
···
38
38
39
39
/* OUT EP 2 is an alias for OUT EP 0 on this HW! */
40
40
struct usb_drv_ep_spec usb_drv_ep_specs[USB_NUM_EPS] = {
41
-
[0] = {USB_ENDPOINT_XFER_CONTROL, USB_ENDPOINT_XFER_CONTROL},
42
-
[1] = {USB_ENDPOINT_TYPE_ANY, USB_ENDPOINT_TYPE_ANY},
43
-
[2] = {USB_ENDPOINT_TYPE_NONE, USB_ENDPOINT_TYPE_ANY},
44
-
[3] = {USB_ENDPOINT_TYPE_ANY, USB_ENDPOINT_TYPE_ANY},
41
+
{.type = {USB_ENDPOINT_XFER_CONTROL, USB_ENDPOINT_XFER_CONTROL}},
42
+
{.type = {USB_ENDPOINT_TYPE_ANY, USB_ENDPOINT_TYPE_ANY}},
43
+
{.type = {USB_ENDPOINT_TYPE_NONE, USB_ENDPOINT_TYPE_ANY}},
44
+
{.type = {USB_ENDPOINT_TYPE_ANY, USB_ENDPOINT_TYPE_ANY}},
45
45
};
46
46
uint8_t usb_drv_ep_specs_flags = 0;
47
47
+7
-5
firmware/target/arm/rk27xx/usb-drv-rk27xx.c
+7
-5
firmware/target/arm/rk27xx/usb-drv-rk27xx.c
···
56
56
volatile void *buf; /* tx/rx buffer address */
57
57
volatile int len; /* size of the transfer (bytes) */
58
58
volatile int cnt; /* number of bytes transfered/received */
59
-
volatile bool block; /* flag indicating that transfer is blocking */
59
+
volatile bool block; /* flag indicating that transfer is blocking */
60
60
struct semaphore complete; /* semaphore for blocking transfers */
61
61
};
62
62
···
73
73
#define DMAINLMADDR(endp) *(4 + (endp)->stat)
74
74
75
75
#define ENDPOINT(num, type, dir, reg) \
76
-
{num, USB_ENDPOINT_XFER_##type, USB_DIR_##dir, reg, false, NULL, 0, 0, true, {{0, 0}, 0, 0}}
76
+
{num, USB_ENDPOINT_XFER_##type, USB_DIR_##dir, reg, NULL, 0, 0, true, {{0, 0}, 0, 0}}
77
77
78
78
static struct endpoint_t ctrlep[2] =
79
79
{
···
284
284
(void)max_packet_size; /* FIXME: support max packet size override */
285
285
286
286
int num = EP_NUM(endpoint);
287
-
int dir = EP_DIR(endpoint);
287
+
// int dir = EP_DIR(endpoint);
288
+
(void)type;
288
289
289
290
struct endpoint_t *endp = &endpoints[num];
290
291
···
299
300
300
301
int usb_drv_deinit_endpoint(int endpoint) {
301
302
int num = EP_NUM(endpoint);
302
-
struct endpoint_t *endp = &endpoints[num];
303
+
// struct endpoint_t *endp = &endpoints[num];
303
304
304
305
/* disable interrupt from this endpoint */
305
306
EN_INT &= ~(1 << (num + 7));
307
+
return 0;
306
308
}
307
309
308
310
/* Set the address (usually it's in a register).
···
376
378
}
377
379
378
380
/* Kill all transfers. Usually you need to set a bit for each endpoint
379
-
* and flush fifos. You should also call the completion handler with
381
+
* and flush fifos. You should also call the completion handler with
380
382
* error status for everything
381
383
*/
382
384
void usb_drv_cancel_all_transfers(void)
+1
firmware/target/mips/ingenic_jz47xx/usb-jz4760.c
+1
firmware/target/mips/ingenic_jz47xx/usb-jz4760.c