Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
echoplayer: implement audio playback
Playback is implemented using a target-specific PCM layer,
using the STM32H7 SAI & DMA registers directly. There are
a number of pop/click issues:
1. Slight click when powering up the amplifiers
2. Click when starting and stopping playback
3. Popping when changing playback frequency
4. Popping when shutting down
It should be possible to eliminate or at least mitigate
(2) to (4) in software, but (1) happens as a result of
powering on the amplifiers while everything is muted so
might be unavoidable.
Change-Id: I398b66596176fb2341beb7deba7bf6f4f3fb82b3
authored by
Aidan MacDonald
and committed by
Solomon Peachy
5c1ae511
b782f15e
+500
-109
+3
-1
firmware/SOURCES
+3
-1
firmware/SOURCES
···
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#endif
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target/arm/stm32/gpio-stm32h7.c
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target/arm/stm32/i2c-stm32h7.c
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-
target/arm/stm32/pcm-stm32h7.c
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target/arm/stm32/sdmmc-stm32h7.c
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target/arm/stm32/spi-stm32h7.c
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target/arm/stm32/system-stm32h7.c
···
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target/arm/stm32/echoplayer/clock-echoplayer.c
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target/arm/stm32/echoplayer/i2c-echoplayer.c
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target/arm/stm32/echoplayer/lcd-echoplayer.c
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#ifndef BOOTLOADER
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target/arm/stm32/echoplayer/pcm-echoplayer.c
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#endif
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target/arm/stm32/echoplayer/power-echoplayer.c
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target/arm/stm32/echoplayer/sdmmc-echoplayer.c
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1966
target/arm/stm32/echoplayer/system-echoplayer.c
+5
firmware/export/config/echor1.h
+5
firmware/export/config/echor1.h
···
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/* Codec / audio hardware defines */
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#define HW_SAMPR_CAPS SAMPR_CAP_ALL_96 // FIXME: check this section
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#define HAVE_ECHOPLAYER_CODEC
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#define HAVE_AIC310X
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#define HAVE_SW_TONE_CONTROLS
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#define HAVE_SW_VOLUME_CONTROL
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+
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#ifndef SIMULATOR
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#define PCM_NATIVE_BITDEPTH 32
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#endif
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/* Button defines */
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#define CONFIG_KEYPAD ECHO_R1_PAD
+4
firmware/export/echoplayer_codec.h
+4
firmware/export/echoplayer_codec.h
···
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#ifndef __ECHOPLAYER_CODEC_H__
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#define __ECHOPLAYER_CODEC_H__
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#include <stdbool.h>
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/* -79 to 0 dB in 0.5 dB steps; software volume control
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* is used because the hardware volume controls "click"
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* when changing the volume */
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AUDIOHW_SETTING(VOLUME, "dB", 1, 5, -790, 0, -200);
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void audiohw_mute(bool mute);
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#endif /* __ECHOPLAYER_CODEC_H__ */
+132
-2
firmware/target/arm/stm32/echoplayer/audiohw-echoplayer.c
+132
-2
firmware/target/arm/stm32/echoplayer/audiohw-echoplayer.c
···
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*
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****************************************************************************/
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#include "audiohw.h"
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#include "kernel.h"
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#include "panic.h"
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#include "aic310x.h"
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#include "pcm_sw_volume.h"
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#include "power-echoplayer.h"
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#include "gpio-stm32h7.h"
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#include "i2c-echoplayer.h"
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+
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static int tlv_read_multiple(uint8_t reg, uint8_t *data, size_t count)
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{
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return stm32_i2c_read_mem(&i2c1_ctl, AIC310X_I2C_ADDR, reg, data, count);
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}
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static int tlv_write_multiple(uint8_t reg, const uint8_t *data, size_t count)
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{
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return stm32_i2c_write_mem(&i2c1_ctl, AIC310X_I2C_ADDR, reg, data, count);
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}
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static struct aic310x tlv_codec = {
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.read_multiple = tlv_read_multiple,
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.write_multiple = tlv_write_multiple,
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};
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struct codec_reg_data
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{
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uint8_t reg;
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uint8_t val;
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};
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static const struct codec_reg_data codec_init_seq[] = {
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/* Set output driver configuration to stereo psuedo-differential */
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{ .reg = AIC310X_HEADSET_DETECT_B, .val = 0x08 },
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+
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/* Clock input is CODEC_CLKIN (bypass codec PLL) */
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{ .reg = AIC310X_CLOCK, .val = 0x01 },
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/* Route left ch. -> left DAC, right ch -> right DAC */
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{ .reg = AIC310X_DATA_PATH, .val = 0x0A },
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/* Power on DACs, set HPLCOM = VCM, set HPRCOM = VCM,
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* enable short circuit protection */
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{ .reg = AIC310X_HPOUT_DRIVER_CTRL, .val = 0x0C },
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{ .reg = AIC310X_DAC_POWER_CTRL, .val = 0xD0 },
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+
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/* Unmute the DACs */
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{ .reg = AIC310X_LEFT_DAC_DIGITAL_VOLUME, .val = 0x00 },
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{ .reg = AIC310X_RIGHT_DAC_DIGITAL_VOLUME, .val = 0x00 },
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+
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/* Route DACs to output drivers */
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{ .reg = AIC310X_DAC_L1_TO_HPLOUT_VOLUME, .val = 0x80 },
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{ .reg = AIC310X_DAC_R1_TO_HPROUT_VOLUME, .val = 0x80 },
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+
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/* Route DACs to line out port */
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{ .reg = AIC310X_DAC_L1_TO_LEFT_LO_VOLUME, .val = 0x80 },
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{ .reg = AIC310X_DAC_R1_TO_RIGHT_LO_VOLUME, .val = 0x80 },
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/* Power on headphone output drivers */
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{ .reg = AIC310X_HPLCOM_LEVEL_CONTROL, .val = 0x01 },
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{ .reg = AIC310X_HPRCOM_LEVEL_CONTROL, .val = 0x01 },
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{ .reg = AIC310X_HPLOUT_LEVEL_CONTROL, .val = 0x01 },
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{ .reg = AIC310X_HPROUT_LEVEL_CONTROL, .val = 0x01 },
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/* Power up line out drivers */
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{ .reg = AIC310X_RIGHT_LO_LEVEL_CONTROL, .val = 0x01 },
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{ .reg = AIC310X_LEFT_LO_LEVEL_CONTROL, .val = 0x01 },
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};
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static void write_aic310x_seq(const struct codec_reg_data *seq, size_t count)
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{
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while (count > 0)
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{
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if (aic310x_write(&tlv_codec, seq->reg, seq->val))
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panicf("aic310x wr fail: %02x", (unsigned int)seq->reg);
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seq++;
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count--;
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}
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}
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static void wait_aic310x_active(void)
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{
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long end_tick = current_tick + HZ;
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while (TIME_BEFORE(current_tick, end_tick))
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{
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uint8_t tmp;
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int err = tlv_read_multiple(AIC310X_PAGE_SELECT, &tmp, 1);
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if (err == 0)
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return;
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sleep(1);
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}
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panicf("aic310x init timeout");
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}
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void audiohw_init(void)
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{
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/* initialize driver */
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aic310x_init(&tlv_codec);
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/* bring 1.8v regulator up */
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echoplayer_enable_1v8_regulator(true);
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/* apply AVDD/DRVDD and DVDD */
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gpio_set_level(GPIO_CODEC_AVDD_EN, 0);
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gpio_set_level(GPIO_CODEC_DVDD_EN, 0);
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/* delay for power stabilization */
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sleep(HZ/100);
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/* bring codec out of reset */
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gpio_set_level(GPIO_CODEC_RESET, 1);
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}
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void audiohw_postinit(void)
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{
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wait_aic310x_active();
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write_aic310x_seq(codec_init_seq, ARRAYLEN(codec_init_seq));
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}
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void audiohw_close(void)
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{
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/* apply reset */
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gpio_set_level(GPIO_CODEC_RESET, 0);
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/* remove power */
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gpio_set_level(GPIO_CODEC_AVDD_EN, 1);
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gpio_set_level(GPIO_CODEC_DVDD_EN, 1);
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/* disable regulator */
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echoplayer_enable_1v8_regulator(false);
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}
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void audiohw_mute(bool mute)
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{
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uint8_t wr_val = (mute ? 0x01 : 0x09);
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/* Mute and unmute at the output drivers */
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aic310x_write(&tlv_codec, AIC310X_HPLOUT_LEVEL_CONTROL, wr_val);
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aic310x_write(&tlv_codec, AIC310X_HPROUT_LEVEL_CONTROL, wr_val);
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aic310x_write(&tlv_codec, AIC310X_LEFT_LO_LEVEL_CONTROL, wr_val);
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aic310x_write(&tlv_codec, AIC310X_RIGHT_LO_LEVEL_CONTROL, wr_val);
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}
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void audiohw_set_volume(int vol_l, int vol_r)
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{
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(void)vol_l;
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(void)vol_r;
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pcm_set_master_volume(vol_l, vol_r);
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}
+2
-1
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
+2
-1
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
···
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/*
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* Use HSE/4 input for PLL1
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* Use HSE/16 input for PLL3
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* PLL2 reserved for audio; configured in target PCM code
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*/
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reg_writef(RCC_PLLCKSELR,
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PLLSRC_V(HSE),
···
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INIT_ATTR static void init_periph_clock(void)
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{
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reg_writef(RCC_D1CCIPR, SDMMCSEL_V(PLL1Q));
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reg_writef(RCC_D2CCIP1R, SPI45SEL_V(HSE));
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reg_writef(RCC_D2CCIP1R, SAI1SEL_V(PLL2P), SPI45SEL_V(HSE));
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reg_writef(RCC_D2CCIP2R, I2C123SEL_V(HSI));
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/* Enable AXI SRAM in sleep mode to allow DMA'ing out of it */
+354
firmware/target/arm/stm32/echoplayer/pcm-echoplayer.c
+354
firmware/target/arm/stm32/echoplayer/pcm-echoplayer.c
···
1
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2026 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "pcm.h"
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#include "pcm_sampr.h"
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#include "pcm-internal.h"
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#include "audiohw.h"
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#include "panic.h"
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#include "nvic-arm.h"
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#include "dmamux-stm32h743.h"
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/sai.h"
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#include "regs/stm32h743/dma.h"
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#include "regs/stm32h743/dmamux.h"
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#include <stdatomic.h>
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/* Configurable bit depth */
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#if PCM_NATIVE_BITDEPTH == 32
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# define PCM_NATIVE_SAMPLE_SIZE 4
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# define DMA_PSIZE_VAL BV_DMA_CHN_CR_PSIZE_32BIT
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# define SAI_DSIZE_VAL BV_SAI_SUBBLOCK_CR1_DS_32BIT
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# define SAI_FIFO_THRESH BV_SAI_SUBBLOCK_CR2_FTH_QUARTER
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# define SAI_FRL_VAL 64
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#elif PCM_NATIVE_BITDEPTH == 24
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# define PCM_NATIVE_SAMPLE_SIZE 4
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# define DMA_PSIZE_VAL BV_DMA_CHN_CR_PSIZE_32BIT
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# define SAI_DSIZE_VAL BV_SAI_SUBBLOCK_CR1_DS_24BIT
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# define SAI_FIFO_THRESH BV_SAI_SUBBLOCK_CR2_FTH_QUARTER
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# define SAI_FRL_VAL 64
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#elif PCM_NATIVE_BITDEPTH == 16
48
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# define PCM_NATIVE_SAMPLE_SIZE 2
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# define DMA_PSIZE_VAL BV_DMA_CHN_CR_PSIZE_16BIT
50
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# define SAI_DSIZE_VAL BV_SAI_SUBBLOCK_CR1_DS_16BIT
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# define SAI_FIFO_THRESH BV_SAI_SUBBLOCK_CR2_FTH_HALF
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# define SAI_FRL_VAL 32
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#else
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# error "Unsupported PCM bit depth"
55
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#endif
56
+
57
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static const uintptr_t sai1 = ITA_SAI1;
58
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static const uintptr_t sai1a = sai1 + ITO_SAI_A;
59
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static const uintptr_t dmamux1 = ITA_DMAMUX1;
60
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static const uintptr_t dma1 = ITA_DMA1;
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static const uintptr_t dma1_ch0 = dma1 + ITO_DMA_CHN(0);
62
+
63
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static atomic_size_t play_lock;
64
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static volatile int play_active;
65
+
66
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static int pcm_last_freq = -1;
67
+
68
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static void play_dma_start(const void *addr, size_t size)
69
+
{
70
+
commit_dcache_range(addr, size);
71
+
72
+
/*
73
+
* The number of transfers is defined by PSIZE, which may
74
+
* be 16-bit or 32-bit depending on PCM native sample size.
75
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* Each FIFO write transfers 1 sample, so we want to set
76
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* NDT = size / PCM_NATIVE_SAMPLE_SIZE.
77
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*
78
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* When MSIZE == 32-bit and PSIZE == 16-bit, the DMA will
79
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* take each 32-bit word from memory and write the lower/upper
80
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* halfwords separately to the FIFO. The number of reads from
81
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* memory in this case is NDT/2, so we're still transferring
82
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* the correct amount of data.
83
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*/
84
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reg_varl(dma1_ch0, DMA_CHN_NDTR) = size / PCM_NATIVE_SAMPLE_SIZE;
85
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reg_varl(dma1_ch0, DMA_CHN_M0AR) = (uintptr_t)addr;
86
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reg_writelf(dma1_ch0, DMA_CHN_CR, EN(1));
87
+
88
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
89
+
}
90
+
91
+
static void sai_init(void)
92
+
{
93
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/* Enable SAI1 and DMA1 */
94
+
reg_writef(RCC_APB2ENR, SAI1EN(1));
95
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reg_writef(RCC_AHB1ENR, DMA1EN(1));
96
+
97
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/* Link DMA1_CH0 to SAI1A */
98
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reg_writelf(dmamux1, DMAMUX_CR(0), DMAREQ_ID(DMAMUX1_REQ_SAI1A_DMA));
99
+
100
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/* Configure DMA1 channel 0 */
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reg_writelf(dma1_ch0, DMA_CHN_CR,
102
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MBURST_V(INCR4), /* 32-bit x 4 burst = 16 bytes */
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PBURST_V(INCR4), /* (16|32)-bit x 4 burst = 8-16 bytes */
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TRBUFF(0), /* bufferable mode not used for SAI */
105
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DBM(0), /* double buffer mode off */
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PL_V(VERYHIGH), /* highest priority */
107
+
MSIZE_V(32BIT), /* read 32-bit words from memory */
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PSIZE(DMA_PSIZE_VAL), /* set according to PCM bit depth */
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MINC(1), /* increment memory address */
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PINC(0), /* don't increment peripheral address */
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CIRC(0), /* circular mode off */
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DIR_V(MEM_TO_PERIPH), /* read from memory, write to SAI */
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PFCTRL_V(DMA), /* DMA is flow controller */
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TCIE(1), /* transfer complete interrupt */
115
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TEIE(1), /* transfer error interrupt */
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DMEIE(1)); /* direct mode error interrupt */
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reg_writelf(dma1_ch0, DMA_CHN_FCR,
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FEIE(1), /* fifo error interrupt */
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DMDIS(1), /* enable fifo mode */
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FTH_V(FULL)); /* fifo threshold = 4 words */
121
+
122
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/* Set peripheral address here since it's constant */
123
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reg_varl(dma1_ch0, DMA_CHN_PAR) =
124
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(uintptr_t)reg_ptrl(sai1a, SAI_SUBBLOCK_DR);
125
+
126
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/* Configure SAI for playback */
127
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reg_writelf(sai1a, SAI_SUBBLOCK_CR1,
128
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OSR_V(256FS), /* MCLK is 256 x Fs */
129
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NOMCK(0), /* MCLK enabled */
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DMAEN(0), /* DMA request disabled */
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SAIEN(0), /* SAI disabled */
132
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OUTDRIV(0), /* drive outputs when SAIEN=1 */
133
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MONO(0), /* stereo mode */
134
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SYNCEN_V(ASYNC), /* no sync with other SAIs */
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CKSTR_V(TX_FALLING_RX_RISING), /* clock edge for sampling */
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LSBFIRST(0), /* transmit samples MSB first */
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DS(SAI_DSIZE_VAL), /* sample size according to bit depth */
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PRTCFG_V(FREE), /* free protocol */
139
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MODE_V(MASTER_TX)); /* operate as bus master */
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reg_writelf(sai1a, SAI_SUBBLOCK_CR2,
141
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MUTEVAL_V(ZERO_SAMPLE), /* send zero sample on mute */
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MUTE(1), /* mute output initially */
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TRIS(0), /* don't tri-state outputs */
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FTH(SAI_FIFO_THRESH)); /* fifo threshold (2 or 4 samples) */
145
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reg_writelf(sai1a, SAI_SUBBLOCK_FRCR,
146
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FSOFF(1), FSPOL(0), FSDEF(1), /* I2S format */
147
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FSALL(SAI_FRL_VAL/2 - 1), /* FS active for half the frame */
148
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FRL(SAI_FRL_VAL - 1)); /* set frame length */
149
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reg_writelf(sai1a, SAI_SUBBLOCK_SLOTR,
150
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SLOTEN(3), NBSLOT(2 - 1), /* enable first two slots */
151
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SLOTSZ_V(DATASZ), /* slot size = data size */
152
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FBOFF(0)); /* no bit offset in slot */
153
+
154
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/* Enable interrupts in NVIC */
155
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nvic_enable_irq(NVIC_IRQN_DMA1_STR0);
156
+
}
157
+
158
+
struct div_settings
159
+
{
160
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uint8_t pllm;
161
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uint8_t plln;
162
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uint8_t pllp;
163
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uint8_t mckdiv;
164
+
};
165
+
166
+
_Static_assert(STM32_HSE_FREQ == 24000000,
167
+
"Audio clock settings only valid for 24MHz HSE");
168
+
169
+
static const struct div_settings div_settings[] = {
170
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[HW_FREQ_96] = { .pllm = 5, .plln = 128 - 1, .pllp = 25 - 1, .mckdiv = 0 }, /* exact */
171
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[HW_FREQ_48] = { .pllm = 5, .plln = 128 - 1, .pllp = 25 - 1, .mckdiv = 2 }, /* exact */
172
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[HW_FREQ_24] = { .pllm = 5, .plln = 128 - 1, .pllp = 25 - 1, .mckdiv = 4 }, /* exact */
173
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[HW_FREQ_12] = { .pllm = 5, .plln = 128 - 1, .pllp = 25 - 1, .mckdiv = 8 }, /* exact */
174
+
175
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[HW_FREQ_88] = { .pllm = 4, .plln = 143 - 1, .pllp = 38 - 1, .mckdiv = 0 }, /* -11ppm error */
176
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[HW_FREQ_44] = { .pllm = 4, .plln = 143 - 1, .pllp = 38 - 1, .mckdiv = 2 }, /* -11ppm error */
177
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[HW_FREQ_22] = { .pllm = 5, .plln = 147 - 1, .pllp = 125 - 1, .mckdiv = 0 }, /* exact */
178
+
[HW_FREQ_11] = { .pllm = 5, .plln = 147 - 1, .pllp = 125 - 1, .mckdiv = 2 }, /* exact */
179
+
180
+
[HW_FREQ_64] = { .pllm = 15, .plln = 256 - 1, .pllp = 25 - 1, .mckdiv = 0 }, /* exact */
181
+
[HW_FREQ_32] = { .pllm = 15, .plln = 256 - 1, .pllp = 25 - 1, .mckdiv = 2 }, /* exact */
182
+
[HW_FREQ_16] = { .pllm = 15, .plln = 256 - 1, .pllp = 25 - 1, .mckdiv = 4 }, /* exact */
183
+
[HW_FREQ_8 ] = { .pllm = 15, .plln = 256 - 1, .pllp = 25 - 1, .mckdiv = 8 }, /* exact */
184
+
};
185
+
186
+
static void sai_set_pll(const struct div_settings *div)
187
+
{
188
+
/* Disable the PLL so it can be reconfigured */
189
+
if (reg_readf(RCC_CR, PLL2RDY))
190
+
{
191
+
reg_writef(RCC_CR, PLL2ON(0));
192
+
while (reg_readf(RCC_CR, PLL2RDY));
193
+
while (reg_readf(RCC_CR, PLL2ON));
194
+
}
195
+
196
+
/* Set the PLL configuration */
197
+
uint32_t pllcfgr = reg_var(RCC_PLLCFGR);
198
+
199
+
reg_writef(RCC_PLLCKSELR,
200
+
DIVM2(div->pllm));
201
+
reg_writef(RCC_PLL2DIVR,
202
+
DIVN(div->plln),
203
+
DIVP(div->pllp),
204
+
DIVQ(0), DIVR(0));
205
+
reg_vwritef(pllcfgr, RCC_PLLCFGR,
206
+
DIVP2EN(1),
207
+
DIVQ2EN(0),
208
+
DIVR2EN(0),
209
+
PLL2FRACEN(0),
210
+
PLL2VCOSEL_V(WIDE));
211
+
212
+
if (div->pllm <= 6)
213
+
reg_vwritef(pllcfgr, RCC_PLLCFGR, PLL2RGE_V(4_8MHZ));
214
+
else if (div->pllm <= 12)
215
+
reg_vwritef(pllcfgr, RCC_PLLCFGR, PLL2RGE_V(2_4MHZ));
216
+
else
217
+
reg_vwritef(pllcfgr, RCC_PLLCFGR, PLL2RGE_V(1_2MHZ));
218
+
219
+
reg_var(RCC_PLLCFGR) = pllcfgr;
220
+
221
+
/* Enable the PLL again */
222
+
reg_writef(RCC_CR, PLL2ON(1));
223
+
while (!reg_readf(RCC_CR, PLL2RDY));
224
+
}
225
+
226
+
static void sai_set_frequency(int freq)
227
+
{
228
+
/* Can't change frequency while the SAI is active */
229
+
if (reg_readlf(sai1a, SAI_SUBBLOCK_CR1, SAIEN))
230
+
panicf("%s while SAI active", __func__);
231
+
232
+
const struct div_settings *div = &div_settings[freq];
233
+
const struct div_settings *old_div = NULL;
234
+
235
+
if (pcm_last_freq >= 0)
236
+
old_div = &div_settings[pcm_last_freq];
237
+
238
+
if (old_div == NULL ||
239
+
div->pllm != old_div->pllm ||
240
+
div->plln != old_div->plln ||
241
+
div->pllp != old_div->pllp)
242
+
{
243
+
sai_set_pll(div);
244
+
}
245
+
246
+
/* Configure the MCK divider in SAI */
247
+
reg_writelf(sai1a, SAI_SUBBLOCK_CR1, MCKDIV(div->mckdiv));
248
+
}
249
+
250
+
static void sink_dma_init(void)
251
+
{
252
+
sai_init();
253
+
audiohw_init();
254
+
}
255
+
256
+
static void sink_set_freq(uint16_t freq)
257
+
{
258
+
/*
259
+
* Muting here doesn't seem to help clicks when switching
260
+
* tracks of different frequencies; the audio may need to
261
+
* be soft-muted in software before the switch.
262
+
*/
263
+
audiohw_mute(true);
264
+
265
+
sai_set_frequency(freq);
266
+
pcm_last_freq = freq;
267
+
268
+
audiohw_mute(false);
269
+
}
270
+
271
+
static void sink_dma_start(const void *addr, size_t size)
272
+
{
273
+
play_active = true;
274
+
275
+
play_dma_start(addr, size);
276
+
reg_writelf(sai1a, SAI_SUBBLOCK_CR1, SAIEN(1), DMAEN(1));
277
+
reg_writelf(sai1a, SAI_SUBBLOCK_CR2, MUTE(0));
278
+
}
279
+
280
+
static void sink_dma_stop(void)
281
+
{
282
+
play_active = false;
283
+
284
+
reg_writelf(sai1a, SAI_SUBBLOCK_CR2, MUTE(1));
285
+
reg_writelf(sai1a, SAI_SUBBLOCK_CR1, SAIEN(0), DMAEN(0));
286
+
reg_writelf(dma1_ch0, DMA_CHN_CR, EN(0));
287
+
288
+
/* Must wait for SAIEN bit to be cleared */
289
+
while (reg_readlf(sai1a, SAI_SUBBLOCK_CR1, SAIEN));
290
+
}
291
+
292
+
static void sink_lock(void)
293
+
{
294
+
/* Disable IRQ on first lock */
295
+
if (atomic_fetch_add_explicit(&play_lock, 1, memory_order_relaxed) == 0)
296
+
nvic_disable_irq_sync(NVIC_IRQN_DMA1_STR0);
297
+
}
298
+
299
+
static void sink_unlock(void)
300
+
{
301
+
/* Enable IRQ on release of last lock */
302
+
if (atomic_fetch_sub_explicit(&play_lock, 1, memory_order_relaxed) == 1)
303
+
nvic_enable_irq(NVIC_IRQN_DMA1_STR0);
304
+
}
305
+
306
+
struct pcm_sink builtin_pcm_sink = {
307
+
.caps = {
308
+
.samprs = hw_freq_sampr,
309
+
.num_samprs = HW_NUM_FREQ,
310
+
.default_freq = HW_FREQ_DEFAULT,
311
+
},
312
+
.ops = {
313
+
.init = sink_dma_init,
314
+
.postinit = audiohw_postinit,
315
+
.set_freq = sink_set_freq,
316
+
.lock = sink_lock,
317
+
.unlock = sink_unlock,
318
+
.play = sink_dma_start,
319
+
.stop = sink_dma_stop,
320
+
},
321
+
};
322
+
323
+
void dma1_ch0_irq_handler(void)
324
+
{
325
+
uint32_t lisr = reg_varl(dma1, DMA_LISR);
326
+
const void *addr;
327
+
size_t size;
328
+
329
+
if (reg_vreadf(lisr, DMA_LISR, TEIF0) ||
330
+
reg_vreadf(lisr, DMA_LISR, DMEIF0) ||
331
+
reg_vreadf(lisr, DMA_LISR, FEIF0))
332
+
{
333
+
reg_assignlf(dma1, DMA_LIFCR, TEIF0(1), DMEIF0(1), FEIF0(1));
334
+
reg_writelf(dma1_ch0, DMA_CHN_CR, EN(0));
335
+
336
+
pcm_play_dma_status_callback(PCM_DMAST_ERR_DMA);
337
+
}
338
+
else if (reg_vreadf(lisr, DMA_LISR, TCIF0))
339
+
{
340
+
reg_assignlf(dma1, DMA_LIFCR, TCIF0(1));
341
+
342
+
/* If we call the complete callback while not playing
343
+
* it can cause the PCM layer to get stuck... somehow */
344
+
if (!play_active)
345
+
return;
346
+
347
+
if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &addr, &size))
348
+
play_dma_start(addr, size);
349
+
}
350
+
else
351
+
{
352
+
panicf("%s: %08lx", __func__, lisr);
353
+
}
354
+
}
-105
firmware/target/arm/stm32/pcm-stm32h7.c
-105
firmware/target/arm/stm32/pcm-stm32h7.c
···
1
-
/***************************************************************************
2
-
* __________ __ ___.
3
-
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
-
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
-
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
-
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
-
* \/ \/ \/ \/ \/
8
-
* $Id$
9
-
*
10
-
* Copyright (C) 2025 Aidan MacDonald
11
-
*
12
-
* This program is free software; you can redistribute it and/or
13
-
* modify it under the terms of the GNU General Public License
14
-
* as published by the Free Software Foundation; either version 2
15
-
* of the License, or (at your option) any later version.
16
-
*
17
-
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18
-
* KIND, either express or implied.
19
-
*
20
-
****************************************************************************/
21
-
#include "pcm.h"
22
-
#include "pcm-internal.h"
23
-
#include "pcm_sampr.h"
24
-
#include "pcm_sink.h"
25
-
26
-
static void sink_set_freq(uint16_t freq)
27
-
{
28
-
(void)freq;
29
-
}
30
-
31
-
static void sink_dma_init(void)
32
-
{
33
-
}
34
-
35
-
static void sink_dma_postinit(void)
36
-
{
37
-
}
38
-
39
-
static void sink_dma_start(const void *addr, size_t size)
40
-
{
41
-
(void)addr;
42
-
(void)size;
43
-
}
44
-
45
-
static void sink_dma_stop(void)
46
-
{
47
-
}
48
-
49
-
static void sink_lock(void)
50
-
{
51
-
}
52
-
53
-
static void sink_unlock(void)
54
-
{
55
-
}
56
-
57
-
struct pcm_sink builtin_pcm_sink = {
58
-
.caps = {
59
-
.samprs = hw_freq_sampr,
60
-
.num_samprs = HW_NUM_FREQ,
61
-
.default_freq = HW_FREQ_DEFAULT,
62
-
},
63
-
.ops = {
64
-
.init = sink_dma_init,
65
-
.postinit = sink_dma_postinit,
66
-
.set_freq = sink_set_freq,
67
-
.lock = sink_lock,
68
-
.unlock = sink_unlock,
69
-
.play = sink_dma_start,
70
-
.stop = sink_dma_stop,
71
-
},
72
-
};
73
-
74
-
#ifdef HAVE_RECORDING
75
-
void pcm_rec_dma_init(void)
76
-
{
77
-
}
78
-
79
-
void pcm_rec_dma_close(void)
80
-
{
81
-
}
82
-
83
-
void pcm_rec_dma_start(void *addr, size_t size)
84
-
{
85
-
(void)addr;
86
-
(void)size;
87
-
}
88
-
89
-
void pcm_rec_dma_stop(void)
90
-
{
91
-
}
92
-
93
-
void pcm_rec_lock(void)
94
-
{
95
-
}
96
-
97
-
void pcm_rec_unlock(void)
98
-
{
99
-
}
100
-
101
-
const void *pcm_rec_dma_get_peak_buffer(void)
102
-
{
103
-
return NULL;
104
-
}
105
-
#endif