+1

firmware/target/arm/nvic-arm.h

reviewed

··· 22 22 #define __NVIC_ARM_H__ 23 23 24 24 #include "system.h" 25 25 + #include "nvic-target.h" 25 26 #include "regs/cortex-m/cm_nvic.h" 26 27 27 28 #define NVIC_MAX_PRIO 0xFF

+167

firmware/target/arm/stm32/nvic-stm32h743.h

reviewed

··· 1 1 + /*************************************************************************** 2 2 + * __________ __ ___. 3 3 + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 + * \/ \/ \/ \/ \/ 8 8 + * $Id$ 9 9 + * 10 10 + * Copyright (C) 2025 by Aidan MacDonald 11 11 + * 12 12 + * This program is free software; you can redistribute it and/or 13 13 + * modify it under the terms of the GNU General Public License 14 14 + * as published by the Free Software Foundation; either version 2 15 15 + * of the License, or (at your option) any later version. 16 16 + * 17 17 + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 18 18 + * KIND, either express or implied. 19 19 + * 20 20 + ****************************************************************************/ 21 21 + #ifndef __NVIC_STM32H743_H__ 22 22 + #define __NVIC_STM32H743_H__ 23 23 + 24 24 + #define NVIC_IRQN_WWDG1 0 25 25 + #define NVIC_IRQN_PVD_PVM 1 26 26 + #define NVIC_IRQN_RTC_TAMP_STAMP_CSS_LSE 2 27 27 + #define NVIC_IRQN_RTC_WKUP 3 28 28 + #define NVIC_IRQN_FLASH 4 29 29 + #define NVIC_IRQN_RCC 5 30 30 + #define NVIC_IRQN_EXTI0 6 31 31 + #define NVIC_IRQN_EXTI1 7 32 32 + #define NVIC_IRQN_EXTI2 8 33 33 + #define NVIC_IRQN_EXTI3 9 34 34 + #define NVIC_IRQN_EXTI4 10 35 35 + #define NVIC_IRQN_DMA1_STR0 11 36 36 + #define NVIC_IRQN_DMA1_STR1 12 37 37 + #define NVIC_IRQN_DMA1_STR2 13 38 38 + #define NVIC_IRQN_DMA1_STR3 14 39 39 + #define NVIC_IRQN_DMA1_STR4 15 40 40 + #define NVIC_IRQN_DMA1_STR5 16 41 41 + #define NVIC_IRQN_DMA1_STR6 17 42 42 + #define NVIC_IRQN_ADC1_2 18 43 43 + #define NVIC_IRQN_FDCAN1_IT0 19 44 44 + #define NVIC_IRQN_FDCAN2_IT0 20 45 45 + #define NVIC_IRQN_FDCAN1_IT1 21 46 46 + #define NVIC_IRQN_FDCAN2_IT1 22 47 47 + #define NVIC_IRQN_EXTI9_5 23 48 48 + #define NVIC_IRQN_TIM1_BRK 24 49 49 + #define NVIC_IRQN_TIM1_UP 25 50 50 + #define NVIC_IRQN_TIM1_TRG_COM 26 51 51 + #define NVIC_IRQN_TIM1_CC 27 52 52 + #define NVIC_IRQN_TIM2 28 53 53 + #define NVIC_IRQN_TIM3 29 54 54 + #define NVIC_IRQN_TIM4 30 55 55 + #define NVIC_IRQN_I2C1_EV 31 56 56 + #define NVIC_IRQN_I2C1_ER 32 57 57 + #define NVIC_IRQN_I2C2_EV 33 58 58 + #define NVIC_IRQN_I2C2_ER 34 59 59 + #define NVIC_IRQN_SPI1 35 60 60 + #define NVIC_IRQN_SPI2 36 61 61 + #define NVIC_IRQN_USART1 37 62 62 + #define NVIC_IRQN_USART2 38 63 63 + #define NVIC_IRQN_USART3 39 64 64 + #define NVIC_IRQN_EXTI15_10 40 65 65 + #define NVIC_IRQN_RTC_ALARM 41 66 66 + #define NVIC_IRQN_TIM8_BRK_TIM12 43 67 67 + #define NVIC_IRQN_TIM8_UP_TIM13 44 68 68 + #define NVIC_IRQN_TIM8_TRG_COM_TIM14 45 69 69 + #define NVIC_IRQN_TIM8_CC 46 70 70 + #define NVIC_IRQN_DMA1_STR7 47 71 71 + #define NVIC_IRQN_FMC 48 72 72 + #define NVIC_IRQN_SDMMC1 49 73 73 + #define NVIC_IRQN_TIM5 50 74 74 + #define NVIC_IRQN_SPI3 51 75 75 + #define NVIC_IRQN_UART4 52 76 76 + #define NVIC_IRQN_UART5 53 77 77 + #define NVIC_IRQN_TIM6_DAC 54 78 78 + #define NVIC_IRQN_TIM7 55 79 79 + #define NVIC_IRQN_DMA2_STR0 56 80 80 + #define NVIC_IRQN_DMA2_STR1 57 81 81 + #define NVIC_IRQN_DMA2_STR2 58 82 82 + #define NVIC_IRQN_DMA2_STR3 59 83 83 + #define NVIC_IRQN_DMA2_STR4 60 84 84 + #define NVIC_IRQN_ETH 61 85 85 + #define NVIC_IRQN_ETH_WKUP 62 86 86 + #define NVIC_IRQN_FDCAN_CAL 63 87 87 + #define NVIC_IRQN_CM7_SEV 64 88 88 + #define NVIC_IRQN_DMA2_STR5 68 89 89 + #define NVIC_IRQN_DMA2_STR6 69 90 90 + #define NVIC_IRQN_DMA2_STR7 70 91 91 + #define NVIC_IRQN_USART6 71 92 92 + #define NVIC_IRQN_I2C3_EV 72 93 93 + #define NVIC_IRQN_I2C3_ER 73 94 94 + #define NVIC_IRQN_OTG_HS_EP1_OUT 74 95 95 + #define NVIC_IRQN_OTG_HS_EP1_IN 75 96 96 + #define NVIC_IRQN_OTG_HS_WKUP 76 97 97 + #define NVIC_IRQN_OTG_HS 77 98 98 + #define NVIC_IRQN_DCMI 78 99 99 + #define NVIC_IRQN_CRYP 79 100 100 + #define NVIC_IRQN_HASH_RNG 80 101 101 + #define NVIC_IRQN_FPU 81 102 102 + #define NVIC_IRQN_UART7 82 103 103 + #define NVIC_IRQN_UART8 83 104 104 + #define NVIC_IRQN_SPI4 84 105 105 + #define NVIC_IRQN_SPI5 85 106 106 + #define NVIC_IRQN_SPI6 86 107 107 + #define NVIC_IRQN_SAI1 87 108 108 + #define NVIC_IRQN_LTDC 88 109 109 + #define NVIC_IRQN_LTDC_ER 89 110 110 + #define NVIC_IRQN_DMA2D 90 111 111 + #define NVIC_IRQN_SAI2 91 112 112 + #define NVIC_IRQN_QUADSPI 92 113 113 + #define NVIC_IRQN_LPTIM1 93 114 114 + #define NVIC_IRQN_CEC 94 115 115 + #define NVIC_IRQN_I2C4_EV 95 116 116 + #define NVIC_IRQN_I2C4_ER 96 117 117 + #define NVIC_IRQN_SPDIF 97 118 118 + #define NVIC_IRQN_OTG_FS_EP1_OUT 98 119 119 + #define NVIC_IRQN_OTG_FS_EP1_IN 99 120 120 + #define NVIC_IRQN_OTG_FS_WKUP 100 121 121 + #define NVIC_IRQN_OTG_FS 101 122 122 + #define NVIC_IRQN_DMAMUX1_OV 102 123 123 + #define NVIC_IRQN_HRTIM1_MST 103 124 124 + #define NVIC_IRQN_HRTIM1_TIMA 104 125 125 + #define NVIC_IRQN_HRTIM1_TIMB 105 126 126 + #define NVIC_IRQN_HRTIM1_TIMC 106 127 127 + #define NVIC_IRQN_HRTIM1_TIMD 107 128 128 + #define NVIC_IRQN_HRTIM1_TIME 108 129 129 + #define NVIC_IRQN_HRTIM1_FLT 109 130 130 + #define NVIC_IRQN_DFSDM1_FLT0 110 131 131 + #define NVIC_IRQN_DFSDM1_FLT1 111 132 132 + #define NVIC_IRQN_DFSDM1_FLT2 112 133 133 + #define NVIC_IRQN_DFSDM1_FLT3 113 134 134 + #define NVIC_IRQN_SAI3 114 135 135 + #define NVIC_IRQN_SWPMI1 115 136 136 + #define NVIC_IRQN_TIM15 116 137 137 + #define NVIC_IRQN_TIM16 117 138 138 + #define NVIC_IRQN_TIM17 118 139 139 + #define NVIC_IRQN_MDIOS_WKUP 119 140 140 + #define NVIC_IRQN_MDIOS 120 141 141 + #define NVIC_IRQN_JPEG 121 142 142 + #define NVIC_IRQN_MDMA 122 143 143 + #define NVIC_IRQN_SDMMC2 124 144 144 + #define NVIC_IRQN_HSEM0 125 145 145 + #define NVIC_IRQN_ADC3 127 146 146 + #define NVIC_IRQN_DMAMUX2_OVR 128 147 147 + #define NVIC_IRQN_BDMA_CH0 129 148 148 + #define NVIC_IRQN_BDMA_CH1 130 149 149 + #define NVIC_IRQN_BDMA_CH2 131 150 150 + #define NVIC_IRQN_BDMA_CH3 132 151 151 + #define NVIC_IRQN_BDMA_CH4 133 152 152 + #define NVIC_IRQN_BDMA_CH5 134 153 153 + #define NVIC_IRQN_BDMA_CH6 135 154 154 + #define NVIC_IRQN_BDMA_CH7 136 155 155 + #define NVIC_IRQN_COMP 137 156 156 + #define NVIC_IRQN_LPTIM2 138 157 157 + #define NVIC_IRQN_LPTIM3 139 158 158 + #define NVIC_IRQN_LPTIM4 140 159 159 + #define NVIC_IRQN_LPTIM5 141 160 160 + #define NVIC_IRQN_LPUART 142 161 161 + #define NVIC_IRQN_WWDG1_RST 143 162 162 + #define NVIC_IRQN_CRS 144 163 163 + #define NVIC_IRQN_RAMECC 145 164 164 + #define NVIC_IRQN_SAI4 146 165 165 + #define NVIC_IRQN_WKUP 149 166 166 + 167 167 + #endif /* __NVIC_STM32H743_H__ */

+32

firmware/target/arm/stm32/nvic-target.h

reviewed

··· 1 1 + /*************************************************************************** 2 2 + * __________ __ ___. 3 3 + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 4 4 + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 5 5 + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 6 6 + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 7 7 + * \/ \/ \/ \/ \/ 8 8 + * $Id$ 9 9 + * 10 10 + * Copyright (C) 2025 by Aidan MacDonald 11 11 + * 12 12 + * This program is free software; you can redistribute it and/or 13 13 + * modify it under the terms of the GNU General Public License 14 14 + * as published by the Free Software Foundation; either version 2 15 15 + * of the License, or (at your option) any later version. 16 16 + * 17 17 + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 18 18 + * KIND, either express or implied. 19 19 + * 20 20 + ****************************************************************************/ 21 21 + #ifndef __NVIC_TARGET_H__ 22 22 + #define __NVIC_TARGET_H__ 23 23 + 24 24 + #include "config.h" 25 25 + 26 26 + #if CONFIG_CPU == STM32H743 27 27 + # include "nvic-stm32h743.h" 28 28 + #else 29 29 + # error "Unknown STM32 CPU!" 30 30 + #endif 31 31 + 32 32 + #endif /* __NVIC_TARGET_H__ */