Rockbox open source high quality audio player as a Music Player Daemon
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rockbox
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libadwaita
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zig
deno
s5l87xx: Add S5L8720 registers
This adds some confirmed and some to-be-confirmed (TBC) registers for Samsung S5L8720, which is used in iPod Nano 4G, iPod Touch 2G and the 920-0614-03 development/prototype board.
All credit goes to Cástor Muñoz <cmvidal@gmail.com>
Change-Id: I9fe5052fe9f05cd33f34de4e228cdb291944aa11
authored by
Vencislav Atanasov
and committed by
Solomon Peachy
88a1d902
6231407d
+274
-74
+6
-6
apps/plugins/crypt_firmware.c
+6
-6
apps/plugins/crypt_firmware.c
···
103
103
static void calc_hash(uint32_t* data, uint32_t size, uint32_t* result)
104
104
{
105
105
uint32_t ptr, i;
106
-
uint32_t ctrl = 2;
106
+
uint32_t config = 2;
107
107
108
108
PWRCONEXT &= ~0x4;
109
109
110
110
for (ptr = 0; ptr < (size >> 2); ptr += 0x10)
111
111
{
112
-
for (i = 0; i < 0x10; i++) HASHDATAIN[i] = data[ptr + i];
113
-
HASHCTRL = ctrl;
114
-
ctrl = 0xA;
115
-
while ((HASHCTRL & 1) != 0);
112
+
for (i = 0; i < 0x10; i++) SHA1DATAIN[i] = data[ptr + i];
113
+
SHA1CONFIG = ctrl;
114
+
config = 0xA;
115
+
while ((SHA1CONFIG & 1) != 0);
116
116
}
117
-
for (i = 0; i < 5; i ++) result[i] = HASHRESULT[i];
117
+
for (i = 0; i < 5; i ++) result[i] = SHA1RESULT[i];
118
118
119
119
PWRCONEXT |= 0x4;
120
120
}
+268
-68
firmware/export/s5l87xx.h
+268
-68
firmware/export/s5l87xx.h
···
33
33
34
34
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
35
35
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
36
-
#elif CONFIG_CPU==S5L8702
36
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
37
37
#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
38
38
#endif
39
39
40
-
#if CONFIG_CPU==S5L8702
40
+
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
41
41
#define DRAM_ORIG 0x08000000
42
42
#define IRAM_ORIG 0x22000000
43
43
44
-
#define DRAM_SIZE (MEMORYSIZE * 0x100000)
45
-
#define IRAM_SIZE 0x40000
44
+
#define IRAM0_ORIG IRAM_ORIG
45
+
#define IRAM0_SIZE 0x20000
46
+
#define IRAM1_ORIG (IRAM0_ORIG + IRAM0_SIZE)
47
+
48
+
#if CONFIG_CPU==S5L8702
49
+
#define IRAM1_SIZE 0x20000
50
+
#elif CONFIG_CPU==S5L8720
51
+
#define IRAM1_SIZE 0x10000
52
+
#endif
53
+
54
+
#define DRAM_SIZE (MEMORYSIZE * 0x100000)
55
+
#define IRAM_SIZE (IRAM0_SIZE + IRAM1_SIZE)
46
56
47
57
#define TTB_SIZE 0x4000
48
58
#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
49
-
50
-
#define IRAM0_ORIG 0x22000000
51
-
#define IRAM0_SIZE 0x20000
52
-
#define IRAM1_ORIG 0x22020000
53
-
#define IRAM1_SIZE 0x20000
54
59
#endif
55
60
56
61
/* 04. CALMADM2E */
···
155
160
#define DSPCLKMD (*(REG32_PTR_T)(CLK_BASE + 0x38)) /* DSP clock mode register */
156
161
#define CLKCON2 (*(REG32_PTR_T)(CLK_BASE + 0x3C)) /* Clock control register 2 */
157
162
#define PWRCONEXT (*(REG32_PTR_T)(CLK_BASE + 0x40)) /* Clock power control register 2 */
158
-
#elif CONFIG_CPU==S5L8702
163
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
159
164
#define CLKCON0 (*((REG32_PTR_T)(CLK_BASE)))
160
165
#define CLKCON1 (*((REG32_PTR_T)(CLK_BASE + 0x04)))
161
166
#define CLKCON2 (*((REG32_PTR_T)(CLK_BASE + 0x08)))
···
170
175
#define PLL2LCNT (*((REG32_PTR_T)(CLK_BASE + 0x38)))
171
176
#define PLLLOCK (*((REG32_PTR_T)(CLK_BASE + 0x40)))
172
177
#define PLLMODE (*((REG32_PTR_T)(CLK_BASE + 0x44)))
178
+
/* s5l8702 only uses PWRCON0 and PWRCON1 */
173
179
#define PWRCON(i) (*((REG32_PTR_T)(CLK_BASE \
174
180
+ ((i) == 4 ? 0x6C : \
175
181
((i) == 3 ? 0x68 : \
···
183
189
#define RSTSR_WDR_BIT (1 << 2)
184
190
#define RSTSR_SWR_BIT (1 << 1)
185
191
#define RSTSR_HWR_BIT (1 << 0)
192
+
193
+
#if CONFIG_CPU==S5L8720
194
+
#define CLKCON6 (*((volatile uint32_t*)(CLK_BASE + 0x70)))
195
+
#endif
186
196
#endif
187
197
188
198
#if CONFIG_CPU==S5L8700
···
198
208
#define CLOCKGATE_SMx 3
199
209
#define CLOCKGATE_SM1 4
200
210
#define CLOCKGATE_ATA 5
211
+
#define CLOCKGATE_NAND 8
201
212
#define CLOCKGATE_SDCI 9
202
213
#define CLOCKGATE_AES 10
214
+
#define CLOCKGATE_NANDECC 12
203
215
#define CLOCKGATE_DMAC0 25
204
216
#define CLOCKGATE_DMAC1 26
205
217
#define CLOCKGATE_ROM 30
···
219
231
#define CLOCKGATE_CHIPID 46
220
232
#define CLOCKGATE_I2S2 47
221
233
#define CLOCKGATE_SPI2 48
234
+
#elif CONFIG_CPU==S5L8720
235
+
/* PWRCON0 - 18 gates (0..17) */
236
+
#define CLOCKGATE_SHA 0
237
+
#define CLOCKGATE_LCD 1 // TBC
238
+
#define CLOCKGATE_USBOTG 2
239
+
#define CLOCKGATE_SMx 3 // TBC
240
+
#define CLOCKGATE_SM1 4 // TBC
241
+
#define CLOCKGATE_NAND 5
242
+
#define CLOCKGATE_AES 7
243
+
#define CLOCKGATE_NANDECC 9
244
+
#define CLOCKGATE_DMAC0 11 // TBC
245
+
#define CLOCKGATE_DMAC1 12 // TBC
246
+
#define CLOCKGATE_ROM 13
247
+
248
+
#define CLOCKGATE_UNK14 14 // this could also be DMAC0
249
+
// #define CLOCKGATE_UNK15 15
250
+
// #define CLOCKGATE_UNK16 16
251
+
// #define CLOCKGATE_UNK17 17
252
+
253
+
/* PWRCON1 - 32 gates (32..63)*/
254
+
// #define CLOCKGATE_RTC 32
255
+
#define CLOCKGATE_CWHEEL 33 // TBC
256
+
#define CLOCKGATE_SPI0 34
257
+
#define CLOCKGATE_USBPHY 35
258
+
#define CLOCKGATE_I2C0 36
259
+
#define CLOCKGATE_TIMERA 37
260
+
261
+
#define CLOCKGATE_I2C1 38 // TBC
262
+
// #define CLOCKGATE_I2S0 39
263
+
#define CLOCKGATE_UARTC 41 // TBC
264
+
// #define CLOCKGATE_I2S1 42
265
+
#define CLOCKGATE_SPI1 43
266
+
#define CLOCKGATE_GPIO 44 // TBC
267
+
#define CLOCKGATE_UNK45 45 // it is used in peicore, also in s5l8702, it is related to 0x3d00_0000 (secure boot ???)
268
+
#define CLOCKGATE_CHIPID 46
269
+
270
+
#define CLOCKGATE_SPI2 47
271
+
// // #define CLOCKGATE_I2S2 47
272
+
// // #define CLOCKGATE_SPI2 48
273
+
274
+
// #define CLOCKGATE_UNK50 50
275
+
// #define CLOCKGATE_UNK52 52
276
+
// #define CLOCKGATE_UNK54 54
277
+
278
+
#define CLOCKGATE_TIMERB 55
279
+
#define CLOCKGATE_TIMERE 56
280
+
#define CLOCKGATE_TIMERF 57
281
+
#define CLOCKGATE_TIMERG 58
282
+
#define CLOCKGATE_TIMERH 59
283
+
#define CLOCKGATE_TIMERI 60
284
+
285
+
#define CLOCKGATE_UNK61 61
286
+
#define CLOCKGATE_UNK62 62
287
+
#define CLOCKGATE_UNK63 63
288
+
289
+
290
+
/* PWRCON2 - 7 gates (64..70) */
291
+
#define CLOCKGATE_SPI3 65 // TBC
292
+
#define CLOCKGATE_UNK66 66
293
+
// #define CLOCKGATE_UNK67 67
294
+
#define CLOCKGATE_SPI4 68 // TBC
295
+
#define CLOCKGATE_TIMERC 69
296
+
#define CLOCKGATE_TIMERD 70
297
+
298
+
299
+
/* PWRCON3 - 15 gates (96..110) */
300
+
#define CLOCKGATE_UNK104 104 // it is used by peicore, related to 0x3880_0000
301
+
#define CLOCKGATE_UNK14_2 107
302
+
303
+
// #define CLOCKGATE_UNK109 109 // it hangs if we disable it
304
+
305
+
306
+
/* PWRCON4 - 24 gates (128..151) */
307
+
#define CLOCKGATE_TIMERA_2 128
308
+
#define CLOCKGATE_TIMERB_2 129
309
+
#define CLOCKGATE_TIMERE_2 130
310
+
#define CLOCKGATE_TIMERF_2 131
311
+
#define CLOCKGATE_TIMERG_2 132
312
+
#define CLOCKGATE_TIMERH_2 133
313
+
#define CLOCKGATE_TIMERI_2 134
314
+
315
+
#define CLOCKGATE_UARTC_2 135 // TBC
316
+
317
+
#define CLOCKGATE_UNK61_2 136
318
+
#define CLOCKGATE_UNK62_2 137
319
+
#define CLOCKGATE_UNK63_2 138
320
+
321
+
#define CLOCKGATE_I2C0_2 139
322
+
#define CLOCKGATE_I2C1_2 140
323
+
324
+
#define CLOCKGATE_SPI0_2 141
325
+
#define CLOCKGATE_SPI1_2 142
326
+
#define CLOCKGATE_SPI2_2 143
327
+
328
+
#define CLOCKGATE_LCD_2 144 // TBC
329
+
330
+
// #define CLOCKGATE_UNK145 145
331
+
332
+
#define CLOCKGATE_SPI3_2 147 // TBC
333
+
#define CLOCKGATE_SPI4_2 148 // TBC
334
+
335
+
#define CLOCKGATE_UNK66_2 149
336
+
337
+
#define CLOCKGATE_TIMERC_2 150
338
+
#define CLOCKGATE_TIMERD_2 151
222
339
#endif
223
340
224
341
/* 06. INTERRUPT CONTROLLER UNIT */
···
286
403
#define MIU_BASE 0x38200000
287
404
#elif CONFIG_CPU==S5L8702
288
405
#define MIU_BASE 0x38100000
406
+
#elif CONFIG_CPU==S5L8720
407
+
#define MIU_BASE 0x3d700000
289
408
#endif
290
409
291
410
#define MIU_REG(off) (*((REG32_PTR_T)(MIU_BASE + (off))))
292
411
293
412
/* SDRAM */
413
+
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
294
414
#define MIUCON (*(REG32_PTR_T)(MIU_BASE)) /* External Memory configuration register */
295
415
#define MIUCOM (*(REG32_PTR_T)(MIU_BASE + 0x04)) /* Command and status register */
296
416
#define MIUAREF (*(REG32_PTR_T)(MIU_BASE + 0x08)) /* Auto-refresh control register */
297
417
#define MIUMRS (*(REG32_PTR_T)(MIU_BASE + 0x0C)) /* SDRAM Mode Register Set Value Register */
298
418
#define MIUSDPARA (*(REG32_PTR_T)(MIU_BASE + 0x10)) /* SDRAM parameter register */
419
+
#elif CONFIG_CPU==S5L8720
420
+
#define MIUCOM (*(REG32_PTR_T)(MIU_BASE + 0x104)) /* Command and status register */
421
+
#define MIUMRS (*(REG32_PTR_T)(MIU_BASE + 0x110)) /* SDRAM Mode Register Set Value Register */
422
+
423
+
#define UNK3E000008 (*(REG32_PTR_T)(0x3e000008))
424
+
#endif
299
425
300
426
/* DDR */
301
427
#define MEMCONF (*(REG32_PTR_T)(MIU_BASE + 0x20)) /* External Memory configuration register */
···
319
445
320
446
/* 08. IODMA CONTROLLER */
321
447
#define DMA_BASE 0x38400000
448
+
449
+
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
450
+
#define DMA0_BASE 0x38200000
451
+
#endif
452
+
453
+
#if CONFIG_CPU==S5L8702
454
+
#define DMA1_BASE 0x39900000
455
+
#elif CONFIG_CPU==S5L8720
456
+
#define DMA1_BASE 0x38700000
457
+
#endif
322
458
323
459
#define DMABASE0 (*(REG32_PTR_T)(DMA_BASE)) /* Base address register for channel 0 */
324
460
#define DMACON0 (*(REG32_PTR_T)(DMA_BASE + 0x04)) /* Configuration register for channel 0 */
···
462
598
#define TDDATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x6C)) /* Data1 Register */
463
599
#define TDPRE (*(REG32_PTR_T)(TIMER_BASE + 0x70)) /* Pre-scale register */
464
600
#define TDCNT (*(REG32_PTR_T)(TIMER_BASE + 0x74)) /* Counter register */
601
+
/* Timer I: 64-bit 5usec timer */
602
+
#define TICNTH (*(REG32_PTR_T)(TIMER_BASE + 0x80))
603
+
#define TICNTL (*(REG32_PTR_T)(TIMER_BASE + 0x84))
604
+
#define TIUNK08 (*(REG32_PTR_T)(TIMER_BASE + 0x88))
605
+
#define TIUNK0C (*(REG32_PTR_T)(TIMER_BASE + 0x8C)) // TBC: DATA0H
606
+
#define TIUNK10 (*(REG32_PTR_T)(TIMER_BASE + 0x90)) // DATA0L
607
+
#define TIUNK14 (*(REG32_PTR_T)(TIMER_BASE + 0x94)) // DATA1H
608
+
#define TIUNK18 (*(REG32_PTR_T)(TIMER_BASE + 0x98)) // DATA1L
465
609
466
610
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
467
611
#define TIMER_FREQ (1843200 * 4 * 26 / 1 / 4) /* 47923200 Hz */
468
612
469
-
#define TREG_80 (*(REG32_PTR_T)(TIMER_BASE + 0x80))
470
-
#define TREG_84 (*(REG32_PTR_T)(TIMER_BASE + 0x84))
471
-
#define FIVE_USEC_TIMER (((uint64_t)TREG_80 << 32) | TREG_84) /* 64bit 5usec timer */
472
-
#define USEC_TIMER (FIVE_USEC_TIMER * 5) /* usecs */
473
-
#elif CONFIG_CPU==S5L8702
474
-
/* 16/32-bit timers:
613
+
#define FIVE_USEC_TIMER (((uint64_t)TICNTH << 32) | TICNTL)
614
+
#define USEC_TIMER (FIVE_USEC_TIMER * 5)
615
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
616
+
/*
617
+
* 16/32-bit timers:
475
618
*
476
619
* - Timers A..D: 16-bit counter, very similar to 16-bit timers described
477
620
* in S5L8700 DS, it seems that the timers C and D are disabled or not
···
480
623
* - Timers E..H: 32-bit counter, they are like 16-bit timers, but the
481
624
* interrupt status for all 32-bit timers is located in TSTAT register.
482
625
*
626
+
* TSTAT:
627
+
* [26]: TIMERE INTOVF
628
+
* [25]: TIMERE INT1
629
+
* [24]: TIMERE INT0
630
+
* [18]: TIMERF INTOVF
631
+
* [17]: TIMERF INT1
632
+
* [16]: TIMERF INT0
633
+
* [10]: TIMERG INTOVF
634
+
* [9]: TIMERG INT1
635
+
* [8]: TIMERG INT0
636
+
* [2]: TIMERH INTOVF
637
+
* [1]: TIMERH INT1
638
+
* [0]: TIMERH INT0
639
+
*
483
640
* - Clock source configuration:
484
641
*
485
642
* TCON[10:8] (Tx_CS) TCON[6]=0 TCON[6]=1
···
493
650
* 11x Ext. Clock 1 Ext. Clock 1
494
651
*
495
652
* On Classic:
496
-
* - Ext. Clock 0: not connected or disabled
497
-
* - Ext. Clock 1: 32768 Hz, external OSC1?, PMU?
498
-
* - ECLK: 12 MHz, external OSC0?
653
+
* Ext. Clock 0: not connected or disabled
654
+
* Ext. Clock 1: 32768 Hz, external OSC1
655
+
* ECLK: 12 MHz, external OSC0
499
656
*/
500
657
#define TIMER_FREQ 12000000 /* ECLK */
501
658
···
607
764
/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
608
765
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
609
766
#define SDCI_BASE 0x3C300000
610
-
#elif CONFIG_CPU==S5L8702
767
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
611
768
#define SDCI_BASE 0x38b00000
612
769
#endif
613
770
···
628
785
#define SDCI_IRQ (*(REG32_PTR_T)(SDCI_BASE + 0x38)) /* Interrupt Source Register */
629
786
#define SDCI_IRQ_MASK (*(REG32_PTR_T)(SDCI_BASE + 0x3c))
630
787
631
-
#if CONFIG_CPU==S5L8702
788
+
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
632
789
#define SDCI_DATA (*(REG32_PTR_T)(SDCI_BASE + 0x40))
633
790
#define SDCI_DMAADDR (*(VOID_PTR_PTR_T)(SDCI_BASE + 0x44))
634
791
#define SDCI_DMASIZE (*(REG32_PTR_T)(SDCI_BASE + 0x48))
···
853
1010
#define I2SRXDB (*(REG32_PTR_T)(I2S_BASE + 0x38)) /* Rx data buffer */
854
1011
#define I2SSTATUS (*(REG32_PTR_T)(I2S_BASE + 0x3C)) /* status register */
855
1012
856
-
#if CONFIG_CPU==S5L8702
1013
+
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
857
1014
#define I2SCLKDIV (*(REG32_PTR_T)(I2S_BASE + 0x40))
858
1015
859
1016
#define I2SCLKGATE(i) ((i) == 2 ? CLOCKGATE_I2S2 : \
···
869
1026
#define IICSTAT (*(REG32_PTR_T)(IIC_BASE + 0x04)) /* Control/Status Register */
870
1027
#define IICADD (*(REG32_PTR_T)(IIC_BASE + 0x08)) /* Bus Address Register */
871
1028
#define IICDS (*(REG32_PTR_T)(IIC_BASE + 0x0C))
872
-
#elif CONFIG_CPU==S5L8702
873
-
/* s5l8702 I2C controller is similar to s5l8700, known differences are:
874
-
875
-
* IICCON[5] is not used in s5l8702.
876
-
* IICCON[13:8] are used to enable interrupts.
877
-
IICSTA2[13:8] are used to read the status and write-clear interrupts.
878
-
Known interrupts:
879
-
[13] STOP on bus (TBC)
880
-
[12] START on bus (TBC)
881
-
[8] byte transmited or received in Master mode (not tested in Slave)
882
-
* IICCON[4] does not clear interrupts, it is enabled when a byte is
883
-
transmited or received, in Master mode the tx/rx of the next byte
884
-
starts when it is written as "1".
885
-
*/
1029
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1030
+
/*
1031
+
* s5l8702 I2C controller is similar to s5l8700, known differences are:
1032
+
*
1033
+
* - IICCON[5] is not used in s5l8702.
1034
+
* - IICCON[13:8] are used to enable interrupts.
1035
+
* IICSTA2[13:8] are used to read the status and write-clear interrupts.
1036
+
* Known interrupts:
1037
+
* [13] STOP on bus (TBC)
1038
+
* [12] START on bus (TBC)
1039
+
* [8] byte transmited or received in Master mode (not tested in Slave)
1040
+
* - IICCON[4] does not clear interrupts, it is enabled when a byte is
1041
+
* transmited or received, in Master mode the tx/rx of the next byte
1042
+
* starts when it is written as "1".
1043
+
*/
886
1044
#define IIC_BASE 0x3C600000
887
1045
888
1046
#define IICCON(bus) (*((REG32_PTR_T)(IIC_BASE + 0x300000 * (bus))))
···
898
1056
CLOCKGATE_I2C0)
899
1057
#endif
900
1058
1059
+
#if CONFIG_CPU == S5L8720
1060
+
#define I2CCLKGATE_2(i) ((i) == 1 ? CLOCKGATE_I2C1_2 : \
1061
+
CLOCKGATE_I2C0_2)
1062
+
#endif
1063
+
901
1064
/* 19. SPI (SERIAL PERHIPERAL INTERFACE) */
902
1065
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
903
1066
#define SPI_BASE 0x3CD00000
···
909
1072
#define SPTDAT (*(REG32_PTR_T)(SPI_BASE + 0x10)) /* Tx Data Register */
910
1073
#define SPRDAT (*(REG32_PTR_T)(SPI_BASE + 0x14)) /* Rx Data Register */
911
1074
#define SPPRE (*(REG32_PTR_T)(SPI_BASE + 0x18)) /* Baud Rate Prescaler Register */
912
-
#elif CONFIG_CPU==S5L8702
1075
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU == S5L8720
913
1076
#define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \
914
1077
(i) == 1 ? 0x3ce00000 : \
915
1078
0x3c300000)
···
928
1091
#define SPICLKDIV(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x30)))
929
1092
#define SPIRXLIMIT(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x34)))
930
1093
#define SPIDD(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x38))) /* TBC */
1094
+
#endif
1095
+
1096
+
#if CONFIG_CPU == S5L8720
1097
+
#define SPIUNK3C(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x3c)))
1098
+
#define SPIUNK40(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x40)))
1099
+
#define SPIUNK4C(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x4c)))
1100
+
1101
+
#define SPICLKGATE_2(i) ((i) == 2 ? CLOCKGATE_SPI2_2 : \
1102
+
(i) == 1 ? CLOCKGATE_SPI1_2 : \
1103
+
CLOCKGATE_SPI0_2)
931
1104
#endif
932
1105
933
1106
/* 20. ADC CONTROLLER */
···
1016
1189
1017
1190
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
1018
1191
#define GPIO_OFFSET_BITS 4
1019
-
#elif CONFIG_CPU==S5L8702
1192
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1020
1193
#define GPIO_OFFSET_BITS 5
1021
1194
#endif
1022
1195
···
1025
1198
#define PUNA(i) (*((REG32_PTR_T)(GPIO_BASE + 0x08 + ((i) << GPIO_OFFSET_BITS))))
1026
1199
#define PUNB(i) (*((REG32_PTR_T)(GPIO_BASE + 0x0c + ((i) << GPIO_OFFSET_BITS))))
1027
1200
1028
-
#if CONFIG_CPU==S5L8702
1201
+
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1029
1202
#define PUNC(i) (*((REG32_PTR_T)(GPIO_BASE + 0x10 + ((i) << GPIO_OFFSET_BITS))))
1030
1203
#endif
1031
1204
···
1056
1229
#define PDAT13 PDAT(13) /* The data register for port 13 */
1057
1230
#define PCON14 PCON(14) /* Configures the pins of port 14 */
1058
1231
#define PDAT14 PDAT(14) /* The data register for port 14 */
1232
+
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
1059
1233
#define PCON15 PCON(15) /* Configures the pins of port 15 */
1234
+
#define PDAT15 PDAT(15) /* Configures the pins of port 15 */
1060
1235
#define PUNK15 PUNB(15) /* Unknown thing for port 15 */
1236
+
#endif
1061
1237
1062
1238
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
1063
1239
#define PCON_ASRAM PCON15 /* Configures the pins of port nor flash */
1064
1240
#define PCON_SDRAM PDAT15 /* Configures the pins of port sdram */
1065
1241
#elif CONFIG_CPU==S5L8702
1242
+
#define GPIO_N_GROUPS 16
1066
1243
#define GPIOCMD (*((REG32_PTR_T)(GPIO_BASE + 0x200)))
1244
+
#elif CONFIG_CPU==S5L8720
1245
+
#define GPIO_N_GROUPS 15
1246
+
#define GPIOCMD (*((REG32_PTR_T)(GPIO_BASE + 0x1e0)))
1247
+
#define GPIOUNK388 (*((REG32_PTR_T)(GPIO_BASE + 0x388)))
1248
+
#define GPIOUNK384 (*((REG32_PTR_T)(GPIO_BASE + 0x384)))
1067
1249
#endif
1068
1250
1069
1251
/* 25. UART */
···
1087
1269
#define UARTC2_BASE_ADDR 0x3CC0C000
1088
1270
#define UARTC2_N_PORTS 1
1089
1271
#define UARTC2_PORT_OFFSET 0x0
1090
-
#elif CONFIG_CPU==S5L8702
1091
-
/* s5l8702 UC87XX HW: 1 UARTC, 4 ports */
1272
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1273
+
/* s5l8702/s5l8720 UC87XX HW: 1 UARTC, 4 ports */
1092
1274
#define UARTC_BASE_ADDR 0x3CC00000
1093
1275
#define UARTC_N_PORTS 4
1094
1276
#define UARTC_PORT_OFFSET 0x4000
···
1099
1281
#define LCD_BASE 0x3C100000
1100
1282
#elif CONFIG_CPU==S5L8701
1101
1283
#define LCD_BASE 0x38600000
1102
-
#elif CONFIG_CPU==S5L8702
1284
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1103
1285
#define LCD_BASE 0x38300000
1104
1286
#endif
1105
1287
···
1148
1330
/* 28. ATA CONTROLLER */
1149
1331
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
1150
1332
#define ATA_BASE 0x38E00000
1151
-
#elif CONFIG_CPU==S5L8702
1333
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1152
1334
#define ATA_BASE 0x38700000
1153
1335
#endif
1154
1336
···
1186
1368
#define ATA_DMA_ADDR (*(VOID_PTR_PTR_T)(ATA_BASE + 0x88))
1187
1369
1188
1370
/* 29. CHIP ID */
1189
-
#define CHIP_ID_BASE 0x3D100000
1190
-
#define REG_ONE (*(REG32_PTR_T)(CHIP_ID_BASE)) /* Receive the first 32 bits from a fuse box */
1191
-
#define REG_TWO (*(REG32_PTR_T)(CHIP_ID_BASE + 0x04)) /* Receive the other 8 bits from a fuse box */
1371
+
#define CHIPID_BASE 0x3D100000
1372
+
1373
+
#define CHIPID_REG_ONE (*(REG32_PTR_T)(CHIPID_BASE)) /* Receive the first 32 bits from a fuse box */
1374
+
#define CHIPID_REG_TWO (*(REG32_PTR_T)(CHIPID_BASE + 0x04)) /* Receive the other 8 bits from a fuse box */
1375
+
1376
+
#if CONFIG_CPU == S5L8720
1377
+
#define CHIPID_INFO (*(REG32_PTR_T)(CHIPID_BASE + 0x08))
1378
+
#endif
1192
1379
1193
1380
/*
1194
1381
The following peripherals are not present in the Samsung S5L8700 datasheet.
···
1198
1385
/* Hardware AES crypto unit - S5L8701+ */
1199
1386
#if CONFIG_CPU==S5L8701
1200
1387
#define AES_BASE 0x39800000
1201
-
#elif CONFIG_CPU==S5L8702
1388
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1202
1389
#define AES_BASE 0x38c00000
1203
1390
#endif
1204
1391
1205
-
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
1392
+
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1206
1393
#define AESCONTROL (*((REG32_PTR_T)(AES_BASE)))
1207
1394
#define AESGO (*((REG32_PTR_T)(AES_BASE + 0x04)))
1208
1395
#define AESUNKREG0 (*((REG32_PTR_T)(AES_BASE + 0x08)))
···
1220
1407
#define AESOUTADDR (*((REG32_PTR_T)(AES_BASE + 0x20)))
1221
1408
#define AESINADDR (*((REG32_PTR_T)(AES_BASE + 0x28)))
1222
1409
#define AESAUXADDR (*((REG32_PTR_T)(AES_BASE + 0x30)))
1223
-
#elif CONFIG_CPU==S5L8702
1410
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1224
1411
#define AESOUTADDR (*((VOID_PTR_PTR_T)(AES_BASE + 0x20)))
1225
1412
#define AESINADDR (*((CONST_VOID_PTR_PTR_T)(AES_BASE + 0x28)))
1226
1413
#define AESAUXADDR (*((VOID_PTR_PTR_T)(AES_BASE + 0x30)))
···
1232
1419
1233
1420
/* SHA-1 unit - S5L8701+ */
1234
1421
#if CONFIG_CPU==S5L8701
1235
-
#define HASH_BASE 0x3C600000
1236
-
1237
-
#define HASHCTRL (*(REG32_PTR_T)(HASH_BASE))
1238
-
#define HASHRESULT ((REG32_PTR_T)(HASH_BASE + 0x20))
1239
-
#define HASHDATAIN ((REG32_PTR_T)(HASH_BASE + 0x40))
1240
-
#elif CONFIG_CPU==S5L8702
1422
+
#define SHA1_BASE 0x3C600000
1423
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU == S5L8720
1241
1424
#define SHA1_BASE 0x38000000
1425
+
#endif
1242
1426
1243
1427
#define SHA1CONFIG (*((REG32_PTR_T)(SHA1_BASE)))
1244
1428
#define SHA1RESET (*((REG32_PTR_T)(SHA1_BASE + 0x04)))
1429
+
1430
+
#if CONFIG_CPU == S5L8720
1431
+
#define SHA1UNK10 (*((REG32_PTR_T)(SHA1_BASE + 0x10)))
1432
+
#endif
1433
+
1245
1434
#define SHA1RESULT ((REG32_PTR_T)(SHA1_BASE + 0x20))
1246
1435
#define SHA1DATAIN ((REG32_PTR_T)(SHA1_BASE + 0x40))
1436
+
1437
+
#if CONFIG_CPU == S5L8720
1438
+
#define SHA1UNK80 (*((REG32_PTR_T)(SHA1_BASE + 0x80)))
1247
1439
#endif
1248
1440
1249
1441
/* Clickwheel controller - S5L8701+ */
1250
-
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
1442
+
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1251
1443
#define WHEEL_BASE 0x3C200000
1252
1444
1253
1445
#define WHEEL00 (*((REG32_PTR_T)(WHEEL_BASE)))
···
1263
1455
/* Synopsys OTG - S5L8701 only */
1264
1456
#if CONFIG_CPU==S5L8701
1265
1457
#define OTGBASE 0x38800000
1266
-
#elif CONFIG_CPU==S5L8702
1458
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1267
1459
#define OTGBASE 0x38400000
1268
1460
#endif
1269
1461
1270
-
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
1462
+
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1271
1463
#define PHYBASE 0x3C400000
1272
1464
1273
1465
/* OTG PHY control registers */
1274
-
#define OPHYPWR (*((REG32_PTR_T)(PHYBASE + 0x000)))
1275
-
#define OPHYCLK (*((REG32_PTR_T)(PHYBASE + 0x004)))
1276
-
#define ORSTCON (*((REG32_PTR_T)(PHYBASE + 0x008)))
1277
-
#define OPHYUNK3 (*((REG32_PTR_T)(PHYBASE + 0x018)))
1278
-
#define OPHYUNK1 (*((REG32_PTR_T)(PHYBASE + 0x01c)))
1279
-
#define OPHYUNK2 (*((REG32_PTR_T)(PHYBASE + 0x044)))
1466
+
#define OPHYPWR (*((REG32_PTR_T)(PHYBASE + 0x00)))
1467
+
#define OPHYCLK (*((REG32_PTR_T)(PHYBASE + 0x04)))
1468
+
#define ORSTCON (*((REG32_PTR_T)(PHYBASE + 0x08)))
1469
+
#define OPHYUNK3 (*((REG32_PTR_T)(PHYBASE + 0x18)))
1470
+
#define OPHYUNK1 (*((REG32_PTR_T)(PHYBASE + 0x1c)))
1471
+
#define OPHYUNK2 (*((REG32_PTR_T)(PHYBASE + 0x44)))
1280
1472
#endif
1281
1473
1282
1474
#if CONFIG_CPU==S5L8701
1283
1475
/* 7 available EPs (0b00000000011101010000000001101011), 6 used */
1284
1476
#define USB_NUM_ENDPOINTS 6
1285
-
#elif CONFIG_CPU==S5L8702
1477
+
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1286
1478
/* 9 available EPs (0b00000001111101010000000111101011), 6 used */
1287
1479
#define USB_NUM_ENDPOINTS 6
1288
1480
#endif
···
1293
1485
#define USB_DW_SHARED_FIFO
1294
1486
#endif
1295
1487
1296
-
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
1488
+
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1297
1489
/* Define this if the DWC implemented on this SoC does not support
1298
1490
DMA or you want to disable it. */
1299
1491
// #define USB_DW_ARCH_SLAVE
1300
1492
#endif
1301
1493
1302
-
#if CONFIG_CPU==S5L8702
1494
+
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1303
1495
/////INTERRUPT CONTROLLERS/////
1304
1496
#define VIC_BASE 0x38E00000
1305
1497
#define VIC_OFFSET 0x1000
···
1485
1677
1486
1678
#define VIC1ADDRESS VICADDRESS(1)
1487
1679
1680
+
#define VIC0EDGE0 (*((REG32_PTR_T)(VICBASE(2)))) // TBC: INTENABLE
1681
+
#define VIC1EDGE0 (*((REG32_PTR_T)(VICBASE(2) + 0x04)))
1682
+
#define VIC0EDGE1 (*((REG32_PTR_T)(VICBASE(2) + 0x08))) // TBC: INTENCLEAR
1683
+
#define VIC1EDGE1 (*((REG32_PTR_T)(VICBASE(2) + 0x0C)))
1684
+
1488
1685
/////INTERRUPTS/////
1686
+
// #define IRQ_UNK5 5
1489
1687
#define IRQ_TIMER32 7
1490
1688
#define IRQ_TIMER 8
1491
1689
#define IRQ_SPI(i) (9+(i)) /* TBC */
···
1497
1695
#define IRQ_DMAC0 IRQ_DMAC(0)
1498
1696
#define IRQ_DMAC1 IRQ_DMAC(1)
1499
1697
#define IRQ_USB_FUNC 19
1698
+
#define IRQ_NAND 20 // TBC: it is so in s5l8900
1500
1699
#define IRQ_I2C(i) (21+(i))
1501
1700
#define IRQ_I2C0 IRQ_I2C(0)
1502
1701
#define IRQ_I2C1 IRQ_I2C(1)
···
1508
1707
#define IRQ_UART3 IRQ_UART(3)
1509
1708
#define IRQ_UART4 IRQ_UART(4) /* obsolete/not implemented on s5l8702 ??? */
1510
1709
#define IRQ_ATA 29
1511
-
#define IRQ_SBOOT 36
1710
+
#define IRQ_SECBOOT 36
1512
1711
#define IRQ_AES 39
1513
1712
#define IRQ_SHA 40
1713
+
#define IRQ_NANDECC 43 // TBC: it is so in s5l8900
1514
1714
#define IRQ_MMC 44
1515
1715
1516
1716
#define IRQ_EXT0 0